1 /* 2 * twl4030-irq.c - TWL4030/TPS659x0 irq support 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Modifications to defer interrupt handling to a kernel thread: 7 * Copyright (C) 2006 MontaVista Software, Inc. 8 * 9 * Based on tlv320aic23.c: 10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 11 * 12 * Code cleanup and modifications to IRQ handler. 13 * by syed khasim <x0khasim@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/init.h> 31 #include <linux/interrupt.h> 32 #include <linux/irq.h> 33 #include <linux/kthread.h> 34 35 #include <linux/i2c/twl4030.h> 36 37 38 /* 39 * TWL4030 IRQ handling has two stages in hardware, and thus in software. 40 * The Primary Interrupt Handler (PIH) stage exposes status bits saying 41 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. 42 * SIH modules are more traditional IRQ components, which support per-IRQ 43 * enable/disable and trigger controls; they do most of the work. 44 * 45 * These chips are designed to support IRQ handling from two different 46 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status 47 * and mask registers in the PIH and SIH modules. 48 * 49 * We set up IRQs starting at a platform-specified base, always starting 50 * with PIH and the SIH for PWR_INT and then usually adding GPIO: 51 * base + 0 .. base + 7 PIH 52 * base + 8 .. base + 15 SIH for PWR_INT 53 * base + 16 .. base + 33 SIH for GPIO 54 */ 55 56 /* PIH register offsets */ 57 #define REG_PIH_ISR_P1 0x01 58 #define REG_PIH_ISR_P2 0x02 59 #define REG_PIH_SIR 0x03 /* for testing */ 60 61 62 /* Linux could (eventually) use either IRQ line */ 63 static int irq_line; 64 65 struct sih { 66 char name[8]; 67 u8 module; /* module id */ 68 u8 control_offset; /* for SIH_CTRL */ 69 bool set_cor; 70 71 u8 bits; /* valid in isr/imr */ 72 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ 73 74 u8 edr_offset; 75 u8 bytes_edr; /* bytelen of EDR */ 76 77 /* SIR ignored -- set interrupt, for testing only */ 78 struct irq_data { 79 u8 isr_offset; 80 u8 imr_offset; 81 } mask[2]; 82 /* + 2 bytes padding */ 83 }; 84 85 #define SIH_INITIALIZER(modname, nbits) \ 86 .module = TWL4030_MODULE_ ## modname, \ 87 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ 88 .bits = nbits, \ 89 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ 90 .edr_offset = TWL4030_ ## modname ## _EDR, \ 91 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ 92 .mask = { { \ 93 .isr_offset = TWL4030_ ## modname ## _ISR1, \ 94 .imr_offset = TWL4030_ ## modname ## _IMR1, \ 95 }, \ 96 { \ 97 .isr_offset = TWL4030_ ## modname ## _ISR2, \ 98 .imr_offset = TWL4030_ ## modname ## _IMR2, \ 99 }, }, 100 101 /* register naming policies are inconsistent ... */ 102 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 103 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD 104 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT 105 106 107 /* Order in this table matches order in PIH_ISR. That is, 108 * BIT(n) in PIH_ISR is sih_modules[n]. 109 */ 110 static const struct sih sih_modules[6] = { 111 [0] = { 112 .name = "gpio", 113 .module = TWL4030_MODULE_GPIO, 114 .control_offset = REG_GPIO_SIH_CTRL, 115 .set_cor = true, 116 .bits = TWL4030_GPIO_MAX, 117 .bytes_ixr = 3, 118 /* Note: *all* of these IRQs default to no-trigger */ 119 .edr_offset = REG_GPIO_EDR1, 120 .bytes_edr = 5, 121 .mask = { { 122 .isr_offset = REG_GPIO_ISR1A, 123 .imr_offset = REG_GPIO_IMR1A, 124 }, { 125 .isr_offset = REG_GPIO_ISR1B, 126 .imr_offset = REG_GPIO_IMR1B, 127 }, }, 128 }, 129 [1] = { 130 .name = "keypad", 131 .set_cor = true, 132 SIH_INITIALIZER(KEYPAD_KEYP, 4) 133 }, 134 [2] = { 135 .name = "bci", 136 .module = TWL4030_MODULE_INTERRUPTS, 137 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, 138 .bits = 12, 139 .bytes_ixr = 2, 140 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, 141 /* Note: most of these IRQs default to no-trigger */ 142 .bytes_edr = 3, 143 .mask = { { 144 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, 145 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, 146 }, { 147 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, 148 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, 149 }, }, 150 }, 151 [3] = { 152 .name = "madc", 153 SIH_INITIALIZER(MADC, 4) 154 }, 155 [4] = { 156 /* USB doesn't use the same SIH organization */ 157 .name = "usb", 158 }, 159 [5] = { 160 .name = "power", 161 .set_cor = true, 162 SIH_INITIALIZER(INT_PWR, 8) 163 }, 164 /* there are no SIH modules #6 or #7 ... */ 165 }; 166 167 #undef TWL4030_MODULE_KEYPAD_KEYP 168 #undef TWL4030_MODULE_INT_PWR 169 #undef TWL4030_INT_PWR_EDR 170 171 /*----------------------------------------------------------------------*/ 172 173 static unsigned twl4030_irq_base; 174 175 static struct completion irq_event; 176 177 /* 178 * This thread processes interrupts reported by the Primary Interrupt Handler. 179 */ 180 static int twl4030_irq_thread(void *data) 181 { 182 long irq = (long)data; 183 struct irq_desc *desc = irq_to_desc(irq); 184 static unsigned i2c_errors; 185 const static unsigned max_i2c_errors = 100; 186 187 if (!desc) { 188 pr_err("twl4030: Invalid IRQ: %ld\n", irq); 189 return -EINVAL; 190 } 191 192 current->flags |= PF_NOFREEZE; 193 194 while (!kthread_should_stop()) { 195 int ret; 196 int module_irq; 197 u8 pih_isr; 198 199 /* Wait for IRQ, then read PIH irq status (also blocking) */ 200 wait_for_completion_interruptible(&irq_event); 201 202 ret = twl4030_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, 203 REG_PIH_ISR_P1); 204 if (ret) { 205 pr_warning("twl4030: I2C error %d reading PIH ISR\n", 206 ret); 207 if (++i2c_errors >= max_i2c_errors) { 208 printk(KERN_ERR "Maximum I2C error count" 209 " exceeded. Terminating %s.\n", 210 __func__); 211 break; 212 } 213 complete(&irq_event); 214 continue; 215 } 216 217 /* these handlers deal with the relevant SIH irq status */ 218 local_irq_disable(); 219 for (module_irq = twl4030_irq_base; 220 pih_isr; 221 pih_isr >>= 1, module_irq++) { 222 if (pih_isr & 0x1) { 223 struct irq_desc *d = irq_to_desc(module_irq); 224 225 if (!d) { 226 pr_err("twl4030: Invalid SIH IRQ: %d\n", 227 module_irq); 228 return -EINVAL; 229 } 230 231 /* These can't be masked ... always warn 232 * if we get any surprises. 233 */ 234 if (d->status & IRQ_DISABLED) 235 note_interrupt(module_irq, d, 236 IRQ_NONE); 237 else 238 d->handle_irq(module_irq, d); 239 } 240 } 241 local_irq_enable(); 242 243 desc->chip->unmask(irq); 244 } 245 246 return 0; 247 } 248 249 /* 250 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. 251 * This is a chained interrupt, so there is no desc->action method for it. 252 * Now we need to query the interrupt controller in the twl4030 to determine 253 * which module is generating the interrupt request. However, we can't do i2c 254 * transactions in interrupt context, so we must defer that work to a kernel 255 * thread. All we do here is acknowledge and mask the interrupt and wakeup 256 * the kernel thread. 257 */ 258 static void handle_twl4030_pih(unsigned int irq, irq_desc_t *desc) 259 { 260 /* Acknowledge, clear *AND* mask the interrupt... */ 261 desc->chip->ack(irq); 262 complete(&irq_event); 263 } 264 265 static struct task_struct *start_twl4030_irq_thread(long irq) 266 { 267 struct task_struct *thread; 268 269 init_completion(&irq_event); 270 thread = kthread_run(twl4030_irq_thread, (void *)irq, "twl4030-irq"); 271 if (!thread) 272 pr_err("twl4030: could not create irq %ld thread!\n", irq); 273 274 return thread; 275 } 276 277 /*----------------------------------------------------------------------*/ 278 279 /* 280 * twl4030_init_sih_modules() ... start from a known state where no 281 * IRQs will be coming in, and where we can quickly enable them then 282 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. 283 * 284 * NOTE: we don't touch EDR registers here; they stay with hardware 285 * defaults or whatever the last value was. Note that when both EDR 286 * bits for an IRQ are clear, that's as if its IMR bit is set... 287 */ 288 static int twl4030_init_sih_modules(unsigned line) 289 { 290 const struct sih *sih; 291 u8 buf[4]; 292 int i; 293 int status; 294 295 /* line 0 == int1_n signal; line 1 == int2_n signal */ 296 if (line > 1) 297 return -EINVAL; 298 299 irq_line = line; 300 301 /* disable all interrupts on our line */ 302 memset(buf, 0xff, sizeof buf); 303 sih = sih_modules; 304 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) { 305 306 /* skip USB -- it's funky */ 307 if (!sih->bytes_ixr) 308 continue; 309 310 status = twl4030_i2c_write(sih->module, buf, 311 sih->mask[line].imr_offset, sih->bytes_ixr); 312 if (status < 0) 313 pr_err("twl4030: err %d initializing %s %s\n", 314 status, sih->name, "IMR"); 315 316 /* Maybe disable "exclusive" mode; buffer second pending irq; 317 * set Clear-On-Read (COR) bit. 318 * 319 * NOTE that sometimes COR polarity is documented as being 320 * inverted: for MADC and BCI, COR=1 means "clear on write". 321 * And for PWR_INT it's not documented... 322 */ 323 if (sih->set_cor) { 324 status = twl4030_i2c_write_u8(sih->module, 325 TWL4030_SIH_CTRL_COR_MASK, 326 sih->control_offset); 327 if (status < 0) 328 pr_err("twl4030: err %d initializing %s %s\n", 329 status, sih->name, "SIH_CTRL"); 330 } 331 } 332 333 sih = sih_modules; 334 for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) { 335 u8 rxbuf[4]; 336 int j; 337 338 /* skip USB */ 339 if (!sih->bytes_ixr) 340 continue; 341 342 /* Clear pending interrupt status. Either the read was 343 * enough, or we need to write those bits. Repeat, in 344 * case an IRQ is pending (PENDDIS=0) ... that's not 345 * uncommon with PWR_INT.PWRON. 346 */ 347 for (j = 0; j < 2; j++) { 348 status = twl4030_i2c_read(sih->module, rxbuf, 349 sih->mask[line].isr_offset, sih->bytes_ixr); 350 if (status < 0) 351 pr_err("twl4030: err %d initializing %s %s\n", 352 status, sih->name, "ISR"); 353 354 if (!sih->set_cor) 355 status = twl4030_i2c_write(sih->module, buf, 356 sih->mask[line].isr_offset, 357 sih->bytes_ixr); 358 /* else COR=1 means read sufficed. 359 * (for most SIH modules...) 360 */ 361 } 362 } 363 364 return 0; 365 } 366 367 static inline void activate_irq(int irq) 368 { 369 #ifdef CONFIG_ARM 370 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it 371 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. 372 */ 373 set_irq_flags(irq, IRQF_VALID); 374 #else 375 /* same effect on other architectures */ 376 set_irq_noprobe(irq); 377 #endif 378 } 379 380 /*----------------------------------------------------------------------*/ 381 382 static DEFINE_SPINLOCK(sih_agent_lock); 383 384 static struct workqueue_struct *wq; 385 386 struct sih_agent { 387 int irq_base; 388 const struct sih *sih; 389 390 u32 imr; 391 bool imr_change_pending; 392 struct work_struct mask_work; 393 394 u32 edge_change; 395 struct work_struct edge_work; 396 }; 397 398 static void twl4030_sih_do_mask(struct work_struct *work) 399 { 400 struct sih_agent *agent; 401 const struct sih *sih; 402 union { 403 u8 bytes[4]; 404 u32 word; 405 } imr; 406 int status; 407 408 agent = container_of(work, struct sih_agent, mask_work); 409 410 /* see what work we have */ 411 spin_lock_irq(&sih_agent_lock); 412 if (agent->imr_change_pending) { 413 sih = agent->sih; 414 /* byte[0] gets overwritten as we write ... */ 415 imr.word = cpu_to_le32(agent->imr << 8); 416 agent->imr_change_pending = false; 417 } else 418 sih = NULL; 419 spin_unlock_irq(&sih_agent_lock); 420 if (!sih) 421 return; 422 423 /* write the whole mask ... simpler than subsetting it */ 424 status = twl4030_i2c_write(sih->module, imr.bytes, 425 sih->mask[irq_line].imr_offset, sih->bytes_ixr); 426 if (status) 427 pr_err("twl4030: %s, %s --> %d\n", __func__, 428 "write", status); 429 } 430 431 static void twl4030_sih_do_edge(struct work_struct *work) 432 { 433 struct sih_agent *agent; 434 const struct sih *sih; 435 u8 bytes[6]; 436 u32 edge_change; 437 int status; 438 439 agent = container_of(work, struct sih_agent, edge_work); 440 441 /* see what work we have */ 442 spin_lock_irq(&sih_agent_lock); 443 edge_change = agent->edge_change; 444 agent->edge_change = 0;; 445 sih = edge_change ? agent->sih : NULL; 446 spin_unlock_irq(&sih_agent_lock); 447 if (!sih) 448 return; 449 450 /* Read, reserving first byte for write scratch. Yes, this 451 * could be cached for some speedup ... but be careful about 452 * any processor on the other IRQ line, EDR registers are 453 * shared. 454 */ 455 status = twl4030_i2c_read(sih->module, bytes + 1, 456 sih->edr_offset, sih->bytes_edr); 457 if (status) { 458 pr_err("twl4030: %s, %s --> %d\n", __func__, 459 "read", status); 460 return; 461 } 462 463 /* Modify only the bits we know must change */ 464 while (edge_change) { 465 int i = fls(edge_change) - 1; 466 struct irq_desc *d = irq_to_desc(i + agent->irq_base); 467 int byte = 1 + (i >> 2); 468 int off = (i & 0x3) * 2; 469 470 if (!d) { 471 pr_err("twl4030: Invalid IRQ: %d\n", 472 i + agent->irq_base); 473 return; 474 } 475 476 bytes[byte] &= ~(0x03 << off); 477 478 spin_lock_irq(&d->lock); 479 if (d->status & IRQ_TYPE_EDGE_RISING) 480 bytes[byte] |= BIT(off + 1); 481 if (d->status & IRQ_TYPE_EDGE_FALLING) 482 bytes[byte] |= BIT(off + 0); 483 spin_unlock_irq(&d->lock); 484 485 edge_change &= ~BIT(i); 486 } 487 488 /* Write */ 489 status = twl4030_i2c_write(sih->module, bytes, 490 sih->edr_offset, sih->bytes_edr); 491 if (status) 492 pr_err("twl4030: %s, %s --> %d\n", __func__, 493 "write", status); 494 } 495 496 /*----------------------------------------------------------------------*/ 497 498 /* 499 * All irq_chip methods get issued from code holding irq_desc[irq].lock, 500 * which can't perform the underlying I2C operations (because they sleep). 501 * So we must hand them off to a thread (workqueue) and cope with asynch 502 * completion, potentially including some re-ordering, of these requests. 503 */ 504 505 static void twl4030_sih_mask(unsigned irq) 506 { 507 struct sih_agent *sih = get_irq_chip_data(irq); 508 unsigned long flags; 509 510 spin_lock_irqsave(&sih_agent_lock, flags); 511 sih->imr |= BIT(irq - sih->irq_base); 512 sih->imr_change_pending = true; 513 queue_work(wq, &sih->mask_work); 514 spin_unlock_irqrestore(&sih_agent_lock, flags); 515 } 516 517 static void twl4030_sih_unmask(unsigned irq) 518 { 519 struct sih_agent *sih = get_irq_chip_data(irq); 520 unsigned long flags; 521 522 spin_lock_irqsave(&sih_agent_lock, flags); 523 sih->imr &= ~BIT(irq - sih->irq_base); 524 sih->imr_change_pending = true; 525 queue_work(wq, &sih->mask_work); 526 spin_unlock_irqrestore(&sih_agent_lock, flags); 527 } 528 529 static int twl4030_sih_set_type(unsigned irq, unsigned trigger) 530 { 531 struct sih_agent *sih = get_irq_chip_data(irq); 532 struct irq_desc *desc = irq_to_desc(irq); 533 unsigned long flags; 534 535 if (!desc) { 536 pr_err("twl4030: Invalid IRQ: %d\n", irq); 537 return -EINVAL; 538 } 539 540 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 541 return -EINVAL; 542 543 spin_lock_irqsave(&sih_agent_lock, flags); 544 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) { 545 desc->status &= ~IRQ_TYPE_SENSE_MASK; 546 desc->status |= trigger; 547 sih->edge_change |= BIT(irq - sih->irq_base); 548 queue_work(wq, &sih->edge_work); 549 } 550 spin_unlock_irqrestore(&sih_agent_lock, flags); 551 return 0; 552 } 553 554 static struct irq_chip twl4030_sih_irq_chip = { 555 .name = "twl4030", 556 .mask = twl4030_sih_mask, 557 .unmask = twl4030_sih_unmask, 558 .set_type = twl4030_sih_set_type, 559 }; 560 561 /*----------------------------------------------------------------------*/ 562 563 static inline int sih_read_isr(const struct sih *sih) 564 { 565 int status; 566 union { 567 u8 bytes[4]; 568 u32 word; 569 } isr; 570 571 /* FIXME need retry-on-error ... */ 572 573 isr.word = 0; 574 status = twl4030_i2c_read(sih->module, isr.bytes, 575 sih->mask[irq_line].isr_offset, sih->bytes_ixr); 576 577 return (status < 0) ? status : le32_to_cpu(isr.word); 578 } 579 580 /* 581 * Generic handler for SIH interrupts ... we "know" this is called 582 * in task context, with IRQs enabled. 583 */ 584 static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) 585 { 586 struct sih_agent *agent = get_irq_data(irq); 587 const struct sih *sih = agent->sih; 588 int isr; 589 590 /* reading ISR acks the IRQs, using clear-on-read mode */ 591 local_irq_enable(); 592 isr = sih_read_isr(sih); 593 local_irq_disable(); 594 595 if (isr < 0) { 596 pr_err("twl4030: %s SIH, read ISR error %d\n", 597 sih->name, isr); 598 /* REVISIT: recover; eventually mask it all, etc */ 599 return; 600 } 601 602 while (isr) { 603 irq = fls(isr); 604 irq--; 605 isr &= ~BIT(irq); 606 607 if (irq < sih->bits) 608 generic_handle_irq(agent->irq_base + irq); 609 else 610 pr_err("twl4030: %s SIH, invalid ISR bit %d\n", 611 sih->name, irq); 612 } 613 } 614 615 static unsigned twl4030_irq_next; 616 617 /* returns the first IRQ used by this SIH bank, 618 * or negative errno 619 */ 620 int twl4030_sih_setup(int module) 621 { 622 int sih_mod; 623 const struct sih *sih = NULL; 624 struct sih_agent *agent; 625 int i, irq; 626 int status = -EINVAL; 627 unsigned irq_base = twl4030_irq_next; 628 629 /* only support modules with standard clear-on-read for now */ 630 for (sih_mod = 0, sih = sih_modules; 631 sih_mod < ARRAY_SIZE(sih_modules); 632 sih_mod++, sih++) { 633 if (sih->module == module && sih->set_cor) { 634 if (!WARN((irq_base + sih->bits) > NR_IRQS, 635 "irq %d for %s too big\n", 636 irq_base + sih->bits, 637 sih->name)) 638 status = 0; 639 break; 640 } 641 } 642 if (status < 0) 643 return status; 644 645 agent = kzalloc(sizeof *agent, GFP_KERNEL); 646 if (!agent) 647 return -ENOMEM; 648 649 status = 0; 650 651 agent->irq_base = irq_base; 652 agent->sih = sih; 653 agent->imr = ~0; 654 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); 655 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); 656 657 for (i = 0; i < sih->bits; i++) { 658 irq = irq_base + i; 659 660 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip, 661 handle_edge_irq); 662 set_irq_chip_data(irq, agent); 663 activate_irq(irq); 664 } 665 666 status = irq_base; 667 twl4030_irq_next += i; 668 669 /* replace generic PIH handler (handle_simple_irq) */ 670 irq = sih_mod + twl4030_irq_base; 671 set_irq_data(irq, agent); 672 set_irq_chained_handler(irq, handle_twl4030_sih); 673 674 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, 675 irq, irq_base, twl4030_irq_next - 1); 676 677 return status; 678 } 679 680 /* FIXME need a call to reverse twl4030_sih_setup() ... */ 681 682 683 /*----------------------------------------------------------------------*/ 684 685 /* FIXME pass in which interrupt line we'll use ... */ 686 #define twl_irq_line 0 687 688 int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) 689 { 690 static struct irq_chip twl4030_irq_chip; 691 692 int status; 693 int i; 694 struct task_struct *task; 695 696 /* 697 * Mask and clear all TWL4030 interrupts since initially we do 698 * not have any TWL4030 module interrupt handlers present 699 */ 700 status = twl4030_init_sih_modules(twl_irq_line); 701 if (status < 0) 702 return status; 703 704 wq = create_singlethread_workqueue("twl4030-irqchip"); 705 if (!wq) { 706 pr_err("twl4030: workqueue FAIL\n"); 707 return -ESRCH; 708 } 709 710 twl4030_irq_base = irq_base; 711 712 /* install an irq handler for each of the SIH modules; 713 * clone dummy irq_chip since PIH can't *do* anything 714 */ 715 twl4030_irq_chip = dummy_irq_chip; 716 twl4030_irq_chip.name = "twl4030"; 717 718 twl4030_sih_irq_chip.ack = dummy_irq_chip.ack; 719 720 for (i = irq_base; i < irq_end; i++) { 721 set_irq_chip_and_handler(i, &twl4030_irq_chip, 722 handle_simple_irq); 723 activate_irq(i); 724 } 725 twl4030_irq_next = i; 726 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", 727 irq_num, irq_base, twl4030_irq_next - 1); 728 729 /* ... and the PWR_INT module ... */ 730 status = twl4030_sih_setup(TWL4030_MODULE_INT); 731 if (status < 0) { 732 pr_err("twl4030: sih_setup PWR INT --> %d\n", status); 733 goto fail; 734 } 735 736 /* install an irq handler to demultiplex the TWL4030 interrupt */ 737 task = start_twl4030_irq_thread(irq_num); 738 if (!task) { 739 pr_err("twl4030: irq thread FAIL\n"); 740 status = -ESRCH; 741 goto fail; 742 } 743 744 set_irq_data(irq_num, task); 745 set_irq_chained_handler(irq_num, handle_twl4030_pih); 746 747 return status; 748 749 fail: 750 for (i = irq_base; i < irq_end; i++) 751 set_irq_chip_and_handler(i, NULL, NULL); 752 destroy_workqueue(wq); 753 wq = NULL; 754 return status; 755 } 756 757 int twl_exit_irq(void) 758 { 759 /* FIXME undo twl_init_irq() */ 760 if (twl4030_irq_base) { 761 pr_err("twl4030: can't yet clean up IRQs?\n"); 762 return -ENOSYS; 763 } 764 return 0; 765 } 766