1 /* 2 * twl4030-irq.c - TWL4030/TPS659x0 irq support 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Modifications to defer interrupt handling to a kernel thread: 7 * Copyright (C) 2006 MontaVista Software, Inc. 8 * 9 * Based on tlv320aic23.c: 10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 11 * 12 * Code cleanup and modifications to IRQ handler. 13 * by syed khasim <x0khasim@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30 #include <linux/init.h> 31 #include <linux/interrupt.h> 32 #include <linux/irq.h> 33 #include <linux/slab.h> 34 35 #include <linux/i2c/twl.h> 36 37 #include "twl-core.h" 38 39 /* 40 * TWL4030 IRQ handling has two stages in hardware, and thus in software. 41 * The Primary Interrupt Handler (PIH) stage exposes status bits saying 42 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. 43 * SIH modules are more traditional IRQ components, which support per-IRQ 44 * enable/disable and trigger controls; they do most of the work. 45 * 46 * These chips are designed to support IRQ handling from two different 47 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status 48 * and mask registers in the PIH and SIH modules. 49 * 50 * We set up IRQs starting at a platform-specified base, always starting 51 * with PIH and the SIH for PWR_INT and then usually adding GPIO: 52 * base + 0 .. base + 7 PIH 53 * base + 8 .. base + 15 SIH for PWR_INT 54 * base + 16 .. base + 33 SIH for GPIO 55 */ 56 57 /* PIH register offsets */ 58 #define REG_PIH_ISR_P1 0x01 59 #define REG_PIH_ISR_P2 0x02 60 #define REG_PIH_SIR 0x03 /* for testing */ 61 62 63 /* Linux could (eventually) use either IRQ line */ 64 static int irq_line; 65 66 struct sih { 67 char name[8]; 68 u8 module; /* module id */ 69 u8 control_offset; /* for SIH_CTRL */ 70 bool set_cor; 71 72 u8 bits; /* valid in isr/imr */ 73 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ 74 75 u8 edr_offset; 76 u8 bytes_edr; /* bytelen of EDR */ 77 78 u8 irq_lines; /* number of supported irq lines */ 79 80 /* SIR ignored -- set interrupt, for testing only */ 81 struct sih_irq_data { 82 u8 isr_offset; 83 u8 imr_offset; 84 } mask[2]; 85 /* + 2 bytes padding */ 86 }; 87 88 static const struct sih *sih_modules; 89 static int nr_sih_modules; 90 91 #define SIH_INITIALIZER(modname, nbits) \ 92 .module = TWL4030_MODULE_ ## modname, \ 93 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ 94 .bits = nbits, \ 95 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ 96 .edr_offset = TWL4030_ ## modname ## _EDR, \ 97 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ 98 .irq_lines = 2, \ 99 .mask = { { \ 100 .isr_offset = TWL4030_ ## modname ## _ISR1, \ 101 .imr_offset = TWL4030_ ## modname ## _IMR1, \ 102 }, \ 103 { \ 104 .isr_offset = TWL4030_ ## modname ## _ISR2, \ 105 .imr_offset = TWL4030_ ## modname ## _IMR2, \ 106 }, }, 107 108 /* register naming policies are inconsistent ... */ 109 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 110 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD 111 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT 112 113 114 /* Order in this table matches order in PIH_ISR. That is, 115 * BIT(n) in PIH_ISR is sih_modules[n]. 116 */ 117 /* sih_modules_twl4030 is used both in twl4030 and twl5030 */ 118 static const struct sih sih_modules_twl4030[6] = { 119 [0] = { 120 .name = "gpio", 121 .module = TWL4030_MODULE_GPIO, 122 .control_offset = REG_GPIO_SIH_CTRL, 123 .set_cor = true, 124 .bits = TWL4030_GPIO_MAX, 125 .bytes_ixr = 3, 126 /* Note: *all* of these IRQs default to no-trigger */ 127 .edr_offset = REG_GPIO_EDR1, 128 .bytes_edr = 5, 129 .irq_lines = 2, 130 .mask = { { 131 .isr_offset = REG_GPIO_ISR1A, 132 .imr_offset = REG_GPIO_IMR1A, 133 }, { 134 .isr_offset = REG_GPIO_ISR1B, 135 .imr_offset = REG_GPIO_IMR1B, 136 }, }, 137 }, 138 [1] = { 139 .name = "keypad", 140 .set_cor = true, 141 SIH_INITIALIZER(KEYPAD_KEYP, 4) 142 }, 143 [2] = { 144 .name = "bci", 145 .module = TWL4030_MODULE_INTERRUPTS, 146 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, 147 .set_cor = true, 148 .bits = 12, 149 .bytes_ixr = 2, 150 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, 151 /* Note: most of these IRQs default to no-trigger */ 152 .bytes_edr = 3, 153 .irq_lines = 2, 154 .mask = { { 155 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, 156 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, 157 }, { 158 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, 159 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, 160 }, }, 161 }, 162 [3] = { 163 .name = "madc", 164 SIH_INITIALIZER(MADC, 4) 165 }, 166 [4] = { 167 /* USB doesn't use the same SIH organization */ 168 .name = "usb", 169 }, 170 [5] = { 171 .name = "power", 172 .set_cor = true, 173 SIH_INITIALIZER(INT_PWR, 8) 174 }, 175 /* there are no SIH modules #6 or #7 ... */ 176 }; 177 178 static const struct sih sih_modules_twl5031[8] = { 179 [0] = { 180 .name = "gpio", 181 .module = TWL4030_MODULE_GPIO, 182 .control_offset = REG_GPIO_SIH_CTRL, 183 .set_cor = true, 184 .bits = TWL4030_GPIO_MAX, 185 .bytes_ixr = 3, 186 /* Note: *all* of these IRQs default to no-trigger */ 187 .edr_offset = REG_GPIO_EDR1, 188 .bytes_edr = 5, 189 .irq_lines = 2, 190 .mask = { { 191 .isr_offset = REG_GPIO_ISR1A, 192 .imr_offset = REG_GPIO_IMR1A, 193 }, { 194 .isr_offset = REG_GPIO_ISR1B, 195 .imr_offset = REG_GPIO_IMR1B, 196 }, }, 197 }, 198 [1] = { 199 .name = "keypad", 200 .set_cor = true, 201 SIH_INITIALIZER(KEYPAD_KEYP, 4) 202 }, 203 [2] = { 204 .name = "bci", 205 .module = TWL5031_MODULE_INTERRUPTS, 206 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, 207 .bits = 7, 208 .bytes_ixr = 1, 209 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, 210 /* Note: most of these IRQs default to no-trigger */ 211 .bytes_edr = 2, 212 .irq_lines = 2, 213 .mask = { { 214 .isr_offset = TWL5031_INTERRUPTS_BCIISR1, 215 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, 216 }, { 217 .isr_offset = TWL5031_INTERRUPTS_BCIISR2, 218 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, 219 }, }, 220 }, 221 [3] = { 222 .name = "madc", 223 SIH_INITIALIZER(MADC, 4) 224 }, 225 [4] = { 226 /* USB doesn't use the same SIH organization */ 227 .name = "usb", 228 }, 229 [5] = { 230 .name = "power", 231 .set_cor = true, 232 SIH_INITIALIZER(INT_PWR, 8) 233 }, 234 [6] = { 235 /* 236 * ECI/DBI doesn't use the same SIH organization. 237 * For example, it supports only one interrupt output line. 238 * That is, the interrupts are seen on both INT1 and INT2 lines. 239 */ 240 .name = "eci_dbi", 241 .module = TWL5031_MODULE_ACCESSORY, 242 .bits = 9, 243 .bytes_ixr = 2, 244 .irq_lines = 1, 245 .mask = { { 246 .isr_offset = TWL5031_ACIIDR_LSB, 247 .imr_offset = TWL5031_ACIIMR_LSB, 248 }, }, 249 250 }, 251 [7] = { 252 /* Audio accessory */ 253 .name = "audio", 254 .module = TWL5031_MODULE_ACCESSORY, 255 .control_offset = TWL5031_ACCSIHCTRL, 256 .bits = 2, 257 .bytes_ixr = 1, 258 .edr_offset = TWL5031_ACCEDR1, 259 /* Note: most of these IRQs default to no-trigger */ 260 .bytes_edr = 1, 261 .irq_lines = 2, 262 .mask = { { 263 .isr_offset = TWL5031_ACCISR1, 264 .imr_offset = TWL5031_ACCIMR1, 265 }, { 266 .isr_offset = TWL5031_ACCISR2, 267 .imr_offset = TWL5031_ACCIMR2, 268 }, }, 269 }, 270 }; 271 272 #undef TWL4030_MODULE_KEYPAD_KEYP 273 #undef TWL4030_MODULE_INT_PWR 274 #undef TWL4030_INT_PWR_EDR 275 276 /*----------------------------------------------------------------------*/ 277 278 static unsigned twl4030_irq_base; 279 280 /* 281 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. 282 * This is a chained interrupt, so there is no desc->action method for it. 283 * Now we need to query the interrupt controller in the twl4030 to determine 284 * which module is generating the interrupt request. However, we can't do i2c 285 * transactions in interrupt context, so we must defer that work to a kernel 286 * thread. All we do here is acknowledge and mask the interrupt and wakeup 287 * the kernel thread. 288 */ 289 static irqreturn_t handle_twl4030_pih(int irq, void *devid) 290 { 291 int module_irq; 292 irqreturn_t ret; 293 u8 pih_isr; 294 295 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, 296 REG_PIH_ISR_P1); 297 if (ret) { 298 pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret); 299 return IRQ_NONE; 300 } 301 302 /* these handlers deal with the relevant SIH irq status */ 303 for (module_irq = twl4030_irq_base; 304 pih_isr; 305 pih_isr >>= 1, module_irq++) { 306 if (pih_isr & 0x1) 307 handle_nested_irq(module_irq); 308 } 309 310 return IRQ_HANDLED; 311 } 312 /*----------------------------------------------------------------------*/ 313 314 /* 315 * twl4030_init_sih_modules() ... start from a known state where no 316 * IRQs will be coming in, and where we can quickly enable them then 317 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. 318 * 319 * NOTE: we don't touch EDR registers here; they stay with hardware 320 * defaults or whatever the last value was. Note that when both EDR 321 * bits for an IRQ are clear, that's as if its IMR bit is set... 322 */ 323 static int twl4030_init_sih_modules(unsigned line) 324 { 325 const struct sih *sih; 326 u8 buf[4]; 327 int i; 328 int status; 329 330 /* line 0 == int1_n signal; line 1 == int2_n signal */ 331 if (line > 1) 332 return -EINVAL; 333 334 irq_line = line; 335 336 /* disable all interrupts on our line */ 337 memset(buf, 0xff, sizeof buf); 338 sih = sih_modules; 339 for (i = 0; i < nr_sih_modules; i++, sih++) { 340 341 /* skip USB -- it's funky */ 342 if (!sih->bytes_ixr) 343 continue; 344 345 /* Not all the SIH modules support multiple interrupt lines */ 346 if (sih->irq_lines <= line) 347 continue; 348 349 status = twl_i2c_write(sih->module, buf, 350 sih->mask[line].imr_offset, sih->bytes_ixr); 351 if (status < 0) 352 pr_err("twl4030: err %d initializing %s %s\n", 353 status, sih->name, "IMR"); 354 355 /* Maybe disable "exclusive" mode; buffer second pending irq; 356 * set Clear-On-Read (COR) bit. 357 * 358 * NOTE that sometimes COR polarity is documented as being 359 * inverted: for MADC, COR=1 means "clear on write". 360 * And for PWR_INT it's not documented... 361 */ 362 if (sih->set_cor) { 363 status = twl_i2c_write_u8(sih->module, 364 TWL4030_SIH_CTRL_COR_MASK, 365 sih->control_offset); 366 if (status < 0) 367 pr_err("twl4030: err %d initializing %s %s\n", 368 status, sih->name, "SIH_CTRL"); 369 } 370 } 371 372 sih = sih_modules; 373 for (i = 0; i < nr_sih_modules; i++, sih++) { 374 u8 rxbuf[4]; 375 int j; 376 377 /* skip USB */ 378 if (!sih->bytes_ixr) 379 continue; 380 381 /* Not all the SIH modules support multiple interrupt lines */ 382 if (sih->irq_lines <= line) 383 continue; 384 385 /* Clear pending interrupt status. Either the read was 386 * enough, or we need to write those bits. Repeat, in 387 * case an IRQ is pending (PENDDIS=0) ... that's not 388 * uncommon with PWR_INT.PWRON. 389 */ 390 for (j = 0; j < 2; j++) { 391 status = twl_i2c_read(sih->module, rxbuf, 392 sih->mask[line].isr_offset, sih->bytes_ixr); 393 if (status < 0) 394 pr_err("twl4030: err %d initializing %s %s\n", 395 status, sih->name, "ISR"); 396 397 if (!sih->set_cor) 398 status = twl_i2c_write(sih->module, buf, 399 sih->mask[line].isr_offset, 400 sih->bytes_ixr); 401 /* else COR=1 means read sufficed. 402 * (for most SIH modules...) 403 */ 404 } 405 } 406 407 return 0; 408 } 409 410 static inline void activate_irq(int irq) 411 { 412 #ifdef CONFIG_ARM 413 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it 414 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. 415 */ 416 set_irq_flags(irq, IRQF_VALID); 417 #else 418 /* same effect on other architectures */ 419 irq_set_noprobe(irq); 420 #endif 421 } 422 423 /*----------------------------------------------------------------------*/ 424 425 struct sih_agent { 426 int irq_base; 427 const struct sih *sih; 428 429 u32 imr; 430 bool imr_change_pending; 431 432 u32 edge_change; 433 434 struct mutex irq_lock; 435 }; 436 437 /*----------------------------------------------------------------------*/ 438 439 /* 440 * All irq_chip methods get issued from code holding irq_desc[irq].lock, 441 * which can't perform the underlying I2C operations (because they sleep). 442 * So we must hand them off to a thread (workqueue) and cope with asynch 443 * completion, potentially including some re-ordering, of these requests. 444 */ 445 446 static void twl4030_sih_mask(struct irq_data *data) 447 { 448 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 449 450 agent->imr |= BIT(data->irq - agent->irq_base); 451 agent->imr_change_pending = true; 452 } 453 454 static void twl4030_sih_unmask(struct irq_data *data) 455 { 456 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 457 458 agent->imr &= ~BIT(data->irq - agent->irq_base); 459 agent->imr_change_pending = true; 460 } 461 462 static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) 463 { 464 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 465 466 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 467 return -EINVAL; 468 469 if (irqd_get_trigger_type(data) != trigger) 470 agent->edge_change |= BIT(data->irq - agent->irq_base); 471 472 return 0; 473 } 474 475 static void twl4030_sih_bus_lock(struct irq_data *data) 476 { 477 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 478 479 mutex_lock(&agent->irq_lock); 480 } 481 482 static void twl4030_sih_bus_sync_unlock(struct irq_data *data) 483 { 484 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 485 const struct sih *sih = agent->sih; 486 int status; 487 488 if (agent->imr_change_pending) { 489 union { 490 u32 word; 491 u8 bytes[4]; 492 } imr; 493 494 /* byte[0] gets overwriten as we write ... */ 495 imr.word = cpu_to_le32(agent->imr << 8); 496 agent->imr_change_pending = false; 497 498 /* write the whole mask ... simpler than subsetting it */ 499 status = twl_i2c_write(sih->module, imr.bytes, 500 sih->mask[irq_line].imr_offset, 501 sih->bytes_ixr); 502 if (status) 503 pr_err("twl4030: %s, %s --> %d\n", __func__, 504 "write", status); 505 } 506 507 if (agent->edge_change) { 508 u32 edge_change; 509 u8 bytes[6]; 510 511 edge_change = agent->edge_change; 512 agent->edge_change = 0; 513 514 /* 515 * Read, reserving first byte for write scratch. Yes, this 516 * could be cached for some speedup ... but be careful about 517 * any processor on the other IRQ line, EDR registers are 518 * shared. 519 */ 520 status = twl_i2c_read(sih->module, bytes + 1, 521 sih->edr_offset, sih->bytes_edr); 522 if (status) { 523 pr_err("twl4030: %s, %s --> %d\n", __func__, 524 "read", status); 525 return; 526 } 527 528 /* Modify only the bits we know must change */ 529 while (edge_change) { 530 int i = fls(edge_change) - 1; 531 struct irq_data *idata; 532 int byte = 1 + (i >> 2); 533 int off = (i & 0x3) * 2; 534 unsigned int type; 535 536 idata = irq_get_irq_data(i + agent->irq_base); 537 538 bytes[byte] &= ~(0x03 << off); 539 540 type = irqd_get_trigger_type(idata); 541 if (type & IRQ_TYPE_EDGE_RISING) 542 bytes[byte] |= BIT(off + 1); 543 if (type & IRQ_TYPE_EDGE_FALLING) 544 bytes[byte] |= BIT(off + 0); 545 546 edge_change &= ~BIT(i); 547 } 548 549 /* Write */ 550 status = twl_i2c_write(sih->module, bytes, 551 sih->edr_offset, sih->bytes_edr); 552 if (status) 553 pr_err("twl4030: %s, %s --> %d\n", __func__, 554 "write", status); 555 } 556 557 mutex_unlock(&agent->irq_lock); 558 } 559 560 static struct irq_chip twl4030_sih_irq_chip = { 561 .name = "twl4030", 562 .irq_mask = twl4030_sih_mask, 563 .irq_unmask = twl4030_sih_unmask, 564 .irq_set_type = twl4030_sih_set_type, 565 .irq_bus_lock = twl4030_sih_bus_lock, 566 .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock, 567 }; 568 569 /*----------------------------------------------------------------------*/ 570 571 static inline int sih_read_isr(const struct sih *sih) 572 { 573 int status; 574 union { 575 u8 bytes[4]; 576 u32 word; 577 } isr; 578 579 /* FIXME need retry-on-error ... */ 580 581 isr.word = 0; 582 status = twl_i2c_read(sih->module, isr.bytes, 583 sih->mask[irq_line].isr_offset, sih->bytes_ixr); 584 585 return (status < 0) ? status : le32_to_cpu(isr.word); 586 } 587 588 /* 589 * Generic handler for SIH interrupts ... we "know" this is called 590 * in task context, with IRQs enabled. 591 */ 592 static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) 593 { 594 struct sih_agent *agent = irq_get_handler_data(irq); 595 const struct sih *sih = agent->sih; 596 int isr; 597 598 /* reading ISR acks the IRQs, using clear-on-read mode */ 599 isr = sih_read_isr(sih); 600 601 if (isr < 0) { 602 pr_err("twl4030: %s SIH, read ISR error %d\n", 603 sih->name, isr); 604 /* REVISIT: recover; eventually mask it all, etc */ 605 return; 606 } 607 608 while (isr) { 609 irq = fls(isr); 610 irq--; 611 isr &= ~BIT(irq); 612 613 if (irq < sih->bits) 614 handle_nested_irq(agent->irq_base + irq); 615 else 616 pr_err("twl4030: %s SIH, invalid ISR bit %d\n", 617 sih->name, irq); 618 } 619 } 620 621 static unsigned twl4030_irq_next; 622 623 /* returns the first IRQ used by this SIH bank, 624 * or negative errno 625 */ 626 int twl4030_sih_setup(int module) 627 { 628 int sih_mod; 629 const struct sih *sih = NULL; 630 struct sih_agent *agent; 631 int i, irq; 632 int status = -EINVAL; 633 unsigned irq_base = twl4030_irq_next; 634 635 /* only support modules with standard clear-on-read for now */ 636 for (sih_mod = 0, sih = sih_modules; 637 sih_mod < nr_sih_modules; 638 sih_mod++, sih++) { 639 if (sih->module == module && sih->set_cor) { 640 if (!WARN((irq_base + sih->bits) > NR_IRQS, 641 "irq %d for %s too big\n", 642 irq_base + sih->bits, 643 sih->name)) 644 status = 0; 645 break; 646 } 647 } 648 if (status < 0) 649 return status; 650 651 agent = kzalloc(sizeof *agent, GFP_KERNEL); 652 if (!agent) 653 return -ENOMEM; 654 655 status = 0; 656 657 agent->irq_base = irq_base; 658 agent->sih = sih; 659 agent->imr = ~0; 660 mutex_init(&agent->irq_lock); 661 662 for (i = 0; i < sih->bits; i++) { 663 irq = irq_base + i; 664 665 irq_set_chip_data(irq, agent); 666 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip, 667 handle_edge_irq); 668 activate_irq(irq); 669 } 670 671 status = irq_base; 672 twl4030_irq_next += i; 673 674 /* replace generic PIH handler (handle_simple_irq) */ 675 irq = sih_mod + twl4030_irq_base; 676 irq_set_handler_data(irq, agent); 677 irq_set_chained_handler(irq, handle_twl4030_sih); 678 679 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, 680 irq, irq_base, twl4030_irq_next - 1); 681 682 return status; 683 } 684 685 /* FIXME need a call to reverse twl4030_sih_setup() ... */ 686 687 688 /*----------------------------------------------------------------------*/ 689 690 /* FIXME pass in which interrupt line we'll use ... */ 691 #define twl_irq_line 0 692 693 int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) 694 { 695 static struct irq_chip twl4030_irq_chip; 696 697 int status; 698 int i; 699 700 /* 701 * Mask and clear all TWL4030 interrupts since initially we do 702 * not have any TWL4030 module interrupt handlers present 703 */ 704 status = twl4030_init_sih_modules(twl_irq_line); 705 if (status < 0) 706 return status; 707 708 twl4030_irq_base = irq_base; 709 710 /* install an irq handler for each of the SIH modules; 711 * clone dummy irq_chip since PIH can't *do* anything 712 */ 713 twl4030_irq_chip = dummy_irq_chip; 714 twl4030_irq_chip.name = "twl4030"; 715 716 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; 717 718 for (i = irq_base; i < irq_end; i++) { 719 irq_set_chip_and_handler(i, &twl4030_irq_chip, 720 handle_simple_irq); 721 irq_set_nested_thread(i, 1); 722 activate_irq(i); 723 } 724 twl4030_irq_next = i; 725 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", 726 irq_num, irq_base, twl4030_irq_next - 1); 727 728 /* ... and the PWR_INT module ... */ 729 status = twl4030_sih_setup(TWL4030_MODULE_INT); 730 if (status < 0) { 731 pr_err("twl4030: sih_setup PWR INT --> %d\n", status); 732 goto fail; 733 } 734 735 /* install an irq handler to demultiplex the TWL4030 interrupt */ 736 status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih, 0, 737 "TWL4030-PIH", NULL); 738 if (status < 0) { 739 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); 740 goto fail_rqirq; 741 } 742 743 return status; 744 fail_rqirq: 745 /* clean up twl4030_sih_setup */ 746 fail: 747 for (i = irq_base; i < irq_end; i++) { 748 irq_set_nested_thread(i, 0); 749 irq_set_chip_and_handler(i, NULL, NULL); 750 } 751 752 return status; 753 } 754 755 int twl4030_exit_irq(void) 756 { 757 /* FIXME undo twl_init_irq() */ 758 if (twl4030_irq_base) { 759 pr_err("twl4030: can't yet clean up IRQs?\n"); 760 return -ENOSYS; 761 } 762 return 0; 763 } 764 765 int twl4030_init_chip_irq(const char *chip) 766 { 767 if (!strcmp(chip, "twl5031")) { 768 sih_modules = sih_modules_twl5031; 769 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); 770 } else { 771 sih_modules = sih_modules_twl4030; 772 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); 773 } 774 775 return 0; 776 } 777