xref: /openbmc/linux/drivers/mfd/stw481x.c (revision 9816d859)
1af873fceSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
260013b94SLinus Walleij /*
360013b94SLinus Walleij  * Core driver for STw4810/STw4811
460013b94SLinus Walleij  *
560013b94SLinus Walleij  * Copyright (C) 2013 ST-Ericsson SA
660013b94SLinus Walleij  * Written on behalf of Linaro for ST-Ericsson
760013b94SLinus Walleij  *
860013b94SLinus Walleij  * Author: Linus Walleij <linus.walleij@linaro.org>
960013b94SLinus Walleij  */
1060013b94SLinus Walleij 
1160013b94SLinus Walleij #include <linux/err.h>
1260013b94SLinus Walleij #include <linux/i2c.h>
1360013b94SLinus Walleij #include <linux/init.h>
1460013b94SLinus Walleij #include <linux/mfd/core.h>
1560013b94SLinus Walleij #include <linux/mfd/stw481x.h>
1660013b94SLinus Walleij #include <linux/module.h>
1760013b94SLinus Walleij #include <linux/regmap.h>
1860013b94SLinus Walleij #include <linux/spinlock.h>
1960013b94SLinus Walleij #include <linux/slab.h>
2060013b94SLinus Walleij 
2160013b94SLinus Walleij /*
2260013b94SLinus Walleij  * This driver can only access the non-USB portions of STw4811, the register
2360013b94SLinus Walleij  * range 0x00-0x10 dealing with USB is bound to the two special I2C pins used
2460013b94SLinus Walleij  * for USB control.
2560013b94SLinus Walleij  */
2660013b94SLinus Walleij 
2760013b94SLinus Walleij /* Registers inside the power control address space */
2860013b94SLinus Walleij #define STW_PC_VCORE_SEL	0x05U
2960013b94SLinus Walleij #define STW_PC_VAUX_SEL		0x06U
3060013b94SLinus Walleij #define STW_PC_VPLL_SEL		0x07U
3160013b94SLinus Walleij 
3260013b94SLinus Walleij /**
3360013b94SLinus Walleij  * stw481x_get_pctl_reg() - get a power control register
3460013b94SLinus Walleij  * @stw481x: handle to the stw481x chip
3560013b94SLinus Walleij  * @reg: power control register to fetch
3660013b94SLinus Walleij  *
3760013b94SLinus Walleij  * The power control registers is a set of one-time-programmable registers
3860013b94SLinus Walleij  * in its own register space, accessed by writing addess bits to these
3960013b94SLinus Walleij  * two registers: bits 7,6,5 of PCTL_REG_LO corresponds to the 3 LSBs of
4060013b94SLinus Walleij  * the address and bits 8,9 of PCTL_REG_HI corresponds to the 2 MSBs of
4160013b94SLinus Walleij  * the address, forming an address space of 5 bits, i.e. 32 registers
4260013b94SLinus Walleij  * 0x00 ... 0x1f can be obtained.
4360013b94SLinus Walleij  */
stw481x_get_pctl_reg(struct stw481x * stw481x,u8 reg)4460013b94SLinus Walleij static int stw481x_get_pctl_reg(struct stw481x *stw481x, u8 reg)
4560013b94SLinus Walleij {
4660013b94SLinus Walleij 	u8 msb = (reg >> 3) & 0x03;
4760013b94SLinus Walleij 	u8 lsb = (reg << 5) & 0xe0;
4860013b94SLinus Walleij 	unsigned int val;
4960013b94SLinus Walleij 	u8 vrfy;
5060013b94SLinus Walleij 	int ret;
5160013b94SLinus Walleij 
5260013b94SLinus Walleij 	ret = regmap_write(stw481x->map, STW_PCTL_REG_HI, msb);
5360013b94SLinus Walleij 	if (ret)
5460013b94SLinus Walleij 		return ret;
5560013b94SLinus Walleij 	ret = regmap_write(stw481x->map, STW_PCTL_REG_LO, lsb);
5660013b94SLinus Walleij 	if (ret)
5760013b94SLinus Walleij 		return ret;
5860013b94SLinus Walleij 	ret = regmap_read(stw481x->map, STW_PCTL_REG_HI, &val);
5960013b94SLinus Walleij 	if (ret)
6060013b94SLinus Walleij 		return ret;
6160013b94SLinus Walleij 	vrfy = (val & 0x03) << 3;
6260013b94SLinus Walleij 	ret = regmap_read(stw481x->map, STW_PCTL_REG_LO, &val);
6360013b94SLinus Walleij 	if (ret)
6460013b94SLinus Walleij 		return ret;
6560013b94SLinus Walleij 	vrfy |= ((val >> 5) & 0x07);
6660013b94SLinus Walleij 	if (vrfy != reg)
6760013b94SLinus Walleij 		return -EIO;
6860013b94SLinus Walleij 	return (val >> 1) & 0x0f;
6960013b94SLinus Walleij }
7060013b94SLinus Walleij 
stw481x_startup(struct stw481x * stw481x)7160013b94SLinus Walleij static int stw481x_startup(struct stw481x *stw481x)
7260013b94SLinus Walleij {
7360013b94SLinus Walleij 	/* Voltages multiplied by 100 */
74223fd9f6SColin Ian King 	static const u8 vcore_val[] = {
75223fd9f6SColin Ian King 		100, 105, 110, 115, 120, 122, 124, 126, 128,
76223fd9f6SColin Ian King 		130, 132, 134, 136, 138, 140, 145
77223fd9f6SColin Ian King 	};
78223fd9f6SColin Ian King 	static const u8 vpll_val[] = { 105, 120, 130, 180 };
79223fd9f6SColin Ian King 	static const u8 vaux_val[] = { 15, 18, 25, 28 };
8060013b94SLinus Walleij 	u8 vcore;
8160013b94SLinus Walleij 	u8 vcore_slp;
8260013b94SLinus Walleij 	u8 vpll;
8360013b94SLinus Walleij 	u8 vaux;
8460013b94SLinus Walleij 	bool vaux_en;
8560013b94SLinus Walleij 	bool it_warn;
8660013b94SLinus Walleij 	int ret;
8760013b94SLinus Walleij 	unsigned int val;
8860013b94SLinus Walleij 
8960013b94SLinus Walleij 	ret = regmap_read(stw481x->map, STW_CONF1, &val);
9060013b94SLinus Walleij 	if (ret)
9160013b94SLinus Walleij 		return ret;
9260013b94SLinus Walleij 	vaux_en = !!(val & STW_CONF1_PDN_VAUX);
9360013b94SLinus Walleij 	it_warn = !!(val & STW_CONF1_IT_WARN);
9460013b94SLinus Walleij 
9560013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "voltages %s\n",
9660013b94SLinus Walleij 		(val & STW_CONF1_V_MONITORING) ? "OK" : "LOW");
9760013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "MMC level shifter %s\n",
9860013b94SLinus Walleij 		(val & STW_CONF1_MMC_LS_STATUS) ? "high impedance" : "ON");
9960013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "VMMC: %s\n",
10060013b94SLinus Walleij 		(val & STW_CONF1_PDN_VMMC) ? "ON" : "disabled");
10160013b94SLinus Walleij 
10260013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "STw481x power control registers:\n");
10360013b94SLinus Walleij 
10460013b94SLinus Walleij 	ret = stw481x_get_pctl_reg(stw481x, STW_PC_VCORE_SEL);
10560013b94SLinus Walleij 	if (ret < 0)
10660013b94SLinus Walleij 		return ret;
10760013b94SLinus Walleij 	vcore = ret & 0x0f;
10860013b94SLinus Walleij 
10960013b94SLinus Walleij 	ret = stw481x_get_pctl_reg(stw481x, STW_PC_VAUX_SEL);
11060013b94SLinus Walleij 	if (ret < 0)
11160013b94SLinus Walleij 		return ret;
11260013b94SLinus Walleij 	vaux = (ret >> 2) & 3;
11360013b94SLinus Walleij 	vpll = (ret >> 4) & 1; /* Save bit 4 */
11460013b94SLinus Walleij 
11560013b94SLinus Walleij 	ret = stw481x_get_pctl_reg(stw481x, STW_PC_VPLL_SEL);
11660013b94SLinus Walleij 	if (ret < 0)
11760013b94SLinus Walleij 		return ret;
11860013b94SLinus Walleij 	vpll |= (ret >> 1) & 2;
11960013b94SLinus Walleij 
12060013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "VCORE: %u.%uV %s\n",
12160013b94SLinus Walleij 		vcore_val[vcore] / 100, vcore_val[vcore] % 100,
12260013b94SLinus Walleij 		(ret & 4) ? "ON" : "OFF");
12360013b94SLinus Walleij 
12460013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "VPLL:  %u.%uV %s\n",
12560013b94SLinus Walleij 		vpll_val[vpll] / 100, vpll_val[vpll] % 100,
12660013b94SLinus Walleij 		(ret & 0x10) ? "ON" : "OFF");
12760013b94SLinus Walleij 
12860013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "VAUX:  %u.%uV %s\n",
12960013b94SLinus Walleij 		vaux_val[vaux] / 10, vaux_val[vaux] % 10,
13060013b94SLinus Walleij 		vaux_en ? "ON" : "OFF");
13160013b94SLinus Walleij 
13260013b94SLinus Walleij 	ret = regmap_read(stw481x->map, STW_CONF2, &val);
13360013b94SLinus Walleij 	if (ret)
13460013b94SLinus Walleij 		return ret;
13560013b94SLinus Walleij 
13660013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "TWARN: %s threshold, %s\n",
13760013b94SLinus Walleij 		it_warn ? "below" : "above",
13860013b94SLinus Walleij 		(val & STW_CONF2_MASK_TWARN) ?
13960013b94SLinus Walleij 		 "enabled" : "mask through VDDOK");
14060013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "VMMC: %s\n",
14160013b94SLinus Walleij 		(val & STW_CONF2_VMMC_EXT) ? "internal" : "external");
14260013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "IT WAKE UP: %s\n",
14360013b94SLinus Walleij 		(val & STW_CONF2_MASK_IT_WAKE_UP) ? "enabled" : "masked");
14460013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "GPO1: %s\n",
14560013b94SLinus Walleij 		(val & STW_CONF2_GPO1) ? "low" : "high impedance");
14660013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "GPO2: %s\n",
14760013b94SLinus Walleij 		(val & STW_CONF2_GPO2) ? "low" : "high impedance");
14860013b94SLinus Walleij 
14960013b94SLinus Walleij 	ret = regmap_read(stw481x->map, STW_VCORE_SLEEP, &val);
15060013b94SLinus Walleij 	if (ret)
15160013b94SLinus Walleij 		return ret;
15260013b94SLinus Walleij 	vcore_slp = val & 0x0f;
15360013b94SLinus Walleij 	dev_info(&stw481x->client->dev, "VCORE SLEEP: %u.%uV\n",
15460013b94SLinus Walleij 		vcore_val[vcore_slp] / 100, vcore_val[vcore_slp] % 100);
15560013b94SLinus Walleij 
15660013b94SLinus Walleij 	return 0;
15760013b94SLinus Walleij }
15860013b94SLinus Walleij 
15960013b94SLinus Walleij /*
16060013b94SLinus Walleij  * MFD cells - we have one cell which is selected operation
16160013b94SLinus Walleij  * mode, and we always have a GPIO cell.
16260013b94SLinus Walleij  */
16360013b94SLinus Walleij static struct mfd_cell stw481x_cells[] = {
16460013b94SLinus Walleij 	{
16560013b94SLinus Walleij 		.of_compatible = "st,stw481x-vmmc",
16660013b94SLinus Walleij 		.name = "stw481x-vmmc-regulator",
16760013b94SLinus Walleij 		.id = -1,
16860013b94SLinus Walleij 	},
16960013b94SLinus Walleij };
17060013b94SLinus Walleij 
171e2f3e9bbSSachin Kamat static const struct regmap_config stw481x_regmap_config = {
17260013b94SLinus Walleij 	.reg_bits = 8,
17360013b94SLinus Walleij 	.val_bits = 8,
17460013b94SLinus Walleij };
17560013b94SLinus Walleij 
stw481x_probe(struct i2c_client * client)17640ee15f7SUwe Kleine-König static int stw481x_probe(struct i2c_client *client)
17760013b94SLinus Walleij {
17860013b94SLinus Walleij 	struct stw481x			*stw481x;
17960013b94SLinus Walleij 	int ret;
18060013b94SLinus Walleij 	int i;
18160013b94SLinus Walleij 
18260013b94SLinus Walleij 	stw481x = devm_kzalloc(&client->dev, sizeof(*stw481x), GFP_KERNEL);
18360013b94SLinus Walleij 	if (!stw481x)
18460013b94SLinus Walleij 		return -ENOMEM;
18560013b94SLinus Walleij 
18660013b94SLinus Walleij 	i2c_set_clientdata(client, stw481x);
18760013b94SLinus Walleij 	stw481x->client = client;
18860013b94SLinus Walleij 	stw481x->map = devm_regmap_init_i2c(client, &stw481x_regmap_config);
189c88fd91bSSachin Kamat 	if (IS_ERR(stw481x->map)) {
190c88fd91bSSachin Kamat 		ret = PTR_ERR(stw481x->map);
191c88fd91bSSachin Kamat 		dev_err(&client->dev, "Failed to allocate register map: %d\n",
192c88fd91bSSachin Kamat 			ret);
193c88fd91bSSachin Kamat 		return ret;
194c88fd91bSSachin Kamat 	}
19560013b94SLinus Walleij 
19660013b94SLinus Walleij 	ret = stw481x_startup(stw481x);
19760013b94SLinus Walleij 	if (ret) {
19860013b94SLinus Walleij 		dev_err(&client->dev, "chip initialization failed\n");
19960013b94SLinus Walleij 		return ret;
20060013b94SLinus Walleij 	}
20160013b94SLinus Walleij 
20260013b94SLinus Walleij 	/* Set up and register the platform devices. */
20360013b94SLinus Walleij 	for (i = 0; i < ARRAY_SIZE(stw481x_cells); i++) {
20460013b94SLinus Walleij 		/* One state holder for all drivers, this is simple */
20560013b94SLinus Walleij 		stw481x_cells[i].platform_data = stw481x;
20660013b94SLinus Walleij 		stw481x_cells[i].pdata_size = sizeof(*stw481x);
20760013b94SLinus Walleij 	}
20860013b94SLinus Walleij 
209e253fb04SLaxman Dewangan 	ret = devm_mfd_add_devices(&client->dev, 0, stw481x_cells,
21060013b94SLinus Walleij 				   ARRAY_SIZE(stw481x_cells), NULL, 0, NULL);
21160013b94SLinus Walleij 	if (ret)
21260013b94SLinus Walleij 		return ret;
21360013b94SLinus Walleij 
21460013b94SLinus Walleij 	dev_info(&client->dev, "initialized STw481x device\n");
21560013b94SLinus Walleij 
21660013b94SLinus Walleij 	return ret;
21760013b94SLinus Walleij }
21860013b94SLinus Walleij 
21960013b94SLinus Walleij /*
22060013b94SLinus Walleij  * This ID table is completely unused, as this is a pure
22160013b94SLinus Walleij  * device-tree probed driver, but it has to be here due to
22260013b94SLinus Walleij  * the structure of the I2C core.
22360013b94SLinus Walleij  */
22460013b94SLinus Walleij static const struct i2c_device_id stw481x_id[] = {
22560013b94SLinus Walleij 	{ "stw481x", 0 },
22660013b94SLinus Walleij 	{ },
22760013b94SLinus Walleij };
2280f63bdedSJavier Martinez Canillas MODULE_DEVICE_TABLE(i2c, stw481x_id);
22960013b94SLinus Walleij 
23060013b94SLinus Walleij static const struct of_device_id stw481x_match[] = {
23160013b94SLinus Walleij 	{ .compatible = "st,stw4810", },
23260013b94SLinus Walleij 	{ .compatible = "st,stw4811", },
23360013b94SLinus Walleij 	{ },
23460013b94SLinus Walleij };
23560013b94SLinus Walleij MODULE_DEVICE_TABLE(of, stw481x_match);
23660013b94SLinus Walleij 
23760013b94SLinus Walleij static struct i2c_driver stw481x_driver = {
23860013b94SLinus Walleij 	.driver = {
23960013b94SLinus Walleij 		.name	= "stw481x",
24060013b94SLinus Walleij 		.of_match_table = stw481x_match,
24160013b94SLinus Walleij 	},
242*9816d859SUwe Kleine-König 	.probe		= stw481x_probe,
24360013b94SLinus Walleij 	.id_table	= stw481x_id,
24460013b94SLinus Walleij };
24560013b94SLinus Walleij 
24660013b94SLinus Walleij module_i2c_driver(stw481x_driver);
24760013b94SLinus Walleij 
24860013b94SLinus Walleij MODULE_AUTHOR("Linus Walleij");
24960013b94SLinus Walleij MODULE_DESCRIPTION("STw481x PMIC driver");
25060013b94SLinus Walleij MODULE_LICENSE("GPL v2");
251