1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ST Microelectronics MFD: stmpe's driver 4 * 5 * Copyright (C) ST-Ericsson SA 2010 6 * 7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 8 */ 9 10 #include <linux/err.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/export.h> 13 #include <linux/kernel.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/of.h> 18 #include <linux/pm.h> 19 #include <linux/slab.h> 20 #include <linux/mfd/core.h> 21 #include <linux/delay.h> 22 #include <linux/regulator/consumer.h> 23 #include "stmpe.h" 24 25 /** 26 * struct stmpe_platform_data - STMPE platform data 27 * @id: device id to distinguish between multiple STMPEs on the same board 28 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 29 * @irq_trigger: IRQ trigger to use for the interrupt to the host 30 * @autosleep: bool to enable/disable stmpe autosleep 31 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 32 */ 33 struct stmpe_platform_data { 34 int id; 35 unsigned int blocks; 36 unsigned int irq_trigger; 37 bool autosleep; 38 int autosleep_timeout; 39 }; 40 41 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 42 { 43 return stmpe->variant->enable(stmpe, blocks, true); 44 } 45 46 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 47 { 48 return stmpe->variant->enable(stmpe, blocks, false); 49 } 50 51 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg) 52 { 53 int ret; 54 55 ret = stmpe->ci->read_byte(stmpe, reg); 56 if (ret < 0) 57 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); 58 59 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); 60 61 return ret; 62 } 63 64 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 65 { 66 int ret; 67 68 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); 69 70 ret = stmpe->ci->write_byte(stmpe, reg, val); 71 if (ret < 0) 72 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret); 73 74 return ret; 75 } 76 77 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 78 { 79 int ret; 80 81 ret = __stmpe_reg_read(stmpe, reg); 82 if (ret < 0) 83 return ret; 84 85 ret &= ~mask; 86 ret |= val; 87 88 return __stmpe_reg_write(stmpe, reg, ret); 89 } 90 91 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, 92 u8 *values) 93 { 94 int ret; 95 96 ret = stmpe->ci->read_block(stmpe, reg, length, values); 97 if (ret < 0) 98 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret); 99 100 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret); 101 stmpe_dump_bytes("stmpe rd: ", values, length); 102 103 return ret; 104 } 105 106 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 107 const u8 *values) 108 { 109 int ret; 110 111 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length); 112 stmpe_dump_bytes("stmpe wr: ", values, length); 113 114 ret = stmpe->ci->write_block(stmpe, reg, length, values); 115 if (ret < 0) 116 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret); 117 118 return ret; 119 } 120 121 /** 122 * stmpe_enable - enable blocks on an STMPE device 123 * @stmpe: Device to work on 124 * @blocks: Mask of blocks (enum stmpe_block values) to enable 125 */ 126 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 127 { 128 int ret; 129 130 mutex_lock(&stmpe->lock); 131 ret = __stmpe_enable(stmpe, blocks); 132 mutex_unlock(&stmpe->lock); 133 134 return ret; 135 } 136 EXPORT_SYMBOL_GPL(stmpe_enable); 137 138 /** 139 * stmpe_disable - disable blocks on an STMPE device 140 * @stmpe: Device to work on 141 * @blocks: Mask of blocks (enum stmpe_block values) to enable 142 */ 143 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 144 { 145 int ret; 146 147 mutex_lock(&stmpe->lock); 148 ret = __stmpe_disable(stmpe, blocks); 149 mutex_unlock(&stmpe->lock); 150 151 return ret; 152 } 153 EXPORT_SYMBOL_GPL(stmpe_disable); 154 155 /** 156 * stmpe_reg_read() - read a single STMPE register 157 * @stmpe: Device to read from 158 * @reg: Register to read 159 */ 160 int stmpe_reg_read(struct stmpe *stmpe, u8 reg) 161 { 162 int ret; 163 164 mutex_lock(&stmpe->lock); 165 ret = __stmpe_reg_read(stmpe, reg); 166 mutex_unlock(&stmpe->lock); 167 168 return ret; 169 } 170 EXPORT_SYMBOL_GPL(stmpe_reg_read); 171 172 /** 173 * stmpe_reg_write() - write a single STMPE register 174 * @stmpe: Device to write to 175 * @reg: Register to write 176 * @val: Value to write 177 */ 178 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 179 { 180 int ret; 181 182 mutex_lock(&stmpe->lock); 183 ret = __stmpe_reg_write(stmpe, reg, val); 184 mutex_unlock(&stmpe->lock); 185 186 return ret; 187 } 188 EXPORT_SYMBOL_GPL(stmpe_reg_write); 189 190 /** 191 * stmpe_set_bits() - set the value of a bitfield in a STMPE register 192 * @stmpe: Device to write to 193 * @reg: Register to write 194 * @mask: Mask of bits to set 195 * @val: Value to set 196 */ 197 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 198 { 199 int ret; 200 201 mutex_lock(&stmpe->lock); 202 ret = __stmpe_set_bits(stmpe, reg, mask, val); 203 mutex_unlock(&stmpe->lock); 204 205 return ret; 206 } 207 EXPORT_SYMBOL_GPL(stmpe_set_bits); 208 209 /** 210 * stmpe_block_read() - read multiple STMPE registers 211 * @stmpe: Device to read from 212 * @reg: First register 213 * @length: Number of registers 214 * @values: Buffer to write to 215 */ 216 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) 217 { 218 int ret; 219 220 mutex_lock(&stmpe->lock); 221 ret = __stmpe_block_read(stmpe, reg, length, values); 222 mutex_unlock(&stmpe->lock); 223 224 return ret; 225 } 226 EXPORT_SYMBOL_GPL(stmpe_block_read); 227 228 /** 229 * stmpe_block_write() - write multiple STMPE registers 230 * @stmpe: Device to write to 231 * @reg: First register 232 * @length: Number of registers 233 * @values: Values to write 234 */ 235 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 236 const u8 *values) 237 { 238 int ret; 239 240 mutex_lock(&stmpe->lock); 241 ret = __stmpe_block_write(stmpe, reg, length, values); 242 mutex_unlock(&stmpe->lock); 243 244 return ret; 245 } 246 EXPORT_SYMBOL_GPL(stmpe_block_write); 247 248 /** 249 * stmpe_set_altfunc()- set the alternate function for STMPE pins 250 * @stmpe: Device to configure 251 * @pins: Bitmask of pins to affect 252 * @block: block to enable alternate functions for 253 * 254 * @pins is assumed to have a bit set for each of the bits whose alternate 255 * function is to be changed, numbered according to the GPIOXY numbers. 256 * 257 * If the GPIO module is not enabled, this function automatically enables it in 258 * order to perform the change. 259 */ 260 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block) 261 { 262 struct stmpe_variant_info *variant = stmpe->variant; 263 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB]; 264 int af_bits = variant->af_bits; 265 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8); 266 int mask = (1 << af_bits) - 1; 267 u8 regs[8]; 268 int af, afperreg, ret; 269 270 if (!variant->get_altfunc) 271 return 0; 272 273 afperreg = 8 / af_bits; 274 mutex_lock(&stmpe->lock); 275 276 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 277 if (ret < 0) 278 goto out; 279 280 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs); 281 if (ret < 0) 282 goto out; 283 284 af = variant->get_altfunc(stmpe, block); 285 286 while (pins) { 287 int pin = __ffs(pins); 288 int regoffset = numregs - (pin / afperreg) - 1; 289 int pos = (pin % afperreg) * (8 / afperreg); 290 291 regs[regoffset] &= ~(mask << pos); 292 regs[regoffset] |= af << pos; 293 294 pins &= ~(1 << pin); 295 } 296 297 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs); 298 299 out: 300 mutex_unlock(&stmpe->lock); 301 return ret; 302 } 303 EXPORT_SYMBOL_GPL(stmpe_set_altfunc); 304 305 /* 306 * GPIO (all variants) 307 */ 308 309 static struct resource stmpe_gpio_resources[] = { 310 /* Start and end filled dynamically */ 311 { 312 .flags = IORESOURCE_IRQ, 313 }, 314 }; 315 316 static const struct mfd_cell stmpe_gpio_cell = { 317 .name = "stmpe-gpio", 318 .of_compatible = "st,stmpe-gpio", 319 .resources = stmpe_gpio_resources, 320 .num_resources = ARRAY_SIZE(stmpe_gpio_resources), 321 }; 322 323 static const struct mfd_cell stmpe_gpio_cell_noirq = { 324 .name = "stmpe-gpio", 325 .of_compatible = "st,stmpe-gpio", 326 /* gpio cell resources consist of an irq only so no resources here */ 327 }; 328 329 /* 330 * Keypad (1601, 2401, 2403) 331 */ 332 333 static struct resource stmpe_keypad_resources[] = { 334 /* Start and end filled dynamically */ 335 { 336 .name = "KEYPAD", 337 .flags = IORESOURCE_IRQ, 338 }, 339 { 340 .name = "KEYPAD_OVER", 341 .flags = IORESOURCE_IRQ, 342 }, 343 }; 344 345 static const struct mfd_cell stmpe_keypad_cell = { 346 .name = "stmpe-keypad", 347 .of_compatible = "st,stmpe-keypad", 348 .resources = stmpe_keypad_resources, 349 .num_resources = ARRAY_SIZE(stmpe_keypad_resources), 350 }; 351 352 /* 353 * PWM (1601, 2401, 2403) 354 */ 355 static struct resource stmpe_pwm_resources[] = { 356 /* Start and end filled dynamically */ 357 { 358 .name = "PWM0", 359 .flags = IORESOURCE_IRQ, 360 }, 361 { 362 .name = "PWM1", 363 .flags = IORESOURCE_IRQ, 364 }, 365 { 366 .name = "PWM2", 367 .flags = IORESOURCE_IRQ, 368 }, 369 }; 370 371 static const struct mfd_cell stmpe_pwm_cell = { 372 .name = "stmpe-pwm", 373 .of_compatible = "st,stmpe-pwm", 374 .resources = stmpe_pwm_resources, 375 .num_resources = ARRAY_SIZE(stmpe_pwm_resources), 376 }; 377 378 /* 379 * STMPE801 380 */ 381 static const u8 stmpe801_regs[] = { 382 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID, 383 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL, 384 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA, 385 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN, 386 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN, 387 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR, 388 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN, 389 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA, 390 391 }; 392 393 static struct stmpe_variant_block stmpe801_blocks[] = { 394 { 395 .cell = &stmpe_gpio_cell, 396 .irq = 0, 397 .block = STMPE_BLOCK_GPIO, 398 }, 399 }; 400 401 static struct stmpe_variant_block stmpe801_blocks_noirq[] = { 402 { 403 .cell = &stmpe_gpio_cell_noirq, 404 .block = STMPE_BLOCK_GPIO, 405 }, 406 }; 407 408 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks, 409 bool enable) 410 { 411 if (blocks & STMPE_BLOCK_GPIO) 412 return 0; 413 else 414 return -EINVAL; 415 } 416 417 static struct stmpe_variant_info stmpe801 = { 418 .name = "stmpe801", 419 .id_val = STMPE801_ID, 420 .id_mask = 0xffff, 421 .num_gpios = 8, 422 .regs = stmpe801_regs, 423 .blocks = stmpe801_blocks, 424 .num_blocks = ARRAY_SIZE(stmpe801_blocks), 425 .num_irqs = STMPE801_NR_INTERNAL_IRQS, 426 .enable = stmpe801_enable, 427 }; 428 429 static struct stmpe_variant_info stmpe801_noirq = { 430 .name = "stmpe801", 431 .id_val = STMPE801_ID, 432 .id_mask = 0xffff, 433 .num_gpios = 8, 434 .regs = stmpe801_regs, 435 .blocks = stmpe801_blocks_noirq, 436 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq), 437 .enable = stmpe801_enable, 438 }; 439 440 /* 441 * Touchscreen (STMPE811 or STMPE610) 442 */ 443 444 static struct resource stmpe_ts_resources[] = { 445 /* Start and end filled dynamically */ 446 { 447 .name = "TOUCH_DET", 448 .flags = IORESOURCE_IRQ, 449 }, 450 { 451 .name = "FIFO_TH", 452 .flags = IORESOURCE_IRQ, 453 }, 454 }; 455 456 static const struct mfd_cell stmpe_ts_cell = { 457 .name = "stmpe-ts", 458 .of_compatible = "st,stmpe-ts", 459 .resources = stmpe_ts_resources, 460 .num_resources = ARRAY_SIZE(stmpe_ts_resources), 461 }; 462 463 /* 464 * ADC (STMPE811) 465 */ 466 467 static struct resource stmpe_adc_resources[] = { 468 /* Start and end filled dynamically */ 469 { 470 .name = "STMPE_TEMP_SENS", 471 .flags = IORESOURCE_IRQ, 472 }, 473 { 474 .name = "STMPE_ADC", 475 .flags = IORESOURCE_IRQ, 476 }, 477 }; 478 479 static const struct mfd_cell stmpe_adc_cell = { 480 .name = "stmpe-adc", 481 .of_compatible = "st,stmpe-adc", 482 .resources = stmpe_adc_resources, 483 .num_resources = ARRAY_SIZE(stmpe_adc_resources), 484 }; 485 486 /* 487 * STMPE811 or STMPE610 488 */ 489 490 static const u8 stmpe811_regs[] = { 491 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, 492 [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL, 493 [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2, 494 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, 495 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, 496 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, 497 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA, 498 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN, 499 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN, 500 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR, 501 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE, 502 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE, 503 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, 504 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, 505 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, 506 [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED, 507 }; 508 509 static struct stmpe_variant_block stmpe811_blocks[] = { 510 { 511 .cell = &stmpe_gpio_cell, 512 .irq = STMPE811_IRQ_GPIOC, 513 .block = STMPE_BLOCK_GPIO, 514 }, 515 { 516 .cell = &stmpe_ts_cell, 517 .irq = STMPE811_IRQ_TOUCH_DET, 518 .block = STMPE_BLOCK_TOUCHSCREEN, 519 }, 520 { 521 .cell = &stmpe_adc_cell, 522 .irq = STMPE811_IRQ_TEMP_SENS, 523 .block = STMPE_BLOCK_ADC, 524 }, 525 }; 526 527 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, 528 bool enable) 529 { 530 unsigned int mask = 0; 531 532 if (blocks & STMPE_BLOCK_GPIO) 533 mask |= STMPE811_SYS_CTRL2_GPIO_OFF; 534 535 if (blocks & STMPE_BLOCK_ADC) 536 mask |= STMPE811_SYS_CTRL2_ADC_OFF; 537 538 if (blocks & STMPE_BLOCK_TOUCHSCREEN) 539 mask |= STMPE811_SYS_CTRL2_TSC_OFF; 540 541 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, 542 enable ? 0 : mask); 543 } 544 545 int stmpe811_adc_common_init(struct stmpe *stmpe) 546 { 547 int ret; 548 u8 adc_ctrl1, adc_ctrl1_mask; 549 550 adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) | 551 STMPE_MOD_12B(stmpe->mod_12b) | 552 STMPE_REF_SEL(stmpe->ref_sel); 553 adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) | 554 STMPE_REF_SEL(0xff); 555 556 ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1, 557 adc_ctrl1_mask, adc_ctrl1); 558 if (ret) { 559 dev_err(stmpe->dev, "Could not setup ADC\n"); 560 return ret; 561 } 562 563 ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2, 564 STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq)); 565 if (ret) { 566 dev_err(stmpe->dev, "Could not setup ADC\n"); 567 return ret; 568 } 569 570 return 0; 571 } 572 EXPORT_SYMBOL_GPL(stmpe811_adc_common_init); 573 574 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 575 { 576 /* 0 for touchscreen, 1 for GPIO */ 577 return block != STMPE_BLOCK_TOUCHSCREEN; 578 } 579 580 static struct stmpe_variant_info stmpe811 = { 581 .name = "stmpe811", 582 .id_val = 0x0811, 583 .id_mask = 0xffff, 584 .num_gpios = 8, 585 .af_bits = 1, 586 .regs = stmpe811_regs, 587 .blocks = stmpe811_blocks, 588 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 589 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 590 .enable = stmpe811_enable, 591 .get_altfunc = stmpe811_get_altfunc, 592 }; 593 594 /* Similar to 811, except number of gpios */ 595 static struct stmpe_variant_info stmpe610 = { 596 .name = "stmpe610", 597 .id_val = 0x0811, 598 .id_mask = 0xffff, 599 .num_gpios = 6, 600 .af_bits = 1, 601 .regs = stmpe811_regs, 602 .blocks = stmpe811_blocks, 603 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 604 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 605 .enable = stmpe811_enable, 606 .get_altfunc = stmpe811_get_altfunc, 607 }; 608 609 /* 610 * STMPE1600 611 * Compared to all others STMPE variant, LSB and MSB regs are located in this 612 * order : LSB addr 613 * MSB addr + 1 614 * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers 615 */ 616 617 static const u8 stmpe1600_regs[] = { 618 [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID, 619 [STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL, 620 [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL, 621 [STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB, 622 [STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB, 623 [STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB, 624 [STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB, 625 [STMPE_IDX_GPCR_LSB] = STMPE1600_REG_GPSR_LSB, 626 [STMPE_IDX_GPCR_CSB] = STMPE1600_REG_GPSR_MSB, 627 [STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB, 628 [STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB, 629 [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB, 630 [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB, 631 [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB, 632 }; 633 634 static struct stmpe_variant_block stmpe1600_blocks[] = { 635 { 636 .cell = &stmpe_gpio_cell, 637 .irq = 0, 638 .block = STMPE_BLOCK_GPIO, 639 }, 640 }; 641 642 static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks, 643 bool enable) 644 { 645 if (blocks & STMPE_BLOCK_GPIO) 646 return 0; 647 else 648 return -EINVAL; 649 } 650 651 static struct stmpe_variant_info stmpe1600 = { 652 .name = "stmpe1600", 653 .id_val = STMPE1600_ID, 654 .id_mask = 0xffff, 655 .num_gpios = 16, 656 .af_bits = 0, 657 .regs = stmpe1600_regs, 658 .blocks = stmpe1600_blocks, 659 .num_blocks = ARRAY_SIZE(stmpe1600_blocks), 660 .num_irqs = STMPE1600_NR_INTERNAL_IRQS, 661 .enable = stmpe1600_enable, 662 }; 663 664 /* 665 * STMPE1601 666 */ 667 668 static const u8 stmpe1601_regs[] = { 669 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, 670 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, 671 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, 672 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, 673 [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB, 674 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, 675 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, 676 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, 677 [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB, 678 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, 679 [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB, 680 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, 681 [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB, 682 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, 683 [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB, 684 [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB, 685 [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB, 686 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, 687 [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB, 688 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, 689 [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB, 690 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB, 691 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, 692 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, 693 [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB, 694 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, 695 }; 696 697 static struct stmpe_variant_block stmpe1601_blocks[] = { 698 { 699 .cell = &stmpe_gpio_cell, 700 .irq = STMPE1601_IRQ_GPIOC, 701 .block = STMPE_BLOCK_GPIO, 702 }, 703 { 704 .cell = &stmpe_keypad_cell, 705 .irq = STMPE1601_IRQ_KEYPAD, 706 .block = STMPE_BLOCK_KEYPAD, 707 }, 708 { 709 .cell = &stmpe_pwm_cell, 710 .irq = STMPE1601_IRQ_PWM0, 711 .block = STMPE_BLOCK_PWM, 712 }, 713 }; 714 715 /* supported autosleep timeout delay (in msecs) */ 716 static const int stmpe_autosleep_delay[] = { 717 4, 16, 32, 64, 128, 256, 512, 1024, 718 }; 719 720 static int stmpe_round_timeout(int timeout) 721 { 722 int i; 723 724 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) { 725 if (stmpe_autosleep_delay[i] >= timeout) 726 return i; 727 } 728 729 /* 730 * requests for delays longer than supported should not return the 731 * longest supported delay 732 */ 733 return -EINVAL; 734 } 735 736 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout) 737 { 738 int ret; 739 740 if (!stmpe->variant->enable_autosleep) 741 return -ENOSYS; 742 743 mutex_lock(&stmpe->lock); 744 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout); 745 mutex_unlock(&stmpe->lock); 746 747 return ret; 748 } 749 750 /* 751 * Both stmpe 1601/2403 support same layout for autosleep 752 */ 753 static int stmpe1601_autosleep(struct stmpe *stmpe, 754 int autosleep_timeout) 755 { 756 int ret, timeout; 757 758 /* choose the best available timeout */ 759 timeout = stmpe_round_timeout(autosleep_timeout); 760 if (timeout < 0) { 761 dev_err(stmpe->dev, "invalid timeout\n"); 762 return timeout; 763 } 764 765 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 766 STMPE1601_AUTOSLEEP_TIMEOUT_MASK, 767 timeout); 768 if (ret < 0) 769 return ret; 770 771 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 772 STPME1601_AUTOSLEEP_ENABLE, 773 STPME1601_AUTOSLEEP_ENABLE); 774 } 775 776 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks, 777 bool enable) 778 { 779 unsigned int mask = 0; 780 781 if (blocks & STMPE_BLOCK_GPIO) 782 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; 783 else 784 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO; 785 786 if (blocks & STMPE_BLOCK_KEYPAD) 787 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; 788 else 789 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC; 790 791 if (blocks & STMPE_BLOCK_PWM) 792 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM; 793 else 794 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; 795 796 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 797 enable ? mask : 0); 798 } 799 800 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 801 { 802 switch (block) { 803 case STMPE_BLOCK_PWM: 804 return 2; 805 806 case STMPE_BLOCK_KEYPAD: 807 return 1; 808 809 case STMPE_BLOCK_GPIO: 810 default: 811 return 0; 812 } 813 } 814 815 static struct stmpe_variant_info stmpe1601 = { 816 .name = "stmpe1601", 817 .id_val = 0x0210, 818 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */ 819 .num_gpios = 16, 820 .af_bits = 2, 821 .regs = stmpe1601_regs, 822 .blocks = stmpe1601_blocks, 823 .num_blocks = ARRAY_SIZE(stmpe1601_blocks), 824 .num_irqs = STMPE1601_NR_INTERNAL_IRQS, 825 .enable = stmpe1601_enable, 826 .get_altfunc = stmpe1601_get_altfunc, 827 .enable_autosleep = stmpe1601_autosleep, 828 }; 829 830 /* 831 * STMPE1801 832 */ 833 static const u8 stmpe1801_regs[] = { 834 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID, 835 [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL, 836 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW, 837 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, 838 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, 839 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW, 840 [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID, 841 [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH, 842 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW, 843 [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID, 844 [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH, 845 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW, 846 [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID, 847 [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH, 848 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW, 849 [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID, 850 [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH, 851 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW, 852 [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID, 853 [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH, 854 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW, 855 [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID, 856 [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH, 857 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW, 858 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW, 859 [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID, 860 [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH, 861 [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH, 862 }; 863 864 static struct stmpe_variant_block stmpe1801_blocks[] = { 865 { 866 .cell = &stmpe_gpio_cell, 867 .irq = STMPE1801_IRQ_GPIOC, 868 .block = STMPE_BLOCK_GPIO, 869 }, 870 { 871 .cell = &stmpe_keypad_cell, 872 .irq = STMPE1801_IRQ_KEYPAD, 873 .block = STMPE_BLOCK_KEYPAD, 874 }, 875 }; 876 877 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks, 878 bool enable) 879 { 880 unsigned int mask = 0; 881 if (blocks & STMPE_BLOCK_GPIO) 882 mask |= STMPE1801_MSK_INT_EN_GPIO; 883 884 if (blocks & STMPE_BLOCK_KEYPAD) 885 mask |= STMPE1801_MSK_INT_EN_KPC; 886 887 return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask, 888 enable ? mask : 0); 889 } 890 891 static int stmpe_reset(struct stmpe *stmpe) 892 { 893 u16 id_val = stmpe->variant->id_val; 894 unsigned long timeout; 895 int ret = 0; 896 u8 reset_bit; 897 898 if (id_val == STMPE811_ID) 899 /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */ 900 reset_bit = STMPE811_SYS_CTRL_RESET; 901 else 902 /* all other STMPE variant use bit 7 of SYS_CTRL register */ 903 reset_bit = STMPE_SYS_CTRL_RESET; 904 905 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], 906 reset_bit, reset_bit); 907 if (ret < 0) 908 return ret; 909 910 msleep(10); 911 912 timeout = jiffies + msecs_to_jiffies(100); 913 while (time_before(jiffies, timeout)) { 914 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); 915 if (ret < 0) 916 return ret; 917 if (!(ret & reset_bit)) 918 return 0; 919 usleep_range(100, 200); 920 } 921 return -EIO; 922 } 923 924 static struct stmpe_variant_info stmpe1801 = { 925 .name = "stmpe1801", 926 .id_val = STMPE1801_ID, 927 .id_mask = 0xfff0, 928 .num_gpios = 18, 929 .af_bits = 0, 930 .regs = stmpe1801_regs, 931 .blocks = stmpe1801_blocks, 932 .num_blocks = ARRAY_SIZE(stmpe1801_blocks), 933 .num_irqs = STMPE1801_NR_INTERNAL_IRQS, 934 .enable = stmpe1801_enable, 935 /* stmpe1801 do not have any gpio alternate function */ 936 .get_altfunc = NULL, 937 }; 938 939 /* 940 * STMPE24XX 941 */ 942 943 static const u8 stmpe24xx_regs[] = { 944 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, 945 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, 946 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, 947 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, 948 [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB, 949 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, 950 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, 951 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, 952 [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB, 953 [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB, 954 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, 955 [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB, 956 [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB, 957 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, 958 [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB, 959 [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB, 960 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, 961 [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB, 962 [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB, 963 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, 964 [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB, 965 [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB, 966 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, 967 [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB, 968 [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB, 969 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB, 970 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB, 971 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, 972 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, 973 [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB, 974 [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB, 975 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, 976 [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB, 977 [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB, 978 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, 979 }; 980 981 static struct stmpe_variant_block stmpe24xx_blocks[] = { 982 { 983 .cell = &stmpe_gpio_cell, 984 .irq = STMPE24XX_IRQ_GPIOC, 985 .block = STMPE_BLOCK_GPIO, 986 }, 987 { 988 .cell = &stmpe_keypad_cell, 989 .irq = STMPE24XX_IRQ_KEYPAD, 990 .block = STMPE_BLOCK_KEYPAD, 991 }, 992 { 993 .cell = &stmpe_pwm_cell, 994 .irq = STMPE24XX_IRQ_PWM0, 995 .block = STMPE_BLOCK_PWM, 996 }, 997 }; 998 999 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks, 1000 bool enable) 1001 { 1002 unsigned int mask = 0; 1003 1004 if (blocks & STMPE_BLOCK_GPIO) 1005 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO; 1006 1007 if (blocks & STMPE_BLOCK_KEYPAD) 1008 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; 1009 1010 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 1011 enable ? mask : 0); 1012 } 1013 1014 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 1015 { 1016 switch (block) { 1017 case STMPE_BLOCK_ROTATOR: 1018 return 2; 1019 1020 case STMPE_BLOCK_KEYPAD: 1021 case STMPE_BLOCK_PWM: 1022 return 1; 1023 1024 case STMPE_BLOCK_GPIO: 1025 default: 1026 return 0; 1027 } 1028 } 1029 1030 static struct stmpe_variant_info stmpe2401 = { 1031 .name = "stmpe2401", 1032 .id_val = 0x0101, 1033 .id_mask = 0xffff, 1034 .num_gpios = 24, 1035 .af_bits = 2, 1036 .regs = stmpe24xx_regs, 1037 .blocks = stmpe24xx_blocks, 1038 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 1039 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 1040 .enable = stmpe24xx_enable, 1041 .get_altfunc = stmpe24xx_get_altfunc, 1042 }; 1043 1044 static struct stmpe_variant_info stmpe2403 = { 1045 .name = "stmpe2403", 1046 .id_val = 0x0120, 1047 .id_mask = 0xffff, 1048 .num_gpios = 24, 1049 .af_bits = 2, 1050 .regs = stmpe24xx_regs, 1051 .blocks = stmpe24xx_blocks, 1052 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 1053 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 1054 .enable = stmpe24xx_enable, 1055 .get_altfunc = stmpe24xx_get_altfunc, 1056 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */ 1057 }; 1058 1059 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = { 1060 [STMPE610] = &stmpe610, 1061 [STMPE801] = &stmpe801, 1062 [STMPE811] = &stmpe811, 1063 [STMPE1600] = &stmpe1600, 1064 [STMPE1601] = &stmpe1601, 1065 [STMPE1801] = &stmpe1801, 1066 [STMPE2401] = &stmpe2401, 1067 [STMPE2403] = &stmpe2403, 1068 }; 1069 1070 /* 1071 * These devices can be connected in a 'no-irq' configuration - the irq pin 1072 * is not used and the device cannot interrupt the CPU. Here we only list 1073 * devices which support this configuration - the driver will fail probing 1074 * for any devices not listed here which are configured in this way. 1075 */ 1076 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = { 1077 [STMPE801] = &stmpe801_noirq, 1078 }; 1079 1080 static irqreturn_t stmpe_irq(int irq, void *data) 1081 { 1082 struct stmpe *stmpe = data; 1083 struct stmpe_variant_info *variant = stmpe->variant; 1084 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1085 u8 israddr; 1086 u8 isr[3]; 1087 int ret; 1088 int i; 1089 1090 if (variant->id_val == STMPE801_ID || 1091 variant->id_val == STMPE1600_ID) { 1092 int base = irq_find_mapping(stmpe->domain, 0); 1093 1094 handle_nested_irq(base); 1095 return IRQ_HANDLED; 1096 } 1097 1098 if (variant->id_val == STMPE1801_ID) 1099 israddr = stmpe->regs[STMPE_IDX_ISR_LSB]; 1100 else 1101 israddr = stmpe->regs[STMPE_IDX_ISR_MSB]; 1102 1103 ret = stmpe_block_read(stmpe, israddr, num, isr); 1104 if (ret < 0) 1105 return IRQ_NONE; 1106 1107 for (i = 0; i < num; i++) { 1108 int bank = num - i - 1; 1109 u8 status = isr[i]; 1110 u8 clear; 1111 1112 status &= stmpe->ier[bank]; 1113 if (!status) 1114 continue; 1115 1116 clear = status; 1117 while (status) { 1118 int bit = __ffs(status); 1119 int line = bank * 8 + bit; 1120 int nestedirq = irq_find_mapping(stmpe->domain, line); 1121 1122 handle_nested_irq(nestedirq); 1123 status &= ~(1 << bit); 1124 } 1125 1126 stmpe_reg_write(stmpe, israddr + i, clear); 1127 } 1128 1129 return IRQ_HANDLED; 1130 } 1131 1132 static void stmpe_irq_lock(struct irq_data *data) 1133 { 1134 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1135 1136 mutex_lock(&stmpe->irq_lock); 1137 } 1138 1139 static void stmpe_irq_sync_unlock(struct irq_data *data) 1140 { 1141 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1142 struct stmpe_variant_info *variant = stmpe->variant; 1143 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1144 int i; 1145 1146 for (i = 0; i < num; i++) { 1147 u8 new = stmpe->ier[i]; 1148 u8 old = stmpe->oldier[i]; 1149 1150 if (new == old) 1151 continue; 1152 1153 stmpe->oldier[i] = new; 1154 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new); 1155 } 1156 1157 mutex_unlock(&stmpe->irq_lock); 1158 } 1159 1160 static void stmpe_irq_mask(struct irq_data *data) 1161 { 1162 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1163 int offset = data->hwirq; 1164 int regoffset = offset / 8; 1165 int mask = 1 << (offset % 8); 1166 1167 stmpe->ier[regoffset] &= ~mask; 1168 } 1169 1170 static void stmpe_irq_unmask(struct irq_data *data) 1171 { 1172 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1173 int offset = data->hwirq; 1174 int regoffset = offset / 8; 1175 int mask = 1 << (offset % 8); 1176 1177 stmpe->ier[regoffset] |= mask; 1178 } 1179 1180 static struct irq_chip stmpe_irq_chip = { 1181 .name = "stmpe", 1182 .irq_bus_lock = stmpe_irq_lock, 1183 .irq_bus_sync_unlock = stmpe_irq_sync_unlock, 1184 .irq_mask = stmpe_irq_mask, 1185 .irq_unmask = stmpe_irq_unmask, 1186 }; 1187 1188 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq, 1189 irq_hw_number_t hwirq) 1190 { 1191 struct stmpe *stmpe = d->host_data; 1192 struct irq_chip *chip = NULL; 1193 1194 if (stmpe->variant->id_val != STMPE801_ID) 1195 chip = &stmpe_irq_chip; 1196 1197 irq_set_chip_data(virq, stmpe); 1198 irq_set_chip_and_handler(virq, chip, handle_edge_irq); 1199 irq_set_nested_thread(virq, 1); 1200 irq_set_noprobe(virq); 1201 1202 return 0; 1203 } 1204 1205 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq) 1206 { 1207 irq_set_chip_and_handler(virq, NULL, NULL); 1208 irq_set_chip_data(virq, NULL); 1209 } 1210 1211 static const struct irq_domain_ops stmpe_irq_ops = { 1212 .map = stmpe_irq_map, 1213 .unmap = stmpe_irq_unmap, 1214 .xlate = irq_domain_xlate_twocell, 1215 }; 1216 1217 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np) 1218 { 1219 int base = 0; 1220 int num_irqs = stmpe->variant->num_irqs; 1221 1222 stmpe->domain = irq_domain_add_simple(np, num_irqs, base, 1223 &stmpe_irq_ops, stmpe); 1224 if (!stmpe->domain) { 1225 dev_err(stmpe->dev, "Failed to create irqdomain\n"); 1226 return -ENOSYS; 1227 } 1228 1229 return 0; 1230 } 1231 1232 static int stmpe_chip_init(struct stmpe *stmpe) 1233 { 1234 unsigned int irq_trigger = stmpe->pdata->irq_trigger; 1235 int autosleep_timeout = stmpe->pdata->autosleep_timeout; 1236 struct stmpe_variant_info *variant = stmpe->variant; 1237 u8 icr = 0; 1238 unsigned int id; 1239 u8 data[2]; 1240 int ret; 1241 1242 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID], 1243 ARRAY_SIZE(data), data); 1244 if (ret < 0) 1245 return ret; 1246 1247 id = (data[0] << 8) | data[1]; 1248 if ((id & variant->id_mask) != variant->id_val) { 1249 dev_err(stmpe->dev, "unknown chip id: %#x\n", id); 1250 return -EINVAL; 1251 } 1252 1253 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id); 1254 1255 /* Disable all modules -- subdrivers should enable what they need. */ 1256 ret = stmpe_disable(stmpe, ~0); 1257 if (ret) 1258 return ret; 1259 1260 ret = stmpe_reset(stmpe); 1261 if (ret < 0) 1262 return ret; 1263 1264 if (stmpe->irq >= 0) { 1265 if (id == STMPE801_ID || id == STMPE1600_ID) 1266 icr = STMPE_SYS_CTRL_INT_EN; 1267 else 1268 icr = STMPE_ICR_LSB_GIM; 1269 1270 /* STMPE801 and STMPE1600 don't support Edge interrupts */ 1271 if (id != STMPE801_ID && id != STMPE1600_ID) { 1272 if (irq_trigger == IRQF_TRIGGER_FALLING || 1273 irq_trigger == IRQF_TRIGGER_RISING) 1274 icr |= STMPE_ICR_LSB_EDGE; 1275 } 1276 1277 if (irq_trigger == IRQF_TRIGGER_RISING || 1278 irq_trigger == IRQF_TRIGGER_HIGH) { 1279 if (id == STMPE801_ID || id == STMPE1600_ID) 1280 icr |= STMPE_SYS_CTRL_INT_HI; 1281 else 1282 icr |= STMPE_ICR_LSB_HIGH; 1283 } 1284 } 1285 1286 if (stmpe->pdata->autosleep) { 1287 ret = stmpe_autosleep(stmpe, autosleep_timeout); 1288 if (ret) 1289 return ret; 1290 } 1291 1292 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr); 1293 } 1294 1295 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell) 1296 { 1297 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1, 1298 NULL, 0, stmpe->domain); 1299 } 1300 1301 static int stmpe_devices_init(struct stmpe *stmpe) 1302 { 1303 struct stmpe_variant_info *variant = stmpe->variant; 1304 unsigned int platform_blocks = stmpe->pdata->blocks; 1305 int ret = -EINVAL; 1306 int i, j; 1307 1308 for (i = 0; i < variant->num_blocks; i++) { 1309 struct stmpe_variant_block *block = &variant->blocks[i]; 1310 1311 if (!(platform_blocks & block->block)) 1312 continue; 1313 1314 for (j = 0; j < block->cell->num_resources; j++) { 1315 struct resource *res = 1316 (struct resource *) &block->cell->resources[j]; 1317 1318 /* Dynamically fill in a variant's IRQ. */ 1319 if (res->flags & IORESOURCE_IRQ) 1320 res->start = res->end = block->irq + j; 1321 } 1322 1323 platform_blocks &= ~block->block; 1324 ret = stmpe_add_device(stmpe, block->cell); 1325 if (ret) 1326 return ret; 1327 } 1328 1329 if (platform_blocks) 1330 dev_warn(stmpe->dev, 1331 "platform wants blocks (%#x) not present on variant", 1332 platform_blocks); 1333 1334 return ret; 1335 } 1336 1337 static void stmpe_of_probe(struct stmpe_platform_data *pdata, 1338 struct device_node *np) 1339 { 1340 struct device_node *child; 1341 1342 pdata->id = of_alias_get_id(np, "stmpe-i2c"); 1343 if (pdata->id < 0) 1344 pdata->id = -1; 1345 1346 of_property_read_u32(np, "st,autosleep-timeout", 1347 &pdata->autosleep_timeout); 1348 1349 pdata->autosleep = (pdata->autosleep_timeout) ? true : false; 1350 1351 for_each_available_child_of_node(np, child) { 1352 if (of_device_is_compatible(child, stmpe_gpio_cell.of_compatible)) 1353 pdata->blocks |= STMPE_BLOCK_GPIO; 1354 else if (of_device_is_compatible(child, stmpe_keypad_cell.of_compatible)) 1355 pdata->blocks |= STMPE_BLOCK_KEYPAD; 1356 else if (of_device_is_compatible(child, stmpe_ts_cell.of_compatible)) 1357 pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN; 1358 else if (of_device_is_compatible(child, stmpe_adc_cell.of_compatible)) 1359 pdata->blocks |= STMPE_BLOCK_ADC; 1360 else if (of_device_is_compatible(child, stmpe_pwm_cell.of_compatible)) 1361 pdata->blocks |= STMPE_BLOCK_PWM; 1362 } 1363 } 1364 1365 /* Called from client specific probe routines */ 1366 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) 1367 { 1368 struct stmpe_platform_data *pdata; 1369 struct device_node *np = ci->dev->of_node; 1370 struct stmpe *stmpe; 1371 struct gpio_desc *irq_gpio; 1372 int ret; 1373 u32 val; 1374 1375 pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL); 1376 if (!pdata) 1377 return -ENOMEM; 1378 1379 stmpe_of_probe(pdata, np); 1380 1381 if (of_find_property(np, "interrupts", NULL) == NULL) 1382 ci->irq = -1; 1383 1384 stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL); 1385 if (!stmpe) 1386 return -ENOMEM; 1387 1388 mutex_init(&stmpe->irq_lock); 1389 mutex_init(&stmpe->lock); 1390 1391 if (!of_property_read_u32(np, "st,sample-time", &val)) 1392 stmpe->sample_time = val; 1393 if (!of_property_read_u32(np, "st,mod-12b", &val)) 1394 stmpe->mod_12b = val; 1395 if (!of_property_read_u32(np, "st,ref-sel", &val)) 1396 stmpe->ref_sel = val; 1397 if (!of_property_read_u32(np, "st,adc-freq", &val)) 1398 stmpe->adc_freq = val; 1399 1400 stmpe->dev = ci->dev; 1401 stmpe->client = ci->client; 1402 stmpe->pdata = pdata; 1403 stmpe->ci = ci; 1404 stmpe->partnum = partnum; 1405 stmpe->variant = stmpe_variant_info[partnum]; 1406 stmpe->regs = stmpe->variant->regs; 1407 stmpe->num_gpios = stmpe->variant->num_gpios; 1408 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc"); 1409 if (!IS_ERR(stmpe->vcc)) { 1410 ret = regulator_enable(stmpe->vcc); 1411 if (ret) 1412 dev_warn(ci->dev, "failed to enable VCC supply\n"); 1413 } 1414 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio"); 1415 if (!IS_ERR(stmpe->vio)) { 1416 ret = regulator_enable(stmpe->vio); 1417 if (ret) 1418 dev_warn(ci->dev, "failed to enable VIO supply\n"); 1419 } 1420 dev_set_drvdata(stmpe->dev, stmpe); 1421 1422 if (ci->init) 1423 ci->init(stmpe); 1424 1425 irq_gpio = devm_gpiod_get_optional(ci->dev, "irq", GPIOD_ASIS); 1426 ret = PTR_ERR_OR_ZERO(irq_gpio); 1427 if (ret) { 1428 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", ret); 1429 return ret; 1430 } 1431 1432 if (irq_gpio) { 1433 stmpe->irq = gpiod_to_irq(irq_gpio); 1434 pdata->irq_trigger = gpiod_is_active_low(irq_gpio) ? 1435 IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH; 1436 } else { 1437 stmpe->irq = ci->irq; 1438 pdata->irq_trigger = IRQF_TRIGGER_NONE; 1439 } 1440 1441 if (stmpe->irq < 0) { 1442 /* use alternate variant info for no-irq mode, if supported */ 1443 dev_info(stmpe->dev, 1444 "%s configured in no-irq mode by platform data\n", 1445 stmpe->variant->name); 1446 if (!stmpe_noirq_variant_info[stmpe->partnum]) { 1447 dev_err(stmpe->dev, 1448 "%s does not support no-irq mode!\n", 1449 stmpe->variant->name); 1450 return -ENODEV; 1451 } 1452 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum]; 1453 } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) { 1454 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq); 1455 } 1456 1457 ret = stmpe_chip_init(stmpe); 1458 if (ret) 1459 return ret; 1460 1461 if (stmpe->irq >= 0) { 1462 ret = stmpe_irq_init(stmpe, np); 1463 if (ret) 1464 return ret; 1465 1466 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL, 1467 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT, 1468 "stmpe", stmpe); 1469 if (ret) { 1470 dev_err(stmpe->dev, "failed to request IRQ: %d\n", 1471 ret); 1472 return ret; 1473 } 1474 } 1475 1476 ret = stmpe_devices_init(stmpe); 1477 if (!ret) 1478 return 0; 1479 1480 dev_err(stmpe->dev, "failed to add children\n"); 1481 mfd_remove_devices(stmpe->dev); 1482 1483 return ret; 1484 } 1485 1486 void stmpe_remove(struct stmpe *stmpe) 1487 { 1488 if (!IS_ERR(stmpe->vio)) 1489 regulator_disable(stmpe->vio); 1490 if (!IS_ERR(stmpe->vcc)) 1491 regulator_disable(stmpe->vcc); 1492 1493 __stmpe_disable(stmpe, STMPE_BLOCK_ADC); 1494 1495 mfd_remove_devices(stmpe->dev); 1496 } 1497 1498 #ifdef CONFIG_PM 1499 static int stmpe_suspend(struct device *dev) 1500 { 1501 struct stmpe *stmpe = dev_get_drvdata(dev); 1502 1503 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1504 enable_irq_wake(stmpe->irq); 1505 1506 return 0; 1507 } 1508 1509 static int stmpe_resume(struct device *dev) 1510 { 1511 struct stmpe *stmpe = dev_get_drvdata(dev); 1512 1513 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1514 disable_irq_wake(stmpe->irq); 1515 1516 return 0; 1517 } 1518 1519 const struct dev_pm_ops stmpe_dev_pm_ops = { 1520 .suspend = stmpe_suspend, 1521 .resume = stmpe_resume, 1522 }; 1523 #endif 1524