1 /* 2 * ST Microelectronics MFD: stmpe's driver 3 * 4 * Copyright (C) ST-Ericsson SA 2010 5 * 6 * License Terms: GNU General Public License, version 2 7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 8 */ 9 10 #include <linux/err.h> 11 #include <linux/gpio.h> 12 #include <linux/export.h> 13 #include <linux/kernel.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pm.h> 20 #include <linux/slab.h> 21 #include <linux/mfd/core.h> 22 #include <linux/delay.h> 23 #include <linux/regulator/consumer.h> 24 #include "stmpe.h" 25 26 /** 27 * struct stmpe_platform_data - STMPE platform data 28 * @id: device id to distinguish between multiple STMPEs on the same board 29 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 30 * @irq_trigger: IRQ trigger to use for the interrupt to the host 31 * @autosleep: bool to enable/disable stmpe autosleep 32 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 33 * @irq_over_gpio: true if gpio is used to get irq 34 * @irq_gpio: gpio number over which irq will be requested (significant only if 35 * irq_over_gpio is true) 36 */ 37 struct stmpe_platform_data { 38 int id; 39 unsigned int blocks; 40 unsigned int irq_trigger; 41 bool autosleep; 42 bool irq_over_gpio; 43 int irq_gpio; 44 int autosleep_timeout; 45 }; 46 47 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 48 { 49 return stmpe->variant->enable(stmpe, blocks, true); 50 } 51 52 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 53 { 54 return stmpe->variant->enable(stmpe, blocks, false); 55 } 56 57 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg) 58 { 59 int ret; 60 61 ret = stmpe->ci->read_byte(stmpe, reg); 62 if (ret < 0) 63 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); 64 65 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); 66 67 return ret; 68 } 69 70 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 71 { 72 int ret; 73 74 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); 75 76 ret = stmpe->ci->write_byte(stmpe, reg, val); 77 if (ret < 0) 78 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret); 79 80 return ret; 81 } 82 83 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 84 { 85 int ret; 86 87 ret = __stmpe_reg_read(stmpe, reg); 88 if (ret < 0) 89 return ret; 90 91 ret &= ~mask; 92 ret |= val; 93 94 return __stmpe_reg_write(stmpe, reg, ret); 95 } 96 97 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, 98 u8 *values) 99 { 100 int ret; 101 102 ret = stmpe->ci->read_block(stmpe, reg, length, values); 103 if (ret < 0) 104 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret); 105 106 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret); 107 stmpe_dump_bytes("stmpe rd: ", values, length); 108 109 return ret; 110 } 111 112 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 113 const u8 *values) 114 { 115 int ret; 116 117 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length); 118 stmpe_dump_bytes("stmpe wr: ", values, length); 119 120 ret = stmpe->ci->write_block(stmpe, reg, length, values); 121 if (ret < 0) 122 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret); 123 124 return ret; 125 } 126 127 /** 128 * stmpe_enable - enable blocks on an STMPE device 129 * @stmpe: Device to work on 130 * @blocks: Mask of blocks (enum stmpe_block values) to enable 131 */ 132 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 133 { 134 int ret; 135 136 mutex_lock(&stmpe->lock); 137 ret = __stmpe_enable(stmpe, blocks); 138 mutex_unlock(&stmpe->lock); 139 140 return ret; 141 } 142 EXPORT_SYMBOL_GPL(stmpe_enable); 143 144 /** 145 * stmpe_disable - disable blocks on an STMPE device 146 * @stmpe: Device to work on 147 * @blocks: Mask of blocks (enum stmpe_block values) to enable 148 */ 149 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 150 { 151 int ret; 152 153 mutex_lock(&stmpe->lock); 154 ret = __stmpe_disable(stmpe, blocks); 155 mutex_unlock(&stmpe->lock); 156 157 return ret; 158 } 159 EXPORT_SYMBOL_GPL(stmpe_disable); 160 161 /** 162 * stmpe_reg_read() - read a single STMPE register 163 * @stmpe: Device to read from 164 * @reg: Register to read 165 */ 166 int stmpe_reg_read(struct stmpe *stmpe, u8 reg) 167 { 168 int ret; 169 170 mutex_lock(&stmpe->lock); 171 ret = __stmpe_reg_read(stmpe, reg); 172 mutex_unlock(&stmpe->lock); 173 174 return ret; 175 } 176 EXPORT_SYMBOL_GPL(stmpe_reg_read); 177 178 /** 179 * stmpe_reg_write() - write a single STMPE register 180 * @stmpe: Device to write to 181 * @reg: Register to write 182 * @val: Value to write 183 */ 184 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 185 { 186 int ret; 187 188 mutex_lock(&stmpe->lock); 189 ret = __stmpe_reg_write(stmpe, reg, val); 190 mutex_unlock(&stmpe->lock); 191 192 return ret; 193 } 194 EXPORT_SYMBOL_GPL(stmpe_reg_write); 195 196 /** 197 * stmpe_set_bits() - set the value of a bitfield in a STMPE register 198 * @stmpe: Device to write to 199 * @reg: Register to write 200 * @mask: Mask of bits to set 201 * @val: Value to set 202 */ 203 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 204 { 205 int ret; 206 207 mutex_lock(&stmpe->lock); 208 ret = __stmpe_set_bits(stmpe, reg, mask, val); 209 mutex_unlock(&stmpe->lock); 210 211 return ret; 212 } 213 EXPORT_SYMBOL_GPL(stmpe_set_bits); 214 215 /** 216 * stmpe_block_read() - read multiple STMPE registers 217 * @stmpe: Device to read from 218 * @reg: First register 219 * @length: Number of registers 220 * @values: Buffer to write to 221 */ 222 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) 223 { 224 int ret; 225 226 mutex_lock(&stmpe->lock); 227 ret = __stmpe_block_read(stmpe, reg, length, values); 228 mutex_unlock(&stmpe->lock); 229 230 return ret; 231 } 232 EXPORT_SYMBOL_GPL(stmpe_block_read); 233 234 /** 235 * stmpe_block_write() - write multiple STMPE registers 236 * @stmpe: Device to write to 237 * @reg: First register 238 * @length: Number of registers 239 * @values: Values to write 240 */ 241 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 242 const u8 *values) 243 { 244 int ret; 245 246 mutex_lock(&stmpe->lock); 247 ret = __stmpe_block_write(stmpe, reg, length, values); 248 mutex_unlock(&stmpe->lock); 249 250 return ret; 251 } 252 EXPORT_SYMBOL_GPL(stmpe_block_write); 253 254 /** 255 * stmpe_set_altfunc()- set the alternate function for STMPE pins 256 * @stmpe: Device to configure 257 * @pins: Bitmask of pins to affect 258 * @block: block to enable alternate functions for 259 * 260 * @pins is assumed to have a bit set for each of the bits whose alternate 261 * function is to be changed, numbered according to the GPIOXY numbers. 262 * 263 * If the GPIO module is not enabled, this function automatically enables it in 264 * order to perform the change. 265 */ 266 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block) 267 { 268 struct stmpe_variant_info *variant = stmpe->variant; 269 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB]; 270 int af_bits = variant->af_bits; 271 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8); 272 int mask = (1 << af_bits) - 1; 273 u8 regs[8]; 274 int af, afperreg, ret; 275 276 if (!variant->get_altfunc) 277 return 0; 278 279 afperreg = 8 / af_bits; 280 mutex_lock(&stmpe->lock); 281 282 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 283 if (ret < 0) 284 goto out; 285 286 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs); 287 if (ret < 0) 288 goto out; 289 290 af = variant->get_altfunc(stmpe, block); 291 292 while (pins) { 293 int pin = __ffs(pins); 294 int regoffset = numregs - (pin / afperreg) - 1; 295 int pos = (pin % afperreg) * (8 / afperreg); 296 297 regs[regoffset] &= ~(mask << pos); 298 regs[regoffset] |= af << pos; 299 300 pins &= ~(1 << pin); 301 } 302 303 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs); 304 305 out: 306 mutex_unlock(&stmpe->lock); 307 return ret; 308 } 309 EXPORT_SYMBOL_GPL(stmpe_set_altfunc); 310 311 /* 312 * GPIO (all variants) 313 */ 314 315 static struct resource stmpe_gpio_resources[] = { 316 /* Start and end filled dynamically */ 317 { 318 .flags = IORESOURCE_IRQ, 319 }, 320 }; 321 322 static const struct mfd_cell stmpe_gpio_cell = { 323 .name = "stmpe-gpio", 324 .of_compatible = "st,stmpe-gpio", 325 .resources = stmpe_gpio_resources, 326 .num_resources = ARRAY_SIZE(stmpe_gpio_resources), 327 }; 328 329 static const struct mfd_cell stmpe_gpio_cell_noirq = { 330 .name = "stmpe-gpio", 331 .of_compatible = "st,stmpe-gpio", 332 /* gpio cell resources consist of an irq only so no resources here */ 333 }; 334 335 /* 336 * Keypad (1601, 2401, 2403) 337 */ 338 339 static struct resource stmpe_keypad_resources[] = { 340 { 341 .name = "KEYPAD", 342 .flags = IORESOURCE_IRQ, 343 }, 344 { 345 .name = "KEYPAD_OVER", 346 .flags = IORESOURCE_IRQ, 347 }, 348 }; 349 350 static const struct mfd_cell stmpe_keypad_cell = { 351 .name = "stmpe-keypad", 352 .of_compatible = "st,stmpe-keypad", 353 .resources = stmpe_keypad_resources, 354 .num_resources = ARRAY_SIZE(stmpe_keypad_resources), 355 }; 356 357 /* 358 * PWM (1601, 2401, 2403) 359 */ 360 static struct resource stmpe_pwm_resources[] = { 361 { 362 .name = "PWM0", 363 .flags = IORESOURCE_IRQ, 364 }, 365 { 366 .name = "PWM1", 367 .flags = IORESOURCE_IRQ, 368 }, 369 { 370 .name = "PWM2", 371 .flags = IORESOURCE_IRQ, 372 }, 373 }; 374 375 static const struct mfd_cell stmpe_pwm_cell = { 376 .name = "stmpe-pwm", 377 .of_compatible = "st,stmpe-pwm", 378 .resources = stmpe_pwm_resources, 379 .num_resources = ARRAY_SIZE(stmpe_pwm_resources), 380 }; 381 382 /* 383 * STMPE801 384 */ 385 static const u8 stmpe801_regs[] = { 386 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID, 387 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL, 388 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA, 389 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN, 390 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN, 391 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR, 392 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN, 393 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA, 394 395 }; 396 397 static struct stmpe_variant_block stmpe801_blocks[] = { 398 { 399 .cell = &stmpe_gpio_cell, 400 .irq = 0, 401 .block = STMPE_BLOCK_GPIO, 402 }, 403 }; 404 405 static struct stmpe_variant_block stmpe801_blocks_noirq[] = { 406 { 407 .cell = &stmpe_gpio_cell_noirq, 408 .block = STMPE_BLOCK_GPIO, 409 }, 410 }; 411 412 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks, 413 bool enable) 414 { 415 if (blocks & STMPE_BLOCK_GPIO) 416 return 0; 417 else 418 return -EINVAL; 419 } 420 421 static struct stmpe_variant_info stmpe801 = { 422 .name = "stmpe801", 423 .id_val = STMPE801_ID, 424 .id_mask = 0xffff, 425 .num_gpios = 8, 426 .regs = stmpe801_regs, 427 .blocks = stmpe801_blocks, 428 .num_blocks = ARRAY_SIZE(stmpe801_blocks), 429 .num_irqs = STMPE801_NR_INTERNAL_IRQS, 430 .enable = stmpe801_enable, 431 }; 432 433 static struct stmpe_variant_info stmpe801_noirq = { 434 .name = "stmpe801", 435 .id_val = STMPE801_ID, 436 .id_mask = 0xffff, 437 .num_gpios = 8, 438 .regs = stmpe801_regs, 439 .blocks = stmpe801_blocks_noirq, 440 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq), 441 .enable = stmpe801_enable, 442 }; 443 444 /* 445 * Touchscreen (STMPE811 or STMPE610) 446 */ 447 448 static struct resource stmpe_ts_resources[] = { 449 { 450 .name = "TOUCH_DET", 451 .flags = IORESOURCE_IRQ, 452 }, 453 { 454 .name = "FIFO_TH", 455 .flags = IORESOURCE_IRQ, 456 }, 457 }; 458 459 static const struct mfd_cell stmpe_ts_cell = { 460 .name = "stmpe-ts", 461 .of_compatible = "st,stmpe-ts", 462 .resources = stmpe_ts_resources, 463 .num_resources = ARRAY_SIZE(stmpe_ts_resources), 464 }; 465 466 /* 467 * ADC (STMPE811) 468 */ 469 470 static struct resource stmpe_adc_resources[] = { 471 { 472 .name = "STMPE_TEMP_SENS", 473 .flags = IORESOURCE_IRQ, 474 }, 475 { 476 .name = "STMPE_ADC", 477 .flags = IORESOURCE_IRQ, 478 }, 479 }; 480 481 static const struct mfd_cell stmpe_adc_cell = { 482 .name = "stmpe-adc", 483 .of_compatible = "st,stmpe-adc", 484 .resources = stmpe_adc_resources, 485 .num_resources = ARRAY_SIZE(stmpe_adc_resources), 486 }; 487 488 /* 489 * STMPE811 or STMPE610 490 */ 491 492 static const u8 stmpe811_regs[] = { 493 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, 494 [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL, 495 [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2, 496 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, 497 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, 498 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, 499 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA, 500 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN, 501 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN, 502 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR, 503 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE, 504 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE, 505 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, 506 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, 507 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, 508 [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED, 509 }; 510 511 static struct stmpe_variant_block stmpe811_blocks[] = { 512 { 513 .cell = &stmpe_gpio_cell, 514 .irq = STMPE811_IRQ_GPIOC, 515 .block = STMPE_BLOCK_GPIO, 516 }, 517 { 518 .cell = &stmpe_ts_cell, 519 .irq = STMPE811_IRQ_TOUCH_DET, 520 .block = STMPE_BLOCK_TOUCHSCREEN, 521 }, 522 { 523 .cell = &stmpe_adc_cell, 524 .irq = STMPE811_IRQ_TEMP_SENS, 525 .block = STMPE_BLOCK_ADC, 526 }, 527 }; 528 529 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, 530 bool enable) 531 { 532 unsigned int mask = 0; 533 534 if (blocks & STMPE_BLOCK_GPIO) 535 mask |= STMPE811_SYS_CTRL2_GPIO_OFF; 536 537 if (blocks & STMPE_BLOCK_ADC) 538 mask |= STMPE811_SYS_CTRL2_ADC_OFF; 539 540 if (blocks & STMPE_BLOCK_TOUCHSCREEN) 541 mask |= STMPE811_SYS_CTRL2_TSC_OFF; 542 543 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, 544 enable ? 0 : mask); 545 } 546 547 int stmpe811_adc_common_init(struct stmpe *stmpe) 548 { 549 int ret; 550 u8 adc_ctrl1, adc_ctrl1_mask; 551 552 adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) | 553 STMPE_MOD_12B(stmpe->mod_12b) | 554 STMPE_REF_SEL(stmpe->ref_sel); 555 adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) | 556 STMPE_REF_SEL(0xff); 557 558 ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1, 559 adc_ctrl1_mask, adc_ctrl1); 560 if (ret) { 561 dev_err(stmpe->dev, "Could not setup ADC\n"); 562 return ret; 563 } 564 565 ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2, 566 STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq)); 567 if (ret) { 568 dev_err(stmpe->dev, "Could not setup ADC\n"); 569 return ret; 570 } 571 572 return 0; 573 } 574 EXPORT_SYMBOL_GPL(stmpe811_adc_common_init); 575 576 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 577 { 578 /* 0 for touchscreen, 1 for GPIO */ 579 return block != STMPE_BLOCK_TOUCHSCREEN; 580 } 581 582 static struct stmpe_variant_info stmpe811 = { 583 .name = "stmpe811", 584 .id_val = 0x0811, 585 .id_mask = 0xffff, 586 .num_gpios = 8, 587 .af_bits = 1, 588 .regs = stmpe811_regs, 589 .blocks = stmpe811_blocks, 590 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 591 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 592 .enable = stmpe811_enable, 593 .get_altfunc = stmpe811_get_altfunc, 594 }; 595 596 /* Similar to 811, except number of gpios */ 597 static struct stmpe_variant_info stmpe610 = { 598 .name = "stmpe610", 599 .id_val = 0x0811, 600 .id_mask = 0xffff, 601 .num_gpios = 6, 602 .af_bits = 1, 603 .regs = stmpe811_regs, 604 .blocks = stmpe811_blocks, 605 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 606 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 607 .enable = stmpe811_enable, 608 .get_altfunc = stmpe811_get_altfunc, 609 }; 610 611 /* 612 * STMPE1600 613 * Compared to all others STMPE variant, LSB and MSB regs are located in this 614 * order : LSB addr 615 * MSB addr + 1 616 * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers 617 */ 618 619 static const u8 stmpe1600_regs[] = { 620 [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID, 621 [STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL, 622 [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL, 623 [STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB, 624 [STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB, 625 [STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB, 626 [STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB, 627 [STMPE_IDX_GPCR_LSB] = STMPE1600_REG_GPSR_LSB, 628 [STMPE_IDX_GPCR_CSB] = STMPE1600_REG_GPSR_MSB, 629 [STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB, 630 [STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB, 631 [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB, 632 [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB, 633 [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB, 634 }; 635 636 static struct stmpe_variant_block stmpe1600_blocks[] = { 637 { 638 .cell = &stmpe_gpio_cell, 639 .irq = 0, 640 .block = STMPE_BLOCK_GPIO, 641 }, 642 }; 643 644 static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks, 645 bool enable) 646 { 647 if (blocks & STMPE_BLOCK_GPIO) 648 return 0; 649 else 650 return -EINVAL; 651 } 652 653 static struct stmpe_variant_info stmpe1600 = { 654 .name = "stmpe1600", 655 .id_val = STMPE1600_ID, 656 .id_mask = 0xffff, 657 .num_gpios = 16, 658 .af_bits = 0, 659 .regs = stmpe1600_regs, 660 .blocks = stmpe1600_blocks, 661 .num_blocks = ARRAY_SIZE(stmpe1600_blocks), 662 .num_irqs = STMPE1600_NR_INTERNAL_IRQS, 663 .enable = stmpe1600_enable, 664 }; 665 666 /* 667 * STMPE1601 668 */ 669 670 static const u8 stmpe1601_regs[] = { 671 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, 672 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, 673 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, 674 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, 675 [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB, 676 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, 677 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, 678 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, 679 [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB, 680 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, 681 [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB, 682 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, 683 [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB, 684 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, 685 [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB, 686 [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB, 687 [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB, 688 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, 689 [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB, 690 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, 691 [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB, 692 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB, 693 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, 694 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, 695 [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB, 696 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, 697 }; 698 699 static struct stmpe_variant_block stmpe1601_blocks[] = { 700 { 701 .cell = &stmpe_gpio_cell, 702 .irq = STMPE1601_IRQ_GPIOC, 703 .block = STMPE_BLOCK_GPIO, 704 }, 705 { 706 .cell = &stmpe_keypad_cell, 707 .irq = STMPE1601_IRQ_KEYPAD, 708 .block = STMPE_BLOCK_KEYPAD, 709 }, 710 { 711 .cell = &stmpe_pwm_cell, 712 .irq = STMPE1601_IRQ_PWM0, 713 .block = STMPE_BLOCK_PWM, 714 }, 715 }; 716 717 /* supported autosleep timeout delay (in msecs) */ 718 static const int stmpe_autosleep_delay[] = { 719 4, 16, 32, 64, 128, 256, 512, 1024, 720 }; 721 722 static int stmpe_round_timeout(int timeout) 723 { 724 int i; 725 726 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) { 727 if (stmpe_autosleep_delay[i] >= timeout) 728 return i; 729 } 730 731 /* 732 * requests for delays longer than supported should not return the 733 * longest supported delay 734 */ 735 return -EINVAL; 736 } 737 738 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout) 739 { 740 int ret; 741 742 if (!stmpe->variant->enable_autosleep) 743 return -ENOSYS; 744 745 mutex_lock(&stmpe->lock); 746 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout); 747 mutex_unlock(&stmpe->lock); 748 749 return ret; 750 } 751 752 /* 753 * Both stmpe 1601/2403 support same layout for autosleep 754 */ 755 static int stmpe1601_autosleep(struct stmpe *stmpe, 756 int autosleep_timeout) 757 { 758 int ret, timeout; 759 760 /* choose the best available timeout */ 761 timeout = stmpe_round_timeout(autosleep_timeout); 762 if (timeout < 0) { 763 dev_err(stmpe->dev, "invalid timeout\n"); 764 return timeout; 765 } 766 767 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 768 STMPE1601_AUTOSLEEP_TIMEOUT_MASK, 769 timeout); 770 if (ret < 0) 771 return ret; 772 773 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 774 STPME1601_AUTOSLEEP_ENABLE, 775 STPME1601_AUTOSLEEP_ENABLE); 776 } 777 778 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks, 779 bool enable) 780 { 781 unsigned int mask = 0; 782 783 if (blocks & STMPE_BLOCK_GPIO) 784 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; 785 else 786 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO; 787 788 if (blocks & STMPE_BLOCK_KEYPAD) 789 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; 790 else 791 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC; 792 793 if (blocks & STMPE_BLOCK_PWM) 794 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM; 795 else 796 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; 797 798 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 799 enable ? mask : 0); 800 } 801 802 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 803 { 804 switch (block) { 805 case STMPE_BLOCK_PWM: 806 return 2; 807 808 case STMPE_BLOCK_KEYPAD: 809 return 1; 810 811 case STMPE_BLOCK_GPIO: 812 default: 813 return 0; 814 } 815 } 816 817 static struct stmpe_variant_info stmpe1601 = { 818 .name = "stmpe1601", 819 .id_val = 0x0210, 820 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */ 821 .num_gpios = 16, 822 .af_bits = 2, 823 .regs = stmpe1601_regs, 824 .blocks = stmpe1601_blocks, 825 .num_blocks = ARRAY_SIZE(stmpe1601_blocks), 826 .num_irqs = STMPE1601_NR_INTERNAL_IRQS, 827 .enable = stmpe1601_enable, 828 .get_altfunc = stmpe1601_get_altfunc, 829 .enable_autosleep = stmpe1601_autosleep, 830 }; 831 832 /* 833 * STMPE1801 834 */ 835 static const u8 stmpe1801_regs[] = { 836 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID, 837 [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL, 838 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW, 839 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, 840 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, 841 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW, 842 [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID, 843 [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH, 844 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW, 845 [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID, 846 [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH, 847 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW, 848 [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID, 849 [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH, 850 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW, 851 [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID, 852 [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH, 853 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW, 854 [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID, 855 [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH, 856 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW, 857 [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID, 858 [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH, 859 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW, 860 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW, 861 [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID, 862 [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH, 863 [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH, 864 }; 865 866 static struct stmpe_variant_block stmpe1801_blocks[] = { 867 { 868 .cell = &stmpe_gpio_cell, 869 .irq = STMPE1801_IRQ_GPIOC, 870 .block = STMPE_BLOCK_GPIO, 871 }, 872 { 873 .cell = &stmpe_keypad_cell, 874 .irq = STMPE1801_IRQ_KEYPAD, 875 .block = STMPE_BLOCK_KEYPAD, 876 }, 877 }; 878 879 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks, 880 bool enable) 881 { 882 unsigned int mask = 0; 883 if (blocks & STMPE_BLOCK_GPIO) 884 mask |= STMPE1801_MSK_INT_EN_GPIO; 885 886 if (blocks & STMPE_BLOCK_KEYPAD) 887 mask |= STMPE1801_MSK_INT_EN_KPC; 888 889 return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask, 890 enable ? mask : 0); 891 } 892 893 static int stmpe_reset(struct stmpe *stmpe) 894 { 895 u16 id_val = stmpe->variant->id_val; 896 unsigned long timeout; 897 int ret = 0; 898 u8 reset_bit; 899 900 if (id_val == STMPE811_ID) 901 /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */ 902 reset_bit = STMPE811_SYS_CTRL_RESET; 903 else 904 /* all other STMPE variant use bit 7 of SYS_CTRL register */ 905 reset_bit = STMPE_SYS_CTRL_RESET; 906 907 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], 908 reset_bit, reset_bit); 909 if (ret < 0) 910 return ret; 911 912 msleep(10); 913 914 timeout = jiffies + msecs_to_jiffies(100); 915 while (time_before(jiffies, timeout)) { 916 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); 917 if (ret < 0) 918 return ret; 919 if (!(ret & reset_bit)) 920 return 0; 921 usleep_range(100, 200); 922 } 923 return -EIO; 924 } 925 926 static struct stmpe_variant_info stmpe1801 = { 927 .name = "stmpe1801", 928 .id_val = STMPE1801_ID, 929 .id_mask = 0xfff0, 930 .num_gpios = 18, 931 .af_bits = 0, 932 .regs = stmpe1801_regs, 933 .blocks = stmpe1801_blocks, 934 .num_blocks = ARRAY_SIZE(stmpe1801_blocks), 935 .num_irqs = STMPE1801_NR_INTERNAL_IRQS, 936 .enable = stmpe1801_enable, 937 /* stmpe1801 do not have any gpio alternate function */ 938 .get_altfunc = NULL, 939 }; 940 941 /* 942 * STMPE24XX 943 */ 944 945 static const u8 stmpe24xx_regs[] = { 946 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, 947 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, 948 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, 949 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, 950 [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB, 951 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, 952 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, 953 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, 954 [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB, 955 [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB, 956 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, 957 [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB, 958 [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB, 959 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, 960 [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB, 961 [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB, 962 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, 963 [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB, 964 [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB, 965 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, 966 [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB, 967 [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB, 968 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, 969 [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB, 970 [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB, 971 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB, 972 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB, 973 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, 974 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, 975 [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB, 976 [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB, 977 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, 978 [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB, 979 [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB, 980 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, 981 }; 982 983 static struct stmpe_variant_block stmpe24xx_blocks[] = { 984 { 985 .cell = &stmpe_gpio_cell, 986 .irq = STMPE24XX_IRQ_GPIOC, 987 .block = STMPE_BLOCK_GPIO, 988 }, 989 { 990 .cell = &stmpe_keypad_cell, 991 .irq = STMPE24XX_IRQ_KEYPAD, 992 .block = STMPE_BLOCK_KEYPAD, 993 }, 994 { 995 .cell = &stmpe_pwm_cell, 996 .irq = STMPE24XX_IRQ_PWM0, 997 .block = STMPE_BLOCK_PWM, 998 }, 999 }; 1000 1001 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks, 1002 bool enable) 1003 { 1004 unsigned int mask = 0; 1005 1006 if (blocks & STMPE_BLOCK_GPIO) 1007 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO; 1008 1009 if (blocks & STMPE_BLOCK_KEYPAD) 1010 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; 1011 1012 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 1013 enable ? mask : 0); 1014 } 1015 1016 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 1017 { 1018 switch (block) { 1019 case STMPE_BLOCK_ROTATOR: 1020 return 2; 1021 1022 case STMPE_BLOCK_KEYPAD: 1023 case STMPE_BLOCK_PWM: 1024 return 1; 1025 1026 case STMPE_BLOCK_GPIO: 1027 default: 1028 return 0; 1029 } 1030 } 1031 1032 static struct stmpe_variant_info stmpe2401 = { 1033 .name = "stmpe2401", 1034 .id_val = 0x0101, 1035 .id_mask = 0xffff, 1036 .num_gpios = 24, 1037 .af_bits = 2, 1038 .regs = stmpe24xx_regs, 1039 .blocks = stmpe24xx_blocks, 1040 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 1041 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 1042 .enable = stmpe24xx_enable, 1043 .get_altfunc = stmpe24xx_get_altfunc, 1044 }; 1045 1046 static struct stmpe_variant_info stmpe2403 = { 1047 .name = "stmpe2403", 1048 .id_val = 0x0120, 1049 .id_mask = 0xffff, 1050 .num_gpios = 24, 1051 .af_bits = 2, 1052 .regs = stmpe24xx_regs, 1053 .blocks = stmpe24xx_blocks, 1054 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 1055 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 1056 .enable = stmpe24xx_enable, 1057 .get_altfunc = stmpe24xx_get_altfunc, 1058 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */ 1059 }; 1060 1061 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = { 1062 [STMPE610] = &stmpe610, 1063 [STMPE801] = &stmpe801, 1064 [STMPE811] = &stmpe811, 1065 [STMPE1600] = &stmpe1600, 1066 [STMPE1601] = &stmpe1601, 1067 [STMPE1801] = &stmpe1801, 1068 [STMPE2401] = &stmpe2401, 1069 [STMPE2403] = &stmpe2403, 1070 }; 1071 1072 /* 1073 * These devices can be connected in a 'no-irq' configuration - the irq pin 1074 * is not used and the device cannot interrupt the CPU. Here we only list 1075 * devices which support this configuration - the driver will fail probing 1076 * for any devices not listed here which are configured in this way. 1077 */ 1078 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = { 1079 [STMPE801] = &stmpe801_noirq, 1080 }; 1081 1082 static irqreturn_t stmpe_irq(int irq, void *data) 1083 { 1084 struct stmpe *stmpe = data; 1085 struct stmpe_variant_info *variant = stmpe->variant; 1086 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1087 u8 israddr; 1088 u8 isr[3]; 1089 int ret; 1090 int i; 1091 1092 if (variant->id_val == STMPE801_ID || 1093 variant->id_val == STMPE1600_ID) { 1094 int base = irq_create_mapping(stmpe->domain, 0); 1095 1096 handle_nested_irq(base); 1097 return IRQ_HANDLED; 1098 } 1099 1100 if (variant->id_val == STMPE1801_ID) 1101 israddr = stmpe->regs[STMPE_IDX_ISR_LSB]; 1102 else 1103 israddr = stmpe->regs[STMPE_IDX_ISR_MSB]; 1104 1105 ret = stmpe_block_read(stmpe, israddr, num, isr); 1106 if (ret < 0) 1107 return IRQ_NONE; 1108 1109 for (i = 0; i < num; i++) { 1110 int bank = num - i - 1; 1111 u8 status = isr[i]; 1112 u8 clear; 1113 1114 status &= stmpe->ier[bank]; 1115 if (!status) 1116 continue; 1117 1118 clear = status; 1119 while (status) { 1120 int bit = __ffs(status); 1121 int line = bank * 8 + bit; 1122 int nestedirq = irq_create_mapping(stmpe->domain, line); 1123 1124 handle_nested_irq(nestedirq); 1125 status &= ~(1 << bit); 1126 } 1127 1128 stmpe_reg_write(stmpe, israddr + i, clear); 1129 } 1130 1131 return IRQ_HANDLED; 1132 } 1133 1134 static void stmpe_irq_lock(struct irq_data *data) 1135 { 1136 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1137 1138 mutex_lock(&stmpe->irq_lock); 1139 } 1140 1141 static void stmpe_irq_sync_unlock(struct irq_data *data) 1142 { 1143 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1144 struct stmpe_variant_info *variant = stmpe->variant; 1145 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1146 int i; 1147 1148 for (i = 0; i < num; i++) { 1149 u8 new = stmpe->ier[i]; 1150 u8 old = stmpe->oldier[i]; 1151 1152 if (new == old) 1153 continue; 1154 1155 stmpe->oldier[i] = new; 1156 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new); 1157 } 1158 1159 mutex_unlock(&stmpe->irq_lock); 1160 } 1161 1162 static void stmpe_irq_mask(struct irq_data *data) 1163 { 1164 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1165 int offset = data->hwirq; 1166 int regoffset = offset / 8; 1167 int mask = 1 << (offset % 8); 1168 1169 stmpe->ier[regoffset] &= ~mask; 1170 } 1171 1172 static void stmpe_irq_unmask(struct irq_data *data) 1173 { 1174 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1175 int offset = data->hwirq; 1176 int regoffset = offset / 8; 1177 int mask = 1 << (offset % 8); 1178 1179 stmpe->ier[regoffset] |= mask; 1180 } 1181 1182 static struct irq_chip stmpe_irq_chip = { 1183 .name = "stmpe", 1184 .irq_bus_lock = stmpe_irq_lock, 1185 .irq_bus_sync_unlock = stmpe_irq_sync_unlock, 1186 .irq_mask = stmpe_irq_mask, 1187 .irq_unmask = stmpe_irq_unmask, 1188 }; 1189 1190 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq, 1191 irq_hw_number_t hwirq) 1192 { 1193 struct stmpe *stmpe = d->host_data; 1194 struct irq_chip *chip = NULL; 1195 1196 if (stmpe->variant->id_val != STMPE801_ID) 1197 chip = &stmpe_irq_chip; 1198 1199 irq_set_chip_data(virq, stmpe); 1200 irq_set_chip_and_handler(virq, chip, handle_edge_irq); 1201 irq_set_nested_thread(virq, 1); 1202 irq_set_noprobe(virq); 1203 1204 return 0; 1205 } 1206 1207 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq) 1208 { 1209 irq_set_chip_and_handler(virq, NULL, NULL); 1210 irq_set_chip_data(virq, NULL); 1211 } 1212 1213 static const struct irq_domain_ops stmpe_irq_ops = { 1214 .map = stmpe_irq_map, 1215 .unmap = stmpe_irq_unmap, 1216 .xlate = irq_domain_xlate_twocell, 1217 }; 1218 1219 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np) 1220 { 1221 int base = 0; 1222 int num_irqs = stmpe->variant->num_irqs; 1223 1224 stmpe->domain = irq_domain_add_simple(np, num_irqs, base, 1225 &stmpe_irq_ops, stmpe); 1226 if (!stmpe->domain) { 1227 dev_err(stmpe->dev, "Failed to create irqdomain\n"); 1228 return -ENOSYS; 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int stmpe_chip_init(struct stmpe *stmpe) 1235 { 1236 unsigned int irq_trigger = stmpe->pdata->irq_trigger; 1237 int autosleep_timeout = stmpe->pdata->autosleep_timeout; 1238 struct stmpe_variant_info *variant = stmpe->variant; 1239 u8 icr = 0; 1240 unsigned int id; 1241 u8 data[2]; 1242 int ret; 1243 1244 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID], 1245 ARRAY_SIZE(data), data); 1246 if (ret < 0) 1247 return ret; 1248 1249 id = (data[0] << 8) | data[1]; 1250 if ((id & variant->id_mask) != variant->id_val) { 1251 dev_err(stmpe->dev, "unknown chip id: %#x\n", id); 1252 return -EINVAL; 1253 } 1254 1255 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id); 1256 1257 /* Disable all modules -- subdrivers should enable what they need. */ 1258 ret = stmpe_disable(stmpe, ~0); 1259 if (ret) 1260 return ret; 1261 1262 ret = stmpe_reset(stmpe); 1263 if (ret < 0) 1264 return ret; 1265 1266 if (stmpe->irq >= 0) { 1267 if (id == STMPE801_ID || id == STMPE1600_ID) 1268 icr = STMPE_SYS_CTRL_INT_EN; 1269 else 1270 icr = STMPE_ICR_LSB_GIM; 1271 1272 /* STMPE801 and STMPE1600 don't support Edge interrupts */ 1273 if (id != STMPE801_ID && id != STMPE1600_ID) { 1274 if (irq_trigger == IRQF_TRIGGER_FALLING || 1275 irq_trigger == IRQF_TRIGGER_RISING) 1276 icr |= STMPE_ICR_LSB_EDGE; 1277 } 1278 1279 if (irq_trigger == IRQF_TRIGGER_RISING || 1280 irq_trigger == IRQF_TRIGGER_HIGH) { 1281 if (id == STMPE801_ID || id == STMPE1600_ID) 1282 icr |= STMPE_SYS_CTRL_INT_HI; 1283 else 1284 icr |= STMPE_ICR_LSB_HIGH; 1285 } 1286 } 1287 1288 if (stmpe->pdata->autosleep) { 1289 ret = stmpe_autosleep(stmpe, autosleep_timeout); 1290 if (ret) 1291 return ret; 1292 } 1293 1294 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr); 1295 } 1296 1297 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell) 1298 { 1299 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1, 1300 NULL, 0, stmpe->domain); 1301 } 1302 1303 static int stmpe_devices_init(struct stmpe *stmpe) 1304 { 1305 struct stmpe_variant_info *variant = stmpe->variant; 1306 unsigned int platform_blocks = stmpe->pdata->blocks; 1307 int ret = -EINVAL; 1308 int i, j; 1309 1310 for (i = 0; i < variant->num_blocks; i++) { 1311 struct stmpe_variant_block *block = &variant->blocks[i]; 1312 1313 if (!(platform_blocks & block->block)) 1314 continue; 1315 1316 for (j = 0; j < block->cell->num_resources; j++) { 1317 struct resource *res = 1318 (struct resource *) &block->cell->resources[j]; 1319 1320 /* Dynamically fill in a variant's IRQ. */ 1321 if (res->flags & IORESOURCE_IRQ) 1322 res->start = res->end = block->irq + j; 1323 } 1324 1325 platform_blocks &= ~block->block; 1326 ret = stmpe_add_device(stmpe, block->cell); 1327 if (ret) 1328 return ret; 1329 } 1330 1331 if (platform_blocks) 1332 dev_warn(stmpe->dev, 1333 "platform wants blocks (%#x) not present on variant", 1334 platform_blocks); 1335 1336 return ret; 1337 } 1338 1339 static void stmpe_of_probe(struct stmpe_platform_data *pdata, 1340 struct device_node *np) 1341 { 1342 struct device_node *child; 1343 1344 pdata->id = of_alias_get_id(np, "stmpe-i2c"); 1345 if (pdata->id < 0) 1346 pdata->id = -1; 1347 1348 pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0, 1349 &pdata->irq_trigger); 1350 if (gpio_is_valid(pdata->irq_gpio)) 1351 pdata->irq_over_gpio = 1; 1352 else 1353 pdata->irq_trigger = IRQF_TRIGGER_NONE; 1354 1355 of_property_read_u32(np, "st,autosleep-timeout", 1356 &pdata->autosleep_timeout); 1357 1358 pdata->autosleep = (pdata->autosleep_timeout) ? true : false; 1359 1360 for_each_child_of_node(np, child) { 1361 if (of_node_name_eq(child, "stmpe_gpio")) { 1362 pdata->blocks |= STMPE_BLOCK_GPIO; 1363 } else if (of_node_name_eq(child, "stmpe_keypad")) { 1364 pdata->blocks |= STMPE_BLOCK_KEYPAD; 1365 } else if (of_node_name_eq(child, "stmpe_touchscreen")) { 1366 pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN; 1367 } else if (of_node_name_eq(child, "stmpe_adc")) { 1368 pdata->blocks |= STMPE_BLOCK_ADC; 1369 } else if (of_node_name_eq(child, "stmpe_pwm")) { 1370 pdata->blocks |= STMPE_BLOCK_PWM; 1371 } else if (of_node_name_eq(child, "stmpe_rotator")) { 1372 pdata->blocks |= STMPE_BLOCK_ROTATOR; 1373 } 1374 } 1375 } 1376 1377 /* Called from client specific probe routines */ 1378 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) 1379 { 1380 struct stmpe_platform_data *pdata; 1381 struct device_node *np = ci->dev->of_node; 1382 struct stmpe *stmpe; 1383 int ret; 1384 u32 val; 1385 1386 pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL); 1387 if (!pdata) 1388 return -ENOMEM; 1389 1390 stmpe_of_probe(pdata, np); 1391 1392 if (of_find_property(np, "interrupts", NULL) == NULL) 1393 ci->irq = -1; 1394 1395 stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL); 1396 if (!stmpe) 1397 return -ENOMEM; 1398 1399 mutex_init(&stmpe->irq_lock); 1400 mutex_init(&stmpe->lock); 1401 1402 if (!of_property_read_u32(np, "st,sample-time", &val)) 1403 stmpe->sample_time = val; 1404 if (!of_property_read_u32(np, "st,mod-12b", &val)) 1405 stmpe->mod_12b = val; 1406 if (!of_property_read_u32(np, "st,ref-sel", &val)) 1407 stmpe->ref_sel = val; 1408 if (!of_property_read_u32(np, "st,adc-freq", &val)) 1409 stmpe->adc_freq = val; 1410 1411 stmpe->dev = ci->dev; 1412 stmpe->client = ci->client; 1413 stmpe->pdata = pdata; 1414 stmpe->ci = ci; 1415 stmpe->partnum = partnum; 1416 stmpe->variant = stmpe_variant_info[partnum]; 1417 stmpe->regs = stmpe->variant->regs; 1418 stmpe->num_gpios = stmpe->variant->num_gpios; 1419 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc"); 1420 if (!IS_ERR(stmpe->vcc)) { 1421 ret = regulator_enable(stmpe->vcc); 1422 if (ret) 1423 dev_warn(ci->dev, "failed to enable VCC supply\n"); 1424 } 1425 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio"); 1426 if (!IS_ERR(stmpe->vio)) { 1427 ret = regulator_enable(stmpe->vio); 1428 if (ret) 1429 dev_warn(ci->dev, "failed to enable VIO supply\n"); 1430 } 1431 dev_set_drvdata(stmpe->dev, stmpe); 1432 1433 if (ci->init) 1434 ci->init(stmpe); 1435 1436 if (pdata->irq_over_gpio) { 1437 ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio, 1438 GPIOF_DIR_IN, "stmpe"); 1439 if (ret) { 1440 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", 1441 ret); 1442 return ret; 1443 } 1444 1445 stmpe->irq = gpio_to_irq(pdata->irq_gpio); 1446 } else { 1447 stmpe->irq = ci->irq; 1448 } 1449 1450 if (stmpe->irq < 0) { 1451 /* use alternate variant info for no-irq mode, if supported */ 1452 dev_info(stmpe->dev, 1453 "%s configured in no-irq mode by platform data\n", 1454 stmpe->variant->name); 1455 if (!stmpe_noirq_variant_info[stmpe->partnum]) { 1456 dev_err(stmpe->dev, 1457 "%s does not support no-irq mode!\n", 1458 stmpe->variant->name); 1459 return -ENODEV; 1460 } 1461 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum]; 1462 } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) { 1463 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq); 1464 } 1465 1466 ret = stmpe_chip_init(stmpe); 1467 if (ret) 1468 return ret; 1469 1470 if (stmpe->irq >= 0) { 1471 ret = stmpe_irq_init(stmpe, np); 1472 if (ret) 1473 return ret; 1474 1475 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL, 1476 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT, 1477 "stmpe", stmpe); 1478 if (ret) { 1479 dev_err(stmpe->dev, "failed to request IRQ: %d\n", 1480 ret); 1481 return ret; 1482 } 1483 } 1484 1485 ret = stmpe_devices_init(stmpe); 1486 if (!ret) 1487 return 0; 1488 1489 dev_err(stmpe->dev, "failed to add children\n"); 1490 mfd_remove_devices(stmpe->dev); 1491 1492 return ret; 1493 } 1494 1495 int stmpe_remove(struct stmpe *stmpe) 1496 { 1497 if (!IS_ERR(stmpe->vio)) 1498 regulator_disable(stmpe->vio); 1499 if (!IS_ERR(stmpe->vcc)) 1500 regulator_disable(stmpe->vcc); 1501 1502 __stmpe_disable(stmpe, STMPE_BLOCK_ADC); 1503 1504 mfd_remove_devices(stmpe->dev); 1505 1506 return 0; 1507 } 1508 1509 #ifdef CONFIG_PM 1510 static int stmpe_suspend(struct device *dev) 1511 { 1512 struct stmpe *stmpe = dev_get_drvdata(dev); 1513 1514 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1515 enable_irq_wake(stmpe->irq); 1516 1517 return 0; 1518 } 1519 1520 static int stmpe_resume(struct device *dev) 1521 { 1522 struct stmpe *stmpe = dev_get_drvdata(dev); 1523 1524 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1525 disable_irq_wake(stmpe->irq); 1526 1527 return 0; 1528 } 1529 1530 const struct dev_pm_ops stmpe_dev_pm_ops = { 1531 .suspend = stmpe_suspend, 1532 .resume = stmpe_resume, 1533 }; 1534 #endif 1535