1 /* 2 * ST Microelectronics MFD: stmpe's driver 3 * 4 * Copyright (C) ST-Ericsson SA 2010 5 * 6 * License Terms: GNU General Public License, version 2 7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 8 */ 9 10 #include <linux/err.h> 11 #include <linux/gpio.h> 12 #include <linux/export.h> 13 #include <linux/kernel.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pm.h> 20 #include <linux/slab.h> 21 #include <linux/mfd/core.h> 22 #include <linux/delay.h> 23 #include <linux/regulator/consumer.h> 24 #include "stmpe.h" 25 26 /** 27 * struct stmpe_platform_data - STMPE platform data 28 * @id: device id to distinguish between multiple STMPEs on the same board 29 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 30 * @irq_trigger: IRQ trigger to use for the interrupt to the host 31 * @autosleep: bool to enable/disable stmpe autosleep 32 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 33 * @irq_over_gpio: true if gpio is used to get irq 34 * @irq_gpio: gpio number over which irq will be requested (significant only if 35 * irq_over_gpio is true) 36 */ 37 struct stmpe_platform_data { 38 int id; 39 unsigned int blocks; 40 unsigned int irq_trigger; 41 bool autosleep; 42 bool irq_over_gpio; 43 int irq_gpio; 44 int autosleep_timeout; 45 }; 46 47 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 48 { 49 return stmpe->variant->enable(stmpe, blocks, true); 50 } 51 52 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 53 { 54 return stmpe->variant->enable(stmpe, blocks, false); 55 } 56 57 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg) 58 { 59 int ret; 60 61 ret = stmpe->ci->read_byte(stmpe, reg); 62 if (ret < 0) 63 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); 64 65 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); 66 67 return ret; 68 } 69 70 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 71 { 72 int ret; 73 74 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); 75 76 ret = stmpe->ci->write_byte(stmpe, reg, val); 77 if (ret < 0) 78 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret); 79 80 return ret; 81 } 82 83 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 84 { 85 int ret; 86 87 ret = __stmpe_reg_read(stmpe, reg); 88 if (ret < 0) 89 return ret; 90 91 ret &= ~mask; 92 ret |= val; 93 94 return __stmpe_reg_write(stmpe, reg, ret); 95 } 96 97 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, 98 u8 *values) 99 { 100 int ret; 101 102 ret = stmpe->ci->read_block(stmpe, reg, length, values); 103 if (ret < 0) 104 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret); 105 106 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret); 107 stmpe_dump_bytes("stmpe rd: ", values, length); 108 109 return ret; 110 } 111 112 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 113 const u8 *values) 114 { 115 int ret; 116 117 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length); 118 stmpe_dump_bytes("stmpe wr: ", values, length); 119 120 ret = stmpe->ci->write_block(stmpe, reg, length, values); 121 if (ret < 0) 122 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret); 123 124 return ret; 125 } 126 127 /** 128 * stmpe_enable - enable blocks on an STMPE device 129 * @stmpe: Device to work on 130 * @blocks: Mask of blocks (enum stmpe_block values) to enable 131 */ 132 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 133 { 134 int ret; 135 136 mutex_lock(&stmpe->lock); 137 ret = __stmpe_enable(stmpe, blocks); 138 mutex_unlock(&stmpe->lock); 139 140 return ret; 141 } 142 EXPORT_SYMBOL_GPL(stmpe_enable); 143 144 /** 145 * stmpe_disable - disable blocks on an STMPE device 146 * @stmpe: Device to work on 147 * @blocks: Mask of blocks (enum stmpe_block values) to enable 148 */ 149 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 150 { 151 int ret; 152 153 mutex_lock(&stmpe->lock); 154 ret = __stmpe_disable(stmpe, blocks); 155 mutex_unlock(&stmpe->lock); 156 157 return ret; 158 } 159 EXPORT_SYMBOL_GPL(stmpe_disable); 160 161 /** 162 * stmpe_reg_read() - read a single STMPE register 163 * @stmpe: Device to read from 164 * @reg: Register to read 165 */ 166 int stmpe_reg_read(struct stmpe *stmpe, u8 reg) 167 { 168 int ret; 169 170 mutex_lock(&stmpe->lock); 171 ret = __stmpe_reg_read(stmpe, reg); 172 mutex_unlock(&stmpe->lock); 173 174 return ret; 175 } 176 EXPORT_SYMBOL_GPL(stmpe_reg_read); 177 178 /** 179 * stmpe_reg_write() - write a single STMPE register 180 * @stmpe: Device to write to 181 * @reg: Register to write 182 * @val: Value to write 183 */ 184 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 185 { 186 int ret; 187 188 mutex_lock(&stmpe->lock); 189 ret = __stmpe_reg_write(stmpe, reg, val); 190 mutex_unlock(&stmpe->lock); 191 192 return ret; 193 } 194 EXPORT_SYMBOL_GPL(stmpe_reg_write); 195 196 /** 197 * stmpe_set_bits() - set the value of a bitfield in a STMPE register 198 * @stmpe: Device to write to 199 * @reg: Register to write 200 * @mask: Mask of bits to set 201 * @val: Value to set 202 */ 203 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 204 { 205 int ret; 206 207 mutex_lock(&stmpe->lock); 208 ret = __stmpe_set_bits(stmpe, reg, mask, val); 209 mutex_unlock(&stmpe->lock); 210 211 return ret; 212 } 213 EXPORT_SYMBOL_GPL(stmpe_set_bits); 214 215 /** 216 * stmpe_block_read() - read multiple STMPE registers 217 * @stmpe: Device to read from 218 * @reg: First register 219 * @length: Number of registers 220 * @values: Buffer to write to 221 */ 222 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) 223 { 224 int ret; 225 226 mutex_lock(&stmpe->lock); 227 ret = __stmpe_block_read(stmpe, reg, length, values); 228 mutex_unlock(&stmpe->lock); 229 230 return ret; 231 } 232 EXPORT_SYMBOL_GPL(stmpe_block_read); 233 234 /** 235 * stmpe_block_write() - write multiple STMPE registers 236 * @stmpe: Device to write to 237 * @reg: First register 238 * @length: Number of registers 239 * @values: Values to write 240 */ 241 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 242 const u8 *values) 243 { 244 int ret; 245 246 mutex_lock(&stmpe->lock); 247 ret = __stmpe_block_write(stmpe, reg, length, values); 248 mutex_unlock(&stmpe->lock); 249 250 return ret; 251 } 252 EXPORT_SYMBOL_GPL(stmpe_block_write); 253 254 /** 255 * stmpe_set_altfunc()- set the alternate function for STMPE pins 256 * @stmpe: Device to configure 257 * @pins: Bitmask of pins to affect 258 * @block: block to enable alternate functions for 259 * 260 * @pins is assumed to have a bit set for each of the bits whose alternate 261 * function is to be changed, numbered according to the GPIOXY numbers. 262 * 263 * If the GPIO module is not enabled, this function automatically enables it in 264 * order to perform the change. 265 */ 266 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block) 267 { 268 struct stmpe_variant_info *variant = stmpe->variant; 269 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB]; 270 int af_bits = variant->af_bits; 271 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8); 272 int mask = (1 << af_bits) - 1; 273 u8 regs[8]; 274 int af, afperreg, ret; 275 276 if (!variant->get_altfunc) 277 return 0; 278 279 afperreg = 8 / af_bits; 280 mutex_lock(&stmpe->lock); 281 282 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 283 if (ret < 0) 284 goto out; 285 286 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs); 287 if (ret < 0) 288 goto out; 289 290 af = variant->get_altfunc(stmpe, block); 291 292 while (pins) { 293 int pin = __ffs(pins); 294 int regoffset = numregs - (pin / afperreg) - 1; 295 int pos = (pin % afperreg) * (8 / afperreg); 296 297 regs[regoffset] &= ~(mask << pos); 298 regs[regoffset] |= af << pos; 299 300 pins &= ~(1 << pin); 301 } 302 303 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs); 304 305 out: 306 mutex_unlock(&stmpe->lock); 307 return ret; 308 } 309 EXPORT_SYMBOL_GPL(stmpe_set_altfunc); 310 311 /* 312 * GPIO (all variants) 313 */ 314 315 static struct resource stmpe_gpio_resources[] = { 316 /* Start and end filled dynamically */ 317 { 318 .flags = IORESOURCE_IRQ, 319 }, 320 }; 321 322 static const struct mfd_cell stmpe_gpio_cell = { 323 .name = "stmpe-gpio", 324 .of_compatible = "st,stmpe-gpio", 325 .resources = stmpe_gpio_resources, 326 .num_resources = ARRAY_SIZE(stmpe_gpio_resources), 327 }; 328 329 static const struct mfd_cell stmpe_gpio_cell_noirq = { 330 .name = "stmpe-gpio", 331 .of_compatible = "st,stmpe-gpio", 332 /* gpio cell resources consist of an irq only so no resources here */ 333 }; 334 335 /* 336 * Keypad (1601, 2401, 2403) 337 */ 338 339 static struct resource stmpe_keypad_resources[] = { 340 { 341 .name = "KEYPAD", 342 .flags = IORESOURCE_IRQ, 343 }, 344 { 345 .name = "KEYPAD_OVER", 346 .flags = IORESOURCE_IRQ, 347 }, 348 }; 349 350 static const struct mfd_cell stmpe_keypad_cell = { 351 .name = "stmpe-keypad", 352 .of_compatible = "st,stmpe-keypad", 353 .resources = stmpe_keypad_resources, 354 .num_resources = ARRAY_SIZE(stmpe_keypad_resources), 355 }; 356 357 /* 358 * PWM (1601, 2401, 2403) 359 */ 360 static struct resource stmpe_pwm_resources[] = { 361 { 362 .name = "PWM0", 363 .flags = IORESOURCE_IRQ, 364 }, 365 { 366 .name = "PWM1", 367 .flags = IORESOURCE_IRQ, 368 }, 369 { 370 .name = "PWM2", 371 .flags = IORESOURCE_IRQ, 372 }, 373 }; 374 375 static const struct mfd_cell stmpe_pwm_cell = { 376 .name = "stmpe-pwm", 377 .of_compatible = "st,stmpe-pwm", 378 .resources = stmpe_pwm_resources, 379 .num_resources = ARRAY_SIZE(stmpe_pwm_resources), 380 }; 381 382 /* 383 * STMPE801 384 */ 385 static const u8 stmpe801_regs[] = { 386 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID, 387 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL, 388 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA, 389 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN, 390 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN, 391 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR, 392 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN, 393 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA, 394 395 }; 396 397 static struct stmpe_variant_block stmpe801_blocks[] = { 398 { 399 .cell = &stmpe_gpio_cell, 400 .irq = 0, 401 .block = STMPE_BLOCK_GPIO, 402 }, 403 }; 404 405 static struct stmpe_variant_block stmpe801_blocks_noirq[] = { 406 { 407 .cell = &stmpe_gpio_cell_noirq, 408 .block = STMPE_BLOCK_GPIO, 409 }, 410 }; 411 412 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks, 413 bool enable) 414 { 415 if (blocks & STMPE_BLOCK_GPIO) 416 return 0; 417 else 418 return -EINVAL; 419 } 420 421 static struct stmpe_variant_info stmpe801 = { 422 .name = "stmpe801", 423 .id_val = STMPE801_ID, 424 .id_mask = 0xffff, 425 .num_gpios = 8, 426 .regs = stmpe801_regs, 427 .blocks = stmpe801_blocks, 428 .num_blocks = ARRAY_SIZE(stmpe801_blocks), 429 .num_irqs = STMPE801_NR_INTERNAL_IRQS, 430 .enable = stmpe801_enable, 431 }; 432 433 static struct stmpe_variant_info stmpe801_noirq = { 434 .name = "stmpe801", 435 .id_val = STMPE801_ID, 436 .id_mask = 0xffff, 437 .num_gpios = 8, 438 .regs = stmpe801_regs, 439 .blocks = stmpe801_blocks_noirq, 440 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq), 441 .enable = stmpe801_enable, 442 }; 443 444 /* 445 * Touchscreen (STMPE811 or STMPE610) 446 */ 447 448 static struct resource stmpe_ts_resources[] = { 449 { 450 .name = "TOUCH_DET", 451 .flags = IORESOURCE_IRQ, 452 }, 453 { 454 .name = "FIFO_TH", 455 .flags = IORESOURCE_IRQ, 456 }, 457 }; 458 459 static const struct mfd_cell stmpe_ts_cell = { 460 .name = "stmpe-ts", 461 .of_compatible = "st,stmpe-ts", 462 .resources = stmpe_ts_resources, 463 .num_resources = ARRAY_SIZE(stmpe_ts_resources), 464 }; 465 466 /* 467 * STMPE811 or STMPE610 468 */ 469 470 static const u8 stmpe811_regs[] = { 471 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, 472 [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL, 473 [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2, 474 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, 475 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, 476 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, 477 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA, 478 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN, 479 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN, 480 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR, 481 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE, 482 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE, 483 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, 484 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, 485 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, 486 [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED, 487 }; 488 489 static struct stmpe_variant_block stmpe811_blocks[] = { 490 { 491 .cell = &stmpe_gpio_cell, 492 .irq = STMPE811_IRQ_GPIOC, 493 .block = STMPE_BLOCK_GPIO, 494 }, 495 { 496 .cell = &stmpe_ts_cell, 497 .irq = STMPE811_IRQ_TOUCH_DET, 498 .block = STMPE_BLOCK_TOUCHSCREEN, 499 }, 500 }; 501 502 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, 503 bool enable) 504 { 505 unsigned int mask = 0; 506 507 if (blocks & STMPE_BLOCK_GPIO) 508 mask |= STMPE811_SYS_CTRL2_GPIO_OFF; 509 510 if (blocks & STMPE_BLOCK_ADC) 511 mask |= STMPE811_SYS_CTRL2_ADC_OFF; 512 513 if (blocks & STMPE_BLOCK_TOUCHSCREEN) 514 mask |= STMPE811_SYS_CTRL2_TSC_OFF; 515 516 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, 517 enable ? 0 : mask); 518 } 519 520 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 521 { 522 /* 0 for touchscreen, 1 for GPIO */ 523 return block != STMPE_BLOCK_TOUCHSCREEN; 524 } 525 526 static struct stmpe_variant_info stmpe811 = { 527 .name = "stmpe811", 528 .id_val = 0x0811, 529 .id_mask = 0xffff, 530 .num_gpios = 8, 531 .af_bits = 1, 532 .regs = stmpe811_regs, 533 .blocks = stmpe811_blocks, 534 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 535 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 536 .enable = stmpe811_enable, 537 .get_altfunc = stmpe811_get_altfunc, 538 }; 539 540 /* Similar to 811, except number of gpios */ 541 static struct stmpe_variant_info stmpe610 = { 542 .name = "stmpe610", 543 .id_val = 0x0811, 544 .id_mask = 0xffff, 545 .num_gpios = 6, 546 .af_bits = 1, 547 .regs = stmpe811_regs, 548 .blocks = stmpe811_blocks, 549 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 550 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 551 .enable = stmpe811_enable, 552 .get_altfunc = stmpe811_get_altfunc, 553 }; 554 555 /* 556 * STMPE1600 557 * Compared to all others STMPE variant, LSB and MSB regs are located in this 558 * order : LSB addr 559 * MSB addr + 1 560 * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers 561 */ 562 563 static const u8 stmpe1600_regs[] = { 564 [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID, 565 [STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL, 566 [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL, 567 [STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB, 568 [STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB, 569 [STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB, 570 [STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB, 571 [STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB, 572 [STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB, 573 [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB, 574 [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB, 575 [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB, 576 }; 577 578 static struct stmpe_variant_block stmpe1600_blocks[] = { 579 { 580 .cell = &stmpe_gpio_cell, 581 .irq = 0, 582 .block = STMPE_BLOCK_GPIO, 583 }, 584 }; 585 586 static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks, 587 bool enable) 588 { 589 if (blocks & STMPE_BLOCK_GPIO) 590 return 0; 591 else 592 return -EINVAL; 593 } 594 595 static struct stmpe_variant_info stmpe1600 = { 596 .name = "stmpe1600", 597 .id_val = STMPE1600_ID, 598 .id_mask = 0xffff, 599 .num_gpios = 16, 600 .af_bits = 0, 601 .regs = stmpe1600_regs, 602 .blocks = stmpe1600_blocks, 603 .num_blocks = ARRAY_SIZE(stmpe1600_blocks), 604 .num_irqs = STMPE1600_NR_INTERNAL_IRQS, 605 .enable = stmpe1600_enable, 606 }; 607 608 /* 609 * STMPE1601 610 */ 611 612 static const u8 stmpe1601_regs[] = { 613 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, 614 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, 615 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, 616 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, 617 [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB, 618 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, 619 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, 620 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, 621 [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB, 622 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, 623 [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB, 624 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, 625 [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB, 626 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, 627 [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB, 628 [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB, 629 [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB, 630 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, 631 [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB, 632 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, 633 [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB, 634 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB, 635 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, 636 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, 637 [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB, 638 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, 639 }; 640 641 static struct stmpe_variant_block stmpe1601_blocks[] = { 642 { 643 .cell = &stmpe_gpio_cell, 644 .irq = STMPE1601_IRQ_GPIOC, 645 .block = STMPE_BLOCK_GPIO, 646 }, 647 { 648 .cell = &stmpe_keypad_cell, 649 .irq = STMPE1601_IRQ_KEYPAD, 650 .block = STMPE_BLOCK_KEYPAD, 651 }, 652 { 653 .cell = &stmpe_pwm_cell, 654 .irq = STMPE1601_IRQ_PWM0, 655 .block = STMPE_BLOCK_PWM, 656 }, 657 }; 658 659 /* supported autosleep timeout delay (in msecs) */ 660 static const int stmpe_autosleep_delay[] = { 661 4, 16, 32, 64, 128, 256, 512, 1024, 662 }; 663 664 static int stmpe_round_timeout(int timeout) 665 { 666 int i; 667 668 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) { 669 if (stmpe_autosleep_delay[i] >= timeout) 670 return i; 671 } 672 673 /* 674 * requests for delays longer than supported should not return the 675 * longest supported delay 676 */ 677 return -EINVAL; 678 } 679 680 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout) 681 { 682 int ret; 683 684 if (!stmpe->variant->enable_autosleep) 685 return -ENOSYS; 686 687 mutex_lock(&stmpe->lock); 688 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout); 689 mutex_unlock(&stmpe->lock); 690 691 return ret; 692 } 693 694 /* 695 * Both stmpe 1601/2403 support same layout for autosleep 696 */ 697 static int stmpe1601_autosleep(struct stmpe *stmpe, 698 int autosleep_timeout) 699 { 700 int ret, timeout; 701 702 /* choose the best available timeout */ 703 timeout = stmpe_round_timeout(autosleep_timeout); 704 if (timeout < 0) { 705 dev_err(stmpe->dev, "invalid timeout\n"); 706 return timeout; 707 } 708 709 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 710 STMPE1601_AUTOSLEEP_TIMEOUT_MASK, 711 timeout); 712 if (ret < 0) 713 return ret; 714 715 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 716 STPME1601_AUTOSLEEP_ENABLE, 717 STPME1601_AUTOSLEEP_ENABLE); 718 } 719 720 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks, 721 bool enable) 722 { 723 unsigned int mask = 0; 724 725 if (blocks & STMPE_BLOCK_GPIO) 726 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; 727 else 728 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO; 729 730 if (blocks & STMPE_BLOCK_KEYPAD) 731 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; 732 else 733 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC; 734 735 if (blocks & STMPE_BLOCK_PWM) 736 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM; 737 else 738 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; 739 740 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 741 enable ? mask : 0); 742 } 743 744 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 745 { 746 switch (block) { 747 case STMPE_BLOCK_PWM: 748 return 2; 749 750 case STMPE_BLOCK_KEYPAD: 751 return 1; 752 753 case STMPE_BLOCK_GPIO: 754 default: 755 return 0; 756 } 757 } 758 759 static struct stmpe_variant_info stmpe1601 = { 760 .name = "stmpe1601", 761 .id_val = 0x0210, 762 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */ 763 .num_gpios = 16, 764 .af_bits = 2, 765 .regs = stmpe1601_regs, 766 .blocks = stmpe1601_blocks, 767 .num_blocks = ARRAY_SIZE(stmpe1601_blocks), 768 .num_irqs = STMPE1601_NR_INTERNAL_IRQS, 769 .enable = stmpe1601_enable, 770 .get_altfunc = stmpe1601_get_altfunc, 771 .enable_autosleep = stmpe1601_autosleep, 772 }; 773 774 /* 775 * STMPE1801 776 */ 777 static const u8 stmpe1801_regs[] = { 778 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID, 779 [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL, 780 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW, 781 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, 782 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, 783 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW, 784 [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID, 785 [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH, 786 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW, 787 [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID, 788 [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH, 789 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW, 790 [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID, 791 [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH, 792 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW, 793 [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID, 794 [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH, 795 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW, 796 [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID, 797 [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH, 798 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW, 799 [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID, 800 [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH, 801 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW, 802 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW, 803 [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID, 804 [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH, 805 [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH, 806 }; 807 808 static struct stmpe_variant_block stmpe1801_blocks[] = { 809 { 810 .cell = &stmpe_gpio_cell, 811 .irq = STMPE1801_IRQ_GPIOC, 812 .block = STMPE_BLOCK_GPIO, 813 }, 814 { 815 .cell = &stmpe_keypad_cell, 816 .irq = STMPE1801_IRQ_KEYPAD, 817 .block = STMPE_BLOCK_KEYPAD, 818 }, 819 }; 820 821 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks, 822 bool enable) 823 { 824 unsigned int mask = 0; 825 if (blocks & STMPE_BLOCK_GPIO) 826 mask |= STMPE1801_MSK_INT_EN_GPIO; 827 828 if (blocks & STMPE_BLOCK_KEYPAD) 829 mask |= STMPE1801_MSK_INT_EN_KPC; 830 831 return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask, 832 enable ? mask : 0); 833 } 834 835 static int stmpe_reset(struct stmpe *stmpe) 836 { 837 u16 id_val = stmpe->variant->id_val; 838 unsigned long timeout; 839 int ret = 0; 840 u8 reset_bit; 841 842 if (id_val == STMPE811_ID) 843 /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */ 844 reset_bit = STMPE811_SYS_CTRL_RESET; 845 else 846 /* all other STMPE variant use bit 7 of SYS_CTRL register */ 847 reset_bit = STMPE_SYS_CTRL_RESET; 848 849 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], 850 reset_bit, reset_bit); 851 if (ret < 0) 852 return ret; 853 854 timeout = jiffies + msecs_to_jiffies(100); 855 while (time_before(jiffies, timeout)) { 856 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); 857 if (ret < 0) 858 return ret; 859 if (!(ret & reset_bit)) 860 return 0; 861 usleep_range(100, 200); 862 } 863 return -EIO; 864 } 865 866 static struct stmpe_variant_info stmpe1801 = { 867 .name = "stmpe1801", 868 .id_val = STMPE1801_ID, 869 .id_mask = 0xfff0, 870 .num_gpios = 18, 871 .af_bits = 0, 872 .regs = stmpe1801_regs, 873 .blocks = stmpe1801_blocks, 874 .num_blocks = ARRAY_SIZE(stmpe1801_blocks), 875 .num_irqs = STMPE1801_NR_INTERNAL_IRQS, 876 .enable = stmpe1801_enable, 877 /* stmpe1801 do not have any gpio alternate function */ 878 .get_altfunc = NULL, 879 }; 880 881 /* 882 * STMPE24XX 883 */ 884 885 static const u8 stmpe24xx_regs[] = { 886 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, 887 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, 888 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, 889 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, 890 [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB, 891 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, 892 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, 893 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, 894 [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB, 895 [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB, 896 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, 897 [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB, 898 [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB, 899 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, 900 [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB, 901 [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB, 902 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, 903 [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB, 904 [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB, 905 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, 906 [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB, 907 [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB, 908 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, 909 [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB, 910 [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB, 911 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB, 912 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB, 913 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, 914 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, 915 [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB, 916 [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB, 917 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, 918 [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB, 919 [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB, 920 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, 921 }; 922 923 static struct stmpe_variant_block stmpe24xx_blocks[] = { 924 { 925 .cell = &stmpe_gpio_cell, 926 .irq = STMPE24XX_IRQ_GPIOC, 927 .block = STMPE_BLOCK_GPIO, 928 }, 929 { 930 .cell = &stmpe_keypad_cell, 931 .irq = STMPE24XX_IRQ_KEYPAD, 932 .block = STMPE_BLOCK_KEYPAD, 933 }, 934 { 935 .cell = &stmpe_pwm_cell, 936 .irq = STMPE24XX_IRQ_PWM0, 937 .block = STMPE_BLOCK_PWM, 938 }, 939 }; 940 941 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks, 942 bool enable) 943 { 944 unsigned int mask = 0; 945 946 if (blocks & STMPE_BLOCK_GPIO) 947 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO; 948 949 if (blocks & STMPE_BLOCK_KEYPAD) 950 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; 951 952 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 953 enable ? mask : 0); 954 } 955 956 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 957 { 958 switch (block) { 959 case STMPE_BLOCK_ROTATOR: 960 return 2; 961 962 case STMPE_BLOCK_KEYPAD: 963 case STMPE_BLOCK_PWM: 964 return 1; 965 966 case STMPE_BLOCK_GPIO: 967 default: 968 return 0; 969 } 970 } 971 972 static struct stmpe_variant_info stmpe2401 = { 973 .name = "stmpe2401", 974 .id_val = 0x0101, 975 .id_mask = 0xffff, 976 .num_gpios = 24, 977 .af_bits = 2, 978 .regs = stmpe24xx_regs, 979 .blocks = stmpe24xx_blocks, 980 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 981 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 982 .enable = stmpe24xx_enable, 983 .get_altfunc = stmpe24xx_get_altfunc, 984 }; 985 986 static struct stmpe_variant_info stmpe2403 = { 987 .name = "stmpe2403", 988 .id_val = 0x0120, 989 .id_mask = 0xffff, 990 .num_gpios = 24, 991 .af_bits = 2, 992 .regs = stmpe24xx_regs, 993 .blocks = stmpe24xx_blocks, 994 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 995 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 996 .enable = stmpe24xx_enable, 997 .get_altfunc = stmpe24xx_get_altfunc, 998 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */ 999 }; 1000 1001 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = { 1002 [STMPE610] = &stmpe610, 1003 [STMPE801] = &stmpe801, 1004 [STMPE811] = &stmpe811, 1005 [STMPE1600] = &stmpe1600, 1006 [STMPE1601] = &stmpe1601, 1007 [STMPE1801] = &stmpe1801, 1008 [STMPE2401] = &stmpe2401, 1009 [STMPE2403] = &stmpe2403, 1010 }; 1011 1012 /* 1013 * These devices can be connected in a 'no-irq' configuration - the irq pin 1014 * is not used and the device cannot interrupt the CPU. Here we only list 1015 * devices which support this configuration - the driver will fail probing 1016 * for any devices not listed here which are configured in this way. 1017 */ 1018 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = { 1019 [STMPE801] = &stmpe801_noirq, 1020 }; 1021 1022 static irqreturn_t stmpe_irq(int irq, void *data) 1023 { 1024 struct stmpe *stmpe = data; 1025 struct stmpe_variant_info *variant = stmpe->variant; 1026 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1027 u8 israddr; 1028 u8 isr[3]; 1029 int ret; 1030 int i; 1031 1032 if (variant->id_val == STMPE801_ID || 1033 variant->id_val == STMPE1600_ID) { 1034 int base = irq_create_mapping(stmpe->domain, 0); 1035 1036 handle_nested_irq(base); 1037 return IRQ_HANDLED; 1038 } 1039 1040 if (variant->id_val == STMPE1801_ID) 1041 israddr = stmpe->regs[STMPE_IDX_ISR_LSB]; 1042 else 1043 israddr = stmpe->regs[STMPE_IDX_ISR_MSB]; 1044 1045 ret = stmpe_block_read(stmpe, israddr, num, isr); 1046 if (ret < 0) 1047 return IRQ_NONE; 1048 1049 for (i = 0; i < num; i++) { 1050 int bank = num - i - 1; 1051 u8 status = isr[i]; 1052 u8 clear; 1053 1054 status &= stmpe->ier[bank]; 1055 if (!status) 1056 continue; 1057 1058 clear = status; 1059 while (status) { 1060 int bit = __ffs(status); 1061 int line = bank * 8 + bit; 1062 int nestedirq = irq_create_mapping(stmpe->domain, line); 1063 1064 handle_nested_irq(nestedirq); 1065 status &= ~(1 << bit); 1066 } 1067 1068 stmpe_reg_write(stmpe, israddr + i, clear); 1069 } 1070 1071 return IRQ_HANDLED; 1072 } 1073 1074 static void stmpe_irq_lock(struct irq_data *data) 1075 { 1076 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1077 1078 mutex_lock(&stmpe->irq_lock); 1079 } 1080 1081 static void stmpe_irq_sync_unlock(struct irq_data *data) 1082 { 1083 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1084 struct stmpe_variant_info *variant = stmpe->variant; 1085 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1086 int i; 1087 1088 for (i = 0; i < num; i++) { 1089 u8 new = stmpe->ier[i]; 1090 u8 old = stmpe->oldier[i]; 1091 1092 if (new == old) 1093 continue; 1094 1095 stmpe->oldier[i] = new; 1096 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new); 1097 } 1098 1099 mutex_unlock(&stmpe->irq_lock); 1100 } 1101 1102 static void stmpe_irq_mask(struct irq_data *data) 1103 { 1104 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1105 int offset = data->hwirq; 1106 int regoffset = offset / 8; 1107 int mask = 1 << (offset % 8); 1108 1109 stmpe->ier[regoffset] &= ~mask; 1110 } 1111 1112 static void stmpe_irq_unmask(struct irq_data *data) 1113 { 1114 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1115 int offset = data->hwirq; 1116 int regoffset = offset / 8; 1117 int mask = 1 << (offset % 8); 1118 1119 stmpe->ier[regoffset] |= mask; 1120 } 1121 1122 static struct irq_chip stmpe_irq_chip = { 1123 .name = "stmpe", 1124 .irq_bus_lock = stmpe_irq_lock, 1125 .irq_bus_sync_unlock = stmpe_irq_sync_unlock, 1126 .irq_mask = stmpe_irq_mask, 1127 .irq_unmask = stmpe_irq_unmask, 1128 }; 1129 1130 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq, 1131 irq_hw_number_t hwirq) 1132 { 1133 struct stmpe *stmpe = d->host_data; 1134 struct irq_chip *chip = NULL; 1135 1136 if (stmpe->variant->id_val != STMPE801_ID) 1137 chip = &stmpe_irq_chip; 1138 1139 irq_set_chip_data(virq, stmpe); 1140 irq_set_chip_and_handler(virq, chip, handle_edge_irq); 1141 irq_set_nested_thread(virq, 1); 1142 irq_set_noprobe(virq); 1143 1144 return 0; 1145 } 1146 1147 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq) 1148 { 1149 irq_set_chip_and_handler(virq, NULL, NULL); 1150 irq_set_chip_data(virq, NULL); 1151 } 1152 1153 static const struct irq_domain_ops stmpe_irq_ops = { 1154 .map = stmpe_irq_map, 1155 .unmap = stmpe_irq_unmap, 1156 .xlate = irq_domain_xlate_twocell, 1157 }; 1158 1159 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np) 1160 { 1161 int base = 0; 1162 int num_irqs = stmpe->variant->num_irqs; 1163 1164 stmpe->domain = irq_domain_add_simple(np, num_irqs, base, 1165 &stmpe_irq_ops, stmpe); 1166 if (!stmpe->domain) { 1167 dev_err(stmpe->dev, "Failed to create irqdomain\n"); 1168 return -ENOSYS; 1169 } 1170 1171 return 0; 1172 } 1173 1174 static int stmpe_chip_init(struct stmpe *stmpe) 1175 { 1176 unsigned int irq_trigger = stmpe->pdata->irq_trigger; 1177 int autosleep_timeout = stmpe->pdata->autosleep_timeout; 1178 struct stmpe_variant_info *variant = stmpe->variant; 1179 u8 icr = 0; 1180 unsigned int id; 1181 u8 data[2]; 1182 int ret; 1183 1184 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID], 1185 ARRAY_SIZE(data), data); 1186 if (ret < 0) 1187 return ret; 1188 1189 id = (data[0] << 8) | data[1]; 1190 if ((id & variant->id_mask) != variant->id_val) { 1191 dev_err(stmpe->dev, "unknown chip id: %#x\n", id); 1192 return -EINVAL; 1193 } 1194 1195 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id); 1196 1197 /* Disable all modules -- subdrivers should enable what they need. */ 1198 ret = stmpe_disable(stmpe, ~0); 1199 if (ret) 1200 return ret; 1201 1202 ret = stmpe_reset(stmpe); 1203 if (ret < 0) 1204 return ret; 1205 1206 if (stmpe->irq >= 0) { 1207 if (id == STMPE801_ID || id == STMPE1600_ID) 1208 icr = STMPE_SYS_CTRL_INT_EN; 1209 else 1210 icr = STMPE_ICR_LSB_GIM; 1211 1212 /* STMPE801 and STMPE1600 don't support Edge interrupts */ 1213 if (id != STMPE801_ID && id != STMPE1600_ID) { 1214 if (irq_trigger == IRQF_TRIGGER_FALLING || 1215 irq_trigger == IRQF_TRIGGER_RISING) 1216 icr |= STMPE_ICR_LSB_EDGE; 1217 } 1218 1219 if (irq_trigger == IRQF_TRIGGER_RISING || 1220 irq_trigger == IRQF_TRIGGER_HIGH) { 1221 if (id == STMPE801_ID || id == STMPE1600_ID) 1222 icr |= STMPE_SYS_CTRL_INT_HI; 1223 else 1224 icr |= STMPE_ICR_LSB_HIGH; 1225 } 1226 } 1227 1228 if (stmpe->pdata->autosleep) { 1229 ret = stmpe_autosleep(stmpe, autosleep_timeout); 1230 if (ret) 1231 return ret; 1232 } 1233 1234 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr); 1235 } 1236 1237 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell) 1238 { 1239 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1, 1240 NULL, 0, stmpe->domain); 1241 } 1242 1243 static int stmpe_devices_init(struct stmpe *stmpe) 1244 { 1245 struct stmpe_variant_info *variant = stmpe->variant; 1246 unsigned int platform_blocks = stmpe->pdata->blocks; 1247 int ret = -EINVAL; 1248 int i, j; 1249 1250 for (i = 0; i < variant->num_blocks; i++) { 1251 struct stmpe_variant_block *block = &variant->blocks[i]; 1252 1253 if (!(platform_blocks & block->block)) 1254 continue; 1255 1256 for (j = 0; j < block->cell->num_resources; j++) { 1257 struct resource *res = 1258 (struct resource *) &block->cell->resources[j]; 1259 1260 /* Dynamically fill in a variant's IRQ. */ 1261 if (res->flags & IORESOURCE_IRQ) 1262 res->start = res->end = block->irq + j; 1263 } 1264 1265 platform_blocks &= ~block->block; 1266 ret = stmpe_add_device(stmpe, block->cell); 1267 if (ret) 1268 return ret; 1269 } 1270 1271 if (platform_blocks) 1272 dev_warn(stmpe->dev, 1273 "platform wants blocks (%#x) not present on variant", 1274 platform_blocks); 1275 1276 return ret; 1277 } 1278 1279 static void stmpe_of_probe(struct stmpe_platform_data *pdata, 1280 struct device_node *np) 1281 { 1282 struct device_node *child; 1283 1284 pdata->id = of_alias_get_id(np, "stmpe-i2c"); 1285 if (pdata->id < 0) 1286 pdata->id = -1; 1287 1288 pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0, 1289 &pdata->irq_trigger); 1290 if (gpio_is_valid(pdata->irq_gpio)) 1291 pdata->irq_over_gpio = 1; 1292 else 1293 pdata->irq_trigger = IRQF_TRIGGER_NONE; 1294 1295 of_property_read_u32(np, "st,autosleep-timeout", 1296 &pdata->autosleep_timeout); 1297 1298 pdata->autosleep = (pdata->autosleep_timeout) ? true : false; 1299 1300 for_each_child_of_node(np, child) { 1301 if (!strcmp(child->name, "stmpe_gpio")) { 1302 pdata->blocks |= STMPE_BLOCK_GPIO; 1303 } else if (!strcmp(child->name, "stmpe_keypad")) { 1304 pdata->blocks |= STMPE_BLOCK_KEYPAD; 1305 } else if (!strcmp(child->name, "stmpe_touchscreen")) { 1306 pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN; 1307 } else if (!strcmp(child->name, "stmpe_adc")) { 1308 pdata->blocks |= STMPE_BLOCK_ADC; 1309 } else if (!strcmp(child->name, "stmpe_pwm")) { 1310 pdata->blocks |= STMPE_BLOCK_PWM; 1311 } else if (!strcmp(child->name, "stmpe_rotator")) { 1312 pdata->blocks |= STMPE_BLOCK_ROTATOR; 1313 } 1314 } 1315 } 1316 1317 /* Called from client specific probe routines */ 1318 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) 1319 { 1320 struct stmpe_platform_data *pdata; 1321 struct device_node *np = ci->dev->of_node; 1322 struct stmpe *stmpe; 1323 int ret; 1324 1325 pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL); 1326 if (!pdata) 1327 return -ENOMEM; 1328 1329 stmpe_of_probe(pdata, np); 1330 1331 if (of_find_property(np, "interrupts", NULL) == NULL) 1332 ci->irq = -1; 1333 1334 stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL); 1335 if (!stmpe) 1336 return -ENOMEM; 1337 1338 mutex_init(&stmpe->irq_lock); 1339 mutex_init(&stmpe->lock); 1340 1341 stmpe->dev = ci->dev; 1342 stmpe->client = ci->client; 1343 stmpe->pdata = pdata; 1344 stmpe->ci = ci; 1345 stmpe->partnum = partnum; 1346 stmpe->variant = stmpe_variant_info[partnum]; 1347 stmpe->regs = stmpe->variant->regs; 1348 stmpe->num_gpios = stmpe->variant->num_gpios; 1349 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc"); 1350 if (!IS_ERR(stmpe->vcc)) { 1351 ret = regulator_enable(stmpe->vcc); 1352 if (ret) 1353 dev_warn(ci->dev, "failed to enable VCC supply\n"); 1354 } 1355 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio"); 1356 if (!IS_ERR(stmpe->vio)) { 1357 ret = regulator_enable(stmpe->vio); 1358 if (ret) 1359 dev_warn(ci->dev, "failed to enable VIO supply\n"); 1360 } 1361 dev_set_drvdata(stmpe->dev, stmpe); 1362 1363 if (ci->init) 1364 ci->init(stmpe); 1365 1366 if (pdata->irq_over_gpio) { 1367 ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio, 1368 GPIOF_DIR_IN, "stmpe"); 1369 if (ret) { 1370 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", 1371 ret); 1372 return ret; 1373 } 1374 1375 stmpe->irq = gpio_to_irq(pdata->irq_gpio); 1376 } else { 1377 stmpe->irq = ci->irq; 1378 } 1379 1380 if (stmpe->irq < 0) { 1381 /* use alternate variant info for no-irq mode, if supported */ 1382 dev_info(stmpe->dev, 1383 "%s configured in no-irq mode by platform data\n", 1384 stmpe->variant->name); 1385 if (!stmpe_noirq_variant_info[stmpe->partnum]) { 1386 dev_err(stmpe->dev, 1387 "%s does not support no-irq mode!\n", 1388 stmpe->variant->name); 1389 return -ENODEV; 1390 } 1391 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum]; 1392 } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) { 1393 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq); 1394 } 1395 1396 ret = stmpe_chip_init(stmpe); 1397 if (ret) 1398 return ret; 1399 1400 if (stmpe->irq >= 0) { 1401 ret = stmpe_irq_init(stmpe, np); 1402 if (ret) 1403 return ret; 1404 1405 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL, 1406 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT, 1407 "stmpe", stmpe); 1408 if (ret) { 1409 dev_err(stmpe->dev, "failed to request IRQ: %d\n", 1410 ret); 1411 return ret; 1412 } 1413 } 1414 1415 ret = stmpe_devices_init(stmpe); 1416 if (!ret) 1417 return 0; 1418 1419 dev_err(stmpe->dev, "failed to add children\n"); 1420 mfd_remove_devices(stmpe->dev); 1421 1422 return ret; 1423 } 1424 1425 int stmpe_remove(struct stmpe *stmpe) 1426 { 1427 if (!IS_ERR(stmpe->vio)) 1428 regulator_disable(stmpe->vio); 1429 if (!IS_ERR(stmpe->vcc)) 1430 regulator_disable(stmpe->vcc); 1431 1432 mfd_remove_devices(stmpe->dev); 1433 1434 return 0; 1435 } 1436 1437 #ifdef CONFIG_PM 1438 static int stmpe_suspend(struct device *dev) 1439 { 1440 struct stmpe *stmpe = dev_get_drvdata(dev); 1441 1442 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1443 enable_irq_wake(stmpe->irq); 1444 1445 return 0; 1446 } 1447 1448 static int stmpe_resume(struct device *dev) 1449 { 1450 struct stmpe *stmpe = dev_get_drvdata(dev); 1451 1452 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1453 disable_irq_wake(stmpe->irq); 1454 1455 return 0; 1456 } 1457 1458 const struct dev_pm_ops stmpe_dev_pm_ops = { 1459 .suspend = stmpe_suspend, 1460 .resume = stmpe_resume, 1461 }; 1462 #endif 1463