1 /* 2 * ST Microelectronics MFD: stmpe's driver 3 * 4 * Copyright (C) ST-Ericsson SA 2010 5 * 6 * License Terms: GNU General Public License, version 2 7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 8 */ 9 10 #include <linux/err.h> 11 #include <linux/gpio.h> 12 #include <linux/export.h> 13 #include <linux/kernel.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pm.h> 20 #include <linux/slab.h> 21 #include <linux/mfd/core.h> 22 #include <linux/delay.h> 23 #include <linux/regulator/consumer.h> 24 #include "stmpe.h" 25 26 /** 27 * struct stmpe_platform_data - STMPE platform data 28 * @id: device id to distinguish between multiple STMPEs on the same board 29 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 30 * @irq_trigger: IRQ trigger to use for the interrupt to the host 31 * @autosleep: bool to enable/disable stmpe autosleep 32 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 33 * @irq_over_gpio: true if gpio is used to get irq 34 * @irq_gpio: gpio number over which irq will be requested (significant only if 35 * irq_over_gpio is true) 36 */ 37 struct stmpe_platform_data { 38 int id; 39 unsigned int blocks; 40 unsigned int irq_trigger; 41 bool autosleep; 42 bool irq_over_gpio; 43 int irq_gpio; 44 int autosleep_timeout; 45 }; 46 47 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 48 { 49 return stmpe->variant->enable(stmpe, blocks, true); 50 } 51 52 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 53 { 54 return stmpe->variant->enable(stmpe, blocks, false); 55 } 56 57 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg) 58 { 59 int ret; 60 61 ret = stmpe->ci->read_byte(stmpe, reg); 62 if (ret < 0) 63 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); 64 65 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); 66 67 return ret; 68 } 69 70 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 71 { 72 int ret; 73 74 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); 75 76 ret = stmpe->ci->write_byte(stmpe, reg, val); 77 if (ret < 0) 78 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret); 79 80 return ret; 81 } 82 83 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 84 { 85 int ret; 86 87 ret = __stmpe_reg_read(stmpe, reg); 88 if (ret < 0) 89 return ret; 90 91 ret &= ~mask; 92 ret |= val; 93 94 return __stmpe_reg_write(stmpe, reg, ret); 95 } 96 97 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, 98 u8 *values) 99 { 100 int ret; 101 102 ret = stmpe->ci->read_block(stmpe, reg, length, values); 103 if (ret < 0) 104 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret); 105 106 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret); 107 stmpe_dump_bytes("stmpe rd: ", values, length); 108 109 return ret; 110 } 111 112 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 113 const u8 *values) 114 { 115 int ret; 116 117 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length); 118 stmpe_dump_bytes("stmpe wr: ", values, length); 119 120 ret = stmpe->ci->write_block(stmpe, reg, length, values); 121 if (ret < 0) 122 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret); 123 124 return ret; 125 } 126 127 /** 128 * stmpe_enable - enable blocks on an STMPE device 129 * @stmpe: Device to work on 130 * @blocks: Mask of blocks (enum stmpe_block values) to enable 131 */ 132 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 133 { 134 int ret; 135 136 mutex_lock(&stmpe->lock); 137 ret = __stmpe_enable(stmpe, blocks); 138 mutex_unlock(&stmpe->lock); 139 140 return ret; 141 } 142 EXPORT_SYMBOL_GPL(stmpe_enable); 143 144 /** 145 * stmpe_disable - disable blocks on an STMPE device 146 * @stmpe: Device to work on 147 * @blocks: Mask of blocks (enum stmpe_block values) to enable 148 */ 149 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 150 { 151 int ret; 152 153 mutex_lock(&stmpe->lock); 154 ret = __stmpe_disable(stmpe, blocks); 155 mutex_unlock(&stmpe->lock); 156 157 return ret; 158 } 159 EXPORT_SYMBOL_GPL(stmpe_disable); 160 161 /** 162 * stmpe_reg_read() - read a single STMPE register 163 * @stmpe: Device to read from 164 * @reg: Register to read 165 */ 166 int stmpe_reg_read(struct stmpe *stmpe, u8 reg) 167 { 168 int ret; 169 170 mutex_lock(&stmpe->lock); 171 ret = __stmpe_reg_read(stmpe, reg); 172 mutex_unlock(&stmpe->lock); 173 174 return ret; 175 } 176 EXPORT_SYMBOL_GPL(stmpe_reg_read); 177 178 /** 179 * stmpe_reg_write() - write a single STMPE register 180 * @stmpe: Device to write to 181 * @reg: Register to write 182 * @val: Value to write 183 */ 184 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 185 { 186 int ret; 187 188 mutex_lock(&stmpe->lock); 189 ret = __stmpe_reg_write(stmpe, reg, val); 190 mutex_unlock(&stmpe->lock); 191 192 return ret; 193 } 194 EXPORT_SYMBOL_GPL(stmpe_reg_write); 195 196 /** 197 * stmpe_set_bits() - set the value of a bitfield in a STMPE register 198 * @stmpe: Device to write to 199 * @reg: Register to write 200 * @mask: Mask of bits to set 201 * @val: Value to set 202 */ 203 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 204 { 205 int ret; 206 207 mutex_lock(&stmpe->lock); 208 ret = __stmpe_set_bits(stmpe, reg, mask, val); 209 mutex_unlock(&stmpe->lock); 210 211 return ret; 212 } 213 EXPORT_SYMBOL_GPL(stmpe_set_bits); 214 215 /** 216 * stmpe_block_read() - read multiple STMPE registers 217 * @stmpe: Device to read from 218 * @reg: First register 219 * @length: Number of registers 220 * @values: Buffer to write to 221 */ 222 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) 223 { 224 int ret; 225 226 mutex_lock(&stmpe->lock); 227 ret = __stmpe_block_read(stmpe, reg, length, values); 228 mutex_unlock(&stmpe->lock); 229 230 return ret; 231 } 232 EXPORT_SYMBOL_GPL(stmpe_block_read); 233 234 /** 235 * stmpe_block_write() - write multiple STMPE registers 236 * @stmpe: Device to write to 237 * @reg: First register 238 * @length: Number of registers 239 * @values: Values to write 240 */ 241 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 242 const u8 *values) 243 { 244 int ret; 245 246 mutex_lock(&stmpe->lock); 247 ret = __stmpe_block_write(stmpe, reg, length, values); 248 mutex_unlock(&stmpe->lock); 249 250 return ret; 251 } 252 EXPORT_SYMBOL_GPL(stmpe_block_write); 253 254 /** 255 * stmpe_set_altfunc()- set the alternate function for STMPE pins 256 * @stmpe: Device to configure 257 * @pins: Bitmask of pins to affect 258 * @block: block to enable alternate functions for 259 * 260 * @pins is assumed to have a bit set for each of the bits whose alternate 261 * function is to be changed, numbered according to the GPIOXY numbers. 262 * 263 * If the GPIO module is not enabled, this function automatically enables it in 264 * order to perform the change. 265 */ 266 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block) 267 { 268 struct stmpe_variant_info *variant = stmpe->variant; 269 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB]; 270 int af_bits = variant->af_bits; 271 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8); 272 int mask = (1 << af_bits) - 1; 273 u8 regs[8]; 274 int af, afperreg, ret; 275 276 if (!variant->get_altfunc) 277 return 0; 278 279 afperreg = 8 / af_bits; 280 mutex_lock(&stmpe->lock); 281 282 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 283 if (ret < 0) 284 goto out; 285 286 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs); 287 if (ret < 0) 288 goto out; 289 290 af = variant->get_altfunc(stmpe, block); 291 292 while (pins) { 293 int pin = __ffs(pins); 294 int regoffset = numregs - (pin / afperreg) - 1; 295 int pos = (pin % afperreg) * (8 / afperreg); 296 297 regs[regoffset] &= ~(mask << pos); 298 regs[regoffset] |= af << pos; 299 300 pins &= ~(1 << pin); 301 } 302 303 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs); 304 305 out: 306 mutex_unlock(&stmpe->lock); 307 return ret; 308 } 309 EXPORT_SYMBOL_GPL(stmpe_set_altfunc); 310 311 /* 312 * GPIO (all variants) 313 */ 314 315 static struct resource stmpe_gpio_resources[] = { 316 /* Start and end filled dynamically */ 317 { 318 .flags = IORESOURCE_IRQ, 319 }, 320 }; 321 322 static const struct mfd_cell stmpe_gpio_cell = { 323 .name = "stmpe-gpio", 324 .of_compatible = "st,stmpe-gpio", 325 .resources = stmpe_gpio_resources, 326 .num_resources = ARRAY_SIZE(stmpe_gpio_resources), 327 }; 328 329 static const struct mfd_cell stmpe_gpio_cell_noirq = { 330 .name = "stmpe-gpio", 331 .of_compatible = "st,stmpe-gpio", 332 /* gpio cell resources consist of an irq only so no resources here */ 333 }; 334 335 /* 336 * Keypad (1601, 2401, 2403) 337 */ 338 339 static struct resource stmpe_keypad_resources[] = { 340 { 341 .name = "KEYPAD", 342 .flags = IORESOURCE_IRQ, 343 }, 344 { 345 .name = "KEYPAD_OVER", 346 .flags = IORESOURCE_IRQ, 347 }, 348 }; 349 350 static const struct mfd_cell stmpe_keypad_cell = { 351 .name = "stmpe-keypad", 352 .of_compatible = "st,stmpe-keypad", 353 .resources = stmpe_keypad_resources, 354 .num_resources = ARRAY_SIZE(stmpe_keypad_resources), 355 }; 356 357 /* 358 * PWM (1601, 2401, 2403) 359 */ 360 static struct resource stmpe_pwm_resources[] = { 361 { 362 .name = "PWM0", 363 .flags = IORESOURCE_IRQ, 364 }, 365 { 366 .name = "PWM1", 367 .flags = IORESOURCE_IRQ, 368 }, 369 { 370 .name = "PWM2", 371 .flags = IORESOURCE_IRQ, 372 }, 373 }; 374 375 static const struct mfd_cell stmpe_pwm_cell = { 376 .name = "stmpe-pwm", 377 .of_compatible = "st,stmpe-pwm", 378 .resources = stmpe_pwm_resources, 379 .num_resources = ARRAY_SIZE(stmpe_pwm_resources), 380 }; 381 382 /* 383 * STMPE801 384 */ 385 static const u8 stmpe801_regs[] = { 386 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID, 387 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL, 388 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA, 389 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN, 390 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN, 391 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR, 392 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN, 393 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA, 394 395 }; 396 397 static struct stmpe_variant_block stmpe801_blocks[] = { 398 { 399 .cell = &stmpe_gpio_cell, 400 .irq = 0, 401 .block = STMPE_BLOCK_GPIO, 402 }, 403 }; 404 405 static struct stmpe_variant_block stmpe801_blocks_noirq[] = { 406 { 407 .cell = &stmpe_gpio_cell_noirq, 408 .block = STMPE_BLOCK_GPIO, 409 }, 410 }; 411 412 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks, 413 bool enable) 414 { 415 if (blocks & STMPE_BLOCK_GPIO) 416 return 0; 417 else 418 return -EINVAL; 419 } 420 421 static struct stmpe_variant_info stmpe801 = { 422 .name = "stmpe801", 423 .id_val = STMPE801_ID, 424 .id_mask = 0xffff, 425 .num_gpios = 8, 426 .regs = stmpe801_regs, 427 .blocks = stmpe801_blocks, 428 .num_blocks = ARRAY_SIZE(stmpe801_blocks), 429 .num_irqs = STMPE801_NR_INTERNAL_IRQS, 430 .enable = stmpe801_enable, 431 }; 432 433 static struct stmpe_variant_info stmpe801_noirq = { 434 .name = "stmpe801", 435 .id_val = STMPE801_ID, 436 .id_mask = 0xffff, 437 .num_gpios = 8, 438 .regs = stmpe801_regs, 439 .blocks = stmpe801_blocks_noirq, 440 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq), 441 .enable = stmpe801_enable, 442 }; 443 444 /* 445 * Touchscreen (STMPE811 or STMPE610) 446 */ 447 448 static struct resource stmpe_ts_resources[] = { 449 { 450 .name = "TOUCH_DET", 451 .flags = IORESOURCE_IRQ, 452 }, 453 { 454 .name = "FIFO_TH", 455 .flags = IORESOURCE_IRQ, 456 }, 457 }; 458 459 static const struct mfd_cell stmpe_ts_cell = { 460 .name = "stmpe-ts", 461 .of_compatible = "st,stmpe-ts", 462 .resources = stmpe_ts_resources, 463 .num_resources = ARRAY_SIZE(stmpe_ts_resources), 464 }; 465 466 /* 467 * STMPE811 or STMPE610 468 */ 469 470 static const u8 stmpe811_regs[] = { 471 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, 472 [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL, 473 [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2, 474 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, 475 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, 476 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, 477 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA, 478 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN, 479 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN, 480 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR, 481 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE, 482 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE, 483 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, 484 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, 485 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, 486 [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED, 487 }; 488 489 static struct stmpe_variant_block stmpe811_blocks[] = { 490 { 491 .cell = &stmpe_gpio_cell, 492 .irq = STMPE811_IRQ_GPIOC, 493 .block = STMPE_BLOCK_GPIO, 494 }, 495 { 496 .cell = &stmpe_ts_cell, 497 .irq = STMPE811_IRQ_TOUCH_DET, 498 .block = STMPE_BLOCK_TOUCHSCREEN, 499 }, 500 }; 501 502 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, 503 bool enable) 504 { 505 unsigned int mask = 0; 506 507 if (blocks & STMPE_BLOCK_GPIO) 508 mask |= STMPE811_SYS_CTRL2_GPIO_OFF; 509 510 if (blocks & STMPE_BLOCK_ADC) 511 mask |= STMPE811_SYS_CTRL2_ADC_OFF; 512 513 if (blocks & STMPE_BLOCK_TOUCHSCREEN) 514 mask |= STMPE811_SYS_CTRL2_TSC_OFF; 515 516 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, 517 enable ? 0 : mask); 518 } 519 520 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 521 { 522 /* 0 for touchscreen, 1 for GPIO */ 523 return block != STMPE_BLOCK_TOUCHSCREEN; 524 } 525 526 static struct stmpe_variant_info stmpe811 = { 527 .name = "stmpe811", 528 .id_val = 0x0811, 529 .id_mask = 0xffff, 530 .num_gpios = 8, 531 .af_bits = 1, 532 .regs = stmpe811_regs, 533 .blocks = stmpe811_blocks, 534 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 535 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 536 .enable = stmpe811_enable, 537 .get_altfunc = stmpe811_get_altfunc, 538 }; 539 540 /* Similar to 811, except number of gpios */ 541 static struct stmpe_variant_info stmpe610 = { 542 .name = "stmpe610", 543 .id_val = 0x0811, 544 .id_mask = 0xffff, 545 .num_gpios = 6, 546 .af_bits = 1, 547 .regs = stmpe811_regs, 548 .blocks = stmpe811_blocks, 549 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 550 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 551 .enable = stmpe811_enable, 552 .get_altfunc = stmpe811_get_altfunc, 553 }; 554 555 /* 556 * STMPE1600 557 * Compared to all others STMPE variant, LSB and MSB regs are located in this 558 * order : LSB addr 559 * MSB addr + 1 560 * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers 561 */ 562 563 static const u8 stmpe1600_regs[] = { 564 [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID, 565 [STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL, 566 [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL, 567 [STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB, 568 [STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB, 569 [STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB, 570 [STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB, 571 [STMPE_IDX_GPCR_LSB] = STMPE1600_REG_GPSR_LSB, 572 [STMPE_IDX_GPCR_CSB] = STMPE1600_REG_GPSR_MSB, 573 [STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB, 574 [STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB, 575 [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB, 576 [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB, 577 [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB, 578 }; 579 580 static struct stmpe_variant_block stmpe1600_blocks[] = { 581 { 582 .cell = &stmpe_gpio_cell, 583 .irq = 0, 584 .block = STMPE_BLOCK_GPIO, 585 }, 586 }; 587 588 static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks, 589 bool enable) 590 { 591 if (blocks & STMPE_BLOCK_GPIO) 592 return 0; 593 else 594 return -EINVAL; 595 } 596 597 static struct stmpe_variant_info stmpe1600 = { 598 .name = "stmpe1600", 599 .id_val = STMPE1600_ID, 600 .id_mask = 0xffff, 601 .num_gpios = 16, 602 .af_bits = 0, 603 .regs = stmpe1600_regs, 604 .blocks = stmpe1600_blocks, 605 .num_blocks = ARRAY_SIZE(stmpe1600_blocks), 606 .num_irqs = STMPE1600_NR_INTERNAL_IRQS, 607 .enable = stmpe1600_enable, 608 }; 609 610 /* 611 * STMPE1601 612 */ 613 614 static const u8 stmpe1601_regs[] = { 615 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, 616 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, 617 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, 618 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, 619 [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB, 620 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, 621 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, 622 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, 623 [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB, 624 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, 625 [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB, 626 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, 627 [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB, 628 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, 629 [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB, 630 [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB, 631 [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB, 632 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, 633 [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB, 634 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, 635 [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB, 636 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB, 637 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, 638 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, 639 [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB, 640 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, 641 }; 642 643 static struct stmpe_variant_block stmpe1601_blocks[] = { 644 { 645 .cell = &stmpe_gpio_cell, 646 .irq = STMPE1601_IRQ_GPIOC, 647 .block = STMPE_BLOCK_GPIO, 648 }, 649 { 650 .cell = &stmpe_keypad_cell, 651 .irq = STMPE1601_IRQ_KEYPAD, 652 .block = STMPE_BLOCK_KEYPAD, 653 }, 654 { 655 .cell = &stmpe_pwm_cell, 656 .irq = STMPE1601_IRQ_PWM0, 657 .block = STMPE_BLOCK_PWM, 658 }, 659 }; 660 661 /* supported autosleep timeout delay (in msecs) */ 662 static const int stmpe_autosleep_delay[] = { 663 4, 16, 32, 64, 128, 256, 512, 1024, 664 }; 665 666 static int stmpe_round_timeout(int timeout) 667 { 668 int i; 669 670 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) { 671 if (stmpe_autosleep_delay[i] >= timeout) 672 return i; 673 } 674 675 /* 676 * requests for delays longer than supported should not return the 677 * longest supported delay 678 */ 679 return -EINVAL; 680 } 681 682 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout) 683 { 684 int ret; 685 686 if (!stmpe->variant->enable_autosleep) 687 return -ENOSYS; 688 689 mutex_lock(&stmpe->lock); 690 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout); 691 mutex_unlock(&stmpe->lock); 692 693 return ret; 694 } 695 696 /* 697 * Both stmpe 1601/2403 support same layout for autosleep 698 */ 699 static int stmpe1601_autosleep(struct stmpe *stmpe, 700 int autosleep_timeout) 701 { 702 int ret, timeout; 703 704 /* choose the best available timeout */ 705 timeout = stmpe_round_timeout(autosleep_timeout); 706 if (timeout < 0) { 707 dev_err(stmpe->dev, "invalid timeout\n"); 708 return timeout; 709 } 710 711 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 712 STMPE1601_AUTOSLEEP_TIMEOUT_MASK, 713 timeout); 714 if (ret < 0) 715 return ret; 716 717 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 718 STPME1601_AUTOSLEEP_ENABLE, 719 STPME1601_AUTOSLEEP_ENABLE); 720 } 721 722 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks, 723 bool enable) 724 { 725 unsigned int mask = 0; 726 727 if (blocks & STMPE_BLOCK_GPIO) 728 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; 729 else 730 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO; 731 732 if (blocks & STMPE_BLOCK_KEYPAD) 733 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; 734 else 735 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC; 736 737 if (blocks & STMPE_BLOCK_PWM) 738 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM; 739 else 740 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; 741 742 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 743 enable ? mask : 0); 744 } 745 746 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 747 { 748 switch (block) { 749 case STMPE_BLOCK_PWM: 750 return 2; 751 752 case STMPE_BLOCK_KEYPAD: 753 return 1; 754 755 case STMPE_BLOCK_GPIO: 756 default: 757 return 0; 758 } 759 } 760 761 static struct stmpe_variant_info stmpe1601 = { 762 .name = "stmpe1601", 763 .id_val = 0x0210, 764 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */ 765 .num_gpios = 16, 766 .af_bits = 2, 767 .regs = stmpe1601_regs, 768 .blocks = stmpe1601_blocks, 769 .num_blocks = ARRAY_SIZE(stmpe1601_blocks), 770 .num_irqs = STMPE1601_NR_INTERNAL_IRQS, 771 .enable = stmpe1601_enable, 772 .get_altfunc = stmpe1601_get_altfunc, 773 .enable_autosleep = stmpe1601_autosleep, 774 }; 775 776 /* 777 * STMPE1801 778 */ 779 static const u8 stmpe1801_regs[] = { 780 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID, 781 [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL, 782 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW, 783 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, 784 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, 785 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW, 786 [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID, 787 [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH, 788 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW, 789 [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID, 790 [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH, 791 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW, 792 [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID, 793 [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH, 794 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW, 795 [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID, 796 [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH, 797 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW, 798 [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID, 799 [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH, 800 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW, 801 [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID, 802 [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH, 803 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW, 804 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW, 805 [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID, 806 [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH, 807 [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH, 808 }; 809 810 static struct stmpe_variant_block stmpe1801_blocks[] = { 811 { 812 .cell = &stmpe_gpio_cell, 813 .irq = STMPE1801_IRQ_GPIOC, 814 .block = STMPE_BLOCK_GPIO, 815 }, 816 { 817 .cell = &stmpe_keypad_cell, 818 .irq = STMPE1801_IRQ_KEYPAD, 819 .block = STMPE_BLOCK_KEYPAD, 820 }, 821 }; 822 823 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks, 824 bool enable) 825 { 826 unsigned int mask = 0; 827 if (blocks & STMPE_BLOCK_GPIO) 828 mask |= STMPE1801_MSK_INT_EN_GPIO; 829 830 if (blocks & STMPE_BLOCK_KEYPAD) 831 mask |= STMPE1801_MSK_INT_EN_KPC; 832 833 return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask, 834 enable ? mask : 0); 835 } 836 837 static int stmpe_reset(struct stmpe *stmpe) 838 { 839 u16 id_val = stmpe->variant->id_val; 840 unsigned long timeout; 841 int ret = 0; 842 u8 reset_bit; 843 844 if (id_val == STMPE811_ID) 845 /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */ 846 reset_bit = STMPE811_SYS_CTRL_RESET; 847 else 848 /* all other STMPE variant use bit 7 of SYS_CTRL register */ 849 reset_bit = STMPE_SYS_CTRL_RESET; 850 851 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], 852 reset_bit, reset_bit); 853 if (ret < 0) 854 return ret; 855 856 msleep(10); 857 858 timeout = jiffies + msecs_to_jiffies(100); 859 while (time_before(jiffies, timeout)) { 860 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); 861 if (ret < 0) 862 return ret; 863 if (!(ret & reset_bit)) 864 return 0; 865 usleep_range(100, 200); 866 } 867 return -EIO; 868 } 869 870 static struct stmpe_variant_info stmpe1801 = { 871 .name = "stmpe1801", 872 .id_val = STMPE1801_ID, 873 .id_mask = 0xfff0, 874 .num_gpios = 18, 875 .af_bits = 0, 876 .regs = stmpe1801_regs, 877 .blocks = stmpe1801_blocks, 878 .num_blocks = ARRAY_SIZE(stmpe1801_blocks), 879 .num_irqs = STMPE1801_NR_INTERNAL_IRQS, 880 .enable = stmpe1801_enable, 881 /* stmpe1801 do not have any gpio alternate function */ 882 .get_altfunc = NULL, 883 }; 884 885 /* 886 * STMPE24XX 887 */ 888 889 static const u8 stmpe24xx_regs[] = { 890 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, 891 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, 892 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, 893 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, 894 [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB, 895 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, 896 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, 897 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, 898 [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB, 899 [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB, 900 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, 901 [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB, 902 [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB, 903 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, 904 [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB, 905 [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB, 906 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, 907 [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB, 908 [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB, 909 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, 910 [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB, 911 [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB, 912 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, 913 [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB, 914 [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB, 915 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB, 916 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB, 917 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, 918 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, 919 [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB, 920 [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB, 921 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, 922 [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB, 923 [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB, 924 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, 925 }; 926 927 static struct stmpe_variant_block stmpe24xx_blocks[] = { 928 { 929 .cell = &stmpe_gpio_cell, 930 .irq = STMPE24XX_IRQ_GPIOC, 931 .block = STMPE_BLOCK_GPIO, 932 }, 933 { 934 .cell = &stmpe_keypad_cell, 935 .irq = STMPE24XX_IRQ_KEYPAD, 936 .block = STMPE_BLOCK_KEYPAD, 937 }, 938 { 939 .cell = &stmpe_pwm_cell, 940 .irq = STMPE24XX_IRQ_PWM0, 941 .block = STMPE_BLOCK_PWM, 942 }, 943 }; 944 945 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks, 946 bool enable) 947 { 948 unsigned int mask = 0; 949 950 if (blocks & STMPE_BLOCK_GPIO) 951 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO; 952 953 if (blocks & STMPE_BLOCK_KEYPAD) 954 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; 955 956 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 957 enable ? mask : 0); 958 } 959 960 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 961 { 962 switch (block) { 963 case STMPE_BLOCK_ROTATOR: 964 return 2; 965 966 case STMPE_BLOCK_KEYPAD: 967 case STMPE_BLOCK_PWM: 968 return 1; 969 970 case STMPE_BLOCK_GPIO: 971 default: 972 return 0; 973 } 974 } 975 976 static struct stmpe_variant_info stmpe2401 = { 977 .name = "stmpe2401", 978 .id_val = 0x0101, 979 .id_mask = 0xffff, 980 .num_gpios = 24, 981 .af_bits = 2, 982 .regs = stmpe24xx_regs, 983 .blocks = stmpe24xx_blocks, 984 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 985 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 986 .enable = stmpe24xx_enable, 987 .get_altfunc = stmpe24xx_get_altfunc, 988 }; 989 990 static struct stmpe_variant_info stmpe2403 = { 991 .name = "stmpe2403", 992 .id_val = 0x0120, 993 .id_mask = 0xffff, 994 .num_gpios = 24, 995 .af_bits = 2, 996 .regs = stmpe24xx_regs, 997 .blocks = stmpe24xx_blocks, 998 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 999 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 1000 .enable = stmpe24xx_enable, 1001 .get_altfunc = stmpe24xx_get_altfunc, 1002 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */ 1003 }; 1004 1005 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = { 1006 [STMPE610] = &stmpe610, 1007 [STMPE801] = &stmpe801, 1008 [STMPE811] = &stmpe811, 1009 [STMPE1600] = &stmpe1600, 1010 [STMPE1601] = &stmpe1601, 1011 [STMPE1801] = &stmpe1801, 1012 [STMPE2401] = &stmpe2401, 1013 [STMPE2403] = &stmpe2403, 1014 }; 1015 1016 /* 1017 * These devices can be connected in a 'no-irq' configuration - the irq pin 1018 * is not used and the device cannot interrupt the CPU. Here we only list 1019 * devices which support this configuration - the driver will fail probing 1020 * for any devices not listed here which are configured in this way. 1021 */ 1022 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = { 1023 [STMPE801] = &stmpe801_noirq, 1024 }; 1025 1026 static irqreturn_t stmpe_irq(int irq, void *data) 1027 { 1028 struct stmpe *stmpe = data; 1029 struct stmpe_variant_info *variant = stmpe->variant; 1030 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1031 u8 israddr; 1032 u8 isr[3]; 1033 int ret; 1034 int i; 1035 1036 if (variant->id_val == STMPE801_ID || 1037 variant->id_val == STMPE1600_ID) { 1038 int base = irq_create_mapping(stmpe->domain, 0); 1039 1040 handle_nested_irq(base); 1041 return IRQ_HANDLED; 1042 } 1043 1044 if (variant->id_val == STMPE1801_ID) 1045 israddr = stmpe->regs[STMPE_IDX_ISR_LSB]; 1046 else 1047 israddr = stmpe->regs[STMPE_IDX_ISR_MSB]; 1048 1049 ret = stmpe_block_read(stmpe, israddr, num, isr); 1050 if (ret < 0) 1051 return IRQ_NONE; 1052 1053 for (i = 0; i < num; i++) { 1054 int bank = num - i - 1; 1055 u8 status = isr[i]; 1056 u8 clear; 1057 1058 status &= stmpe->ier[bank]; 1059 if (!status) 1060 continue; 1061 1062 clear = status; 1063 while (status) { 1064 int bit = __ffs(status); 1065 int line = bank * 8 + bit; 1066 int nestedirq = irq_create_mapping(stmpe->domain, line); 1067 1068 handle_nested_irq(nestedirq); 1069 status &= ~(1 << bit); 1070 } 1071 1072 stmpe_reg_write(stmpe, israddr + i, clear); 1073 } 1074 1075 return IRQ_HANDLED; 1076 } 1077 1078 static void stmpe_irq_lock(struct irq_data *data) 1079 { 1080 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1081 1082 mutex_lock(&stmpe->irq_lock); 1083 } 1084 1085 static void stmpe_irq_sync_unlock(struct irq_data *data) 1086 { 1087 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1088 struct stmpe_variant_info *variant = stmpe->variant; 1089 int num = DIV_ROUND_UP(variant->num_irqs, 8); 1090 int i; 1091 1092 for (i = 0; i < num; i++) { 1093 u8 new = stmpe->ier[i]; 1094 u8 old = stmpe->oldier[i]; 1095 1096 if (new == old) 1097 continue; 1098 1099 stmpe->oldier[i] = new; 1100 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new); 1101 } 1102 1103 mutex_unlock(&stmpe->irq_lock); 1104 } 1105 1106 static void stmpe_irq_mask(struct irq_data *data) 1107 { 1108 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1109 int offset = data->hwirq; 1110 int regoffset = offset / 8; 1111 int mask = 1 << (offset % 8); 1112 1113 stmpe->ier[regoffset] &= ~mask; 1114 } 1115 1116 static void stmpe_irq_unmask(struct irq_data *data) 1117 { 1118 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1119 int offset = data->hwirq; 1120 int regoffset = offset / 8; 1121 int mask = 1 << (offset % 8); 1122 1123 stmpe->ier[regoffset] |= mask; 1124 } 1125 1126 static struct irq_chip stmpe_irq_chip = { 1127 .name = "stmpe", 1128 .irq_bus_lock = stmpe_irq_lock, 1129 .irq_bus_sync_unlock = stmpe_irq_sync_unlock, 1130 .irq_mask = stmpe_irq_mask, 1131 .irq_unmask = stmpe_irq_unmask, 1132 }; 1133 1134 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq, 1135 irq_hw_number_t hwirq) 1136 { 1137 struct stmpe *stmpe = d->host_data; 1138 struct irq_chip *chip = NULL; 1139 1140 if (stmpe->variant->id_val != STMPE801_ID) 1141 chip = &stmpe_irq_chip; 1142 1143 irq_set_chip_data(virq, stmpe); 1144 irq_set_chip_and_handler(virq, chip, handle_edge_irq); 1145 irq_set_nested_thread(virq, 1); 1146 irq_set_noprobe(virq); 1147 1148 return 0; 1149 } 1150 1151 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq) 1152 { 1153 irq_set_chip_and_handler(virq, NULL, NULL); 1154 irq_set_chip_data(virq, NULL); 1155 } 1156 1157 static const struct irq_domain_ops stmpe_irq_ops = { 1158 .map = stmpe_irq_map, 1159 .unmap = stmpe_irq_unmap, 1160 .xlate = irq_domain_xlate_twocell, 1161 }; 1162 1163 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np) 1164 { 1165 int base = 0; 1166 int num_irqs = stmpe->variant->num_irqs; 1167 1168 stmpe->domain = irq_domain_add_simple(np, num_irqs, base, 1169 &stmpe_irq_ops, stmpe); 1170 if (!stmpe->domain) { 1171 dev_err(stmpe->dev, "Failed to create irqdomain\n"); 1172 return -ENOSYS; 1173 } 1174 1175 return 0; 1176 } 1177 1178 static int stmpe_chip_init(struct stmpe *stmpe) 1179 { 1180 unsigned int irq_trigger = stmpe->pdata->irq_trigger; 1181 int autosleep_timeout = stmpe->pdata->autosleep_timeout; 1182 struct stmpe_variant_info *variant = stmpe->variant; 1183 u8 icr = 0; 1184 unsigned int id; 1185 u8 data[2]; 1186 int ret; 1187 1188 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID], 1189 ARRAY_SIZE(data), data); 1190 if (ret < 0) 1191 return ret; 1192 1193 id = (data[0] << 8) | data[1]; 1194 if ((id & variant->id_mask) != variant->id_val) { 1195 dev_err(stmpe->dev, "unknown chip id: %#x\n", id); 1196 return -EINVAL; 1197 } 1198 1199 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id); 1200 1201 /* Disable all modules -- subdrivers should enable what they need. */ 1202 ret = stmpe_disable(stmpe, ~0); 1203 if (ret) 1204 return ret; 1205 1206 ret = stmpe_reset(stmpe); 1207 if (ret < 0) 1208 return ret; 1209 1210 if (stmpe->irq >= 0) { 1211 if (id == STMPE801_ID || id == STMPE1600_ID) 1212 icr = STMPE_SYS_CTRL_INT_EN; 1213 else 1214 icr = STMPE_ICR_LSB_GIM; 1215 1216 /* STMPE801 and STMPE1600 don't support Edge interrupts */ 1217 if (id != STMPE801_ID && id != STMPE1600_ID) { 1218 if (irq_trigger == IRQF_TRIGGER_FALLING || 1219 irq_trigger == IRQF_TRIGGER_RISING) 1220 icr |= STMPE_ICR_LSB_EDGE; 1221 } 1222 1223 if (irq_trigger == IRQF_TRIGGER_RISING || 1224 irq_trigger == IRQF_TRIGGER_HIGH) { 1225 if (id == STMPE801_ID || id == STMPE1600_ID) 1226 icr |= STMPE_SYS_CTRL_INT_HI; 1227 else 1228 icr |= STMPE_ICR_LSB_HIGH; 1229 } 1230 } 1231 1232 if (stmpe->pdata->autosleep) { 1233 ret = stmpe_autosleep(stmpe, autosleep_timeout); 1234 if (ret) 1235 return ret; 1236 } 1237 1238 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr); 1239 } 1240 1241 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell) 1242 { 1243 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1, 1244 NULL, 0, stmpe->domain); 1245 } 1246 1247 static int stmpe_devices_init(struct stmpe *stmpe) 1248 { 1249 struct stmpe_variant_info *variant = stmpe->variant; 1250 unsigned int platform_blocks = stmpe->pdata->blocks; 1251 int ret = -EINVAL; 1252 int i, j; 1253 1254 for (i = 0; i < variant->num_blocks; i++) { 1255 struct stmpe_variant_block *block = &variant->blocks[i]; 1256 1257 if (!(platform_blocks & block->block)) 1258 continue; 1259 1260 for (j = 0; j < block->cell->num_resources; j++) { 1261 struct resource *res = 1262 (struct resource *) &block->cell->resources[j]; 1263 1264 /* Dynamically fill in a variant's IRQ. */ 1265 if (res->flags & IORESOURCE_IRQ) 1266 res->start = res->end = block->irq + j; 1267 } 1268 1269 platform_blocks &= ~block->block; 1270 ret = stmpe_add_device(stmpe, block->cell); 1271 if (ret) 1272 return ret; 1273 } 1274 1275 if (platform_blocks) 1276 dev_warn(stmpe->dev, 1277 "platform wants blocks (%#x) not present on variant", 1278 platform_blocks); 1279 1280 return ret; 1281 } 1282 1283 static void stmpe_of_probe(struct stmpe_platform_data *pdata, 1284 struct device_node *np) 1285 { 1286 struct device_node *child; 1287 1288 pdata->id = of_alias_get_id(np, "stmpe-i2c"); 1289 if (pdata->id < 0) 1290 pdata->id = -1; 1291 1292 pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0, 1293 &pdata->irq_trigger); 1294 if (gpio_is_valid(pdata->irq_gpio)) 1295 pdata->irq_over_gpio = 1; 1296 else 1297 pdata->irq_trigger = IRQF_TRIGGER_NONE; 1298 1299 of_property_read_u32(np, "st,autosleep-timeout", 1300 &pdata->autosleep_timeout); 1301 1302 pdata->autosleep = (pdata->autosleep_timeout) ? true : false; 1303 1304 for_each_child_of_node(np, child) { 1305 if (of_node_name_eq(child, "stmpe_gpio")) { 1306 pdata->blocks |= STMPE_BLOCK_GPIO; 1307 } else if (of_node_name_eq(child, "stmpe_keypad")) { 1308 pdata->blocks |= STMPE_BLOCK_KEYPAD; 1309 } else if (of_node_name_eq(child, "stmpe_touchscreen")) { 1310 pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN; 1311 } else if (of_node_name_eq(child, "stmpe_adc")) { 1312 pdata->blocks |= STMPE_BLOCK_ADC; 1313 } else if (of_node_name_eq(child, "stmpe_pwm")) { 1314 pdata->blocks |= STMPE_BLOCK_PWM; 1315 } else if (of_node_name_eq(child, "stmpe_rotator")) { 1316 pdata->blocks |= STMPE_BLOCK_ROTATOR; 1317 } 1318 } 1319 } 1320 1321 /* Called from client specific probe routines */ 1322 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) 1323 { 1324 struct stmpe_platform_data *pdata; 1325 struct device_node *np = ci->dev->of_node; 1326 struct stmpe *stmpe; 1327 int ret; 1328 1329 pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL); 1330 if (!pdata) 1331 return -ENOMEM; 1332 1333 stmpe_of_probe(pdata, np); 1334 1335 if (of_find_property(np, "interrupts", NULL) == NULL) 1336 ci->irq = -1; 1337 1338 stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL); 1339 if (!stmpe) 1340 return -ENOMEM; 1341 1342 mutex_init(&stmpe->irq_lock); 1343 mutex_init(&stmpe->lock); 1344 1345 stmpe->dev = ci->dev; 1346 stmpe->client = ci->client; 1347 stmpe->pdata = pdata; 1348 stmpe->ci = ci; 1349 stmpe->partnum = partnum; 1350 stmpe->variant = stmpe_variant_info[partnum]; 1351 stmpe->regs = stmpe->variant->regs; 1352 stmpe->num_gpios = stmpe->variant->num_gpios; 1353 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc"); 1354 if (!IS_ERR(stmpe->vcc)) { 1355 ret = regulator_enable(stmpe->vcc); 1356 if (ret) 1357 dev_warn(ci->dev, "failed to enable VCC supply\n"); 1358 } 1359 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio"); 1360 if (!IS_ERR(stmpe->vio)) { 1361 ret = regulator_enable(stmpe->vio); 1362 if (ret) 1363 dev_warn(ci->dev, "failed to enable VIO supply\n"); 1364 } 1365 dev_set_drvdata(stmpe->dev, stmpe); 1366 1367 if (ci->init) 1368 ci->init(stmpe); 1369 1370 if (pdata->irq_over_gpio) { 1371 ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio, 1372 GPIOF_DIR_IN, "stmpe"); 1373 if (ret) { 1374 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", 1375 ret); 1376 return ret; 1377 } 1378 1379 stmpe->irq = gpio_to_irq(pdata->irq_gpio); 1380 } else { 1381 stmpe->irq = ci->irq; 1382 } 1383 1384 if (stmpe->irq < 0) { 1385 /* use alternate variant info for no-irq mode, if supported */ 1386 dev_info(stmpe->dev, 1387 "%s configured in no-irq mode by platform data\n", 1388 stmpe->variant->name); 1389 if (!stmpe_noirq_variant_info[stmpe->partnum]) { 1390 dev_err(stmpe->dev, 1391 "%s does not support no-irq mode!\n", 1392 stmpe->variant->name); 1393 return -ENODEV; 1394 } 1395 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum]; 1396 } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) { 1397 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq); 1398 } 1399 1400 ret = stmpe_chip_init(stmpe); 1401 if (ret) 1402 return ret; 1403 1404 if (stmpe->irq >= 0) { 1405 ret = stmpe_irq_init(stmpe, np); 1406 if (ret) 1407 return ret; 1408 1409 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL, 1410 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT, 1411 "stmpe", stmpe); 1412 if (ret) { 1413 dev_err(stmpe->dev, "failed to request IRQ: %d\n", 1414 ret); 1415 return ret; 1416 } 1417 } 1418 1419 ret = stmpe_devices_init(stmpe); 1420 if (!ret) 1421 return 0; 1422 1423 dev_err(stmpe->dev, "failed to add children\n"); 1424 mfd_remove_devices(stmpe->dev); 1425 1426 return ret; 1427 } 1428 1429 int stmpe_remove(struct stmpe *stmpe) 1430 { 1431 if (!IS_ERR(stmpe->vio)) 1432 regulator_disable(stmpe->vio); 1433 if (!IS_ERR(stmpe->vcc)) 1434 regulator_disable(stmpe->vcc); 1435 1436 mfd_remove_devices(stmpe->dev); 1437 1438 return 0; 1439 } 1440 1441 #ifdef CONFIG_PM 1442 static int stmpe_suspend(struct device *dev) 1443 { 1444 struct stmpe *stmpe = dev_get_drvdata(dev); 1445 1446 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1447 enable_irq_wake(stmpe->irq); 1448 1449 return 0; 1450 } 1451 1452 static int stmpe_resume(struct device *dev) 1453 { 1454 struct stmpe *stmpe = dev_get_drvdata(dev); 1455 1456 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1457 disable_irq_wake(stmpe->irq); 1458 1459 return 0; 1460 } 1461 1462 const struct dev_pm_ops stmpe_dev_pm_ops = { 1463 .suspend = stmpe_suspend, 1464 .resume = stmpe_resume, 1465 }; 1466 #endif 1467