1 /* 2 * ST Microelectronics MFD: stmpe's driver 3 * 4 * Copyright (C) ST-Ericsson SA 2010 5 * 6 * License Terms: GNU General Public License, version 2 7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 8 */ 9 10 #include <linux/err.h> 11 #include <linux/gpio.h> 12 #include <linux/export.h> 13 #include <linux/kernel.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pm.h> 20 #include <linux/slab.h> 21 #include <linux/mfd/core.h> 22 #include <linux/delay.h> 23 #include <linux/regulator/consumer.h> 24 #include "stmpe.h" 25 26 /** 27 * struct stmpe_platform_data - STMPE platform data 28 * @id: device id to distinguish between multiple STMPEs on the same board 29 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*) 30 * @irq_trigger: IRQ trigger to use for the interrupt to the host 31 * @autosleep: bool to enable/disable stmpe autosleep 32 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep 33 * @irq_over_gpio: true if gpio is used to get irq 34 * @irq_gpio: gpio number over which irq will be requested (significant only if 35 * irq_over_gpio is true) 36 */ 37 struct stmpe_platform_data { 38 int id; 39 unsigned int blocks; 40 unsigned int irq_trigger; 41 bool autosleep; 42 bool irq_over_gpio; 43 int irq_gpio; 44 int autosleep_timeout; 45 }; 46 47 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 48 { 49 return stmpe->variant->enable(stmpe, blocks, true); 50 } 51 52 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 53 { 54 return stmpe->variant->enable(stmpe, blocks, false); 55 } 56 57 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg) 58 { 59 int ret; 60 61 ret = stmpe->ci->read_byte(stmpe, reg); 62 if (ret < 0) 63 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); 64 65 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); 66 67 return ret; 68 } 69 70 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 71 { 72 int ret; 73 74 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); 75 76 ret = stmpe->ci->write_byte(stmpe, reg, val); 77 if (ret < 0) 78 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret); 79 80 return ret; 81 } 82 83 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 84 { 85 int ret; 86 87 ret = __stmpe_reg_read(stmpe, reg); 88 if (ret < 0) 89 return ret; 90 91 ret &= ~mask; 92 ret |= val; 93 94 return __stmpe_reg_write(stmpe, reg, ret); 95 } 96 97 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, 98 u8 *values) 99 { 100 int ret; 101 102 ret = stmpe->ci->read_block(stmpe, reg, length, values); 103 if (ret < 0) 104 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret); 105 106 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret); 107 stmpe_dump_bytes("stmpe rd: ", values, length); 108 109 return ret; 110 } 111 112 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 113 const u8 *values) 114 { 115 int ret; 116 117 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length); 118 stmpe_dump_bytes("stmpe wr: ", values, length); 119 120 ret = stmpe->ci->write_block(stmpe, reg, length, values); 121 if (ret < 0) 122 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret); 123 124 return ret; 125 } 126 127 /** 128 * stmpe_enable - enable blocks on an STMPE device 129 * @stmpe: Device to work on 130 * @blocks: Mask of blocks (enum stmpe_block values) to enable 131 */ 132 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks) 133 { 134 int ret; 135 136 mutex_lock(&stmpe->lock); 137 ret = __stmpe_enable(stmpe, blocks); 138 mutex_unlock(&stmpe->lock); 139 140 return ret; 141 } 142 EXPORT_SYMBOL_GPL(stmpe_enable); 143 144 /** 145 * stmpe_disable - disable blocks on an STMPE device 146 * @stmpe: Device to work on 147 * @blocks: Mask of blocks (enum stmpe_block values) to enable 148 */ 149 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks) 150 { 151 int ret; 152 153 mutex_lock(&stmpe->lock); 154 ret = __stmpe_disable(stmpe, blocks); 155 mutex_unlock(&stmpe->lock); 156 157 return ret; 158 } 159 EXPORT_SYMBOL_GPL(stmpe_disable); 160 161 /** 162 * stmpe_reg_read() - read a single STMPE register 163 * @stmpe: Device to read from 164 * @reg: Register to read 165 */ 166 int stmpe_reg_read(struct stmpe *stmpe, u8 reg) 167 { 168 int ret; 169 170 mutex_lock(&stmpe->lock); 171 ret = __stmpe_reg_read(stmpe, reg); 172 mutex_unlock(&stmpe->lock); 173 174 return ret; 175 } 176 EXPORT_SYMBOL_GPL(stmpe_reg_read); 177 178 /** 179 * stmpe_reg_write() - write a single STMPE register 180 * @stmpe: Device to write to 181 * @reg: Register to write 182 * @val: Value to write 183 */ 184 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) 185 { 186 int ret; 187 188 mutex_lock(&stmpe->lock); 189 ret = __stmpe_reg_write(stmpe, reg, val); 190 mutex_unlock(&stmpe->lock); 191 192 return ret; 193 } 194 EXPORT_SYMBOL_GPL(stmpe_reg_write); 195 196 /** 197 * stmpe_set_bits() - set the value of a bitfield in a STMPE register 198 * @stmpe: Device to write to 199 * @reg: Register to write 200 * @mask: Mask of bits to set 201 * @val: Value to set 202 */ 203 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) 204 { 205 int ret; 206 207 mutex_lock(&stmpe->lock); 208 ret = __stmpe_set_bits(stmpe, reg, mask, val); 209 mutex_unlock(&stmpe->lock); 210 211 return ret; 212 } 213 EXPORT_SYMBOL_GPL(stmpe_set_bits); 214 215 /** 216 * stmpe_block_read() - read multiple STMPE registers 217 * @stmpe: Device to read from 218 * @reg: First register 219 * @length: Number of registers 220 * @values: Buffer to write to 221 */ 222 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) 223 { 224 int ret; 225 226 mutex_lock(&stmpe->lock); 227 ret = __stmpe_block_read(stmpe, reg, length, values); 228 mutex_unlock(&stmpe->lock); 229 230 return ret; 231 } 232 EXPORT_SYMBOL_GPL(stmpe_block_read); 233 234 /** 235 * stmpe_block_write() - write multiple STMPE registers 236 * @stmpe: Device to write to 237 * @reg: First register 238 * @length: Number of registers 239 * @values: Values to write 240 */ 241 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, 242 const u8 *values) 243 { 244 int ret; 245 246 mutex_lock(&stmpe->lock); 247 ret = __stmpe_block_write(stmpe, reg, length, values); 248 mutex_unlock(&stmpe->lock); 249 250 return ret; 251 } 252 EXPORT_SYMBOL_GPL(stmpe_block_write); 253 254 /** 255 * stmpe_set_altfunc()- set the alternate function for STMPE pins 256 * @stmpe: Device to configure 257 * @pins: Bitmask of pins to affect 258 * @block: block to enable alternate functions for 259 * 260 * @pins is assumed to have a bit set for each of the bits whose alternate 261 * function is to be changed, numbered according to the GPIOXY numbers. 262 * 263 * If the GPIO module is not enabled, this function automatically enables it in 264 * order to perform the change. 265 */ 266 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block) 267 { 268 struct stmpe_variant_info *variant = stmpe->variant; 269 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB]; 270 int af_bits = variant->af_bits; 271 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8); 272 int mask = (1 << af_bits) - 1; 273 u8 regs[8]; 274 int af, afperreg, ret; 275 276 if (!variant->get_altfunc) 277 return 0; 278 279 afperreg = 8 / af_bits; 280 mutex_lock(&stmpe->lock); 281 282 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 283 if (ret < 0) 284 goto out; 285 286 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs); 287 if (ret < 0) 288 goto out; 289 290 af = variant->get_altfunc(stmpe, block); 291 292 while (pins) { 293 int pin = __ffs(pins); 294 int regoffset = numregs - (pin / afperreg) - 1; 295 int pos = (pin % afperreg) * (8 / afperreg); 296 297 regs[regoffset] &= ~(mask << pos); 298 regs[regoffset] |= af << pos; 299 300 pins &= ~(1 << pin); 301 } 302 303 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs); 304 305 out: 306 mutex_unlock(&stmpe->lock); 307 return ret; 308 } 309 EXPORT_SYMBOL_GPL(stmpe_set_altfunc); 310 311 /* 312 * GPIO (all variants) 313 */ 314 315 static struct resource stmpe_gpio_resources[] = { 316 /* Start and end filled dynamically */ 317 { 318 .flags = IORESOURCE_IRQ, 319 }, 320 }; 321 322 static const struct mfd_cell stmpe_gpio_cell = { 323 .name = "stmpe-gpio", 324 .of_compatible = "st,stmpe-gpio", 325 .resources = stmpe_gpio_resources, 326 .num_resources = ARRAY_SIZE(stmpe_gpio_resources), 327 }; 328 329 static const struct mfd_cell stmpe_gpio_cell_noirq = { 330 .name = "stmpe-gpio", 331 .of_compatible = "st,stmpe-gpio", 332 /* gpio cell resources consist of an irq only so no resources here */ 333 }; 334 335 /* 336 * Keypad (1601, 2401, 2403) 337 */ 338 339 static struct resource stmpe_keypad_resources[] = { 340 { 341 .name = "KEYPAD", 342 .flags = IORESOURCE_IRQ, 343 }, 344 { 345 .name = "KEYPAD_OVER", 346 .flags = IORESOURCE_IRQ, 347 }, 348 }; 349 350 static const struct mfd_cell stmpe_keypad_cell = { 351 .name = "stmpe-keypad", 352 .of_compatible = "st,stmpe-keypad", 353 .resources = stmpe_keypad_resources, 354 .num_resources = ARRAY_SIZE(stmpe_keypad_resources), 355 }; 356 357 /* 358 * PWM (1601, 2401, 2403) 359 */ 360 static struct resource stmpe_pwm_resources[] = { 361 { 362 .name = "PWM0", 363 .flags = IORESOURCE_IRQ, 364 }, 365 { 366 .name = "PWM1", 367 .flags = IORESOURCE_IRQ, 368 }, 369 { 370 .name = "PWM2", 371 .flags = IORESOURCE_IRQ, 372 }, 373 }; 374 375 static const struct mfd_cell stmpe_pwm_cell = { 376 .name = "stmpe-pwm", 377 .of_compatible = "st,stmpe-pwm", 378 .resources = stmpe_pwm_resources, 379 .num_resources = ARRAY_SIZE(stmpe_pwm_resources), 380 }; 381 382 /* 383 * STMPE801 384 */ 385 static const u8 stmpe801_regs[] = { 386 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID, 387 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL, 388 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA, 389 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN, 390 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN, 391 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR, 392 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN, 393 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA, 394 395 }; 396 397 static struct stmpe_variant_block stmpe801_blocks[] = { 398 { 399 .cell = &stmpe_gpio_cell, 400 .irq = 0, 401 .block = STMPE_BLOCK_GPIO, 402 }, 403 }; 404 405 static struct stmpe_variant_block stmpe801_blocks_noirq[] = { 406 { 407 .cell = &stmpe_gpio_cell_noirq, 408 .block = STMPE_BLOCK_GPIO, 409 }, 410 }; 411 412 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks, 413 bool enable) 414 { 415 if (blocks & STMPE_BLOCK_GPIO) 416 return 0; 417 else 418 return -EINVAL; 419 } 420 421 static struct stmpe_variant_info stmpe801 = { 422 .name = "stmpe801", 423 .id_val = STMPE801_ID, 424 .id_mask = 0xffff, 425 .num_gpios = 8, 426 .regs = stmpe801_regs, 427 .blocks = stmpe801_blocks, 428 .num_blocks = ARRAY_SIZE(stmpe801_blocks), 429 .num_irqs = STMPE801_NR_INTERNAL_IRQS, 430 .enable = stmpe801_enable, 431 }; 432 433 static struct stmpe_variant_info stmpe801_noirq = { 434 .name = "stmpe801", 435 .id_val = STMPE801_ID, 436 .id_mask = 0xffff, 437 .num_gpios = 8, 438 .regs = stmpe801_regs, 439 .blocks = stmpe801_blocks_noirq, 440 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq), 441 .enable = stmpe801_enable, 442 }; 443 444 /* 445 * Touchscreen (STMPE811 or STMPE610) 446 */ 447 448 static struct resource stmpe_ts_resources[] = { 449 { 450 .name = "TOUCH_DET", 451 .flags = IORESOURCE_IRQ, 452 }, 453 { 454 .name = "FIFO_TH", 455 .flags = IORESOURCE_IRQ, 456 }, 457 }; 458 459 static const struct mfd_cell stmpe_ts_cell = { 460 .name = "stmpe-ts", 461 .of_compatible = "st,stmpe-ts", 462 .resources = stmpe_ts_resources, 463 .num_resources = ARRAY_SIZE(stmpe_ts_resources), 464 }; 465 466 /* 467 * STMPE811 or STMPE610 468 */ 469 470 static const u8 stmpe811_regs[] = { 471 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, 472 [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL, 473 [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2, 474 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, 475 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, 476 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, 477 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA, 478 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN, 479 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN, 480 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR, 481 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE, 482 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE, 483 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, 484 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, 485 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, 486 [STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED, 487 }; 488 489 static struct stmpe_variant_block stmpe811_blocks[] = { 490 { 491 .cell = &stmpe_gpio_cell, 492 .irq = STMPE811_IRQ_GPIOC, 493 .block = STMPE_BLOCK_GPIO, 494 }, 495 { 496 .cell = &stmpe_ts_cell, 497 .irq = STMPE811_IRQ_TOUCH_DET, 498 .block = STMPE_BLOCK_TOUCHSCREEN, 499 }, 500 }; 501 502 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, 503 bool enable) 504 { 505 unsigned int mask = 0; 506 507 if (blocks & STMPE_BLOCK_GPIO) 508 mask |= STMPE811_SYS_CTRL2_GPIO_OFF; 509 510 if (blocks & STMPE_BLOCK_ADC) 511 mask |= STMPE811_SYS_CTRL2_ADC_OFF; 512 513 if (blocks & STMPE_BLOCK_TOUCHSCREEN) 514 mask |= STMPE811_SYS_CTRL2_TSC_OFF; 515 516 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, 517 enable ? 0 : mask); 518 } 519 520 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 521 { 522 /* 0 for touchscreen, 1 for GPIO */ 523 return block != STMPE_BLOCK_TOUCHSCREEN; 524 } 525 526 static struct stmpe_variant_info stmpe811 = { 527 .name = "stmpe811", 528 .id_val = 0x0811, 529 .id_mask = 0xffff, 530 .num_gpios = 8, 531 .af_bits = 1, 532 .regs = stmpe811_regs, 533 .blocks = stmpe811_blocks, 534 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 535 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 536 .enable = stmpe811_enable, 537 .get_altfunc = stmpe811_get_altfunc, 538 }; 539 540 /* Similar to 811, except number of gpios */ 541 static struct stmpe_variant_info stmpe610 = { 542 .name = "stmpe610", 543 .id_val = 0x0811, 544 .id_mask = 0xffff, 545 .num_gpios = 6, 546 .af_bits = 1, 547 .regs = stmpe811_regs, 548 .blocks = stmpe811_blocks, 549 .num_blocks = ARRAY_SIZE(stmpe811_blocks), 550 .num_irqs = STMPE811_NR_INTERNAL_IRQS, 551 .enable = stmpe811_enable, 552 .get_altfunc = stmpe811_get_altfunc, 553 }; 554 555 /* 556 * STMPE1601 557 */ 558 559 static const u8 stmpe1601_regs[] = { 560 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, 561 [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, 562 [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, 563 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, 564 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, 565 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, 566 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, 567 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, 568 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, 569 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, 570 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, 571 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, 572 [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB, 573 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, 574 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, 575 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, 576 [STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB, 577 }; 578 579 static struct stmpe_variant_block stmpe1601_blocks[] = { 580 { 581 .cell = &stmpe_gpio_cell, 582 .irq = STMPE1601_IRQ_GPIOC, 583 .block = STMPE_BLOCK_GPIO, 584 }, 585 { 586 .cell = &stmpe_keypad_cell, 587 .irq = STMPE1601_IRQ_KEYPAD, 588 .block = STMPE_BLOCK_KEYPAD, 589 }, 590 { 591 .cell = &stmpe_pwm_cell, 592 .irq = STMPE1601_IRQ_PWM0, 593 .block = STMPE_BLOCK_PWM, 594 }, 595 }; 596 597 /* supported autosleep timeout delay (in msecs) */ 598 static const int stmpe_autosleep_delay[] = { 599 4, 16, 32, 64, 128, 256, 512, 1024, 600 }; 601 602 static int stmpe_round_timeout(int timeout) 603 { 604 int i; 605 606 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) { 607 if (stmpe_autosleep_delay[i] >= timeout) 608 return i; 609 } 610 611 /* 612 * requests for delays longer than supported should not return the 613 * longest supported delay 614 */ 615 return -EINVAL; 616 } 617 618 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout) 619 { 620 int ret; 621 622 if (!stmpe->variant->enable_autosleep) 623 return -ENOSYS; 624 625 mutex_lock(&stmpe->lock); 626 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout); 627 mutex_unlock(&stmpe->lock); 628 629 return ret; 630 } 631 632 /* 633 * Both stmpe 1601/2403 support same layout for autosleep 634 */ 635 static int stmpe1601_autosleep(struct stmpe *stmpe, 636 int autosleep_timeout) 637 { 638 int ret, timeout; 639 640 /* choose the best available timeout */ 641 timeout = stmpe_round_timeout(autosleep_timeout); 642 if (timeout < 0) { 643 dev_err(stmpe->dev, "invalid timeout\n"); 644 return timeout; 645 } 646 647 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 648 STMPE1601_AUTOSLEEP_TIMEOUT_MASK, 649 timeout); 650 if (ret < 0) 651 return ret; 652 653 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], 654 STPME1601_AUTOSLEEP_ENABLE, 655 STPME1601_AUTOSLEEP_ENABLE); 656 } 657 658 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks, 659 bool enable) 660 { 661 unsigned int mask = 0; 662 663 if (blocks & STMPE_BLOCK_GPIO) 664 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; 665 else 666 mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO; 667 668 if (blocks & STMPE_BLOCK_KEYPAD) 669 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; 670 else 671 mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC; 672 673 if (blocks & STMPE_BLOCK_PWM) 674 mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM; 675 else 676 mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; 677 678 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 679 enable ? mask : 0); 680 } 681 682 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 683 { 684 switch (block) { 685 case STMPE_BLOCK_PWM: 686 return 2; 687 688 case STMPE_BLOCK_KEYPAD: 689 return 1; 690 691 case STMPE_BLOCK_GPIO: 692 default: 693 return 0; 694 } 695 } 696 697 static struct stmpe_variant_info stmpe1601 = { 698 .name = "stmpe1601", 699 .id_val = 0x0210, 700 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */ 701 .num_gpios = 16, 702 .af_bits = 2, 703 .regs = stmpe1601_regs, 704 .blocks = stmpe1601_blocks, 705 .num_blocks = ARRAY_SIZE(stmpe1601_blocks), 706 .num_irqs = STMPE1601_NR_INTERNAL_IRQS, 707 .enable = stmpe1601_enable, 708 .get_altfunc = stmpe1601_get_altfunc, 709 .enable_autosleep = stmpe1601_autosleep, 710 }; 711 712 /* 713 * STMPE1801 714 */ 715 static const u8 stmpe1801_regs[] = { 716 [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID, 717 [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL, 718 [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW, 719 [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, 720 [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, 721 [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW, 722 [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW, 723 [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW, 724 [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW, 725 [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW, 726 [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW, 727 [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW, 728 [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW, 729 [STMPE_IDX_ISGPIOR_LSB] = STMPE1801_REG_INT_STA_GPIO_LOW, 730 }; 731 732 static struct stmpe_variant_block stmpe1801_blocks[] = { 733 { 734 .cell = &stmpe_gpio_cell, 735 .irq = STMPE1801_IRQ_GPIOC, 736 .block = STMPE_BLOCK_GPIO, 737 }, 738 { 739 .cell = &stmpe_keypad_cell, 740 .irq = STMPE1801_IRQ_KEYPAD, 741 .block = STMPE_BLOCK_KEYPAD, 742 }, 743 }; 744 745 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks, 746 bool enable) 747 { 748 unsigned int mask = 0; 749 if (blocks & STMPE_BLOCK_GPIO) 750 mask |= STMPE1801_MSK_INT_EN_GPIO; 751 752 if (blocks & STMPE_BLOCK_KEYPAD) 753 mask |= STMPE1801_MSK_INT_EN_KPC; 754 755 return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask, 756 enable ? mask : 0); 757 } 758 759 static int stmpe1801_reset(struct stmpe *stmpe) 760 { 761 unsigned long timeout; 762 int ret = 0; 763 764 ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], 765 STMPE1801_MSK_SYS_CTRL_RESET, STMPE1801_MSK_SYS_CTRL_RESET); 766 if (ret < 0) 767 return ret; 768 769 timeout = jiffies + msecs_to_jiffies(100); 770 while (time_before(jiffies, timeout)) { 771 ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); 772 if (ret < 0) 773 return ret; 774 if (!(ret & STMPE1801_MSK_SYS_CTRL_RESET)) 775 return 0; 776 usleep_range(100, 200); 777 } 778 return -EIO; 779 } 780 781 static struct stmpe_variant_info stmpe1801 = { 782 .name = "stmpe1801", 783 .id_val = STMPE1801_ID, 784 .id_mask = 0xfff0, 785 .num_gpios = 18, 786 .af_bits = 0, 787 .regs = stmpe1801_regs, 788 .blocks = stmpe1801_blocks, 789 .num_blocks = ARRAY_SIZE(stmpe1801_blocks), 790 .num_irqs = STMPE1801_NR_INTERNAL_IRQS, 791 .enable = stmpe1801_enable, 792 /* stmpe1801 do not have any gpio alternate function */ 793 .get_altfunc = NULL, 794 }; 795 796 /* 797 * STMPE24XX 798 */ 799 800 static const u8 stmpe24xx_regs[] = { 801 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, 802 [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, 803 [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, 804 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, 805 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, 806 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, 807 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, 808 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, 809 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, 810 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, 811 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, 812 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, 813 [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB, 814 [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB, 815 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, 816 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, 817 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, 818 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, 819 }; 820 821 static struct stmpe_variant_block stmpe24xx_blocks[] = { 822 { 823 .cell = &stmpe_gpio_cell, 824 .irq = STMPE24XX_IRQ_GPIOC, 825 .block = STMPE_BLOCK_GPIO, 826 }, 827 { 828 .cell = &stmpe_keypad_cell, 829 .irq = STMPE24XX_IRQ_KEYPAD, 830 .block = STMPE_BLOCK_KEYPAD, 831 }, 832 { 833 .cell = &stmpe_pwm_cell, 834 .irq = STMPE24XX_IRQ_PWM0, 835 .block = STMPE_BLOCK_PWM, 836 }, 837 }; 838 839 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks, 840 bool enable) 841 { 842 unsigned int mask = 0; 843 844 if (blocks & STMPE_BLOCK_GPIO) 845 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO; 846 847 if (blocks & STMPE_BLOCK_KEYPAD) 848 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; 849 850 return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, 851 enable ? mask : 0); 852 } 853 854 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) 855 { 856 switch (block) { 857 case STMPE_BLOCK_ROTATOR: 858 return 2; 859 860 case STMPE_BLOCK_KEYPAD: 861 case STMPE_BLOCK_PWM: 862 return 1; 863 864 case STMPE_BLOCK_GPIO: 865 default: 866 return 0; 867 } 868 } 869 870 static struct stmpe_variant_info stmpe2401 = { 871 .name = "stmpe2401", 872 .id_val = 0x0101, 873 .id_mask = 0xffff, 874 .num_gpios = 24, 875 .af_bits = 2, 876 .regs = stmpe24xx_regs, 877 .blocks = stmpe24xx_blocks, 878 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 879 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 880 .enable = stmpe24xx_enable, 881 .get_altfunc = stmpe24xx_get_altfunc, 882 }; 883 884 static struct stmpe_variant_info stmpe2403 = { 885 .name = "stmpe2403", 886 .id_val = 0x0120, 887 .id_mask = 0xffff, 888 .num_gpios = 24, 889 .af_bits = 2, 890 .regs = stmpe24xx_regs, 891 .blocks = stmpe24xx_blocks, 892 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), 893 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, 894 .enable = stmpe24xx_enable, 895 .get_altfunc = stmpe24xx_get_altfunc, 896 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */ 897 }; 898 899 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = { 900 [STMPE610] = &stmpe610, 901 [STMPE801] = &stmpe801, 902 [STMPE811] = &stmpe811, 903 [STMPE1601] = &stmpe1601, 904 [STMPE1801] = &stmpe1801, 905 [STMPE2401] = &stmpe2401, 906 [STMPE2403] = &stmpe2403, 907 }; 908 909 /* 910 * These devices can be connected in a 'no-irq' configuration - the irq pin 911 * is not used and the device cannot interrupt the CPU. Here we only list 912 * devices which support this configuration - the driver will fail probing 913 * for any devices not listed here which are configured in this way. 914 */ 915 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = { 916 [STMPE801] = &stmpe801_noirq, 917 }; 918 919 static irqreturn_t stmpe_irq(int irq, void *data) 920 { 921 struct stmpe *stmpe = data; 922 struct stmpe_variant_info *variant = stmpe->variant; 923 int num = DIV_ROUND_UP(variant->num_irqs, 8); 924 u8 israddr; 925 u8 isr[3]; 926 int ret; 927 int i; 928 929 if (variant->id_val == STMPE801_ID) { 930 int base = irq_create_mapping(stmpe->domain, 0); 931 932 handle_nested_irq(base); 933 return IRQ_HANDLED; 934 } 935 936 if (variant->id_val == STMPE1801_ID) 937 israddr = stmpe->regs[STMPE_IDX_ISR_LSB]; 938 else 939 israddr = stmpe->regs[STMPE_IDX_ISR_MSB]; 940 941 ret = stmpe_block_read(stmpe, israddr, num, isr); 942 if (ret < 0) 943 return IRQ_NONE; 944 945 for (i = 0; i < num; i++) { 946 int bank = num - i - 1; 947 u8 status = isr[i]; 948 u8 clear; 949 950 status &= stmpe->ier[bank]; 951 if (!status) 952 continue; 953 954 clear = status; 955 while (status) { 956 int bit = __ffs(status); 957 int line = bank * 8 + bit; 958 int nestedirq = irq_create_mapping(stmpe->domain, line); 959 960 handle_nested_irq(nestedirq); 961 status &= ~(1 << bit); 962 } 963 964 stmpe_reg_write(stmpe, israddr + i, clear); 965 } 966 967 return IRQ_HANDLED; 968 } 969 970 static void stmpe_irq_lock(struct irq_data *data) 971 { 972 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 973 974 mutex_lock(&stmpe->irq_lock); 975 } 976 977 static void stmpe_irq_sync_unlock(struct irq_data *data) 978 { 979 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 980 struct stmpe_variant_info *variant = stmpe->variant; 981 int num = DIV_ROUND_UP(variant->num_irqs, 8); 982 int i; 983 984 for (i = 0; i < num; i++) { 985 u8 new = stmpe->ier[i]; 986 u8 old = stmpe->oldier[i]; 987 988 if (new == old) 989 continue; 990 991 stmpe->oldier[i] = new; 992 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new); 993 } 994 995 mutex_unlock(&stmpe->irq_lock); 996 } 997 998 static void stmpe_irq_mask(struct irq_data *data) 999 { 1000 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1001 int offset = data->hwirq; 1002 int regoffset = offset / 8; 1003 int mask = 1 << (offset % 8); 1004 1005 stmpe->ier[regoffset] &= ~mask; 1006 } 1007 1008 static void stmpe_irq_unmask(struct irq_data *data) 1009 { 1010 struct stmpe *stmpe = irq_data_get_irq_chip_data(data); 1011 int offset = data->hwirq; 1012 int regoffset = offset / 8; 1013 int mask = 1 << (offset % 8); 1014 1015 stmpe->ier[regoffset] |= mask; 1016 } 1017 1018 static struct irq_chip stmpe_irq_chip = { 1019 .name = "stmpe", 1020 .irq_bus_lock = stmpe_irq_lock, 1021 .irq_bus_sync_unlock = stmpe_irq_sync_unlock, 1022 .irq_mask = stmpe_irq_mask, 1023 .irq_unmask = stmpe_irq_unmask, 1024 }; 1025 1026 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq, 1027 irq_hw_number_t hwirq) 1028 { 1029 struct stmpe *stmpe = d->host_data; 1030 struct irq_chip *chip = NULL; 1031 1032 if (stmpe->variant->id_val != STMPE801_ID) 1033 chip = &stmpe_irq_chip; 1034 1035 irq_set_chip_data(virq, stmpe); 1036 irq_set_chip_and_handler(virq, chip, handle_edge_irq); 1037 irq_set_nested_thread(virq, 1); 1038 irq_set_noprobe(virq); 1039 1040 return 0; 1041 } 1042 1043 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq) 1044 { 1045 irq_set_chip_and_handler(virq, NULL, NULL); 1046 irq_set_chip_data(virq, NULL); 1047 } 1048 1049 static const struct irq_domain_ops stmpe_irq_ops = { 1050 .map = stmpe_irq_map, 1051 .unmap = stmpe_irq_unmap, 1052 .xlate = irq_domain_xlate_twocell, 1053 }; 1054 1055 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np) 1056 { 1057 int base = 0; 1058 int num_irqs = stmpe->variant->num_irqs; 1059 1060 stmpe->domain = irq_domain_add_simple(np, num_irqs, base, 1061 &stmpe_irq_ops, stmpe); 1062 if (!stmpe->domain) { 1063 dev_err(stmpe->dev, "Failed to create irqdomain\n"); 1064 return -ENOSYS; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static int stmpe_chip_init(struct stmpe *stmpe) 1071 { 1072 unsigned int irq_trigger = stmpe->pdata->irq_trigger; 1073 int autosleep_timeout = stmpe->pdata->autosleep_timeout; 1074 struct stmpe_variant_info *variant = stmpe->variant; 1075 u8 icr = 0; 1076 unsigned int id; 1077 u8 data[2]; 1078 int ret; 1079 1080 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID], 1081 ARRAY_SIZE(data), data); 1082 if (ret < 0) 1083 return ret; 1084 1085 id = (data[0] << 8) | data[1]; 1086 if ((id & variant->id_mask) != variant->id_val) { 1087 dev_err(stmpe->dev, "unknown chip id: %#x\n", id); 1088 return -EINVAL; 1089 } 1090 1091 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id); 1092 1093 /* Disable all modules -- subdrivers should enable what they need. */ 1094 ret = stmpe_disable(stmpe, ~0); 1095 if (ret) 1096 return ret; 1097 1098 if (id == STMPE1801_ID) { 1099 ret = stmpe1801_reset(stmpe); 1100 if (ret < 0) 1101 return ret; 1102 } 1103 1104 if (stmpe->irq >= 0) { 1105 if (id == STMPE801_ID) 1106 icr = STMPE801_REG_SYS_CTRL_INT_EN; 1107 else 1108 icr = STMPE_ICR_LSB_GIM; 1109 1110 /* STMPE801 doesn't support Edge interrupts */ 1111 if (id != STMPE801_ID) { 1112 if (irq_trigger == IRQF_TRIGGER_FALLING || 1113 irq_trigger == IRQF_TRIGGER_RISING) 1114 icr |= STMPE_ICR_LSB_EDGE; 1115 } 1116 1117 if (irq_trigger == IRQF_TRIGGER_RISING || 1118 irq_trigger == IRQF_TRIGGER_HIGH) { 1119 if (id == STMPE801_ID) 1120 icr |= STMPE801_REG_SYS_CTRL_INT_HI; 1121 else 1122 icr |= STMPE_ICR_LSB_HIGH; 1123 } 1124 } 1125 1126 if (stmpe->pdata->autosleep) { 1127 ret = stmpe_autosleep(stmpe, autosleep_timeout); 1128 if (ret) 1129 return ret; 1130 } 1131 1132 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr); 1133 } 1134 1135 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell) 1136 { 1137 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1, 1138 NULL, 0, stmpe->domain); 1139 } 1140 1141 static int stmpe_devices_init(struct stmpe *stmpe) 1142 { 1143 struct stmpe_variant_info *variant = stmpe->variant; 1144 unsigned int platform_blocks = stmpe->pdata->blocks; 1145 int ret = -EINVAL; 1146 int i, j; 1147 1148 for (i = 0; i < variant->num_blocks; i++) { 1149 struct stmpe_variant_block *block = &variant->blocks[i]; 1150 1151 if (!(platform_blocks & block->block)) 1152 continue; 1153 1154 for (j = 0; j < block->cell->num_resources; j++) { 1155 struct resource *res = 1156 (struct resource *) &block->cell->resources[j]; 1157 1158 /* Dynamically fill in a variant's IRQ. */ 1159 if (res->flags & IORESOURCE_IRQ) 1160 res->start = res->end = block->irq + j; 1161 } 1162 1163 platform_blocks &= ~block->block; 1164 ret = stmpe_add_device(stmpe, block->cell); 1165 if (ret) 1166 return ret; 1167 } 1168 1169 if (platform_blocks) 1170 dev_warn(stmpe->dev, 1171 "platform wants blocks (%#x) not present on variant", 1172 platform_blocks); 1173 1174 return ret; 1175 } 1176 1177 static void stmpe_of_probe(struct stmpe_platform_data *pdata, 1178 struct device_node *np) 1179 { 1180 struct device_node *child; 1181 1182 pdata->id = of_alias_get_id(np, "stmpe-i2c"); 1183 if (pdata->id < 0) 1184 pdata->id = -1; 1185 1186 pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0, 1187 &pdata->irq_trigger); 1188 if (gpio_is_valid(pdata->irq_gpio)) 1189 pdata->irq_over_gpio = 1; 1190 else 1191 pdata->irq_trigger = IRQF_TRIGGER_NONE; 1192 1193 of_property_read_u32(np, "st,autosleep-timeout", 1194 &pdata->autosleep_timeout); 1195 1196 pdata->autosleep = (pdata->autosleep_timeout) ? true : false; 1197 1198 for_each_child_of_node(np, child) { 1199 if (!strcmp(child->name, "stmpe_gpio")) { 1200 pdata->blocks |= STMPE_BLOCK_GPIO; 1201 } else if (!strcmp(child->name, "stmpe_keypad")) { 1202 pdata->blocks |= STMPE_BLOCK_KEYPAD; 1203 } else if (!strcmp(child->name, "stmpe_touchscreen")) { 1204 pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN; 1205 } else if (!strcmp(child->name, "stmpe_adc")) { 1206 pdata->blocks |= STMPE_BLOCK_ADC; 1207 } else if (!strcmp(child->name, "stmpe_pwm")) { 1208 pdata->blocks |= STMPE_BLOCK_PWM; 1209 } else if (!strcmp(child->name, "stmpe_rotator")) { 1210 pdata->blocks |= STMPE_BLOCK_ROTATOR; 1211 } 1212 } 1213 } 1214 1215 /* Called from client specific probe routines */ 1216 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) 1217 { 1218 struct stmpe_platform_data *pdata; 1219 struct device_node *np = ci->dev->of_node; 1220 struct stmpe *stmpe; 1221 int ret; 1222 1223 pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL); 1224 if (!pdata) 1225 return -ENOMEM; 1226 1227 stmpe_of_probe(pdata, np); 1228 1229 if (of_find_property(np, "interrupts", NULL) == NULL) 1230 ci->irq = -1; 1231 1232 stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL); 1233 if (!stmpe) 1234 return -ENOMEM; 1235 1236 mutex_init(&stmpe->irq_lock); 1237 mutex_init(&stmpe->lock); 1238 1239 stmpe->dev = ci->dev; 1240 stmpe->client = ci->client; 1241 stmpe->pdata = pdata; 1242 stmpe->ci = ci; 1243 stmpe->partnum = partnum; 1244 stmpe->variant = stmpe_variant_info[partnum]; 1245 stmpe->regs = stmpe->variant->regs; 1246 stmpe->num_gpios = stmpe->variant->num_gpios; 1247 stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc"); 1248 if (!IS_ERR(stmpe->vcc)) { 1249 ret = regulator_enable(stmpe->vcc); 1250 if (ret) 1251 dev_warn(ci->dev, "failed to enable VCC supply\n"); 1252 } 1253 stmpe->vio = devm_regulator_get_optional(ci->dev, "vio"); 1254 if (!IS_ERR(stmpe->vio)) { 1255 ret = regulator_enable(stmpe->vio); 1256 if (ret) 1257 dev_warn(ci->dev, "failed to enable VIO supply\n"); 1258 } 1259 dev_set_drvdata(stmpe->dev, stmpe); 1260 1261 if (ci->init) 1262 ci->init(stmpe); 1263 1264 if (pdata->irq_over_gpio) { 1265 ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio, 1266 GPIOF_DIR_IN, "stmpe"); 1267 if (ret) { 1268 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", 1269 ret); 1270 return ret; 1271 } 1272 1273 stmpe->irq = gpio_to_irq(pdata->irq_gpio); 1274 } else { 1275 stmpe->irq = ci->irq; 1276 } 1277 1278 if (stmpe->irq < 0) { 1279 /* use alternate variant info for no-irq mode, if supported */ 1280 dev_info(stmpe->dev, 1281 "%s configured in no-irq mode by platform data\n", 1282 stmpe->variant->name); 1283 if (!stmpe_noirq_variant_info[stmpe->partnum]) { 1284 dev_err(stmpe->dev, 1285 "%s does not support no-irq mode!\n", 1286 stmpe->variant->name); 1287 return -ENODEV; 1288 } 1289 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum]; 1290 } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) { 1291 pdata->irq_trigger = irq_get_trigger_type(stmpe->irq); 1292 } 1293 1294 ret = stmpe_chip_init(stmpe); 1295 if (ret) 1296 return ret; 1297 1298 if (stmpe->irq >= 0) { 1299 ret = stmpe_irq_init(stmpe, np); 1300 if (ret) 1301 return ret; 1302 1303 ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL, 1304 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT, 1305 "stmpe", stmpe); 1306 if (ret) { 1307 dev_err(stmpe->dev, "failed to request IRQ: %d\n", 1308 ret); 1309 return ret; 1310 } 1311 } 1312 1313 ret = stmpe_devices_init(stmpe); 1314 if (!ret) 1315 return 0; 1316 1317 dev_err(stmpe->dev, "failed to add children\n"); 1318 mfd_remove_devices(stmpe->dev); 1319 1320 return ret; 1321 } 1322 1323 int stmpe_remove(struct stmpe *stmpe) 1324 { 1325 if (!IS_ERR(stmpe->vio)) 1326 regulator_disable(stmpe->vio); 1327 if (!IS_ERR(stmpe->vcc)) 1328 regulator_disable(stmpe->vcc); 1329 1330 mfd_remove_devices(stmpe->dev); 1331 1332 return 0; 1333 } 1334 1335 #ifdef CONFIG_PM 1336 static int stmpe_suspend(struct device *dev) 1337 { 1338 struct stmpe *stmpe = dev_get_drvdata(dev); 1339 1340 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1341 enable_irq_wake(stmpe->irq); 1342 1343 return 0; 1344 } 1345 1346 static int stmpe_resume(struct device *dev) 1347 { 1348 struct stmpe *stmpe = dev_get_drvdata(dev); 1349 1350 if (stmpe->irq >= 0 && device_may_wakeup(dev)) 1351 disable_irq_wake(stmpe->irq); 1352 1353 return 0; 1354 } 1355 1356 const struct dev_pm_ops stmpe_dev_pm_ops = { 1357 .suspend = stmpe_suspend, 1358 .resume = stmpe_resume, 1359 }; 1360 #endif 1361