xref: /openbmc/linux/drivers/mfd/sta2x11-mfd.c (revision 8a10bc9d) 
1 /*
2  * Copyright (c) 2009-2011 Wind River Systems, Inc.
3  * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12  * See the GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17  *
18  */
19 
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/errno.h>
24 #include <linux/device.h>
25 #include <linux/slab.h>
26 #include <linux/list.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/seq_file.h>
31 #include <linux/platform_device.h>
32 #include <linux/mfd/core.h>
33 #include <linux/mfd/sta2x11-mfd.h>
34 #include <linux/regmap.h>
35 
36 #include <asm/sta2x11.h>
37 
38 static inline int __reg_within_range(unsigned int r,
39 				     unsigned int start,
40 				     unsigned int end)
41 {
42 	return ((r >= start) && (r <= end));
43 }
44 
45 /* This describes STA2X11 MFD chip for us, we may have several */
46 struct sta2x11_mfd {
47 	struct sta2x11_instance *instance;
48 	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
49 	spinlock_t lock[sta2x11_n_mfd_plat_devs];
50 	struct list_head list;
51 	void __iomem *regs[sta2x11_n_mfd_plat_devs];
52 };
53 
54 static LIST_HEAD(sta2x11_mfd_list);
55 
56 /* Three functions to act on the list */
57 static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
58 {
59 	struct sta2x11_instance *instance;
60 	struct sta2x11_mfd *mfd;
61 
62 	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
63 		pr_warning("%s: Unspecified device, "
64 			    "using first instance\n", __func__);
65 		return list_entry(sta2x11_mfd_list.next,
66 				  struct sta2x11_mfd, list);
67 	}
68 
69 	instance = sta2x11_get_instance(pdev);
70 	if (!instance)
71 		return NULL;
72 	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
73 		if (mfd->instance == instance)
74 			return mfd;
75 	}
76 	return NULL;
77 }
78 
79 static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
80 {
81 	int i;
82 	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
83 	struct sta2x11_instance *instance;
84 
85 	if (mfd)
86 		return -EBUSY;
87 	instance = sta2x11_get_instance(pdev);
88 	if (!instance)
89 		return -EINVAL;
90 	mfd = kzalloc(sizeof(*mfd), flags);
91 	if (!mfd)
92 		return -ENOMEM;
93 	INIT_LIST_HEAD(&mfd->list);
94 	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
95 		spin_lock_init(&mfd->lock[i]);
96 	mfd->instance = instance;
97 	list_add(&mfd->list, &sta2x11_mfd_list);
98 	return 0;
99 }
100 
101 /* This function is exported and is not expected to fail */
102 u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
103 		       enum sta2x11_mfd_plat_dev index)
104 {
105 	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
106 	u32 r;
107 	unsigned long flags;
108 	void __iomem *regs;
109 
110 	if (!mfd) {
111 		dev_warn(&pdev->dev, ": can't access sctl regs\n");
112 		return 0;
113 	}
114 
115 	regs = mfd->regs[index];
116 	if (!regs) {
117 		dev_warn(&pdev->dev, ": system ctl not initialized\n");
118 		return 0;
119 	}
120 	spin_lock_irqsave(&mfd->lock[index], flags);
121 	r = readl(regs + reg);
122 	r &= ~mask;
123 	r |= val;
124 	if (mask)
125 		writel(r, regs + reg);
126 	spin_unlock_irqrestore(&mfd->lock[index], flags);
127 	return r;
128 }
129 EXPORT_SYMBOL(__sta2x11_mfd_mask);
130 
131 int sta2x11_mfd_get_regs_data(struct platform_device *dev,
132 			      enum sta2x11_mfd_plat_dev index,
133 			      void __iomem **regs,
134 			      spinlock_t **lock)
135 {
136 	struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
137 	struct sta2x11_mfd *mfd;
138 
139 	if (!pdev)
140 		return -ENODEV;
141 	mfd = sta2x11_mfd_find(pdev);
142 	if (!mfd)
143 		return -ENODEV;
144 	if (index >= sta2x11_n_mfd_plat_devs)
145 		return -ENODEV;
146 	*regs = mfd->regs[index];
147 	*lock = &mfd->lock[index];
148 	pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
149 	return *regs ? 0 : -ENODEV;
150 }
151 EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
152 
153 /*
154  * Special sta2x11-mfd regmap lock/unlock functions
155  */
156 
157 static void sta2x11_regmap_lock(void *__lock)
158 {
159 	spinlock_t *lock = __lock;
160 	spin_lock(lock);
161 }
162 
163 static void sta2x11_regmap_unlock(void *__lock)
164 {
165 	spinlock_t *lock = __lock;
166 	spin_unlock(lock);
167 }
168 
169 /* OTP (one time programmable registers do not require locking */
170 static void sta2x11_regmap_nolock(void *__lock)
171 {
172 }
173 
174 static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
175 	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
176 	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
177 	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
178 	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
179 };
180 
181 static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
182 {
183 	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
184 }
185 
186 static struct regmap_config sta2x11_sctl_regmap_config = {
187 	.reg_bits = 32,
188 	.reg_stride = 4,
189 	.val_bits = 32,
190 	.lock = sta2x11_regmap_lock,
191 	.unlock = sta2x11_regmap_unlock,
192 	.max_register = SCTL_SCRSTSTA,
193 	.writeable_reg = sta2x11_sctl_writeable_reg,
194 };
195 
196 static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
197 {
198 	return (reg == STA2X11_SECR_CR) ||
199 		__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
200 }
201 
202 static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
203 {
204 	return false;
205 }
206 
207 static struct regmap_config sta2x11_scr_regmap_config = {
208 	.reg_bits = 32,
209 	.reg_stride = 4,
210 	.val_bits = 32,
211 	.lock = sta2x11_regmap_nolock,
212 	.unlock = sta2x11_regmap_nolock,
213 	.max_register = STA2X11_SECR_FVR1,
214 	.readable_reg = sta2x11_scr_readable_reg,
215 	.writeable_reg = sta2x11_scr_writeable_reg,
216 };
217 
218 static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
219 {
220 	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
221 	if (reg >= APBREG_BSR_SARAC)
222 		reg -= APBREG_BSR_SARAC;
223 	switch (reg) {
224 	case APBREG_BSR:
225 	case APBREG_PAER:
226 	case APBREG_PWAC:
227 	case APBREG_PRAC:
228 	case APBREG_PCG:
229 	case APBREG_PUR:
230 	case APBREG_EMU_PCG:
231 		return true;
232 	default:
233 		return false;
234 	}
235 }
236 
237 static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
238 {
239 	if (reg >= APBREG_BSR_SARAC)
240 		reg -= APBREG_BSR_SARAC;
241 	if (!sta2x11_apbreg_readable_reg(dev, reg))
242 		return false;
243 	return reg != APBREG_PAER;
244 }
245 
246 static struct regmap_config sta2x11_apbreg_regmap_config = {
247 	.reg_bits = 32,
248 	.reg_stride = 4,
249 	.val_bits = 32,
250 	.lock = sta2x11_regmap_lock,
251 	.unlock = sta2x11_regmap_unlock,
252 	.max_register = APBREG_EMU_PCG_SARAC,
253 	.readable_reg = sta2x11_apbreg_readable_reg,
254 	.writeable_reg = sta2x11_apbreg_writeable_reg,
255 };
256 
257 static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
258 					      unsigned int reg)
259 {
260 	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
261 		__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
262 		__reg_within_range(reg, MASTER_LOCK_REG,
263 				   SYSTEM_CONFIG_STATUS_REG) ||
264 		reg == MSP_CLK_CTRL_REG ||
265 		__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
266 }
267 
268 static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
269 					       unsigned int reg)
270 {
271 	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
272 		return false;
273 	switch (reg) {
274 	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
275 	case SYSTEM_CONFIG_STATUS_REG:
276 	case COMPENSATION_REG1:
277 	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
278 	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
279 		return false;
280 	default:
281 		return true;
282 	}
283 }
284 
285 static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
286 	.reg_bits = 32,
287 	.reg_stride = 4,
288 	.val_bits = 32,
289 	.lock = sta2x11_regmap_lock,
290 	.unlock = sta2x11_regmap_unlock,
291 	.max_register = TEST_CTL_REG,
292 	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
293 	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
294 };
295 
296 static struct regmap_config *
297 sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
298 	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
299 	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
300 	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
301 	[sta2x11_scr] = &sta2x11_scr_regmap_config,
302 };
303 
304 /* Probe for the four platform devices */
305 
306 static int sta2x11_mfd_platform_probe(struct platform_device *dev,
307 				      enum sta2x11_mfd_plat_dev index)
308 {
309 	struct pci_dev **pdev;
310 	struct sta2x11_mfd *mfd;
311 	struct resource *res;
312 	const char *name = sta2x11_mfd_names[index];
313 	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
314 
315 	pdev = dev_get_platdata(&dev->dev);
316 	mfd = sta2x11_mfd_find(*pdev);
317 	if (!mfd)
318 		return -ENODEV;
319 	if (!regmap_config)
320 		return -ENODEV;
321 
322 	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
323 	if (!res)
324 		return -ENOMEM;
325 
326 	if (!request_mem_region(res->start, resource_size(res), name))
327 		return -EBUSY;
328 
329 	mfd->regs[index] = ioremap(res->start, resource_size(res));
330 	if (!mfd->regs[index]) {
331 		release_mem_region(res->start, resource_size(res));
332 		return -ENOMEM;
333 	}
334 	regmap_config->lock_arg = &mfd->lock;
335 	/*
336 	   No caching, registers could be reached both via regmap and via
337 	   void __iomem *
338 	*/
339 	regmap_config->cache_type = REGCACHE_NONE;
340 	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
341 						   regmap_config);
342 	WARN_ON(IS_ERR(mfd->regmap[index]));
343 
344 	return 0;
345 }
346 
347 static int sta2x11_sctl_probe(struct platform_device *dev)
348 {
349 	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
350 }
351 
352 static int sta2x11_apbreg_probe(struct platform_device *dev)
353 {
354 	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
355 }
356 
357 static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
358 {
359 	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
360 }
361 
362 static int sta2x11_scr_probe(struct platform_device *dev)
363 {
364 	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
365 }
366 
367 /* The three platform drivers */
368 static struct platform_driver sta2x11_sctl_platform_driver = {
369 	.driver = {
370 		.name	= STA2X11_MFD_SCTL_NAME,
371 		.owner	= THIS_MODULE,
372 	},
373 	.probe		= sta2x11_sctl_probe,
374 };
375 
376 static int __init sta2x11_sctl_init(void)
377 {
378 	pr_info("%s\n", __func__);
379 	return platform_driver_register(&sta2x11_sctl_platform_driver);
380 }
381 
382 static struct platform_driver sta2x11_platform_driver = {
383 	.driver = {
384 		.name	= STA2X11_MFD_APBREG_NAME,
385 		.owner	= THIS_MODULE,
386 	},
387 	.probe		= sta2x11_apbreg_probe,
388 };
389 
390 static int __init sta2x11_apbreg_init(void)
391 {
392 	pr_info("%s\n", __func__);
393 	return platform_driver_register(&sta2x11_platform_driver);
394 }
395 
396 static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
397 	.driver = {
398 		.name	= STA2X11_MFD_APB_SOC_REGS_NAME,
399 		.owner	= THIS_MODULE,
400 	},
401 	.probe		= sta2x11_apb_soc_regs_probe,
402 };
403 
404 static int __init sta2x11_apb_soc_regs_init(void)
405 {
406 	pr_info("%s\n", __func__);
407 	return platform_driver_register(&sta2x11_apb_soc_regs_platform_driver);
408 }
409 
410 static struct platform_driver sta2x11_scr_platform_driver = {
411 	.driver = {
412 		.name = STA2X11_MFD_SCR_NAME,
413 		.owner = THIS_MODULE,
414 	},
415 	.probe = sta2x11_scr_probe,
416 };
417 
418 static int __init sta2x11_scr_init(void)
419 {
420 	pr_info("%s\n", __func__);
421 	return platform_driver_register(&sta2x11_scr_platform_driver);
422 }
423 
424 
425 /*
426  * What follows are the PCI devices that host the above pdevs.
427  * Each logic block is 4kB and they are all consecutive: we use this info.
428  */
429 
430 /* Mfd 0 device */
431 
432 /* Mfd 0, Bar 0 */
433 enum mfd0_bar0_cells {
434 	STA2X11_GPIO_0 = 0,
435 	STA2X11_GPIO_1,
436 	STA2X11_GPIO_2,
437 	STA2X11_GPIO_3,
438 	STA2X11_SCTL,
439 	STA2X11_SCR,
440 	STA2X11_TIME,
441 };
442 /* Mfd 0 , Bar 1 */
443 enum mfd0_bar1_cells {
444 	STA2X11_APBREG = 0,
445 };
446 #define CELL_4K(_name, _cell) { \
447 		.name = _name, \
448 		.start = _cell * 4096, .end = _cell * 4096 + 4095, \
449 		.flags = IORESOURCE_MEM, \
450 		}
451 
452 static const struct resource gpio_resources[] = {
453 	{
454 		/* 4 consecutive cells, 1 driver */
455 		.name = STA2X11_MFD_GPIO_NAME,
456 		.start = 0,
457 		.end = (4 * 4096) - 1,
458 		.flags = IORESOURCE_MEM,
459 	}
460 };
461 static const struct resource sctl_resources[] = {
462 	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
463 };
464 static const struct resource scr_resources[] = {
465 	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
466 };
467 static const struct resource time_resources[] = {
468 	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
469 };
470 
471 static const struct resource apbreg_resources[] = {
472 	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
473 };
474 
475 #define DEV(_name, _r) \
476 	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
477 
478 static struct mfd_cell sta2x11_mfd0_bar0[] = {
479 	/* offset 0: we add pdata later */
480 	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
481 	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
482 	DEV(STA2X11_MFD_SCR_NAME,  scr_resources),
483 	DEV(STA2X11_MFD_TIME_NAME, time_resources),
484 };
485 
486 static struct mfd_cell sta2x11_mfd0_bar1[] = {
487 	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
488 };
489 
490 /* Mfd 1 devices */
491 
492 /* Mfd 1, Bar 0 */
493 enum mfd1_bar0_cells {
494 	STA2X11_VIC = 0,
495 };
496 
497 /* Mfd 1, Bar 1 */
498 enum mfd1_bar1_cells {
499 	STA2X11_APB_SOC_REGS = 0,
500 };
501 
502 static const struct resource vic_resources[] = {
503 	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
504 };
505 
506 static const struct resource apb_soc_regs_resources[] = {
507 	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
508 };
509 
510 static struct mfd_cell sta2x11_mfd1_bar0[] = {
511 	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
512 };
513 
514 static struct mfd_cell sta2x11_mfd1_bar1[] = {
515 	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
516 };
517 
518 
519 static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
520 {
521 	pci_save_state(pdev);
522 	pci_disable_device(pdev);
523 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
524 
525 	return 0;
526 }
527 
528 static int sta2x11_mfd_resume(struct pci_dev *pdev)
529 {
530 	int err;
531 
532 	pci_set_power_state(pdev, PCI_D0);
533 	err = pci_enable_device(pdev);
534 	if (err)
535 		return err;
536 	pci_restore_state(pdev);
537 
538 	return 0;
539 }
540 
541 struct sta2x11_mfd_bar_setup_data {
542 	struct mfd_cell *cells;
543 	int ncells;
544 };
545 
546 struct sta2x11_mfd_setup_data {
547 	struct sta2x11_mfd_bar_setup_data bars[2];
548 };
549 
550 #define STA2X11_MFD0 0
551 #define STA2X11_MFD1 1
552 
553 static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
554 	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
555 	[STA2X11_MFD0] = {
556 		.bars = {
557 			[0] = {
558 				.cells = sta2x11_mfd0_bar0,
559 				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
560 			},
561 			[1] = {
562 				.cells = sta2x11_mfd0_bar1,
563 				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
564 			},
565 		},
566 	},
567 	/* Mfd 1: vic / apb-soc-regs */
568 	[STA2X11_MFD1] = {
569 		.bars = {
570 			[0] = {
571 				.cells = sta2x11_mfd1_bar0,
572 				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
573 			},
574 			[1] = {
575 				.cells = sta2x11_mfd1_bar1,
576 				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
577 			},
578 		},
579 	},
580 };
581 
582 static void sta2x11_mfd_setup(struct pci_dev *pdev,
583 			      struct sta2x11_mfd_setup_data *sd)
584 {
585 	int i, j;
586 	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
587 		for (j = 0; j < sd->bars[i].ncells; j++) {
588 			sd->bars[i].cells[j].pdata_size = sizeof(pdev);
589 			sd->bars[i].cells[j].platform_data = &pdev;
590 		}
591 }
592 
593 static int sta2x11_mfd_probe(struct pci_dev *pdev,
594 			     const struct pci_device_id *pci_id)
595 {
596 	int err, i;
597 	struct sta2x11_mfd_setup_data *setup_data;
598 
599 	dev_info(&pdev->dev, "%s\n", __func__);
600 
601 	err = pci_enable_device(pdev);
602 	if (err) {
603 		dev_err(&pdev->dev, "Can't enable device.\n");
604 		return err;
605 	}
606 
607 	err = pci_enable_msi(pdev);
608 	if (err)
609 		dev_info(&pdev->dev, "Enable msi failed\n");
610 
611 	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
612 		&mfd_setup_data[STA2X11_MFD0] :
613 		&mfd_setup_data[STA2X11_MFD1];
614 
615 	/* platform data is the pci device for all of them */
616 	sta2x11_mfd_setup(pdev, setup_data);
617 
618 	/* Record this pdev before mfd_add_devices: their probe looks for it */
619 	if (!sta2x11_mfd_find(pdev))
620 		sta2x11_mfd_add(pdev, GFP_ATOMIC);
621 
622 	/* Just 2 bars for all mfd's at present */
623 	for (i = 0; i < 2; i++) {
624 		err = mfd_add_devices(&pdev->dev, -1,
625 				      setup_data->bars[i].cells,
626 				      setup_data->bars[i].ncells,
627 				      &pdev->resource[i],
628 				      0, NULL);
629 		if (err) {
630 			dev_err(&pdev->dev,
631 				"mfd_add_devices[%d] failed: %d\n", i, err);
632 			goto err_disable;
633 		}
634 	}
635 
636 	return 0;
637 
638 err_disable:
639 	mfd_remove_devices(&pdev->dev);
640 	pci_disable_device(pdev);
641 	pci_disable_msi(pdev);
642 	return err;
643 }
644 
645 static const struct pci_device_id sta2x11_mfd_tbl[] = {
646 	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
647 	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
648 	{0,},
649 };
650 
651 static struct pci_driver sta2x11_mfd_driver = {
652 	.name =		"sta2x11-mfd",
653 	.id_table =	sta2x11_mfd_tbl,
654 	.probe =	sta2x11_mfd_probe,
655 	.suspend =	sta2x11_mfd_suspend,
656 	.resume =	sta2x11_mfd_resume,
657 };
658 
659 static int __init sta2x11_mfd_init(void)
660 {
661 	pr_info("%s\n", __func__);
662 	return pci_register_driver(&sta2x11_mfd_driver);
663 }
664 
665 /*
666  * All of this must be ready before "normal" devices like MMCI appear.
667  * But MFD (the pci device) can't be too early. The following choice
668  * prepares platform drivers very early and probe the PCI device later,
669  * but before other PCI devices.
670  */
671 subsys_initcall(sta2x11_apbreg_init);
672 subsys_initcall(sta2x11_sctl_init);
673 subsys_initcall(sta2x11_apb_soc_regs_init);
674 subsys_initcall(sta2x11_scr_init);
675 rootfs_initcall(sta2x11_mfd_init);
676 
677 MODULE_LICENSE("GPL v2");
678 MODULE_AUTHOR("Wind River");
679 MODULE_DESCRIPTION("STA2x11 mfd for GPIO, SCTL and APBREG");
680 MODULE_DEVICE_TABLE(pci, sta2x11_mfd_tbl);
681