1 /* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved. 2 * Copyright (c) 2010, Google Inc. 3 * 4 * Original authors: Code Aurora Forum 5 * 6 * Author: Dima Zavin <dima@android.com> 7 * - Largely rewritten from original to not be an i2c driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 and 11 * only version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #define pr_fmt(fmt) "%s: " fmt, __func__ 20 21 #include <linux/delay.h> 22 #include <linux/err.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/ssbi.h> 28 #include <linux/module.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 32 /* SSBI 2.0 controller registers */ 33 #define SSBI2_CMD 0x0008 34 #define SSBI2_RD 0x0010 35 #define SSBI2_STATUS 0x0014 36 #define SSBI2_MODE2 0x001C 37 38 /* SSBI_CMD fields */ 39 #define SSBI_CMD_RDWRN (1 << 24) 40 41 /* SSBI_STATUS fields */ 42 #define SSBI_STATUS_RD_READY (1 << 2) 43 #define SSBI_STATUS_READY (1 << 1) 44 #define SSBI_STATUS_MCHN_BUSY (1 << 0) 45 46 /* SSBI_MODE2 fields */ 47 #define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04 48 #define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT) 49 50 #define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \ 51 (((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \ 52 SSBI_MODE2_REG_ADDR_15_8_MASK)) 53 54 /* SSBI PMIC Arbiter command registers */ 55 #define SSBI_PA_CMD 0x0000 56 #define SSBI_PA_RD_STATUS 0x0004 57 58 /* SSBI_PA_CMD fields */ 59 #define SSBI_PA_CMD_RDWRN (1 << 24) 60 #define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/ 61 62 /* SSBI_PA_RD_STATUS fields */ 63 #define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27) 64 #define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26) 65 66 #define SSBI_TIMEOUT_US 100 67 68 enum ssbi_controller_type { 69 MSM_SBI_CTRL_SSBI = 0, 70 MSM_SBI_CTRL_SSBI2, 71 MSM_SBI_CTRL_PMIC_ARBITER, 72 }; 73 74 struct ssbi { 75 struct device *slave; 76 void __iomem *base; 77 spinlock_t lock; 78 enum ssbi_controller_type controller_type; 79 int (*read)(struct ssbi *, u16 addr, u8 *buf, int len); 80 int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len); 81 }; 82 83 static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg) 84 { 85 return readl(ssbi->base + reg); 86 } 87 88 static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg) 89 { 90 writel(val, ssbi->base + reg); 91 } 92 93 /* 94 * Via private exchange with one of the original authors, the hardware 95 * should generally finish a transaction in about 5us. The worst 96 * case, is when using the arbiter and both other CPUs have just 97 * started trying to use the SSBI bus will result in a time of about 98 * 20us. It should never take longer than this. 99 * 100 * As such, this wait merely spins, with a udelay. 101 */ 102 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) 103 { 104 u32 timeout = SSBI_TIMEOUT_US; 105 u32 val; 106 107 while (timeout--) { 108 val = ssbi_readl(ssbi, SSBI2_STATUS); 109 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) 110 return 0; 111 udelay(1); 112 } 113 114 return -ETIMEDOUT; 115 } 116 117 static int 118 ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) 119 { 120 u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16); 121 int ret = 0; 122 123 if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) { 124 u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2); 125 mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr); 126 ssbi_writel(ssbi, mode2, SSBI2_MODE2); 127 } 128 129 while (len) { 130 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0); 131 if (ret) 132 goto err; 133 134 ssbi_writel(ssbi, cmd, SSBI2_CMD); 135 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0); 136 if (ret) 137 goto err; 138 *buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff; 139 len--; 140 } 141 142 err: 143 return ret; 144 } 145 146 static int 147 ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len) 148 { 149 int ret = 0; 150 151 if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) { 152 u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2); 153 mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr); 154 ssbi_writel(ssbi, mode2, SSBI2_MODE2); 155 } 156 157 while (len) { 158 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0); 159 if (ret) 160 goto err; 161 162 ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD); 163 ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY); 164 if (ret) 165 goto err; 166 buf++; 167 len--; 168 } 169 170 err: 171 return ret; 172 } 173 174 /* 175 * See ssbi_wait_mask for an explanation of the time and the 176 * busywait. 177 */ 178 static inline int 179 ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data) 180 { 181 u32 timeout = SSBI_TIMEOUT_US; 182 u32 rd_status = 0; 183 184 ssbi_writel(ssbi, cmd, SSBI_PA_CMD); 185 186 while (timeout--) { 187 rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS); 188 189 if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED) 190 return -EPERM; 191 192 if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) { 193 if (data) 194 *data = rd_status & 0xff; 195 return 0; 196 } 197 udelay(1); 198 } 199 200 return -ETIMEDOUT; 201 } 202 203 static int 204 ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) 205 { 206 u32 cmd; 207 int ret = 0; 208 209 cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8; 210 211 while (len) { 212 ret = ssbi_pa_transfer(ssbi, cmd, buf); 213 if (ret) 214 goto err; 215 buf++; 216 len--; 217 } 218 219 err: 220 return ret; 221 } 222 223 static int 224 ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len) 225 { 226 u32 cmd; 227 int ret = 0; 228 229 while (len) { 230 cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf; 231 ret = ssbi_pa_transfer(ssbi, cmd, NULL); 232 if (ret) 233 goto err; 234 buf++; 235 len--; 236 } 237 238 err: 239 return ret; 240 } 241 242 int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len) 243 { 244 struct ssbi *ssbi = dev_get_drvdata(dev); 245 unsigned long flags; 246 int ret; 247 248 spin_lock_irqsave(&ssbi->lock, flags); 249 ret = ssbi->read(ssbi, addr, buf, len); 250 spin_unlock_irqrestore(&ssbi->lock, flags); 251 252 return ret; 253 } 254 EXPORT_SYMBOL_GPL(ssbi_read); 255 256 int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len) 257 { 258 struct ssbi *ssbi = dev_get_drvdata(dev); 259 unsigned long flags; 260 int ret; 261 262 spin_lock_irqsave(&ssbi->lock, flags); 263 ret = ssbi->write(ssbi, addr, buf, len); 264 spin_unlock_irqrestore(&ssbi->lock, flags); 265 266 return ret; 267 } 268 EXPORT_SYMBOL_GPL(ssbi_write); 269 270 static int ssbi_probe(struct platform_device *pdev) 271 { 272 struct device_node *np = pdev->dev.of_node; 273 struct resource *mem_res; 274 struct ssbi *ssbi; 275 const char *type; 276 277 ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL); 278 if (!ssbi) 279 return -ENOMEM; 280 281 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 282 ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res); 283 if (IS_ERR(ssbi->base)) 284 return PTR_ERR(ssbi->base); 285 286 platform_set_drvdata(pdev, ssbi); 287 288 type = of_get_property(np, "qcom,controller-type", NULL); 289 if (type == NULL) { 290 dev_err(&pdev->dev, "Missing qcom,controller-type property\n"); 291 return -EINVAL; 292 } 293 dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type); 294 if (strcmp(type, "ssbi") == 0) 295 ssbi->controller_type = MSM_SBI_CTRL_SSBI; 296 else if (strcmp(type, "ssbi2") == 0) 297 ssbi->controller_type = MSM_SBI_CTRL_SSBI2; 298 else if (strcmp(type, "pmic-arbiter") == 0) 299 ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER; 300 else { 301 dev_err(&pdev->dev, "Unknown qcom,controller-type\n"); 302 return -EINVAL; 303 } 304 305 if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) { 306 ssbi->read = ssbi_pa_read_bytes; 307 ssbi->write = ssbi_pa_write_bytes; 308 } else { 309 ssbi->read = ssbi_read_bytes; 310 ssbi->write = ssbi_write_bytes; 311 } 312 313 spin_lock_init(&ssbi->lock); 314 315 return devm_of_platform_populate(&pdev->dev); 316 } 317 318 static const struct of_device_id ssbi_match_table[] = { 319 { .compatible = "qcom,ssbi" }, 320 {} 321 }; 322 MODULE_DEVICE_TABLE(of, ssbi_match_table); 323 324 static struct platform_driver ssbi_driver = { 325 .probe = ssbi_probe, 326 .driver = { 327 .name = "ssbi", 328 .of_match_table = ssbi_match_table, 329 }, 330 }; 331 module_platform_driver(ssbi_driver); 332 333 MODULE_LICENSE("GPL v2"); 334 MODULE_VERSION("1.0"); 335 MODULE_ALIAS("platform:ssbi"); 336 MODULE_AUTHOR("Dima Zavin <dima@android.com>"); 337