1 /* linux/drivers/mfd/sm501.c 2 * 3 * Copyright (C) 2006 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * Vincent Sanders <vince@simtec.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * SM501 MFD driver 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/list.h> 19 #include <linux/device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pci.h> 22 #include <linux/i2c-gpio.h> 23 24 #include <linux/sm501.h> 25 #include <linux/sm501-regs.h> 26 #include <linux/serial_8250.h> 27 28 #include <asm/io.h> 29 30 struct sm501_device { 31 struct list_head list; 32 struct platform_device pdev; 33 }; 34 35 struct sm501_gpio; 36 37 #ifdef CONFIG_MFD_SM501_GPIO 38 #include <linux/gpio.h> 39 40 struct sm501_gpio_chip { 41 struct gpio_chip gpio; 42 struct sm501_gpio *ourgpio; /* to get back to parent. */ 43 void __iomem *regbase; 44 void __iomem *control; /* address of control reg. */ 45 }; 46 47 struct sm501_gpio { 48 struct sm501_gpio_chip low; 49 struct sm501_gpio_chip high; 50 spinlock_t lock; 51 52 unsigned int registered : 1; 53 void __iomem *regs; 54 struct resource *regs_res; 55 }; 56 #else 57 struct sm501_gpio { 58 /* no gpio support, empty definition for sm501_devdata. */ 59 }; 60 #endif 61 62 struct sm501_devdata { 63 spinlock_t reg_lock; 64 struct mutex clock_lock; 65 struct list_head devices; 66 struct sm501_gpio gpio; 67 68 struct device *dev; 69 struct resource *io_res; 70 struct resource *mem_res; 71 struct resource *regs_claim; 72 struct sm501_platdata *platdata; 73 74 75 unsigned int in_suspend; 76 unsigned long pm_misc; 77 78 int unit_power[20]; 79 unsigned int pdev_id; 80 unsigned int irq; 81 void __iomem *regs; 82 unsigned int rev; 83 }; 84 85 86 #define MHZ (1000 * 1000) 87 88 #ifdef DEBUG 89 static const unsigned int div_tab[] = { 90 [0] = 1, 91 [1] = 2, 92 [2] = 4, 93 [3] = 8, 94 [4] = 16, 95 [5] = 32, 96 [6] = 64, 97 [7] = 128, 98 [8] = 3, 99 [9] = 6, 100 [10] = 12, 101 [11] = 24, 102 [12] = 48, 103 [13] = 96, 104 [14] = 192, 105 [15] = 384, 106 [16] = 5, 107 [17] = 10, 108 [18] = 20, 109 [19] = 40, 110 [20] = 80, 111 [21] = 160, 112 [22] = 320, 113 [23] = 604, 114 }; 115 116 static unsigned long decode_div(unsigned long pll2, unsigned long val, 117 unsigned int lshft, unsigned int selbit, 118 unsigned long mask) 119 { 120 if (val & selbit) 121 pll2 = 288 * MHZ; 122 123 return pll2 / div_tab[(val >> lshft) & mask]; 124 } 125 126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x) 127 128 /* sm501_dump_clk 129 * 130 * Print out the current clock configuration for the device 131 */ 132 133 static void sm501_dump_clk(struct sm501_devdata *sm) 134 { 135 unsigned long misct = readl(sm->regs + SM501_MISC_TIMING); 136 unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK); 137 unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK); 138 unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL); 139 unsigned long sdclk0, sdclk1; 140 unsigned long pll2 = 0; 141 142 switch (misct & 0x30) { 143 case 0x00: 144 pll2 = 336 * MHZ; 145 break; 146 case 0x10: 147 pll2 = 288 * MHZ; 148 break; 149 case 0x20: 150 pll2 = 240 * MHZ; 151 break; 152 case 0x30: 153 pll2 = 192 * MHZ; 154 break; 155 } 156 157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; 158 sdclk0 /= div_tab[((misct >> 8) & 0xf)]; 159 160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; 161 sdclk1 /= div_tab[((misct >> 16) & 0xf)]; 162 163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", 164 misct, pm0, pm1); 165 166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", 167 fmt_freq(pll2), sdclk0, sdclk1); 168 169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); 170 171 dev_dbg(sm->dev, "PM0[%c]: " 172 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 174 (pmc & 3 ) == 0 ? '*' : '-', 175 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), 176 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), 177 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), 178 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); 179 180 dev_dbg(sm->dev, "PM1[%c]: " 181 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 183 (pmc & 3 ) == 1 ? '*' : '-', 184 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), 185 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), 186 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), 187 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); 188 } 189 190 static void sm501_dump_regs(struct sm501_devdata *sm) 191 { 192 void __iomem *regs = sm->regs; 193 194 dev_info(sm->dev, "System Control %08x\n", 195 readl(regs + SM501_SYSTEM_CONTROL)); 196 dev_info(sm->dev, "Misc Control %08x\n", 197 readl(regs + SM501_MISC_CONTROL)); 198 dev_info(sm->dev, "GPIO Control Low %08x\n", 199 readl(regs + SM501_GPIO31_0_CONTROL)); 200 dev_info(sm->dev, "GPIO Control Hi %08x\n", 201 readl(regs + SM501_GPIO63_32_CONTROL)); 202 dev_info(sm->dev, "DRAM Control %08x\n", 203 readl(regs + SM501_DRAM_CONTROL)); 204 dev_info(sm->dev, "Arbitration Ctrl %08x\n", 205 readl(regs + SM501_ARBTRTN_CONTROL)); 206 dev_info(sm->dev, "Misc Timing %08x\n", 207 readl(regs + SM501_MISC_TIMING)); 208 } 209 210 static void sm501_dump_gate(struct sm501_devdata *sm) 211 { 212 dev_info(sm->dev, "CurrentGate %08x\n", 213 readl(sm->regs + SM501_CURRENT_GATE)); 214 dev_info(sm->dev, "CurrentClock %08x\n", 215 readl(sm->regs + SM501_CURRENT_CLOCK)); 216 dev_info(sm->dev, "PowerModeControl %08x\n", 217 readl(sm->regs + SM501_POWER_MODE_CONTROL)); 218 } 219 220 #else 221 static inline void sm501_dump_gate(struct sm501_devdata *sm) { } 222 static inline void sm501_dump_regs(struct sm501_devdata *sm) { } 223 static inline void sm501_dump_clk(struct sm501_devdata *sm) { } 224 #endif 225 226 /* sm501_sync_regs 227 * 228 * ensure the 229 */ 230 231 static void sm501_sync_regs(struct sm501_devdata *sm) 232 { 233 readl(sm->regs); 234 } 235 236 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) 237 { 238 /* during suspend/resume, we are currently not allowed to sleep, 239 * so change to using mdelay() instead of msleep() if we 240 * are in one of these paths */ 241 242 if (sm->in_suspend) 243 mdelay(delay); 244 else 245 msleep(delay); 246 } 247 248 /* sm501_misc_control 249 * 250 * alters the miscellaneous control parameters 251 */ 252 253 int sm501_misc_control(struct device *dev, 254 unsigned long set, unsigned long clear) 255 { 256 struct sm501_devdata *sm = dev_get_drvdata(dev); 257 unsigned long misc; 258 unsigned long save; 259 unsigned long to; 260 261 spin_lock_irqsave(&sm->reg_lock, save); 262 263 misc = readl(sm->regs + SM501_MISC_CONTROL); 264 to = (misc & ~clear) | set; 265 266 if (to != misc) { 267 writel(to, sm->regs + SM501_MISC_CONTROL); 268 sm501_sync_regs(sm); 269 270 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); 271 } 272 273 spin_unlock_irqrestore(&sm->reg_lock, save); 274 return to; 275 } 276 277 EXPORT_SYMBOL_GPL(sm501_misc_control); 278 279 /* sm501_modify_reg 280 * 281 * Modify a register in the SM501 which may be shared with other 282 * drivers. 283 */ 284 285 unsigned long sm501_modify_reg(struct device *dev, 286 unsigned long reg, 287 unsigned long set, 288 unsigned long clear) 289 { 290 struct sm501_devdata *sm = dev_get_drvdata(dev); 291 unsigned long data; 292 unsigned long save; 293 294 spin_lock_irqsave(&sm->reg_lock, save); 295 296 data = readl(sm->regs + reg); 297 data |= set; 298 data &= ~clear; 299 300 writel(data, sm->regs + reg); 301 sm501_sync_regs(sm); 302 303 spin_unlock_irqrestore(&sm->reg_lock, save); 304 305 return data; 306 } 307 308 EXPORT_SYMBOL_GPL(sm501_modify_reg); 309 310 /* sm501_unit_power 311 * 312 * alters the power active gate to set specific units on or off 313 */ 314 315 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) 316 { 317 struct sm501_devdata *sm = dev_get_drvdata(dev); 318 unsigned long mode; 319 unsigned long gate; 320 unsigned long clock; 321 322 mutex_lock(&sm->clock_lock); 323 324 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 325 gate = readl(sm->regs + SM501_CURRENT_GATE); 326 clock = readl(sm->regs + SM501_CURRENT_CLOCK); 327 328 mode &= 3; /* get current power mode */ 329 330 if (unit >= ARRAY_SIZE(sm->unit_power)) { 331 dev_err(dev, "%s: bad unit %d\n", __func__, unit); 332 goto already; 333 } 334 335 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit, 336 sm->unit_power[unit], to); 337 338 if (to == 0 && sm->unit_power[unit] == 0) { 339 dev_err(sm->dev, "unit %d is already shutdown\n", unit); 340 goto already; 341 } 342 343 sm->unit_power[unit] += to ? 1 : -1; 344 to = sm->unit_power[unit] ? 1 : 0; 345 346 if (to) { 347 if (gate & (1 << unit)) 348 goto already; 349 gate |= (1 << unit); 350 } else { 351 if (!(gate & (1 << unit))) 352 goto already; 353 gate &= ~(1 << unit); 354 } 355 356 switch (mode) { 357 case 1: 358 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 359 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 360 mode = 0; 361 break; 362 case 2: 363 case 0: 364 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 365 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 366 mode = 1; 367 break; 368 369 default: 370 return -1; 371 } 372 373 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 374 sm501_sync_regs(sm); 375 376 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 377 gate, clock, mode); 378 379 sm501_mdelay(sm, 16); 380 381 already: 382 mutex_unlock(&sm->clock_lock); 383 return gate; 384 } 385 386 EXPORT_SYMBOL_GPL(sm501_unit_power); 387 388 389 /* Perform a rounded division. */ 390 static long sm501fb_round_div(long num, long denom) 391 { 392 /* n / d + 1 / 2 = (2n + d) / 2d */ 393 return (2 * num + denom) / (2 * denom); 394 } 395 396 /* clock value structure. */ 397 struct sm501_clock { 398 unsigned long mclk; 399 int divider; 400 int shift; 401 unsigned int m, n, k; 402 }; 403 404 /* sm501_calc_clock 405 * 406 * Calculates the nearest discrete clock frequency that 407 * can be achieved with the specified input clock. 408 * the maximum divisor is 3 or 5 409 */ 410 411 static int sm501_calc_clock(unsigned long freq, 412 struct sm501_clock *clock, 413 int max_div, 414 unsigned long mclk, 415 long *best_diff) 416 { 417 int ret = 0; 418 int divider; 419 int shift; 420 long diff; 421 422 /* try dividers 1 and 3 for CRT and for panel, 423 try divider 5 for panel only.*/ 424 425 for (divider = 1; divider <= max_div; divider += 2) { 426 /* try all 8 shift values.*/ 427 for (shift = 0; shift < 8; shift++) { 428 /* Calculate difference to requested clock */ 429 diff = sm501fb_round_div(mclk, divider << shift) - freq; 430 if (diff < 0) 431 diff = -diff; 432 433 /* If it is less than the current, use it */ 434 if (diff < *best_diff) { 435 *best_diff = diff; 436 437 clock->mclk = mclk; 438 clock->divider = divider; 439 clock->shift = shift; 440 ret = 1; 441 } 442 } 443 } 444 445 return ret; 446 } 447 448 /* sm501_calc_pll 449 * 450 * Calculates the nearest discrete clock frequency that can be 451 * achieved using the programmable PLL. 452 * the maximum divisor is 3 or 5 453 */ 454 455 static unsigned long sm501_calc_pll(unsigned long freq, 456 struct sm501_clock *clock, 457 int max_div) 458 { 459 unsigned long mclk; 460 unsigned int m, n, k; 461 long best_diff = 999999999; 462 463 /* 464 * The SM502 datasheet doesn't specify the min/max values for M and N. 465 * N = 1 at least doesn't work in practice. 466 */ 467 for (m = 2; m <= 255; m++) { 468 for (n = 2; n <= 127; n++) { 469 for (k = 0; k <= 1; k++) { 470 mclk = (24000000UL * m / n) >> k; 471 472 if (sm501_calc_clock(freq, clock, max_div, 473 mclk, &best_diff)) { 474 clock->m = m; 475 clock->n = n; 476 clock->k = k; 477 } 478 } 479 } 480 } 481 482 /* Return best clock. */ 483 return clock->mclk / (clock->divider << clock->shift); 484 } 485 486 /* sm501_select_clock 487 * 488 * Calculates the nearest discrete clock frequency that can be 489 * achieved using the 288MHz and 336MHz PLLs. 490 * the maximum divisor is 3 or 5 491 */ 492 493 static unsigned long sm501_select_clock(unsigned long freq, 494 struct sm501_clock *clock, 495 int max_div) 496 { 497 unsigned long mclk; 498 long best_diff = 999999999; 499 500 /* Try 288MHz and 336MHz clocks. */ 501 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { 502 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); 503 } 504 505 /* Return best clock. */ 506 return clock->mclk / (clock->divider << clock->shift); 507 } 508 509 /* sm501_set_clock 510 * 511 * set one of the four clock sources to the closest available frequency to 512 * the one specified 513 */ 514 515 unsigned long sm501_set_clock(struct device *dev, 516 int clksrc, 517 unsigned long req_freq) 518 { 519 struct sm501_devdata *sm = dev_get_drvdata(dev); 520 unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 521 unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE); 522 unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK); 523 unsigned char reg; 524 unsigned int pll_reg = 0; 525 unsigned long sm501_freq; /* the actual frequency acheived */ 526 527 struct sm501_clock to; 528 529 /* find achivable discrete frequency and setup register value 530 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK 531 * has an extra bit for the divider */ 532 533 switch (clksrc) { 534 case SM501_CLOCK_P2XCLK: 535 /* This clock is divided in half so to achive the 536 * requested frequency the value must be multiplied by 537 * 2. This clock also has an additional pre divisor */ 538 539 if (sm->rev >= 0xC0) { 540 /* SM502 -> use the programmable PLL */ 541 sm501_freq = (sm501_calc_pll(2 * req_freq, 542 &to, 5) / 2); 543 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 544 if (to.divider == 3) 545 reg |= 0x08; /* /3 divider required */ 546 else if (to.divider == 5) 547 reg |= 0x10; /* /5 divider required */ 548 reg |= 0x40; /* select the programmable PLL */ 549 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; 550 } else { 551 sm501_freq = (sm501_select_clock(2 * req_freq, 552 &to, 5) / 2); 553 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 554 if (to.divider == 3) 555 reg |= 0x08; /* /3 divider required */ 556 else if (to.divider == 5) 557 reg |= 0x10; /* /5 divider required */ 558 if (to.mclk != 288000000) 559 reg |= 0x20; /* which mclk pll is source */ 560 } 561 break; 562 563 case SM501_CLOCK_V2XCLK: 564 /* This clock is divided in half so to achive the 565 * requested frequency the value must be multiplied by 2. */ 566 567 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 568 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 569 if (to.divider == 3) 570 reg |= 0x08; /* /3 divider required */ 571 if (to.mclk != 288000000) 572 reg |= 0x10; /* which mclk pll is source */ 573 break; 574 575 case SM501_CLOCK_MCLK: 576 case SM501_CLOCK_M1XCLK: 577 /* These clocks are the same and not further divided */ 578 579 sm501_freq = sm501_select_clock( req_freq, &to, 3); 580 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 581 if (to.divider == 3) 582 reg |= 0x08; /* /3 divider required */ 583 if (to.mclk != 288000000) 584 reg |= 0x10; /* which mclk pll is source */ 585 break; 586 587 default: 588 return 0; /* this is bad */ 589 } 590 591 mutex_lock(&sm->clock_lock); 592 593 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 594 gate = readl(sm->regs + SM501_CURRENT_GATE); 595 clock = readl(sm->regs + SM501_CURRENT_CLOCK); 596 597 clock = clock & ~(0xFF << clksrc); 598 clock |= reg<<clksrc; 599 600 mode &= 3; /* find current mode */ 601 602 switch (mode) { 603 case 1: 604 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 605 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 606 mode = 0; 607 break; 608 case 2: 609 case 0: 610 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 611 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 612 mode = 1; 613 break; 614 615 default: 616 mutex_unlock(&sm->clock_lock); 617 return -1; 618 } 619 620 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 621 622 if (pll_reg) 623 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); 624 625 sm501_sync_regs(sm); 626 627 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 628 gate, clock, mode); 629 630 sm501_mdelay(sm, 16); 631 mutex_unlock(&sm->clock_lock); 632 633 sm501_dump_clk(sm); 634 635 return sm501_freq; 636 } 637 638 EXPORT_SYMBOL_GPL(sm501_set_clock); 639 640 /* sm501_find_clock 641 * 642 * finds the closest available frequency for a given clock 643 */ 644 645 unsigned long sm501_find_clock(struct device *dev, 646 int clksrc, 647 unsigned long req_freq) 648 { 649 struct sm501_devdata *sm = dev_get_drvdata(dev); 650 unsigned long sm501_freq; /* the frequency achiveable by the 501 */ 651 struct sm501_clock to; 652 653 switch (clksrc) { 654 case SM501_CLOCK_P2XCLK: 655 if (sm->rev >= 0xC0) { 656 /* SM502 -> use the programmable PLL */ 657 sm501_freq = (sm501_calc_pll(2 * req_freq, 658 &to, 5) / 2); 659 } else { 660 sm501_freq = (sm501_select_clock(2 * req_freq, 661 &to, 5) / 2); 662 } 663 break; 664 665 case SM501_CLOCK_V2XCLK: 666 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 667 break; 668 669 case SM501_CLOCK_MCLK: 670 case SM501_CLOCK_M1XCLK: 671 sm501_freq = sm501_select_clock(req_freq, &to, 3); 672 break; 673 674 default: 675 sm501_freq = 0; /* error */ 676 } 677 678 return sm501_freq; 679 } 680 681 EXPORT_SYMBOL_GPL(sm501_find_clock); 682 683 static struct sm501_device *to_sm_device(struct platform_device *pdev) 684 { 685 return container_of(pdev, struct sm501_device, pdev); 686 } 687 688 /* sm501_device_release 689 * 690 * A release function for the platform devices we create to allow us to 691 * free any items we allocated 692 */ 693 694 static void sm501_device_release(struct device *dev) 695 { 696 kfree(to_sm_device(to_platform_device(dev))); 697 } 698 699 /* sm501_create_subdev 700 * 701 * Create a skeleton platform device with resources for passing to a 702 * sub-driver 703 */ 704 705 static struct platform_device * 706 sm501_create_subdev(struct sm501_devdata *sm, char *name, 707 unsigned int res_count, unsigned int platform_data_size) 708 { 709 struct sm501_device *smdev; 710 711 smdev = kzalloc(sizeof(struct sm501_device) + 712 (sizeof(struct resource) * res_count) + 713 platform_data_size, GFP_KERNEL); 714 if (!smdev) 715 return NULL; 716 717 smdev->pdev.dev.release = sm501_device_release; 718 719 smdev->pdev.name = name; 720 smdev->pdev.id = sm->pdev_id; 721 smdev->pdev.dev.parent = sm->dev; 722 723 if (res_count) { 724 smdev->pdev.resource = (struct resource *)(smdev+1); 725 smdev->pdev.num_resources = res_count; 726 } 727 if (platform_data_size) 728 smdev->pdev.dev.platform_data = (void *)(smdev+1); 729 730 return &smdev->pdev; 731 } 732 733 /* sm501_register_device 734 * 735 * Register a platform device created with sm501_create_subdev() 736 */ 737 738 static int sm501_register_device(struct sm501_devdata *sm, 739 struct platform_device *pdev) 740 { 741 struct sm501_device *smdev = to_sm_device(pdev); 742 int ptr; 743 int ret; 744 745 for (ptr = 0; ptr < pdev->num_resources; ptr++) { 746 printk(KERN_DEBUG "%s[%d] flags %08lx: %08llx..%08llx\n", 747 pdev->name, ptr, 748 pdev->resource[ptr].flags, 749 (unsigned long long)pdev->resource[ptr].start, 750 (unsigned long long)pdev->resource[ptr].end); 751 } 752 753 ret = platform_device_register(pdev); 754 755 if (ret >= 0) { 756 dev_dbg(sm->dev, "registered %s\n", pdev->name); 757 list_add_tail(&smdev->list, &sm->devices); 758 } else 759 dev_err(sm->dev, "error registering %s (%d)\n", 760 pdev->name, ret); 761 762 return ret; 763 } 764 765 /* sm501_create_subio 766 * 767 * Fill in an IO resource for a sub device 768 */ 769 770 static void sm501_create_subio(struct sm501_devdata *sm, 771 struct resource *res, 772 resource_size_t offs, 773 resource_size_t size) 774 { 775 res->flags = IORESOURCE_MEM; 776 res->parent = sm->io_res; 777 res->start = sm->io_res->start + offs; 778 res->end = res->start + size - 1; 779 } 780 781 /* sm501_create_mem 782 * 783 * Fill in an MEM resource for a sub device 784 */ 785 786 static void sm501_create_mem(struct sm501_devdata *sm, 787 struct resource *res, 788 resource_size_t *offs, 789 resource_size_t size) 790 { 791 *offs -= size; /* adjust memory size */ 792 793 res->flags = IORESOURCE_MEM; 794 res->parent = sm->mem_res; 795 res->start = sm->mem_res->start + *offs; 796 res->end = res->start + size - 1; 797 } 798 799 /* sm501_create_irq 800 * 801 * Fill in an IRQ resource for a sub device 802 */ 803 804 static void sm501_create_irq(struct sm501_devdata *sm, 805 struct resource *res) 806 { 807 res->flags = IORESOURCE_IRQ; 808 res->parent = NULL; 809 res->start = res->end = sm->irq; 810 } 811 812 static int sm501_register_usbhost(struct sm501_devdata *sm, 813 resource_size_t *mem_avail) 814 { 815 struct platform_device *pdev; 816 817 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0); 818 if (!pdev) 819 return -ENOMEM; 820 821 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000); 822 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024); 823 sm501_create_irq(sm, &pdev->resource[2]); 824 825 return sm501_register_device(sm, pdev); 826 } 827 828 static void sm501_setup_uart_data(struct sm501_devdata *sm, 829 struct plat_serial8250_port *uart_data, 830 unsigned int offset) 831 { 832 uart_data->membase = sm->regs + offset; 833 uart_data->mapbase = sm->io_res->start + offset; 834 uart_data->iotype = UPIO_MEM; 835 uart_data->irq = sm->irq; 836 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 837 uart_data->regshift = 2; 838 uart_data->uartclk = (9600 * 16); 839 } 840 841 static int sm501_register_uart(struct sm501_devdata *sm, int devices) 842 { 843 struct platform_device *pdev; 844 struct plat_serial8250_port *uart_data; 845 846 pdev = sm501_create_subdev(sm, "serial8250", 0, 847 sizeof(struct plat_serial8250_port) * 3); 848 if (!pdev) 849 return -ENOMEM; 850 851 uart_data = pdev->dev.platform_data; 852 853 if (devices & SM501_USE_UART0) { 854 sm501_setup_uart_data(sm, uart_data++, 0x30000); 855 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1); 856 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0); 857 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0); 858 } 859 if (devices & SM501_USE_UART1) { 860 sm501_setup_uart_data(sm, uart_data++, 0x30020); 861 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1); 862 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0); 863 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0); 864 } 865 866 pdev->id = PLAT8250_DEV_SM501; 867 868 return sm501_register_device(sm, pdev); 869 } 870 871 static int sm501_register_display(struct sm501_devdata *sm, 872 resource_size_t *mem_avail) 873 { 874 struct platform_device *pdev; 875 876 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0); 877 if (!pdev) 878 return -ENOMEM; 879 880 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000); 881 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000); 882 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail); 883 sm501_create_irq(sm, &pdev->resource[3]); 884 885 return sm501_register_device(sm, pdev); 886 } 887 888 #ifdef CONFIG_MFD_SM501_GPIO 889 890 static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc) 891 { 892 return container_of(gc, struct sm501_gpio_chip, gpio); 893 } 894 895 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio) 896 { 897 return container_of(gpio, struct sm501_devdata, gpio); 898 } 899 900 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) 901 902 { 903 struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip); 904 unsigned long result; 905 906 result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW); 907 result >>= offset; 908 909 return result & 1UL; 910 } 911 912 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, 913 unsigned long bit) 914 { 915 unsigned long ctrl; 916 917 /* check and modify if this pin is not set as gpio. */ 918 919 if (readl(smchip->control) & bit) { 920 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, 921 "changing mode of gpio, bit %08lx\n", bit); 922 923 ctrl = readl(smchip->control); 924 ctrl &= ~bit; 925 writel(ctrl, smchip->control); 926 927 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); 928 } 929 } 930 931 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 932 933 { 934 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip); 935 struct sm501_gpio *smgpio = smchip->ourgpio; 936 unsigned long bit = 1 << offset; 937 void __iomem *regs = smchip->regbase; 938 unsigned long save; 939 unsigned long val; 940 941 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 942 __func__, chip, offset); 943 944 spin_lock_irqsave(&smgpio->lock, save); 945 946 val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit; 947 if (value) 948 val |= bit; 949 writel(val, regs); 950 951 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 952 sm501_gpio_ensure_gpio(smchip, bit); 953 954 spin_unlock_irqrestore(&smgpio->lock, save); 955 } 956 957 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) 958 { 959 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip); 960 struct sm501_gpio *smgpio = smchip->ourgpio; 961 void __iomem *regs = smchip->regbase; 962 unsigned long bit = 1 << offset; 963 unsigned long save; 964 unsigned long ddr; 965 966 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 967 __func__, chip, offset); 968 969 spin_lock_irqsave(&smgpio->lock, save); 970 971 ddr = readl(regs + SM501_GPIO_DDR_LOW); 972 writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); 973 974 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 975 sm501_gpio_ensure_gpio(smchip, bit); 976 977 spin_unlock_irqrestore(&smgpio->lock, save); 978 979 return 0; 980 } 981 982 static int sm501_gpio_output(struct gpio_chip *chip, 983 unsigned offset, int value) 984 { 985 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip); 986 struct sm501_gpio *smgpio = smchip->ourgpio; 987 unsigned long bit = 1 << offset; 988 void __iomem *regs = smchip->regbase; 989 unsigned long save; 990 unsigned long val; 991 unsigned long ddr; 992 993 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n", 994 __func__, chip, offset, value); 995 996 spin_lock_irqsave(&smgpio->lock, save); 997 998 val = readl(regs + SM501_GPIO_DATA_LOW); 999 if (value) 1000 val |= bit; 1001 else 1002 val &= ~bit; 1003 writel(val, regs); 1004 1005 ddr = readl(regs + SM501_GPIO_DDR_LOW); 1006 writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); 1007 1008 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 1009 writel(val, regs + SM501_GPIO_DATA_LOW); 1010 1011 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 1012 spin_unlock_irqrestore(&smgpio->lock, save); 1013 1014 return 0; 1015 } 1016 1017 static struct gpio_chip gpio_chip_template = { 1018 .ngpio = 32, 1019 .direction_input = sm501_gpio_input, 1020 .direction_output = sm501_gpio_output, 1021 .set = sm501_gpio_set, 1022 .get = sm501_gpio_get, 1023 }; 1024 1025 static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm, 1026 struct sm501_gpio *gpio, 1027 struct sm501_gpio_chip *chip) 1028 { 1029 struct sm501_platdata *pdata = sm->platdata; 1030 struct gpio_chip *gchip = &chip->gpio; 1031 int base = pdata->gpio_base; 1032 1033 chip->gpio = gpio_chip_template; 1034 1035 if (chip == &gpio->high) { 1036 if (base > 0) 1037 base += 32; 1038 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; 1039 chip->control = sm->regs + SM501_GPIO63_32_CONTROL; 1040 gchip->label = "SM501-HIGH"; 1041 } else { 1042 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; 1043 chip->control = sm->regs + SM501_GPIO31_0_CONTROL; 1044 gchip->label = "SM501-LOW"; 1045 } 1046 1047 gchip->base = base; 1048 chip->ourgpio = gpio; 1049 1050 return gpiochip_add(gchip); 1051 } 1052 1053 static int __devinit sm501_register_gpio(struct sm501_devdata *sm) 1054 { 1055 struct sm501_gpio *gpio = &sm->gpio; 1056 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1057 int ret; 1058 int tmp; 1059 1060 dev_dbg(sm->dev, "registering gpio block %08llx\n", 1061 (unsigned long long)iobase); 1062 1063 spin_lock_init(&gpio->lock); 1064 1065 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio"); 1066 if (gpio->regs_res == NULL) { 1067 dev_err(sm->dev, "gpio: failed to request region\n"); 1068 return -ENXIO; 1069 } 1070 1071 gpio->regs = ioremap(iobase, 0x20); 1072 if (gpio->regs == NULL) { 1073 dev_err(sm->dev, "gpio: failed to remap registers\n"); 1074 ret = -ENXIO; 1075 goto err_claimed; 1076 } 1077 1078 /* Register both our chips. */ 1079 1080 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low); 1081 if (ret) { 1082 dev_err(sm->dev, "failed to add low chip\n"); 1083 goto err_mapped; 1084 } 1085 1086 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high); 1087 if (ret) { 1088 dev_err(sm->dev, "failed to add high chip\n"); 1089 goto err_low_chip; 1090 } 1091 1092 gpio->registered = 1; 1093 1094 return 0; 1095 1096 err_low_chip: 1097 tmp = gpiochip_remove(&gpio->low.gpio); 1098 if (tmp) { 1099 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n"); 1100 return ret; 1101 } 1102 1103 err_mapped: 1104 iounmap(gpio->regs); 1105 1106 err_claimed: 1107 release_resource(gpio->regs_res); 1108 kfree(gpio->regs_res); 1109 1110 return ret; 1111 } 1112 1113 static void sm501_gpio_remove(struct sm501_devdata *sm) 1114 { 1115 struct sm501_gpio *gpio = &sm->gpio; 1116 int ret; 1117 1118 if (!sm->gpio.registered) 1119 return; 1120 1121 ret = gpiochip_remove(&gpio->low.gpio); 1122 if (ret) 1123 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n"); 1124 1125 ret = gpiochip_remove(&gpio->high.gpio); 1126 if (ret) 1127 dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n"); 1128 1129 iounmap(gpio->regs); 1130 release_resource(gpio->regs_res); 1131 kfree(gpio->regs_res); 1132 } 1133 1134 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin) 1135 { 1136 struct sm501_gpio *gpio = &sm->gpio; 1137 int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base; 1138 1139 return (pin % 32) + base; 1140 } 1141 1142 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1143 { 1144 return sm->gpio.registered; 1145 } 1146 #else 1147 static inline int sm501_register_gpio(struct sm501_devdata *sm) 1148 { 1149 return 0; 1150 } 1151 1152 static inline void sm501_gpio_remove(struct sm501_devdata *sm) 1153 { 1154 } 1155 1156 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin) 1157 { 1158 return -1; 1159 } 1160 1161 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1162 { 1163 return 0; 1164 } 1165 #endif 1166 1167 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm, 1168 struct sm501_platdata_gpio_i2c *iic) 1169 { 1170 struct i2c_gpio_platform_data *icd; 1171 struct platform_device *pdev; 1172 1173 pdev = sm501_create_subdev(sm, "i2c-gpio", 0, 1174 sizeof(struct i2c_gpio_platform_data)); 1175 if (!pdev) 1176 return -ENOMEM; 1177 1178 icd = pdev->dev.platform_data; 1179 1180 /* We keep the pin_sda and pin_scl fields relative in case the 1181 * same platform data is passed to >1 SM501. 1182 */ 1183 1184 icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda); 1185 icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl); 1186 icd->timeout = iic->timeout; 1187 icd->udelay = iic->udelay; 1188 1189 /* note, we can't use either of the pin numbers, as the i2c-gpio 1190 * driver uses the platform.id field to generate the bus number 1191 * to register with the i2c core; The i2c core doesn't have enough 1192 * entries to deal with anything we currently use. 1193 */ 1194 1195 pdev->id = iic->bus_num; 1196 1197 dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n", 1198 iic->bus_num, 1199 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl); 1200 1201 return sm501_register_device(sm, pdev); 1202 } 1203 1204 static int sm501_register_gpio_i2c(struct sm501_devdata *sm, 1205 struct sm501_platdata *pdata) 1206 { 1207 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c; 1208 int index; 1209 int ret; 1210 1211 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) { 1212 ret = sm501_register_gpio_i2c_instance(sm, iic); 1213 if (ret < 0) 1214 return ret; 1215 } 1216 1217 return 0; 1218 } 1219 1220 /* sm501_dbg_regs 1221 * 1222 * Debug attribute to attach to parent device to show core registers 1223 */ 1224 1225 static ssize_t sm501_dbg_regs(struct device *dev, 1226 struct device_attribute *attr, char *buff) 1227 { 1228 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 1229 unsigned int reg; 1230 char *ptr = buff; 1231 int ret; 1232 1233 for (reg = 0x00; reg < 0x70; reg += 4) { 1234 ret = sprintf(ptr, "%08x = %08x\n", 1235 reg, readl(sm->regs + reg)); 1236 ptr += ret; 1237 } 1238 1239 return ptr - buff; 1240 } 1241 1242 1243 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL); 1244 1245 /* sm501_init_reg 1246 * 1247 * Helper function for the init code to setup a register 1248 * 1249 * clear the bits which are set in r->mask, and then set 1250 * the bits set in r->set. 1251 */ 1252 1253 static inline void sm501_init_reg(struct sm501_devdata *sm, 1254 unsigned long reg, 1255 struct sm501_reg_init *r) 1256 { 1257 unsigned long tmp; 1258 1259 tmp = readl(sm->regs + reg); 1260 tmp &= ~r->mask; 1261 tmp |= r->set; 1262 writel(tmp, sm->regs + reg); 1263 } 1264 1265 /* sm501_init_regs 1266 * 1267 * Setup core register values 1268 */ 1269 1270 static void sm501_init_regs(struct sm501_devdata *sm, 1271 struct sm501_initdata *init) 1272 { 1273 sm501_misc_control(sm->dev, 1274 init->misc_control.set, 1275 init->misc_control.mask); 1276 1277 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing); 1278 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low); 1279 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high); 1280 1281 if (init->m1xclk) { 1282 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk); 1283 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk); 1284 } 1285 1286 if (init->mclk) { 1287 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); 1288 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); 1289 } 1290 1291 } 1292 1293 /* Check the PLL sources for the M1CLK and M1XCLK 1294 * 1295 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then 1296 * there is a risk (see errata AB-5) that the SM501 will cease proper 1297 * function. If this happens, then it is likely the SM501 will 1298 * hang the system. 1299 */ 1300 1301 static int sm501_check_clocks(struct sm501_devdata *sm) 1302 { 1303 unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK); 1304 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); 1305 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); 1306 1307 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0)); 1308 } 1309 1310 static unsigned int sm501_mem_local[] = { 1311 [0] = 4*1024*1024, 1312 [1] = 8*1024*1024, 1313 [2] = 16*1024*1024, 1314 [3] = 32*1024*1024, 1315 [4] = 64*1024*1024, 1316 [5] = 2*1024*1024, 1317 }; 1318 1319 /* sm501_init_dev 1320 * 1321 * Common init code for an SM501 1322 */ 1323 1324 static int __devinit sm501_init_dev(struct sm501_devdata *sm) 1325 { 1326 struct sm501_initdata *idata; 1327 struct sm501_platdata *pdata; 1328 resource_size_t mem_avail; 1329 unsigned long dramctrl; 1330 unsigned long devid; 1331 int ret; 1332 1333 mutex_init(&sm->clock_lock); 1334 spin_lock_init(&sm->reg_lock); 1335 1336 INIT_LIST_HEAD(&sm->devices); 1337 1338 devid = readl(sm->regs + SM501_DEVICEID); 1339 1340 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { 1341 dev_err(sm->dev, "incorrect device id %08lx\n", devid); 1342 return -EINVAL; 1343 } 1344 1345 /* disable irqs */ 1346 writel(0, sm->regs + SM501_IRQ_MASK); 1347 1348 dramctrl = readl(sm->regs + SM501_DRAM_CONTROL); 1349 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; 1350 1351 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", 1352 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq); 1353 1354 sm->rev = devid & SM501_DEVICEID_REVMASK; 1355 1356 sm501_dump_gate(sm); 1357 1358 ret = device_create_file(sm->dev, &dev_attr_dbg_regs); 1359 if (ret) 1360 dev_err(sm->dev, "failed to create debug regs file\n"); 1361 1362 sm501_dump_clk(sm); 1363 1364 /* check to see if we have some device initialisation */ 1365 1366 pdata = sm->platdata; 1367 idata = pdata ? pdata->init : NULL; 1368 1369 if (idata) { 1370 sm501_init_regs(sm, idata); 1371 1372 if (idata->devices & SM501_USE_USB_HOST) 1373 sm501_register_usbhost(sm, &mem_avail); 1374 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1)) 1375 sm501_register_uart(sm, idata->devices); 1376 if (idata->devices & SM501_USE_GPIO) 1377 sm501_register_gpio(sm); 1378 } 1379 1380 if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) { 1381 if (!sm501_gpio_isregistered(sm)) 1382 dev_err(sm->dev, "no gpio available for i2c gpio.\n"); 1383 else 1384 sm501_register_gpio_i2c(sm, pdata); 1385 } 1386 1387 ret = sm501_check_clocks(sm); 1388 if (ret) { 1389 dev_err(sm->dev, "M1X and M clocks sourced from different " 1390 "PLLs\n"); 1391 return -EINVAL; 1392 } 1393 1394 /* always create a framebuffer */ 1395 sm501_register_display(sm, &mem_avail); 1396 1397 return 0; 1398 } 1399 1400 static int __devinit sm501_plat_probe(struct platform_device *dev) 1401 { 1402 struct sm501_devdata *sm; 1403 int ret; 1404 1405 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL); 1406 if (sm == NULL) { 1407 dev_err(&dev->dev, "no memory for device data\n"); 1408 ret = -ENOMEM; 1409 goto err1; 1410 } 1411 1412 sm->dev = &dev->dev; 1413 sm->pdev_id = dev->id; 1414 sm->platdata = dev->dev.platform_data; 1415 1416 ret = platform_get_irq(dev, 0); 1417 if (ret < 0) { 1418 dev_err(&dev->dev, "failed to get irq resource\n"); 1419 goto err_res; 1420 } 1421 sm->irq = ret; 1422 1423 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 1424 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1425 if (sm->io_res == NULL || sm->mem_res == NULL) { 1426 dev_err(&dev->dev, "failed to get IO resource\n"); 1427 ret = -ENOENT; 1428 goto err_res; 1429 } 1430 1431 sm->regs_claim = request_mem_region(sm->io_res->start, 1432 0x100, "sm501"); 1433 1434 if (sm->regs_claim == NULL) { 1435 dev_err(&dev->dev, "cannot claim registers\n"); 1436 ret = -EBUSY; 1437 goto err_res; 1438 } 1439 1440 platform_set_drvdata(dev, sm); 1441 1442 sm->regs = ioremap(sm->io_res->start, 1443 (sm->io_res->end - sm->io_res->start) - 1); 1444 1445 if (sm->regs == NULL) { 1446 dev_err(&dev->dev, "cannot remap registers\n"); 1447 ret = -EIO; 1448 goto err_claim; 1449 } 1450 1451 return sm501_init_dev(sm); 1452 1453 err_claim: 1454 release_resource(sm->regs_claim); 1455 kfree(sm->regs_claim); 1456 err_res: 1457 kfree(sm); 1458 err1: 1459 return ret; 1460 1461 } 1462 1463 #ifdef CONFIG_PM 1464 1465 /* power management support */ 1466 1467 static void sm501_set_power(struct sm501_devdata *sm, int on) 1468 { 1469 struct sm501_platdata *pd = sm->platdata; 1470 1471 if (pd == NULL) 1472 return; 1473 1474 if (pd->get_power) { 1475 if (pd->get_power(sm->dev) == on) { 1476 dev_dbg(sm->dev, "is already %d\n", on); 1477 return; 1478 } 1479 } 1480 1481 if (pd->set_power) { 1482 dev_dbg(sm->dev, "setting power to %d\n", on); 1483 1484 pd->set_power(sm->dev, on); 1485 sm501_mdelay(sm, 10); 1486 } 1487 } 1488 1489 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) 1490 { 1491 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1492 1493 sm->in_suspend = 1; 1494 sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL); 1495 1496 sm501_dump_regs(sm); 1497 1498 if (sm->platdata) { 1499 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF) 1500 sm501_set_power(sm, 0); 1501 } 1502 1503 return 0; 1504 } 1505 1506 static int sm501_plat_resume(struct platform_device *pdev) 1507 { 1508 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1509 1510 sm501_set_power(sm, 1); 1511 1512 sm501_dump_regs(sm); 1513 sm501_dump_gate(sm); 1514 sm501_dump_clk(sm); 1515 1516 /* check to see if we are in the same state as when suspended */ 1517 1518 if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { 1519 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); 1520 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); 1521 1522 /* our suspend causes the controller state to change, 1523 * either by something attempting setup, power loss, 1524 * or an external reset event on power change */ 1525 1526 if (sm->platdata && sm->platdata->init) { 1527 sm501_init_regs(sm, sm->platdata->init); 1528 } 1529 } 1530 1531 /* dump our state from resume */ 1532 1533 sm501_dump_regs(sm); 1534 sm501_dump_clk(sm); 1535 1536 sm->in_suspend = 0; 1537 1538 return 0; 1539 } 1540 #else 1541 #define sm501_plat_suspend NULL 1542 #define sm501_plat_resume NULL 1543 #endif 1544 1545 /* Initialisation data for PCI devices */ 1546 1547 static struct sm501_initdata sm501_pci_initdata = { 1548 .gpio_high = { 1549 .set = 0x3F000000, /* 24bit panel */ 1550 .mask = 0x0, 1551 }, 1552 .misc_timing = { 1553 .set = 0x010100, /* SDRAM timing */ 1554 .mask = 0x1F1F00, 1555 }, 1556 .misc_control = { 1557 .set = SM501_MISC_PNL_24BIT, 1558 .mask = 0, 1559 }, 1560 1561 .devices = SM501_USE_ALL, 1562 1563 /* Errata AB-3 says that 72MHz is the fastest available 1564 * for 33MHZ PCI with proper bus-mastering operation */ 1565 1566 .mclk = 72 * MHZ, 1567 .m1xclk = 144 * MHZ, 1568 }; 1569 1570 static struct sm501_platdata_fbsub sm501_pdata_fbsub = { 1571 .flags = (SM501FB_FLAG_USE_INIT_MODE | 1572 SM501FB_FLAG_USE_HWCURSOR | 1573 SM501FB_FLAG_USE_HWACCEL | 1574 SM501FB_FLAG_DISABLE_AT_EXIT), 1575 }; 1576 1577 static struct sm501_platdata_fb sm501_fb_pdata = { 1578 .fb_route = SM501_FB_OWN, 1579 .fb_crt = &sm501_pdata_fbsub, 1580 .fb_pnl = &sm501_pdata_fbsub, 1581 }; 1582 1583 static struct sm501_platdata sm501_pci_platdata = { 1584 .init = &sm501_pci_initdata, 1585 .fb = &sm501_fb_pdata, 1586 .gpio_base = -1, 1587 }; 1588 1589 static int __devinit sm501_pci_probe(struct pci_dev *dev, 1590 const struct pci_device_id *id) 1591 { 1592 struct sm501_devdata *sm; 1593 int err; 1594 1595 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL); 1596 if (sm == NULL) { 1597 dev_err(&dev->dev, "no memory for device data\n"); 1598 err = -ENOMEM; 1599 goto err1; 1600 } 1601 1602 /* set a default set of platform data */ 1603 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata; 1604 1605 /* set a hopefully unique id for our child platform devices */ 1606 sm->pdev_id = 32 + dev->devfn; 1607 1608 pci_set_drvdata(dev, sm); 1609 1610 err = pci_enable_device(dev); 1611 if (err) { 1612 dev_err(&dev->dev, "cannot enable device\n"); 1613 goto err2; 1614 } 1615 1616 sm->dev = &dev->dev; 1617 sm->irq = dev->irq; 1618 1619 #ifdef __BIG_ENDIAN 1620 /* if the system is big-endian, we most probably have a 1621 * translation in the IO layer making the PCI bus little endian 1622 * so make the framebuffer swapped pixels */ 1623 1624 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN; 1625 #endif 1626 1627 /* check our resources */ 1628 1629 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) { 1630 dev_err(&dev->dev, "region #0 is not memory?\n"); 1631 err = -EINVAL; 1632 goto err3; 1633 } 1634 1635 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) { 1636 dev_err(&dev->dev, "region #1 is not memory?\n"); 1637 err = -EINVAL; 1638 goto err3; 1639 } 1640 1641 /* make our resources ready for sharing */ 1642 1643 sm->io_res = &dev->resource[1]; 1644 sm->mem_res = &dev->resource[0]; 1645 1646 sm->regs_claim = request_mem_region(sm->io_res->start, 1647 0x100, "sm501"); 1648 if (sm->regs_claim == NULL) { 1649 dev_err(&dev->dev, "cannot claim registers\n"); 1650 err= -EBUSY; 1651 goto err3; 1652 } 1653 1654 sm->regs = pci_ioremap_bar(dev, 1); 1655 1656 if (sm->regs == NULL) { 1657 dev_err(&dev->dev, "cannot remap registers\n"); 1658 err = -EIO; 1659 goto err4; 1660 } 1661 1662 sm501_init_dev(sm); 1663 return 0; 1664 1665 err4: 1666 release_resource(sm->regs_claim); 1667 kfree(sm->regs_claim); 1668 err3: 1669 pci_disable_device(dev); 1670 err2: 1671 pci_set_drvdata(dev, NULL); 1672 kfree(sm); 1673 err1: 1674 return err; 1675 } 1676 1677 static void sm501_remove_sub(struct sm501_devdata *sm, 1678 struct sm501_device *smdev) 1679 { 1680 list_del(&smdev->list); 1681 platform_device_unregister(&smdev->pdev); 1682 } 1683 1684 static void sm501_dev_remove(struct sm501_devdata *sm) 1685 { 1686 struct sm501_device *smdev, *tmp; 1687 1688 list_for_each_entry_safe(smdev, tmp, &sm->devices, list) 1689 sm501_remove_sub(sm, smdev); 1690 1691 device_remove_file(sm->dev, &dev_attr_dbg_regs); 1692 1693 sm501_gpio_remove(sm); 1694 } 1695 1696 static void __devexit sm501_pci_remove(struct pci_dev *dev) 1697 { 1698 struct sm501_devdata *sm = pci_get_drvdata(dev); 1699 1700 sm501_dev_remove(sm); 1701 iounmap(sm->regs); 1702 1703 release_resource(sm->regs_claim); 1704 kfree(sm->regs_claim); 1705 1706 pci_set_drvdata(dev, NULL); 1707 pci_disable_device(dev); 1708 } 1709 1710 static int sm501_plat_remove(struct platform_device *dev) 1711 { 1712 struct sm501_devdata *sm = platform_get_drvdata(dev); 1713 1714 sm501_dev_remove(sm); 1715 iounmap(sm->regs); 1716 1717 release_resource(sm->regs_claim); 1718 kfree(sm->regs_claim); 1719 1720 return 0; 1721 } 1722 1723 static struct pci_device_id sm501_pci_tbl[] = { 1724 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1725 { 0, }, 1726 }; 1727 1728 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); 1729 1730 static struct pci_driver sm501_pci_driver = { 1731 .name = "sm501", 1732 .id_table = sm501_pci_tbl, 1733 .probe = sm501_pci_probe, 1734 .remove = __devexit_p(sm501_pci_remove), 1735 }; 1736 1737 MODULE_ALIAS("platform:sm501"); 1738 1739 static struct platform_driver sm501_plat_driver = { 1740 .driver = { 1741 .name = "sm501", 1742 .owner = THIS_MODULE, 1743 }, 1744 .probe = sm501_plat_probe, 1745 .remove = sm501_plat_remove, 1746 .suspend = sm501_plat_suspend, 1747 .resume = sm501_plat_resume, 1748 }; 1749 1750 static int __init sm501_base_init(void) 1751 { 1752 platform_driver_register(&sm501_plat_driver); 1753 return pci_register_driver(&sm501_pci_driver); 1754 } 1755 1756 static void __exit sm501_base_exit(void) 1757 { 1758 platform_driver_unregister(&sm501_plat_driver); 1759 pci_unregister_driver(&sm501_pci_driver); 1760 } 1761 1762 module_init(sm501_base_init); 1763 module_exit(sm501_base_exit); 1764 1765 MODULE_DESCRIPTION("SM501 Core Driver"); 1766 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders"); 1767 MODULE_LICENSE("GPL v2"); 1768