1 /* linux/drivers/mfd/sm501.c 2 * 3 * Copyright (C) 2006 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * Vincent Sanders <vince@simtec.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * SM501 MFD driver 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/list.h> 19 #include <linux/device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pci.h> 22 #include <linux/i2c-gpio.h> 23 24 #include <linux/sm501.h> 25 #include <linux/sm501-regs.h> 26 #include <linux/serial_8250.h> 27 28 #include <asm/io.h> 29 30 struct sm501_device { 31 struct list_head list; 32 struct platform_device pdev; 33 }; 34 35 struct sm501_gpio; 36 37 #ifdef CONFIG_MFD_SM501_GPIO 38 #include <linux/gpio.h> 39 40 struct sm501_gpio_chip { 41 struct gpio_chip gpio; 42 struct sm501_gpio *ourgpio; /* to get back to parent. */ 43 void __iomem *regbase; 44 }; 45 46 struct sm501_gpio { 47 struct sm501_gpio_chip low; 48 struct sm501_gpio_chip high; 49 spinlock_t lock; 50 51 unsigned int registered : 1; 52 void __iomem *regs; 53 struct resource *regs_res; 54 }; 55 #else 56 struct sm501_gpio { 57 /* no gpio support, empty definition for sm501_devdata. */ 58 }; 59 #endif 60 61 struct sm501_devdata { 62 spinlock_t reg_lock; 63 struct mutex clock_lock; 64 struct list_head devices; 65 struct sm501_gpio gpio; 66 67 struct device *dev; 68 struct resource *io_res; 69 struct resource *mem_res; 70 struct resource *regs_claim; 71 struct sm501_platdata *platdata; 72 73 74 unsigned int in_suspend; 75 unsigned long pm_misc; 76 77 int unit_power[20]; 78 unsigned int pdev_id; 79 unsigned int irq; 80 void __iomem *regs; 81 unsigned int rev; 82 }; 83 84 85 #define MHZ (1000 * 1000) 86 87 #ifdef DEBUG 88 static const unsigned int div_tab[] = { 89 [0] = 1, 90 [1] = 2, 91 [2] = 4, 92 [3] = 8, 93 [4] = 16, 94 [5] = 32, 95 [6] = 64, 96 [7] = 128, 97 [8] = 3, 98 [9] = 6, 99 [10] = 12, 100 [11] = 24, 101 [12] = 48, 102 [13] = 96, 103 [14] = 192, 104 [15] = 384, 105 [16] = 5, 106 [17] = 10, 107 [18] = 20, 108 [19] = 40, 109 [20] = 80, 110 [21] = 160, 111 [22] = 320, 112 [23] = 604, 113 }; 114 115 static unsigned long decode_div(unsigned long pll2, unsigned long val, 116 unsigned int lshft, unsigned int selbit, 117 unsigned long mask) 118 { 119 if (val & selbit) 120 pll2 = 288 * MHZ; 121 122 return pll2 / div_tab[(val >> lshft) & mask]; 123 } 124 125 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x) 126 127 /* sm501_dump_clk 128 * 129 * Print out the current clock configuration for the device 130 */ 131 132 static void sm501_dump_clk(struct sm501_devdata *sm) 133 { 134 unsigned long misct = readl(sm->regs + SM501_MISC_TIMING); 135 unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK); 136 unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK); 137 unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL); 138 unsigned long sdclk0, sdclk1; 139 unsigned long pll2 = 0; 140 141 switch (misct & 0x30) { 142 case 0x00: 143 pll2 = 336 * MHZ; 144 break; 145 case 0x10: 146 pll2 = 288 * MHZ; 147 break; 148 case 0x20: 149 pll2 = 240 * MHZ; 150 break; 151 case 0x30: 152 pll2 = 192 * MHZ; 153 break; 154 } 155 156 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; 157 sdclk0 /= div_tab[((misct >> 8) & 0xf)]; 158 159 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; 160 sdclk1 /= div_tab[((misct >> 16) & 0xf)]; 161 162 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", 163 misct, pm0, pm1); 164 165 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", 166 fmt_freq(pll2), sdclk0, sdclk1); 167 168 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); 169 170 dev_dbg(sm->dev, "PM0[%c]: " 171 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 172 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 173 (pmc & 3 ) == 0 ? '*' : '-', 174 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), 175 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), 176 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), 177 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); 178 179 dev_dbg(sm->dev, "PM1[%c]: " 180 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 181 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 182 (pmc & 3 ) == 1 ? '*' : '-', 183 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), 184 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), 185 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), 186 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); 187 } 188 189 static void sm501_dump_regs(struct sm501_devdata *sm) 190 { 191 void __iomem *regs = sm->regs; 192 193 dev_info(sm->dev, "System Control %08x\n", 194 readl(regs + SM501_SYSTEM_CONTROL)); 195 dev_info(sm->dev, "Misc Control %08x\n", 196 readl(regs + SM501_MISC_CONTROL)); 197 dev_info(sm->dev, "GPIO Control Low %08x\n", 198 readl(regs + SM501_GPIO31_0_CONTROL)); 199 dev_info(sm->dev, "GPIO Control Hi %08x\n", 200 readl(regs + SM501_GPIO63_32_CONTROL)); 201 dev_info(sm->dev, "DRAM Control %08x\n", 202 readl(regs + SM501_DRAM_CONTROL)); 203 dev_info(sm->dev, "Arbitration Ctrl %08x\n", 204 readl(regs + SM501_ARBTRTN_CONTROL)); 205 dev_info(sm->dev, "Misc Timing %08x\n", 206 readl(regs + SM501_MISC_TIMING)); 207 } 208 209 static void sm501_dump_gate(struct sm501_devdata *sm) 210 { 211 dev_info(sm->dev, "CurrentGate %08x\n", 212 readl(sm->regs + SM501_CURRENT_GATE)); 213 dev_info(sm->dev, "CurrentClock %08x\n", 214 readl(sm->regs + SM501_CURRENT_CLOCK)); 215 dev_info(sm->dev, "PowerModeControl %08x\n", 216 readl(sm->regs + SM501_POWER_MODE_CONTROL)); 217 } 218 219 #else 220 static inline void sm501_dump_gate(struct sm501_devdata *sm) { } 221 static inline void sm501_dump_regs(struct sm501_devdata *sm) { } 222 static inline void sm501_dump_clk(struct sm501_devdata *sm) { } 223 #endif 224 225 /* sm501_sync_regs 226 * 227 * ensure the 228 */ 229 230 static void sm501_sync_regs(struct sm501_devdata *sm) 231 { 232 readl(sm->regs); 233 } 234 235 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) 236 { 237 /* during suspend/resume, we are currently not allowed to sleep, 238 * so change to using mdelay() instead of msleep() if we 239 * are in one of these paths */ 240 241 if (sm->in_suspend) 242 mdelay(delay); 243 else 244 msleep(delay); 245 } 246 247 /* sm501_misc_control 248 * 249 * alters the miscellaneous control parameters 250 */ 251 252 int sm501_misc_control(struct device *dev, 253 unsigned long set, unsigned long clear) 254 { 255 struct sm501_devdata *sm = dev_get_drvdata(dev); 256 unsigned long misc; 257 unsigned long save; 258 unsigned long to; 259 260 spin_lock_irqsave(&sm->reg_lock, save); 261 262 misc = readl(sm->regs + SM501_MISC_CONTROL); 263 to = (misc & ~clear) | set; 264 265 if (to != misc) { 266 writel(to, sm->regs + SM501_MISC_CONTROL); 267 sm501_sync_regs(sm); 268 269 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); 270 } 271 272 spin_unlock_irqrestore(&sm->reg_lock, save); 273 return to; 274 } 275 276 EXPORT_SYMBOL_GPL(sm501_misc_control); 277 278 /* sm501_modify_reg 279 * 280 * Modify a register in the SM501 which may be shared with other 281 * drivers. 282 */ 283 284 unsigned long sm501_modify_reg(struct device *dev, 285 unsigned long reg, 286 unsigned long set, 287 unsigned long clear) 288 { 289 struct sm501_devdata *sm = dev_get_drvdata(dev); 290 unsigned long data; 291 unsigned long save; 292 293 spin_lock_irqsave(&sm->reg_lock, save); 294 295 data = readl(sm->regs + reg); 296 data |= set; 297 data &= ~clear; 298 299 writel(data, sm->regs + reg); 300 sm501_sync_regs(sm); 301 302 spin_unlock_irqrestore(&sm->reg_lock, save); 303 304 return data; 305 } 306 307 EXPORT_SYMBOL_GPL(sm501_modify_reg); 308 309 /* sm501_unit_power 310 * 311 * alters the power active gate to set specific units on or off 312 */ 313 314 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) 315 { 316 struct sm501_devdata *sm = dev_get_drvdata(dev); 317 unsigned long mode; 318 unsigned long gate; 319 unsigned long clock; 320 321 mutex_lock(&sm->clock_lock); 322 323 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 324 gate = readl(sm->regs + SM501_CURRENT_GATE); 325 clock = readl(sm->regs + SM501_CURRENT_CLOCK); 326 327 mode &= 3; /* get current power mode */ 328 329 if (unit >= ARRAY_SIZE(sm->unit_power)) { 330 dev_err(dev, "%s: bad unit %d\n", __func__, unit); 331 goto already; 332 } 333 334 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit, 335 sm->unit_power[unit], to); 336 337 if (to == 0 && sm->unit_power[unit] == 0) { 338 dev_err(sm->dev, "unit %d is already shutdown\n", unit); 339 goto already; 340 } 341 342 sm->unit_power[unit] += to ? 1 : -1; 343 to = sm->unit_power[unit] ? 1 : 0; 344 345 if (to) { 346 if (gate & (1 << unit)) 347 goto already; 348 gate |= (1 << unit); 349 } else { 350 if (!(gate & (1 << unit))) 351 goto already; 352 gate &= ~(1 << unit); 353 } 354 355 switch (mode) { 356 case 1: 357 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 358 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 359 mode = 0; 360 break; 361 case 2: 362 case 0: 363 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 364 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 365 mode = 1; 366 break; 367 368 default: 369 return -1; 370 } 371 372 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 373 sm501_sync_regs(sm); 374 375 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 376 gate, clock, mode); 377 378 sm501_mdelay(sm, 16); 379 380 already: 381 mutex_unlock(&sm->clock_lock); 382 return gate; 383 } 384 385 EXPORT_SYMBOL_GPL(sm501_unit_power); 386 387 388 /* Perform a rounded division. */ 389 static long sm501fb_round_div(long num, long denom) 390 { 391 /* n / d + 1 / 2 = (2n + d) / 2d */ 392 return (2 * num + denom) / (2 * denom); 393 } 394 395 /* clock value structure. */ 396 struct sm501_clock { 397 unsigned long mclk; 398 int divider; 399 int shift; 400 unsigned int m, n, k; 401 }; 402 403 /* sm501_calc_clock 404 * 405 * Calculates the nearest discrete clock frequency that 406 * can be achieved with the specified input clock. 407 * the maximum divisor is 3 or 5 408 */ 409 410 static int sm501_calc_clock(unsigned long freq, 411 struct sm501_clock *clock, 412 int max_div, 413 unsigned long mclk, 414 long *best_diff) 415 { 416 int ret = 0; 417 int divider; 418 int shift; 419 long diff; 420 421 /* try dividers 1 and 3 for CRT and for panel, 422 try divider 5 for panel only.*/ 423 424 for (divider = 1; divider <= max_div; divider += 2) { 425 /* try all 8 shift values.*/ 426 for (shift = 0; shift < 8; shift++) { 427 /* Calculate difference to requested clock */ 428 diff = sm501fb_round_div(mclk, divider << shift) - freq; 429 if (diff < 0) 430 diff = -diff; 431 432 /* If it is less than the current, use it */ 433 if (diff < *best_diff) { 434 *best_diff = diff; 435 436 clock->mclk = mclk; 437 clock->divider = divider; 438 clock->shift = shift; 439 ret = 1; 440 } 441 } 442 } 443 444 return ret; 445 } 446 447 /* sm501_calc_pll 448 * 449 * Calculates the nearest discrete clock frequency that can be 450 * achieved using the programmable PLL. 451 * the maximum divisor is 3 or 5 452 */ 453 454 static unsigned long sm501_calc_pll(unsigned long freq, 455 struct sm501_clock *clock, 456 int max_div) 457 { 458 unsigned long mclk; 459 unsigned int m, n, k; 460 long best_diff = 999999999; 461 462 /* 463 * The SM502 datasheet doesn't specify the min/max values for M and N. 464 * N = 1 at least doesn't work in practice. 465 */ 466 for (m = 2; m <= 255; m++) { 467 for (n = 2; n <= 127; n++) { 468 for (k = 0; k <= 1; k++) { 469 mclk = (24000000UL * m / n) >> k; 470 471 if (sm501_calc_clock(freq, clock, max_div, 472 mclk, &best_diff)) { 473 clock->m = m; 474 clock->n = n; 475 clock->k = k; 476 } 477 } 478 } 479 } 480 481 /* Return best clock. */ 482 return clock->mclk / (clock->divider << clock->shift); 483 } 484 485 /* sm501_select_clock 486 * 487 * Calculates the nearest discrete clock frequency that can be 488 * achieved using the 288MHz and 336MHz PLLs. 489 * the maximum divisor is 3 or 5 490 */ 491 492 static unsigned long sm501_select_clock(unsigned long freq, 493 struct sm501_clock *clock, 494 int max_div) 495 { 496 unsigned long mclk; 497 long best_diff = 999999999; 498 499 /* Try 288MHz and 336MHz clocks. */ 500 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { 501 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); 502 } 503 504 /* Return best clock. */ 505 return clock->mclk / (clock->divider << clock->shift); 506 } 507 508 /* sm501_set_clock 509 * 510 * set one of the four clock sources to the closest available frequency to 511 * the one specified 512 */ 513 514 unsigned long sm501_set_clock(struct device *dev, 515 int clksrc, 516 unsigned long req_freq) 517 { 518 struct sm501_devdata *sm = dev_get_drvdata(dev); 519 unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 520 unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE); 521 unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK); 522 unsigned char reg; 523 unsigned int pll_reg = 0; 524 unsigned long sm501_freq; /* the actual frequency acheived */ 525 526 struct sm501_clock to; 527 528 /* find achivable discrete frequency and setup register value 529 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK 530 * has an extra bit for the divider */ 531 532 switch (clksrc) { 533 case SM501_CLOCK_P2XCLK: 534 /* This clock is divided in half so to achive the 535 * requested frequency the value must be multiplied by 536 * 2. This clock also has an additional pre divisor */ 537 538 if (sm->rev >= 0xC0) { 539 /* SM502 -> use the programmable PLL */ 540 sm501_freq = (sm501_calc_pll(2 * req_freq, 541 &to, 5) / 2); 542 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 543 if (to.divider == 3) 544 reg |= 0x08; /* /3 divider required */ 545 else if (to.divider == 5) 546 reg |= 0x10; /* /5 divider required */ 547 reg |= 0x40; /* select the programmable PLL */ 548 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; 549 } else { 550 sm501_freq = (sm501_select_clock(2 * req_freq, 551 &to, 5) / 2); 552 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 553 if (to.divider == 3) 554 reg |= 0x08; /* /3 divider required */ 555 else if (to.divider == 5) 556 reg |= 0x10; /* /5 divider required */ 557 if (to.mclk != 288000000) 558 reg |= 0x20; /* which mclk pll is source */ 559 } 560 break; 561 562 case SM501_CLOCK_V2XCLK: 563 /* This clock is divided in half so to achive the 564 * requested frequency the value must be multiplied by 2. */ 565 566 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 567 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 568 if (to.divider == 3) 569 reg |= 0x08; /* /3 divider required */ 570 if (to.mclk != 288000000) 571 reg |= 0x10; /* which mclk pll is source */ 572 break; 573 574 case SM501_CLOCK_MCLK: 575 case SM501_CLOCK_M1XCLK: 576 /* These clocks are the same and not further divided */ 577 578 sm501_freq = sm501_select_clock( req_freq, &to, 3); 579 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 580 if (to.divider == 3) 581 reg |= 0x08; /* /3 divider required */ 582 if (to.mclk != 288000000) 583 reg |= 0x10; /* which mclk pll is source */ 584 break; 585 586 default: 587 return 0; /* this is bad */ 588 } 589 590 mutex_lock(&sm->clock_lock); 591 592 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 593 gate = readl(sm->regs + SM501_CURRENT_GATE); 594 clock = readl(sm->regs + SM501_CURRENT_CLOCK); 595 596 clock = clock & ~(0xFF << clksrc); 597 clock |= reg<<clksrc; 598 599 mode &= 3; /* find current mode */ 600 601 switch (mode) { 602 case 1: 603 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 604 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 605 mode = 0; 606 break; 607 case 2: 608 case 0: 609 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 610 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 611 mode = 1; 612 break; 613 614 default: 615 mutex_unlock(&sm->clock_lock); 616 return -1; 617 } 618 619 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 620 621 if (pll_reg) 622 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); 623 624 sm501_sync_regs(sm); 625 626 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 627 gate, clock, mode); 628 629 sm501_mdelay(sm, 16); 630 mutex_unlock(&sm->clock_lock); 631 632 sm501_dump_clk(sm); 633 634 return sm501_freq; 635 } 636 637 EXPORT_SYMBOL_GPL(sm501_set_clock); 638 639 /* sm501_find_clock 640 * 641 * finds the closest available frequency for a given clock 642 */ 643 644 unsigned long sm501_find_clock(struct device *dev, 645 int clksrc, 646 unsigned long req_freq) 647 { 648 struct sm501_devdata *sm = dev_get_drvdata(dev); 649 unsigned long sm501_freq; /* the frequency achiveable by the 501 */ 650 struct sm501_clock to; 651 652 switch (clksrc) { 653 case SM501_CLOCK_P2XCLK: 654 if (sm->rev >= 0xC0) { 655 /* SM502 -> use the programmable PLL */ 656 sm501_freq = (sm501_calc_pll(2 * req_freq, 657 &to, 5) / 2); 658 } else { 659 sm501_freq = (sm501_select_clock(2 * req_freq, 660 &to, 5) / 2); 661 } 662 break; 663 664 case SM501_CLOCK_V2XCLK: 665 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 666 break; 667 668 case SM501_CLOCK_MCLK: 669 case SM501_CLOCK_M1XCLK: 670 sm501_freq = sm501_select_clock(req_freq, &to, 3); 671 break; 672 673 default: 674 sm501_freq = 0; /* error */ 675 } 676 677 return sm501_freq; 678 } 679 680 EXPORT_SYMBOL_GPL(sm501_find_clock); 681 682 static struct sm501_device *to_sm_device(struct platform_device *pdev) 683 { 684 return container_of(pdev, struct sm501_device, pdev); 685 } 686 687 /* sm501_device_release 688 * 689 * A release function for the platform devices we create to allow us to 690 * free any items we allocated 691 */ 692 693 static void sm501_device_release(struct device *dev) 694 { 695 kfree(to_sm_device(to_platform_device(dev))); 696 } 697 698 /* sm501_create_subdev 699 * 700 * Create a skeleton platform device with resources for passing to a 701 * sub-driver 702 */ 703 704 static struct platform_device * 705 sm501_create_subdev(struct sm501_devdata *sm, char *name, 706 unsigned int res_count, unsigned int platform_data_size) 707 { 708 struct sm501_device *smdev; 709 710 smdev = kzalloc(sizeof(struct sm501_device) + 711 (sizeof(struct resource) * res_count) + 712 platform_data_size, GFP_KERNEL); 713 if (!smdev) 714 return NULL; 715 716 smdev->pdev.dev.release = sm501_device_release; 717 718 smdev->pdev.name = name; 719 smdev->pdev.id = sm->pdev_id; 720 smdev->pdev.dev.parent = sm->dev; 721 722 if (res_count) { 723 smdev->pdev.resource = (struct resource *)(smdev+1); 724 smdev->pdev.num_resources = res_count; 725 } 726 if (platform_data_size) 727 smdev->pdev.dev.platform_data = (void *)(smdev+1); 728 729 return &smdev->pdev; 730 } 731 732 /* sm501_register_device 733 * 734 * Register a platform device created with sm501_create_subdev() 735 */ 736 737 static int sm501_register_device(struct sm501_devdata *sm, 738 struct platform_device *pdev) 739 { 740 struct sm501_device *smdev = to_sm_device(pdev); 741 int ptr; 742 int ret; 743 744 for (ptr = 0; ptr < pdev->num_resources; ptr++) { 745 printk(KERN_DEBUG "%s[%d] flags %08lx: %08llx..%08llx\n", 746 pdev->name, ptr, 747 pdev->resource[ptr].flags, 748 (unsigned long long)pdev->resource[ptr].start, 749 (unsigned long long)pdev->resource[ptr].end); 750 } 751 752 ret = platform_device_register(pdev); 753 754 if (ret >= 0) { 755 dev_dbg(sm->dev, "registered %s\n", pdev->name); 756 list_add_tail(&smdev->list, &sm->devices); 757 } else 758 dev_err(sm->dev, "error registering %s (%d)\n", 759 pdev->name, ret); 760 761 return ret; 762 } 763 764 /* sm501_create_subio 765 * 766 * Fill in an IO resource for a sub device 767 */ 768 769 static void sm501_create_subio(struct sm501_devdata *sm, 770 struct resource *res, 771 resource_size_t offs, 772 resource_size_t size) 773 { 774 res->flags = IORESOURCE_MEM; 775 res->parent = sm->io_res; 776 res->start = sm->io_res->start + offs; 777 res->end = res->start + size - 1; 778 } 779 780 /* sm501_create_mem 781 * 782 * Fill in an MEM resource for a sub device 783 */ 784 785 static void sm501_create_mem(struct sm501_devdata *sm, 786 struct resource *res, 787 resource_size_t *offs, 788 resource_size_t size) 789 { 790 *offs -= size; /* adjust memory size */ 791 792 res->flags = IORESOURCE_MEM; 793 res->parent = sm->mem_res; 794 res->start = sm->mem_res->start + *offs; 795 res->end = res->start + size - 1; 796 } 797 798 /* sm501_create_irq 799 * 800 * Fill in an IRQ resource for a sub device 801 */ 802 803 static void sm501_create_irq(struct sm501_devdata *sm, 804 struct resource *res) 805 { 806 res->flags = IORESOURCE_IRQ; 807 res->parent = NULL; 808 res->start = res->end = sm->irq; 809 } 810 811 static int sm501_register_usbhost(struct sm501_devdata *sm, 812 resource_size_t *mem_avail) 813 { 814 struct platform_device *pdev; 815 816 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0); 817 if (!pdev) 818 return -ENOMEM; 819 820 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000); 821 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024); 822 sm501_create_irq(sm, &pdev->resource[2]); 823 824 return sm501_register_device(sm, pdev); 825 } 826 827 static void sm501_setup_uart_data(struct sm501_devdata *sm, 828 struct plat_serial8250_port *uart_data, 829 unsigned int offset) 830 { 831 uart_data->membase = sm->regs + offset; 832 uart_data->mapbase = sm->io_res->start + offset; 833 uart_data->iotype = UPIO_MEM; 834 uart_data->irq = sm->irq; 835 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 836 uart_data->regshift = 2; 837 uart_data->uartclk = (9600 * 16); 838 } 839 840 static int sm501_register_uart(struct sm501_devdata *sm, int devices) 841 { 842 struct platform_device *pdev; 843 struct plat_serial8250_port *uart_data; 844 845 pdev = sm501_create_subdev(sm, "serial8250", 0, 846 sizeof(struct plat_serial8250_port) * 3); 847 if (!pdev) 848 return -ENOMEM; 849 850 uart_data = pdev->dev.platform_data; 851 852 if (devices & SM501_USE_UART0) { 853 sm501_setup_uart_data(sm, uart_data++, 0x30000); 854 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1); 855 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0); 856 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0); 857 } 858 if (devices & SM501_USE_UART1) { 859 sm501_setup_uart_data(sm, uart_data++, 0x30020); 860 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1); 861 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0); 862 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0); 863 } 864 865 pdev->id = PLAT8250_DEV_SM501; 866 867 return sm501_register_device(sm, pdev); 868 } 869 870 static int sm501_register_display(struct sm501_devdata *sm, 871 resource_size_t *mem_avail) 872 { 873 struct platform_device *pdev; 874 875 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0); 876 if (!pdev) 877 return -ENOMEM; 878 879 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000); 880 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000); 881 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail); 882 sm501_create_irq(sm, &pdev->resource[3]); 883 884 return sm501_register_device(sm, pdev); 885 } 886 887 #ifdef CONFIG_MFD_SM501_GPIO 888 889 static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc) 890 { 891 return container_of(gc, struct sm501_gpio_chip, gpio); 892 } 893 894 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio) 895 { 896 return container_of(gpio, struct sm501_devdata, gpio); 897 } 898 899 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) 900 901 { 902 struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip); 903 unsigned long result; 904 905 result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW); 906 result >>= offset; 907 908 return result & 1UL; 909 } 910 911 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 912 913 { 914 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip); 915 struct sm501_gpio *smgpio = smchip->ourgpio; 916 unsigned long bit = 1 << offset; 917 void __iomem *regs = smchip->regbase; 918 unsigned long save; 919 unsigned long val; 920 921 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 922 __func__, chip, offset); 923 924 spin_lock_irqsave(&smgpio->lock, save); 925 926 val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit; 927 if (value) 928 val |= bit; 929 writel(val, regs); 930 931 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 932 spin_unlock_irqrestore(&smgpio->lock, save); 933 } 934 935 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) 936 { 937 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip); 938 struct sm501_gpio *smgpio = smchip->ourgpio; 939 void __iomem *regs = smchip->regbase; 940 unsigned long bit = 1 << offset; 941 unsigned long save; 942 unsigned long ddr; 943 944 dev_info(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 945 __func__, chip, offset); 946 947 spin_lock_irqsave(&smgpio->lock, save); 948 949 ddr = readl(regs + SM501_GPIO_DDR_LOW); 950 writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); 951 952 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 953 spin_unlock_irqrestore(&smgpio->lock, save); 954 955 return 0; 956 } 957 958 static int sm501_gpio_output(struct gpio_chip *chip, 959 unsigned offset, int value) 960 { 961 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip); 962 struct sm501_gpio *smgpio = smchip->ourgpio; 963 unsigned long bit = 1 << offset; 964 void __iomem *regs = smchip->regbase; 965 unsigned long save; 966 unsigned long val; 967 unsigned long ddr; 968 969 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n", 970 __func__, chip, offset, value); 971 972 spin_lock_irqsave(&smgpio->lock, save); 973 974 val = readl(regs + SM501_GPIO_DATA_LOW); 975 if (value) 976 val |= bit; 977 else 978 val &= ~bit; 979 writel(val, regs); 980 981 ddr = readl(regs + SM501_GPIO_DDR_LOW); 982 writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); 983 984 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 985 writel(val, regs + SM501_GPIO_DATA_LOW); 986 987 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 988 spin_unlock_irqrestore(&smgpio->lock, save); 989 990 return 0; 991 } 992 993 static struct gpio_chip gpio_chip_template = { 994 .ngpio = 32, 995 .direction_input = sm501_gpio_input, 996 .direction_output = sm501_gpio_output, 997 .set = sm501_gpio_set, 998 .get = sm501_gpio_get, 999 }; 1000 1001 static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm, 1002 struct sm501_gpio *gpio, 1003 struct sm501_gpio_chip *chip) 1004 { 1005 struct sm501_platdata *pdata = sm->platdata; 1006 struct gpio_chip *gchip = &chip->gpio; 1007 int base = pdata->gpio_base; 1008 1009 chip->gpio = gpio_chip_template; 1010 1011 if (chip == &gpio->high) { 1012 if (base > 0) 1013 base += 32; 1014 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; 1015 gchip->label = "SM501-HIGH"; 1016 } else { 1017 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; 1018 gchip->label = "SM501-LOW"; 1019 } 1020 1021 gchip->base = base; 1022 chip->ourgpio = gpio; 1023 1024 return gpiochip_add(gchip); 1025 } 1026 1027 static int sm501_register_gpio(struct sm501_devdata *sm) 1028 { 1029 struct sm501_gpio *gpio = &sm->gpio; 1030 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1031 int ret; 1032 int tmp; 1033 1034 dev_dbg(sm->dev, "registering gpio block %08llx\n", 1035 (unsigned long long)iobase); 1036 1037 spin_lock_init(&gpio->lock); 1038 1039 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio"); 1040 if (gpio->regs_res == NULL) { 1041 dev_err(sm->dev, "gpio: failed to request region\n"); 1042 return -ENXIO; 1043 } 1044 1045 gpio->regs = ioremap(iobase, 0x20); 1046 if (gpio->regs == NULL) { 1047 dev_err(sm->dev, "gpio: failed to remap registers\n"); 1048 ret = -ENXIO; 1049 goto err_claimed; 1050 } 1051 1052 /* Register both our chips. */ 1053 1054 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low); 1055 if (ret) { 1056 dev_err(sm->dev, "failed to add low chip\n"); 1057 goto err_mapped; 1058 } 1059 1060 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high); 1061 if (ret) { 1062 dev_err(sm->dev, "failed to add high chip\n"); 1063 goto err_low_chip; 1064 } 1065 1066 gpio->registered = 1; 1067 1068 return 0; 1069 1070 err_low_chip: 1071 tmp = gpiochip_remove(&gpio->low.gpio); 1072 if (tmp) { 1073 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n"); 1074 return ret; 1075 } 1076 1077 err_mapped: 1078 iounmap(gpio->regs); 1079 1080 err_claimed: 1081 release_resource(gpio->regs_res); 1082 kfree(gpio->regs_res); 1083 1084 return ret; 1085 } 1086 1087 static void sm501_gpio_remove(struct sm501_devdata *sm) 1088 { 1089 struct sm501_gpio *gpio = &sm->gpio; 1090 int ret; 1091 1092 if (!sm->gpio.registered) 1093 return; 1094 1095 ret = gpiochip_remove(&gpio->low.gpio); 1096 if (ret) 1097 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n"); 1098 1099 ret = gpiochip_remove(&gpio->high.gpio); 1100 if (ret) 1101 dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n"); 1102 1103 iounmap(gpio->regs); 1104 release_resource(gpio->regs_res); 1105 kfree(gpio->regs_res); 1106 } 1107 1108 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin) 1109 { 1110 struct sm501_gpio *gpio = &sm->gpio; 1111 int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base; 1112 1113 return (pin % 32) + base; 1114 } 1115 1116 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1117 { 1118 return sm->gpio.registered; 1119 } 1120 #else 1121 static inline int sm501_register_gpio(struct sm501_devdata *sm) 1122 { 1123 return 0; 1124 } 1125 1126 static inline void sm501_gpio_remove(struct sm501_devdata *sm) 1127 { 1128 } 1129 1130 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin) 1131 { 1132 return -1; 1133 } 1134 1135 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1136 { 1137 return 0; 1138 } 1139 #endif 1140 1141 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm, 1142 struct sm501_platdata_gpio_i2c *iic) 1143 { 1144 struct i2c_gpio_platform_data *icd; 1145 struct platform_device *pdev; 1146 1147 pdev = sm501_create_subdev(sm, "i2c-gpio", 0, 1148 sizeof(struct i2c_gpio_platform_data)); 1149 if (!pdev) 1150 return -ENOMEM; 1151 1152 icd = pdev->dev.platform_data; 1153 1154 /* We keep the pin_sda and pin_scl fields relative in case the 1155 * same platform data is passed to >1 SM501. 1156 */ 1157 1158 icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda); 1159 icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl); 1160 icd->timeout = iic->timeout; 1161 icd->udelay = iic->udelay; 1162 1163 /* note, we can't use either of the pin numbers, as the i2c-gpio 1164 * driver uses the platform.id field to generate the bus number 1165 * to register with the i2c core; The i2c core doesn't have enough 1166 * entries to deal with anything we currently use. 1167 */ 1168 1169 pdev->id = iic->bus_num; 1170 1171 dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n", 1172 iic->bus_num, 1173 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl); 1174 1175 return sm501_register_device(sm, pdev); 1176 } 1177 1178 static int sm501_register_gpio_i2c(struct sm501_devdata *sm, 1179 struct sm501_platdata *pdata) 1180 { 1181 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c; 1182 int index; 1183 int ret; 1184 1185 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) { 1186 ret = sm501_register_gpio_i2c_instance(sm, iic); 1187 if (ret < 0) 1188 return ret; 1189 } 1190 1191 return 0; 1192 } 1193 1194 /* sm501_dbg_regs 1195 * 1196 * Debug attribute to attach to parent device to show core registers 1197 */ 1198 1199 static ssize_t sm501_dbg_regs(struct device *dev, 1200 struct device_attribute *attr, char *buff) 1201 { 1202 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 1203 unsigned int reg; 1204 char *ptr = buff; 1205 int ret; 1206 1207 for (reg = 0x00; reg < 0x70; reg += 4) { 1208 ret = sprintf(ptr, "%08x = %08x\n", 1209 reg, readl(sm->regs + reg)); 1210 ptr += ret; 1211 } 1212 1213 return ptr - buff; 1214 } 1215 1216 1217 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL); 1218 1219 /* sm501_init_reg 1220 * 1221 * Helper function for the init code to setup a register 1222 * 1223 * clear the bits which are set in r->mask, and then set 1224 * the bits set in r->set. 1225 */ 1226 1227 static inline void sm501_init_reg(struct sm501_devdata *sm, 1228 unsigned long reg, 1229 struct sm501_reg_init *r) 1230 { 1231 unsigned long tmp; 1232 1233 tmp = readl(sm->regs + reg); 1234 tmp &= ~r->mask; 1235 tmp |= r->set; 1236 writel(tmp, sm->regs + reg); 1237 } 1238 1239 /* sm501_init_regs 1240 * 1241 * Setup core register values 1242 */ 1243 1244 static void sm501_init_regs(struct sm501_devdata *sm, 1245 struct sm501_initdata *init) 1246 { 1247 sm501_misc_control(sm->dev, 1248 init->misc_control.set, 1249 init->misc_control.mask); 1250 1251 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing); 1252 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low); 1253 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high); 1254 1255 if (init->m1xclk) { 1256 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk); 1257 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk); 1258 } 1259 1260 if (init->mclk) { 1261 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); 1262 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); 1263 } 1264 1265 } 1266 1267 /* Check the PLL sources for the M1CLK and M1XCLK 1268 * 1269 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then 1270 * there is a risk (see errata AB-5) that the SM501 will cease proper 1271 * function. If this happens, then it is likely the SM501 will 1272 * hang the system. 1273 */ 1274 1275 static int sm501_check_clocks(struct sm501_devdata *sm) 1276 { 1277 unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK); 1278 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); 1279 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); 1280 1281 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0)); 1282 } 1283 1284 static unsigned int sm501_mem_local[] = { 1285 [0] = 4*1024*1024, 1286 [1] = 8*1024*1024, 1287 [2] = 16*1024*1024, 1288 [3] = 32*1024*1024, 1289 [4] = 64*1024*1024, 1290 [5] = 2*1024*1024, 1291 }; 1292 1293 /* sm501_init_dev 1294 * 1295 * Common init code for an SM501 1296 */ 1297 1298 static int sm501_init_dev(struct sm501_devdata *sm) 1299 { 1300 struct sm501_initdata *idata; 1301 struct sm501_platdata *pdata; 1302 resource_size_t mem_avail; 1303 unsigned long dramctrl; 1304 unsigned long devid; 1305 int ret; 1306 1307 mutex_init(&sm->clock_lock); 1308 spin_lock_init(&sm->reg_lock); 1309 1310 INIT_LIST_HEAD(&sm->devices); 1311 1312 devid = readl(sm->regs + SM501_DEVICEID); 1313 1314 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { 1315 dev_err(sm->dev, "incorrect device id %08lx\n", devid); 1316 return -EINVAL; 1317 } 1318 1319 /* disable irqs */ 1320 writel(0, sm->regs + SM501_IRQ_MASK); 1321 1322 dramctrl = readl(sm->regs + SM501_DRAM_CONTROL); 1323 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; 1324 1325 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", 1326 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq); 1327 1328 sm->rev = devid & SM501_DEVICEID_REVMASK; 1329 1330 sm501_dump_gate(sm); 1331 1332 ret = device_create_file(sm->dev, &dev_attr_dbg_regs); 1333 if (ret) 1334 dev_err(sm->dev, "failed to create debug regs file\n"); 1335 1336 sm501_dump_clk(sm); 1337 1338 /* check to see if we have some device initialisation */ 1339 1340 pdata = sm->platdata; 1341 idata = pdata ? pdata->init : NULL; 1342 1343 if (idata) { 1344 sm501_init_regs(sm, idata); 1345 1346 if (idata->devices & SM501_USE_USB_HOST) 1347 sm501_register_usbhost(sm, &mem_avail); 1348 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1)) 1349 sm501_register_uart(sm, idata->devices); 1350 if (idata->devices & SM501_USE_GPIO) 1351 sm501_register_gpio(sm); 1352 } 1353 1354 if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) { 1355 if (!sm501_gpio_isregistered(sm)) 1356 dev_err(sm->dev, "no gpio available for i2c gpio.\n"); 1357 else 1358 sm501_register_gpio_i2c(sm, pdata); 1359 } 1360 1361 ret = sm501_check_clocks(sm); 1362 if (ret) { 1363 dev_err(sm->dev, "M1X and M clocks sourced from different " 1364 "PLLs\n"); 1365 return -EINVAL; 1366 } 1367 1368 /* always create a framebuffer */ 1369 sm501_register_display(sm, &mem_avail); 1370 1371 return 0; 1372 } 1373 1374 static int sm501_plat_probe(struct platform_device *dev) 1375 { 1376 struct sm501_devdata *sm; 1377 int err; 1378 1379 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL); 1380 if (sm == NULL) { 1381 dev_err(&dev->dev, "no memory for device data\n"); 1382 err = -ENOMEM; 1383 goto err1; 1384 } 1385 1386 sm->dev = &dev->dev; 1387 sm->pdev_id = dev->id; 1388 sm->irq = platform_get_irq(dev, 0); 1389 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 1390 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1391 sm->platdata = dev->dev.platform_data; 1392 1393 if (sm->irq < 0) { 1394 dev_err(&dev->dev, "failed to get irq resource\n"); 1395 err = sm->irq; 1396 goto err_res; 1397 } 1398 1399 if (sm->io_res == NULL || sm->mem_res == NULL) { 1400 dev_err(&dev->dev, "failed to get IO resource\n"); 1401 err = -ENOENT; 1402 goto err_res; 1403 } 1404 1405 sm->regs_claim = request_mem_region(sm->io_res->start, 1406 0x100, "sm501"); 1407 1408 if (sm->regs_claim == NULL) { 1409 dev_err(&dev->dev, "cannot claim registers\n"); 1410 err= -EBUSY; 1411 goto err_res; 1412 } 1413 1414 platform_set_drvdata(dev, sm); 1415 1416 sm->regs = ioremap(sm->io_res->start, 1417 (sm->io_res->end - sm->io_res->start) - 1); 1418 1419 if (sm->regs == NULL) { 1420 dev_err(&dev->dev, "cannot remap registers\n"); 1421 err = -EIO; 1422 goto err_claim; 1423 } 1424 1425 return sm501_init_dev(sm); 1426 1427 err_claim: 1428 release_resource(sm->regs_claim); 1429 kfree(sm->regs_claim); 1430 err_res: 1431 kfree(sm); 1432 err1: 1433 return err; 1434 1435 } 1436 1437 #ifdef CONFIG_PM 1438 1439 /* power management support */ 1440 1441 static void sm501_set_power(struct sm501_devdata *sm, int on) 1442 { 1443 struct sm501_platdata *pd = sm->platdata; 1444 1445 if (pd == NULL) 1446 return; 1447 1448 if (pd->get_power) { 1449 if (pd->get_power(sm->dev) == on) { 1450 dev_dbg(sm->dev, "is already %d\n", on); 1451 return; 1452 } 1453 } 1454 1455 if (pd->set_power) { 1456 dev_dbg(sm->dev, "setting power to %d\n", on); 1457 1458 pd->set_power(sm->dev, on); 1459 sm501_mdelay(sm, 10); 1460 } 1461 } 1462 1463 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) 1464 { 1465 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1466 1467 sm->in_suspend = 1; 1468 sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL); 1469 1470 sm501_dump_regs(sm); 1471 1472 if (sm->platdata) { 1473 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF) 1474 sm501_set_power(sm, 0); 1475 } 1476 1477 return 0; 1478 } 1479 1480 static int sm501_plat_resume(struct platform_device *pdev) 1481 { 1482 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1483 1484 sm501_set_power(sm, 1); 1485 1486 sm501_dump_regs(sm); 1487 sm501_dump_gate(sm); 1488 sm501_dump_clk(sm); 1489 1490 /* check to see if we are in the same state as when suspended */ 1491 1492 if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { 1493 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); 1494 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); 1495 1496 /* our suspend causes the controller state to change, 1497 * either by something attempting setup, power loss, 1498 * or an external reset event on power change */ 1499 1500 if (sm->platdata && sm->platdata->init) { 1501 sm501_init_regs(sm, sm->platdata->init); 1502 } 1503 } 1504 1505 /* dump our state from resume */ 1506 1507 sm501_dump_regs(sm); 1508 sm501_dump_clk(sm); 1509 1510 sm->in_suspend = 0; 1511 1512 return 0; 1513 } 1514 #else 1515 #define sm501_plat_suspend NULL 1516 #define sm501_plat_resume NULL 1517 #endif 1518 1519 /* Initialisation data for PCI devices */ 1520 1521 static struct sm501_initdata sm501_pci_initdata = { 1522 .gpio_high = { 1523 .set = 0x3F000000, /* 24bit panel */ 1524 .mask = 0x0, 1525 }, 1526 .misc_timing = { 1527 .set = 0x010100, /* SDRAM timing */ 1528 .mask = 0x1F1F00, 1529 }, 1530 .misc_control = { 1531 .set = SM501_MISC_PNL_24BIT, 1532 .mask = 0, 1533 }, 1534 1535 .devices = SM501_USE_ALL, 1536 1537 /* Errata AB-3 says that 72MHz is the fastest available 1538 * for 33MHZ PCI with proper bus-mastering operation */ 1539 1540 .mclk = 72 * MHZ, 1541 .m1xclk = 144 * MHZ, 1542 }; 1543 1544 static struct sm501_platdata_fbsub sm501_pdata_fbsub = { 1545 .flags = (SM501FB_FLAG_USE_INIT_MODE | 1546 SM501FB_FLAG_USE_HWCURSOR | 1547 SM501FB_FLAG_USE_HWACCEL | 1548 SM501FB_FLAG_DISABLE_AT_EXIT), 1549 }; 1550 1551 static struct sm501_platdata_fb sm501_fb_pdata = { 1552 .fb_route = SM501_FB_OWN, 1553 .fb_crt = &sm501_pdata_fbsub, 1554 .fb_pnl = &sm501_pdata_fbsub, 1555 }; 1556 1557 static struct sm501_platdata sm501_pci_platdata = { 1558 .init = &sm501_pci_initdata, 1559 .fb = &sm501_fb_pdata, 1560 .gpio_base = -1, 1561 }; 1562 1563 static int sm501_pci_probe(struct pci_dev *dev, 1564 const struct pci_device_id *id) 1565 { 1566 struct sm501_devdata *sm; 1567 int err; 1568 1569 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL); 1570 if (sm == NULL) { 1571 dev_err(&dev->dev, "no memory for device data\n"); 1572 err = -ENOMEM; 1573 goto err1; 1574 } 1575 1576 /* set a default set of platform data */ 1577 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata; 1578 1579 /* set a hopefully unique id for our child platform devices */ 1580 sm->pdev_id = 32 + dev->devfn; 1581 1582 pci_set_drvdata(dev, sm); 1583 1584 err = pci_enable_device(dev); 1585 if (err) { 1586 dev_err(&dev->dev, "cannot enable device\n"); 1587 goto err2; 1588 } 1589 1590 sm->dev = &dev->dev; 1591 sm->irq = dev->irq; 1592 1593 #ifdef __BIG_ENDIAN 1594 /* if the system is big-endian, we most probably have a 1595 * translation in the IO layer making the PCI bus little endian 1596 * so make the framebuffer swapped pixels */ 1597 1598 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN; 1599 #endif 1600 1601 /* check our resources */ 1602 1603 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) { 1604 dev_err(&dev->dev, "region #0 is not memory?\n"); 1605 err = -EINVAL; 1606 goto err3; 1607 } 1608 1609 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) { 1610 dev_err(&dev->dev, "region #1 is not memory?\n"); 1611 err = -EINVAL; 1612 goto err3; 1613 } 1614 1615 /* make our resources ready for sharing */ 1616 1617 sm->io_res = &dev->resource[1]; 1618 sm->mem_res = &dev->resource[0]; 1619 1620 sm->regs_claim = request_mem_region(sm->io_res->start, 1621 0x100, "sm501"); 1622 if (sm->regs_claim == NULL) { 1623 dev_err(&dev->dev, "cannot claim registers\n"); 1624 err= -EBUSY; 1625 goto err3; 1626 } 1627 1628 sm->regs = pci_ioremap_bar(dev, 1); 1629 1630 if (sm->regs == NULL) { 1631 dev_err(&dev->dev, "cannot remap registers\n"); 1632 err = -EIO; 1633 goto err4; 1634 } 1635 1636 sm501_init_dev(sm); 1637 return 0; 1638 1639 err4: 1640 release_resource(sm->regs_claim); 1641 kfree(sm->regs_claim); 1642 err3: 1643 pci_disable_device(dev); 1644 err2: 1645 pci_set_drvdata(dev, NULL); 1646 kfree(sm); 1647 err1: 1648 return err; 1649 } 1650 1651 static void sm501_remove_sub(struct sm501_devdata *sm, 1652 struct sm501_device *smdev) 1653 { 1654 list_del(&smdev->list); 1655 platform_device_unregister(&smdev->pdev); 1656 } 1657 1658 static void sm501_dev_remove(struct sm501_devdata *sm) 1659 { 1660 struct sm501_device *smdev, *tmp; 1661 1662 list_for_each_entry_safe(smdev, tmp, &sm->devices, list) 1663 sm501_remove_sub(sm, smdev); 1664 1665 device_remove_file(sm->dev, &dev_attr_dbg_regs); 1666 1667 sm501_gpio_remove(sm); 1668 } 1669 1670 static void sm501_pci_remove(struct pci_dev *dev) 1671 { 1672 struct sm501_devdata *sm = pci_get_drvdata(dev); 1673 1674 sm501_dev_remove(sm); 1675 iounmap(sm->regs); 1676 1677 release_resource(sm->regs_claim); 1678 kfree(sm->regs_claim); 1679 1680 pci_set_drvdata(dev, NULL); 1681 pci_disable_device(dev); 1682 } 1683 1684 static int sm501_plat_remove(struct platform_device *dev) 1685 { 1686 struct sm501_devdata *sm = platform_get_drvdata(dev); 1687 1688 sm501_dev_remove(sm); 1689 iounmap(sm->regs); 1690 1691 release_resource(sm->regs_claim); 1692 kfree(sm->regs_claim); 1693 1694 return 0; 1695 } 1696 1697 static struct pci_device_id sm501_pci_tbl[] = { 1698 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1699 { 0, }, 1700 }; 1701 1702 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); 1703 1704 static struct pci_driver sm501_pci_drv = { 1705 .name = "sm501", 1706 .id_table = sm501_pci_tbl, 1707 .probe = sm501_pci_probe, 1708 .remove = sm501_pci_remove, 1709 }; 1710 1711 MODULE_ALIAS("platform:sm501"); 1712 1713 static struct platform_driver sm501_plat_drv = { 1714 .driver = { 1715 .name = "sm501", 1716 .owner = THIS_MODULE, 1717 }, 1718 .probe = sm501_plat_probe, 1719 .remove = sm501_plat_remove, 1720 .suspend = sm501_plat_suspend, 1721 .resume = sm501_plat_resume, 1722 }; 1723 1724 static int __init sm501_base_init(void) 1725 { 1726 platform_driver_register(&sm501_plat_drv); 1727 return pci_register_driver(&sm501_pci_drv); 1728 } 1729 1730 static void __exit sm501_base_exit(void) 1731 { 1732 platform_driver_unregister(&sm501_plat_drv); 1733 pci_unregister_driver(&sm501_pci_drv); 1734 } 1735 1736 module_init(sm501_base_init); 1737 module_exit(sm501_base_exit); 1738 1739 MODULE_DESCRIPTION("SM501 Core Driver"); 1740 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders"); 1741 MODULE_LICENSE("GPL v2"); 1742