1 /* linux/drivers/mfd/sm501.c 2 * 3 * Copyright (C) 2006 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * Vincent Sanders <vince@simtec.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * SM501 MFD driver 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/list.h> 19 #include <linux/device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pci.h> 22 23 #include <linux/sm501.h> 24 #include <linux/sm501-regs.h> 25 #include <linux/serial_8250.h> 26 27 #include <asm/io.h> 28 29 struct sm501_device { 30 struct list_head list; 31 struct platform_device pdev; 32 }; 33 34 struct sm501_devdata { 35 spinlock_t reg_lock; 36 struct mutex clock_lock; 37 struct list_head devices; 38 39 struct device *dev; 40 struct resource *io_res; 41 struct resource *mem_res; 42 struct resource *regs_claim; 43 struct sm501_platdata *platdata; 44 45 unsigned int in_suspend; 46 unsigned long pm_misc; 47 48 int unit_power[20]; 49 unsigned int pdev_id; 50 unsigned int irq; 51 void __iomem *regs; 52 unsigned int rev; 53 }; 54 55 #define MHZ (1000 * 1000) 56 57 #ifdef DEBUG 58 static const unsigned int div_tab[] = { 59 [0] = 1, 60 [1] = 2, 61 [2] = 4, 62 [3] = 8, 63 [4] = 16, 64 [5] = 32, 65 [6] = 64, 66 [7] = 128, 67 [8] = 3, 68 [9] = 6, 69 [10] = 12, 70 [11] = 24, 71 [12] = 48, 72 [13] = 96, 73 [14] = 192, 74 [15] = 384, 75 [16] = 5, 76 [17] = 10, 77 [18] = 20, 78 [19] = 40, 79 [20] = 80, 80 [21] = 160, 81 [22] = 320, 82 [23] = 604, 83 }; 84 85 static unsigned long decode_div(unsigned long pll2, unsigned long val, 86 unsigned int lshft, unsigned int selbit, 87 unsigned long mask) 88 { 89 if (val & selbit) 90 pll2 = 288 * MHZ; 91 92 return pll2 / div_tab[(val >> lshft) & mask]; 93 } 94 95 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x) 96 97 /* sm501_dump_clk 98 * 99 * Print out the current clock configuration for the device 100 */ 101 102 static void sm501_dump_clk(struct sm501_devdata *sm) 103 { 104 unsigned long misct = readl(sm->regs + SM501_MISC_TIMING); 105 unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK); 106 unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK); 107 unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL); 108 unsigned long sdclk0, sdclk1; 109 unsigned long pll2 = 0; 110 111 switch (misct & 0x30) { 112 case 0x00: 113 pll2 = 336 * MHZ; 114 break; 115 case 0x10: 116 pll2 = 288 * MHZ; 117 break; 118 case 0x20: 119 pll2 = 240 * MHZ; 120 break; 121 case 0x30: 122 pll2 = 192 * MHZ; 123 break; 124 } 125 126 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; 127 sdclk0 /= div_tab[((misct >> 8) & 0xf)]; 128 129 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; 130 sdclk1 /= div_tab[((misct >> 16) & 0xf)]; 131 132 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", 133 misct, pm0, pm1); 134 135 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", 136 fmt_freq(pll2), sdclk0, sdclk1); 137 138 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); 139 140 dev_dbg(sm->dev, "PM0[%c]: " 141 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 142 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 143 (pmc & 3 ) == 0 ? '*' : '-', 144 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), 145 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), 146 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), 147 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); 148 149 dev_dbg(sm->dev, "PM1[%c]: " 150 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 151 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 152 (pmc & 3 ) == 1 ? '*' : '-', 153 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), 154 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), 155 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), 156 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); 157 } 158 159 static void sm501_dump_regs(struct sm501_devdata *sm) 160 { 161 void __iomem *regs = sm->regs; 162 163 dev_info(sm->dev, "System Control %08x\n", 164 readl(regs + SM501_SYSTEM_CONTROL)); 165 dev_info(sm->dev, "Misc Control %08x\n", 166 readl(regs + SM501_MISC_CONTROL)); 167 dev_info(sm->dev, "GPIO Control Low %08x\n", 168 readl(regs + SM501_GPIO31_0_CONTROL)); 169 dev_info(sm->dev, "GPIO Control Hi %08x\n", 170 readl(regs + SM501_GPIO63_32_CONTROL)); 171 dev_info(sm->dev, "DRAM Control %08x\n", 172 readl(regs + SM501_DRAM_CONTROL)); 173 dev_info(sm->dev, "Arbitration Ctrl %08x\n", 174 readl(regs + SM501_ARBTRTN_CONTROL)); 175 dev_info(sm->dev, "Misc Timing %08x\n", 176 readl(regs + SM501_MISC_TIMING)); 177 } 178 179 static void sm501_dump_gate(struct sm501_devdata *sm) 180 { 181 dev_info(sm->dev, "CurrentGate %08x\n", 182 readl(sm->regs + SM501_CURRENT_GATE)); 183 dev_info(sm->dev, "CurrentClock %08x\n", 184 readl(sm->regs + SM501_CURRENT_CLOCK)); 185 dev_info(sm->dev, "PowerModeControl %08x\n", 186 readl(sm->regs + SM501_POWER_MODE_CONTROL)); 187 } 188 189 #else 190 static inline void sm501_dump_gate(struct sm501_devdata *sm) { } 191 static inline void sm501_dump_regs(struct sm501_devdata *sm) { } 192 static inline void sm501_dump_clk(struct sm501_devdata *sm) { } 193 #endif 194 195 /* sm501_sync_regs 196 * 197 * ensure the 198 */ 199 200 static void sm501_sync_regs(struct sm501_devdata *sm) 201 { 202 readl(sm->regs); 203 } 204 205 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) 206 { 207 /* during suspend/resume, we are currently not allowed to sleep, 208 * so change to using mdelay() instead of msleep() if we 209 * are in one of these paths */ 210 211 if (sm->in_suspend) 212 mdelay(delay); 213 else 214 msleep(delay); 215 } 216 217 /* sm501_misc_control 218 * 219 * alters the miscellaneous control parameters 220 */ 221 222 int sm501_misc_control(struct device *dev, 223 unsigned long set, unsigned long clear) 224 { 225 struct sm501_devdata *sm = dev_get_drvdata(dev); 226 unsigned long misc; 227 unsigned long save; 228 unsigned long to; 229 230 spin_lock_irqsave(&sm->reg_lock, save); 231 232 misc = readl(sm->regs + SM501_MISC_CONTROL); 233 to = (misc & ~clear) | set; 234 235 if (to != misc) { 236 writel(to, sm->regs + SM501_MISC_CONTROL); 237 sm501_sync_regs(sm); 238 239 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); 240 } 241 242 spin_unlock_irqrestore(&sm->reg_lock, save); 243 return to; 244 } 245 246 EXPORT_SYMBOL_GPL(sm501_misc_control); 247 248 /* sm501_modify_reg 249 * 250 * Modify a register in the SM501 which may be shared with other 251 * drivers. 252 */ 253 254 unsigned long sm501_modify_reg(struct device *dev, 255 unsigned long reg, 256 unsigned long set, 257 unsigned long clear) 258 { 259 struct sm501_devdata *sm = dev_get_drvdata(dev); 260 unsigned long data; 261 unsigned long save; 262 263 spin_lock_irqsave(&sm->reg_lock, save); 264 265 data = readl(sm->regs + reg); 266 data |= set; 267 data &= ~clear; 268 269 writel(data, sm->regs + reg); 270 sm501_sync_regs(sm); 271 272 spin_unlock_irqrestore(&sm->reg_lock, save); 273 274 return data; 275 } 276 277 EXPORT_SYMBOL_GPL(sm501_modify_reg); 278 279 unsigned long sm501_gpio_get(struct device *dev, 280 unsigned long gpio) 281 { 282 struct sm501_devdata *sm = dev_get_drvdata(dev); 283 unsigned long result; 284 unsigned long reg; 285 286 reg = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW; 287 result = readl(sm->regs + reg); 288 289 result >>= (gpio & 31); 290 return result & 1UL; 291 } 292 293 EXPORT_SYMBOL_GPL(sm501_gpio_get); 294 295 void sm501_gpio_set(struct device *dev, 296 unsigned long gpio, 297 unsigned int to, 298 unsigned int dir) 299 { 300 struct sm501_devdata *sm = dev_get_drvdata(dev); 301 302 unsigned long bit = 1 << (gpio & 31); 303 unsigned long base; 304 unsigned long save; 305 unsigned long val; 306 307 base = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW; 308 base += SM501_GPIO; 309 310 spin_lock_irqsave(&sm->reg_lock, save); 311 312 val = readl(sm->regs + base) & ~bit; 313 if (to) 314 val |= bit; 315 writel(val, sm->regs + base); 316 317 val = readl(sm->regs + SM501_GPIO_DDR_LOW) & ~bit; 318 if (dir) 319 val |= bit; 320 321 writel(val, sm->regs + SM501_GPIO_DDR_LOW); 322 sm501_sync_regs(sm); 323 324 spin_unlock_irqrestore(&sm->reg_lock, save); 325 326 } 327 328 EXPORT_SYMBOL_GPL(sm501_gpio_set); 329 330 331 /* sm501_unit_power 332 * 333 * alters the power active gate to set specific units on or off 334 */ 335 336 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) 337 { 338 struct sm501_devdata *sm = dev_get_drvdata(dev); 339 unsigned long mode; 340 unsigned long gate; 341 unsigned long clock; 342 343 mutex_lock(&sm->clock_lock); 344 345 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 346 gate = readl(sm->regs + SM501_CURRENT_GATE); 347 clock = readl(sm->regs + SM501_CURRENT_CLOCK); 348 349 mode &= 3; /* get current power mode */ 350 351 if (unit >= ARRAY_SIZE(sm->unit_power)) { 352 dev_err(dev, "%s: bad unit %d\n", __func__, unit); 353 goto already; 354 } 355 356 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit, 357 sm->unit_power[unit], to); 358 359 if (to == 0 && sm->unit_power[unit] == 0) { 360 dev_err(sm->dev, "unit %d is already shutdown\n", unit); 361 goto already; 362 } 363 364 sm->unit_power[unit] += to ? 1 : -1; 365 to = sm->unit_power[unit] ? 1 : 0; 366 367 if (to) { 368 if (gate & (1 << unit)) 369 goto already; 370 gate |= (1 << unit); 371 } else { 372 if (!(gate & (1 << unit))) 373 goto already; 374 gate &= ~(1 << unit); 375 } 376 377 switch (mode) { 378 case 1: 379 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 380 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 381 mode = 0; 382 break; 383 case 2: 384 case 0: 385 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 386 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 387 mode = 1; 388 break; 389 390 default: 391 return -1; 392 } 393 394 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 395 sm501_sync_regs(sm); 396 397 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 398 gate, clock, mode); 399 400 sm501_mdelay(sm, 16); 401 402 already: 403 mutex_unlock(&sm->clock_lock); 404 return gate; 405 } 406 407 EXPORT_SYMBOL_GPL(sm501_unit_power); 408 409 410 /* Perform a rounded division. */ 411 static long sm501fb_round_div(long num, long denom) 412 { 413 /* n / d + 1 / 2 = (2n + d) / 2d */ 414 return (2 * num + denom) / (2 * denom); 415 } 416 417 /* clock value structure. */ 418 struct sm501_clock { 419 unsigned long mclk; 420 int divider; 421 int shift; 422 unsigned int m, n, k; 423 }; 424 425 /* sm501_calc_clock 426 * 427 * Calculates the nearest discrete clock frequency that 428 * can be achieved with the specified input clock. 429 * the maximum divisor is 3 or 5 430 */ 431 432 static int sm501_calc_clock(unsigned long freq, 433 struct sm501_clock *clock, 434 int max_div, 435 unsigned long mclk, 436 long *best_diff) 437 { 438 int ret = 0; 439 int divider; 440 int shift; 441 long diff; 442 443 /* try dividers 1 and 3 for CRT and for panel, 444 try divider 5 for panel only.*/ 445 446 for (divider = 1; divider <= max_div; divider += 2) { 447 /* try all 8 shift values.*/ 448 for (shift = 0; shift < 8; shift++) { 449 /* Calculate difference to requested clock */ 450 diff = sm501fb_round_div(mclk, divider << shift) - freq; 451 if (diff < 0) 452 diff = -diff; 453 454 /* If it is less than the current, use it */ 455 if (diff < *best_diff) { 456 *best_diff = diff; 457 458 clock->mclk = mclk; 459 clock->divider = divider; 460 clock->shift = shift; 461 ret = 1; 462 } 463 } 464 } 465 466 return ret; 467 } 468 469 /* sm501_calc_pll 470 * 471 * Calculates the nearest discrete clock frequency that can be 472 * achieved using the programmable PLL. 473 * the maximum divisor is 3 or 5 474 */ 475 476 static unsigned long sm501_calc_pll(unsigned long freq, 477 struct sm501_clock *clock, 478 int max_div) 479 { 480 unsigned long mclk; 481 unsigned int m, n, k; 482 long best_diff = 999999999; 483 484 /* 485 * The SM502 datasheet doesn't specify the min/max values for M and N. 486 * N = 1 at least doesn't work in practice. 487 */ 488 for (m = 2; m <= 255; m++) { 489 for (n = 2; n <= 127; n++) { 490 for (k = 0; k <= 1; k++) { 491 mclk = (24000000UL * m / n) >> k; 492 493 if (sm501_calc_clock(freq, clock, max_div, 494 mclk, &best_diff)) { 495 clock->m = m; 496 clock->n = n; 497 clock->k = k; 498 } 499 } 500 } 501 } 502 503 /* Return best clock. */ 504 return clock->mclk / (clock->divider << clock->shift); 505 } 506 507 /* sm501_select_clock 508 * 509 * Calculates the nearest discrete clock frequency that can be 510 * achieved using the 288MHz and 336MHz PLLs. 511 * the maximum divisor is 3 or 5 512 */ 513 514 static unsigned long sm501_select_clock(unsigned long freq, 515 struct sm501_clock *clock, 516 int max_div) 517 { 518 unsigned long mclk; 519 long best_diff = 999999999; 520 521 /* Try 288MHz and 336MHz clocks. */ 522 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { 523 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); 524 } 525 526 /* Return best clock. */ 527 return clock->mclk / (clock->divider << clock->shift); 528 } 529 530 /* sm501_set_clock 531 * 532 * set one of the four clock sources to the closest available frequency to 533 * the one specified 534 */ 535 536 unsigned long sm501_set_clock(struct device *dev, 537 int clksrc, 538 unsigned long req_freq) 539 { 540 struct sm501_devdata *sm = dev_get_drvdata(dev); 541 unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 542 unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE); 543 unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK); 544 unsigned char reg; 545 unsigned int pll_reg = 0; 546 unsigned long sm501_freq; /* the actual frequency acheived */ 547 548 struct sm501_clock to; 549 550 /* find achivable discrete frequency and setup register value 551 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK 552 * has an extra bit for the divider */ 553 554 switch (clksrc) { 555 case SM501_CLOCK_P2XCLK: 556 /* This clock is divided in half so to achive the 557 * requested frequency the value must be multiplied by 558 * 2. This clock also has an additional pre divisor */ 559 560 if (sm->rev >= 0xC0) { 561 /* SM502 -> use the programmable PLL */ 562 sm501_freq = (sm501_calc_pll(2 * req_freq, 563 &to, 5) / 2); 564 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 565 if (to.divider == 3) 566 reg |= 0x08; /* /3 divider required */ 567 else if (to.divider == 5) 568 reg |= 0x10; /* /5 divider required */ 569 reg |= 0x40; /* select the programmable PLL */ 570 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; 571 } else { 572 sm501_freq = (sm501_select_clock(2 * req_freq, 573 &to, 5) / 2); 574 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 575 if (to.divider == 3) 576 reg |= 0x08; /* /3 divider required */ 577 else if (to.divider == 5) 578 reg |= 0x10; /* /5 divider required */ 579 if (to.mclk != 288000000) 580 reg |= 0x20; /* which mclk pll is source */ 581 } 582 break; 583 584 case SM501_CLOCK_V2XCLK: 585 /* This clock is divided in half so to achive the 586 * requested frequency the value must be multiplied by 2. */ 587 588 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 589 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 590 if (to.divider == 3) 591 reg |= 0x08; /* /3 divider required */ 592 if (to.mclk != 288000000) 593 reg |= 0x10; /* which mclk pll is source */ 594 break; 595 596 case SM501_CLOCK_MCLK: 597 case SM501_CLOCK_M1XCLK: 598 /* These clocks are the same and not further divided */ 599 600 sm501_freq = sm501_select_clock( req_freq, &to, 3); 601 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 602 if (to.divider == 3) 603 reg |= 0x08; /* /3 divider required */ 604 if (to.mclk != 288000000) 605 reg |= 0x10; /* which mclk pll is source */ 606 break; 607 608 default: 609 return 0; /* this is bad */ 610 } 611 612 mutex_lock(&sm->clock_lock); 613 614 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL); 615 gate = readl(sm->regs + SM501_CURRENT_GATE); 616 clock = readl(sm->regs + SM501_CURRENT_CLOCK); 617 618 clock = clock & ~(0xFF << clksrc); 619 clock |= reg<<clksrc; 620 621 mode &= 3; /* find current mode */ 622 623 switch (mode) { 624 case 1: 625 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 626 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 627 mode = 0; 628 break; 629 case 2: 630 case 0: 631 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 632 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 633 mode = 1; 634 break; 635 636 default: 637 mutex_unlock(&sm->clock_lock); 638 return -1; 639 } 640 641 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 642 643 if (pll_reg) 644 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); 645 646 sm501_sync_regs(sm); 647 648 dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 649 gate, clock, mode); 650 651 sm501_mdelay(sm, 16); 652 mutex_unlock(&sm->clock_lock); 653 654 sm501_dump_clk(sm); 655 656 return sm501_freq; 657 } 658 659 EXPORT_SYMBOL_GPL(sm501_set_clock); 660 661 /* sm501_find_clock 662 * 663 * finds the closest available frequency for a given clock 664 */ 665 666 unsigned long sm501_find_clock(struct device *dev, 667 int clksrc, 668 unsigned long req_freq) 669 { 670 struct sm501_devdata *sm = dev_get_drvdata(dev); 671 unsigned long sm501_freq; /* the frequency achiveable by the 501 */ 672 struct sm501_clock to; 673 674 switch (clksrc) { 675 case SM501_CLOCK_P2XCLK: 676 if (sm->rev >= 0xC0) { 677 /* SM502 -> use the programmable PLL */ 678 sm501_freq = (sm501_calc_pll(2 * req_freq, 679 &to, 5) / 2); 680 } else { 681 sm501_freq = (sm501_select_clock(2 * req_freq, 682 &to, 5) / 2); 683 } 684 break; 685 686 case SM501_CLOCK_V2XCLK: 687 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 688 break; 689 690 case SM501_CLOCK_MCLK: 691 case SM501_CLOCK_M1XCLK: 692 sm501_freq = sm501_select_clock(req_freq, &to, 3); 693 break; 694 695 default: 696 sm501_freq = 0; /* error */ 697 } 698 699 return sm501_freq; 700 } 701 702 EXPORT_SYMBOL_GPL(sm501_find_clock); 703 704 static struct sm501_device *to_sm_device(struct platform_device *pdev) 705 { 706 return container_of(pdev, struct sm501_device, pdev); 707 } 708 709 /* sm501_device_release 710 * 711 * A release function for the platform devices we create to allow us to 712 * free any items we allocated 713 */ 714 715 static void sm501_device_release(struct device *dev) 716 { 717 kfree(to_sm_device(to_platform_device(dev))); 718 } 719 720 /* sm501_create_subdev 721 * 722 * Create a skeleton platform device with resources for passing to a 723 * sub-driver 724 */ 725 726 static struct platform_device * 727 sm501_create_subdev(struct sm501_devdata *sm, char *name, 728 unsigned int res_count, unsigned int platform_data_size) 729 { 730 struct sm501_device *smdev; 731 732 smdev = kzalloc(sizeof(struct sm501_device) + 733 (sizeof(struct resource) * res_count) + 734 platform_data_size, GFP_KERNEL); 735 if (!smdev) 736 return NULL; 737 738 smdev->pdev.dev.release = sm501_device_release; 739 740 smdev->pdev.name = name; 741 smdev->pdev.id = sm->pdev_id; 742 smdev->pdev.dev.parent = sm->dev; 743 744 if (res_count) { 745 smdev->pdev.resource = (struct resource *)(smdev+1); 746 smdev->pdev.num_resources = res_count; 747 } 748 if (platform_data_size) 749 smdev->pdev.dev.platform_data = (void *)(smdev+1); 750 751 return &smdev->pdev; 752 } 753 754 /* sm501_register_device 755 * 756 * Register a platform device created with sm501_create_subdev() 757 */ 758 759 static int sm501_register_device(struct sm501_devdata *sm, 760 struct platform_device *pdev) 761 { 762 struct sm501_device *smdev = to_sm_device(pdev); 763 int ptr; 764 int ret; 765 766 for (ptr = 0; ptr < pdev->num_resources; ptr++) { 767 printk("%s[%d] flags %08lx: %08llx..%08llx\n", 768 pdev->name, ptr, 769 pdev->resource[ptr].flags, 770 (unsigned long long)pdev->resource[ptr].start, 771 (unsigned long long)pdev->resource[ptr].end); 772 } 773 774 ret = platform_device_register(pdev); 775 776 if (ret >= 0) { 777 dev_dbg(sm->dev, "registered %s\n", pdev->name); 778 list_add_tail(&smdev->list, &sm->devices); 779 } else 780 dev_err(sm->dev, "error registering %s (%d)\n", 781 pdev->name, ret); 782 783 return ret; 784 } 785 786 /* sm501_create_subio 787 * 788 * Fill in an IO resource for a sub device 789 */ 790 791 static void sm501_create_subio(struct sm501_devdata *sm, 792 struct resource *res, 793 resource_size_t offs, 794 resource_size_t size) 795 { 796 res->flags = IORESOURCE_MEM; 797 res->parent = sm->io_res; 798 res->start = sm->io_res->start + offs; 799 res->end = res->start + size - 1; 800 } 801 802 /* sm501_create_mem 803 * 804 * Fill in an MEM resource for a sub device 805 */ 806 807 static void sm501_create_mem(struct sm501_devdata *sm, 808 struct resource *res, 809 resource_size_t *offs, 810 resource_size_t size) 811 { 812 *offs -= size; /* adjust memory size */ 813 814 res->flags = IORESOURCE_MEM; 815 res->parent = sm->mem_res; 816 res->start = sm->mem_res->start + *offs; 817 res->end = res->start + size - 1; 818 } 819 820 /* sm501_create_irq 821 * 822 * Fill in an IRQ resource for a sub device 823 */ 824 825 static void sm501_create_irq(struct sm501_devdata *sm, 826 struct resource *res) 827 { 828 res->flags = IORESOURCE_IRQ; 829 res->parent = NULL; 830 res->start = res->end = sm->irq; 831 } 832 833 static int sm501_register_usbhost(struct sm501_devdata *sm, 834 resource_size_t *mem_avail) 835 { 836 struct platform_device *pdev; 837 838 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0); 839 if (!pdev) 840 return -ENOMEM; 841 842 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000); 843 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024); 844 sm501_create_irq(sm, &pdev->resource[2]); 845 846 return sm501_register_device(sm, pdev); 847 } 848 849 static void sm501_setup_uart_data(struct sm501_devdata *sm, 850 struct plat_serial8250_port *uart_data, 851 unsigned int offset) 852 { 853 uart_data->membase = sm->regs + offset; 854 uart_data->mapbase = sm->io_res->start + offset; 855 uart_data->iotype = UPIO_MEM; 856 uart_data->irq = sm->irq; 857 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 858 uart_data->regshift = 2; 859 uart_data->uartclk = (9600 * 16); 860 } 861 862 static int sm501_register_uart(struct sm501_devdata *sm, int devices) 863 { 864 struct platform_device *pdev; 865 struct plat_serial8250_port *uart_data; 866 867 pdev = sm501_create_subdev(sm, "serial8250", 0, 868 sizeof(struct plat_serial8250_port) * 3); 869 if (!pdev) 870 return -ENOMEM; 871 872 uart_data = pdev->dev.platform_data; 873 874 if (devices & SM501_USE_UART0) { 875 sm501_setup_uart_data(sm, uart_data++, 0x30000); 876 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1); 877 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0); 878 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0); 879 } 880 if (devices & SM501_USE_UART1) { 881 sm501_setup_uart_data(sm, uart_data++, 0x30020); 882 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1); 883 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0); 884 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0); 885 } 886 887 pdev->id = PLAT8250_DEV_SM501; 888 889 return sm501_register_device(sm, pdev); 890 } 891 892 static int sm501_register_display(struct sm501_devdata *sm, 893 resource_size_t *mem_avail) 894 { 895 struct platform_device *pdev; 896 897 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0); 898 if (!pdev) 899 return -ENOMEM; 900 901 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000); 902 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000); 903 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail); 904 sm501_create_irq(sm, &pdev->resource[3]); 905 906 return sm501_register_device(sm, pdev); 907 } 908 909 /* sm501_dbg_regs 910 * 911 * Debug attribute to attach to parent device to show core registers 912 */ 913 914 static ssize_t sm501_dbg_regs(struct device *dev, 915 struct device_attribute *attr, char *buff) 916 { 917 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 918 unsigned int reg; 919 char *ptr = buff; 920 int ret; 921 922 for (reg = 0x00; reg < 0x70; reg += 4) { 923 ret = sprintf(ptr, "%08x = %08x\n", 924 reg, readl(sm->regs + reg)); 925 ptr += ret; 926 } 927 928 return ptr - buff; 929 } 930 931 932 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL); 933 934 /* sm501_init_reg 935 * 936 * Helper function for the init code to setup a register 937 * 938 * clear the bits which are set in r->mask, and then set 939 * the bits set in r->set. 940 */ 941 942 static inline void sm501_init_reg(struct sm501_devdata *sm, 943 unsigned long reg, 944 struct sm501_reg_init *r) 945 { 946 unsigned long tmp; 947 948 tmp = readl(sm->regs + reg); 949 tmp &= ~r->mask; 950 tmp |= r->set; 951 writel(tmp, sm->regs + reg); 952 } 953 954 /* sm501_init_regs 955 * 956 * Setup core register values 957 */ 958 959 static void sm501_init_regs(struct sm501_devdata *sm, 960 struct sm501_initdata *init) 961 { 962 sm501_misc_control(sm->dev, 963 init->misc_control.set, 964 init->misc_control.mask); 965 966 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing); 967 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low); 968 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high); 969 970 if (init->m1xclk) { 971 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk); 972 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk); 973 } 974 975 if (init->mclk) { 976 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); 977 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); 978 } 979 980 } 981 982 /* Check the PLL sources for the M1CLK and M1XCLK 983 * 984 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then 985 * there is a risk (see errata AB-5) that the SM501 will cease proper 986 * function. If this happens, then it is likely the SM501 will 987 * hang the system. 988 */ 989 990 static int sm501_check_clocks(struct sm501_devdata *sm) 991 { 992 unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK); 993 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); 994 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); 995 996 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0)); 997 } 998 999 static unsigned int sm501_mem_local[] = { 1000 [0] = 4*1024*1024, 1001 [1] = 8*1024*1024, 1002 [2] = 16*1024*1024, 1003 [3] = 32*1024*1024, 1004 [4] = 64*1024*1024, 1005 [5] = 2*1024*1024, 1006 }; 1007 1008 /* sm501_init_dev 1009 * 1010 * Common init code for an SM501 1011 */ 1012 1013 static int sm501_init_dev(struct sm501_devdata *sm) 1014 { 1015 struct sm501_initdata *idata; 1016 resource_size_t mem_avail; 1017 unsigned long dramctrl; 1018 unsigned long devid; 1019 int ret; 1020 1021 mutex_init(&sm->clock_lock); 1022 spin_lock_init(&sm->reg_lock); 1023 1024 INIT_LIST_HEAD(&sm->devices); 1025 1026 devid = readl(sm->regs + SM501_DEVICEID); 1027 1028 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { 1029 dev_err(sm->dev, "incorrect device id %08lx\n", devid); 1030 return -EINVAL; 1031 } 1032 1033 /* disable irqs */ 1034 writel(0, sm->regs + SM501_IRQ_MASK); 1035 1036 dramctrl = readl(sm->regs + SM501_DRAM_CONTROL); 1037 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; 1038 1039 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", 1040 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq); 1041 1042 sm->rev = devid & SM501_DEVICEID_REVMASK; 1043 1044 sm501_dump_gate(sm); 1045 1046 ret = device_create_file(sm->dev, &dev_attr_dbg_regs); 1047 if (ret) 1048 dev_err(sm->dev, "failed to create debug regs file\n"); 1049 1050 sm501_dump_clk(sm); 1051 1052 /* check to see if we have some device initialisation */ 1053 1054 idata = sm->platdata ? sm->platdata->init : NULL; 1055 if (idata) { 1056 sm501_init_regs(sm, idata); 1057 1058 if (idata->devices & SM501_USE_USB_HOST) 1059 sm501_register_usbhost(sm, &mem_avail); 1060 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1)) 1061 sm501_register_uart(sm, idata->devices); 1062 } 1063 1064 ret = sm501_check_clocks(sm); 1065 if (ret) { 1066 dev_err(sm->dev, "M1X and M clocks sourced from different " 1067 "PLLs\n"); 1068 return -EINVAL; 1069 } 1070 1071 /* always create a framebuffer */ 1072 sm501_register_display(sm, &mem_avail); 1073 1074 return 0; 1075 } 1076 1077 static int sm501_plat_probe(struct platform_device *dev) 1078 { 1079 struct sm501_devdata *sm; 1080 int err; 1081 1082 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL); 1083 if (sm == NULL) { 1084 dev_err(&dev->dev, "no memory for device data\n"); 1085 err = -ENOMEM; 1086 goto err1; 1087 } 1088 1089 sm->dev = &dev->dev; 1090 sm->pdev_id = dev->id; 1091 sm->irq = platform_get_irq(dev, 0); 1092 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 1093 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1094 sm->platdata = dev->dev.platform_data; 1095 1096 if (sm->irq < 0) { 1097 dev_err(&dev->dev, "failed to get irq resource\n"); 1098 err = sm->irq; 1099 goto err_res; 1100 } 1101 1102 if (sm->io_res == NULL || sm->mem_res == NULL) { 1103 dev_err(&dev->dev, "failed to get IO resource\n"); 1104 err = -ENOENT; 1105 goto err_res; 1106 } 1107 1108 sm->regs_claim = request_mem_region(sm->io_res->start, 1109 0x100, "sm501"); 1110 1111 if (sm->regs_claim == NULL) { 1112 dev_err(&dev->dev, "cannot claim registers\n"); 1113 err= -EBUSY; 1114 goto err_res; 1115 } 1116 1117 platform_set_drvdata(dev, sm); 1118 1119 sm->regs = ioremap(sm->io_res->start, 1120 (sm->io_res->end - sm->io_res->start) - 1); 1121 1122 if (sm->regs == NULL) { 1123 dev_err(&dev->dev, "cannot remap registers\n"); 1124 err = -EIO; 1125 goto err_claim; 1126 } 1127 1128 return sm501_init_dev(sm); 1129 1130 err_claim: 1131 release_resource(sm->regs_claim); 1132 kfree(sm->regs_claim); 1133 err_res: 1134 kfree(sm); 1135 err1: 1136 return err; 1137 1138 } 1139 1140 #ifdef CONFIG_PM 1141 /* power management support */ 1142 1143 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) 1144 { 1145 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1146 1147 sm->in_suspend = 1; 1148 sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL); 1149 1150 sm501_dump_regs(sm); 1151 return 0; 1152 } 1153 1154 static int sm501_plat_resume(struct platform_device *pdev) 1155 { 1156 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1157 1158 sm501_dump_regs(sm); 1159 sm501_dump_gate(sm); 1160 sm501_dump_clk(sm); 1161 1162 /* check to see if we are in the same state as when suspended */ 1163 1164 if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { 1165 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); 1166 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); 1167 1168 /* our suspend causes the controller state to change, 1169 * either by something attempting setup, power loss, 1170 * or an external reset event on power change */ 1171 1172 if (sm->platdata && sm->platdata->init) { 1173 sm501_init_regs(sm, sm->platdata->init); 1174 } 1175 } 1176 1177 /* dump our state from resume */ 1178 1179 sm501_dump_regs(sm); 1180 sm501_dump_clk(sm); 1181 1182 sm->in_suspend = 0; 1183 1184 return 0; 1185 } 1186 #else 1187 #define sm501_plat_suspend NULL 1188 #define sm501_plat_resume NULL 1189 #endif 1190 1191 /* Initialisation data for PCI devices */ 1192 1193 static struct sm501_initdata sm501_pci_initdata = { 1194 .gpio_high = { 1195 .set = 0x3F000000, /* 24bit panel */ 1196 .mask = 0x0, 1197 }, 1198 .misc_timing = { 1199 .set = 0x010100, /* SDRAM timing */ 1200 .mask = 0x1F1F00, 1201 }, 1202 .misc_control = { 1203 .set = SM501_MISC_PNL_24BIT, 1204 .mask = 0, 1205 }, 1206 1207 .devices = SM501_USE_ALL, 1208 1209 /* Errata AB-3 says that 72MHz is the fastest available 1210 * for 33MHZ PCI with proper bus-mastering operation */ 1211 1212 .mclk = 72 * MHZ, 1213 .m1xclk = 144 * MHZ, 1214 }; 1215 1216 static struct sm501_platdata_fbsub sm501_pdata_fbsub = { 1217 .flags = (SM501FB_FLAG_USE_INIT_MODE | 1218 SM501FB_FLAG_USE_HWCURSOR | 1219 SM501FB_FLAG_USE_HWACCEL | 1220 SM501FB_FLAG_DISABLE_AT_EXIT), 1221 }; 1222 1223 static struct sm501_platdata_fb sm501_fb_pdata = { 1224 .fb_route = SM501_FB_OWN, 1225 .fb_crt = &sm501_pdata_fbsub, 1226 .fb_pnl = &sm501_pdata_fbsub, 1227 }; 1228 1229 static struct sm501_platdata sm501_pci_platdata = { 1230 .init = &sm501_pci_initdata, 1231 .fb = &sm501_fb_pdata, 1232 }; 1233 1234 static int sm501_pci_probe(struct pci_dev *dev, 1235 const struct pci_device_id *id) 1236 { 1237 struct sm501_devdata *sm; 1238 int err; 1239 1240 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL); 1241 if (sm == NULL) { 1242 dev_err(&dev->dev, "no memory for device data\n"); 1243 err = -ENOMEM; 1244 goto err1; 1245 } 1246 1247 /* set a default set of platform data */ 1248 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata; 1249 1250 /* set a hopefully unique id for our child platform devices */ 1251 sm->pdev_id = 32 + dev->devfn; 1252 1253 pci_set_drvdata(dev, sm); 1254 1255 err = pci_enable_device(dev); 1256 if (err) { 1257 dev_err(&dev->dev, "cannot enable device\n"); 1258 goto err2; 1259 } 1260 1261 sm->dev = &dev->dev; 1262 sm->irq = dev->irq; 1263 1264 #ifdef __BIG_ENDIAN 1265 /* if the system is big-endian, we most probably have a 1266 * translation in the IO layer making the PCI bus little endian 1267 * so make the framebuffer swapped pixels */ 1268 1269 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN; 1270 #endif 1271 1272 /* check our resources */ 1273 1274 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) { 1275 dev_err(&dev->dev, "region #0 is not memory?\n"); 1276 err = -EINVAL; 1277 goto err3; 1278 } 1279 1280 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) { 1281 dev_err(&dev->dev, "region #1 is not memory?\n"); 1282 err = -EINVAL; 1283 goto err3; 1284 } 1285 1286 /* make our resources ready for sharing */ 1287 1288 sm->io_res = &dev->resource[1]; 1289 sm->mem_res = &dev->resource[0]; 1290 1291 sm->regs_claim = request_mem_region(sm->io_res->start, 1292 0x100, "sm501"); 1293 if (sm->regs_claim == NULL) { 1294 dev_err(&dev->dev, "cannot claim registers\n"); 1295 err= -EBUSY; 1296 goto err3; 1297 } 1298 1299 sm->regs = ioremap(pci_resource_start(dev, 1), 1300 pci_resource_len(dev, 1)); 1301 1302 if (sm->regs == NULL) { 1303 dev_err(&dev->dev, "cannot remap registers\n"); 1304 err = -EIO; 1305 goto err4; 1306 } 1307 1308 sm501_init_dev(sm); 1309 return 0; 1310 1311 err4: 1312 release_resource(sm->regs_claim); 1313 kfree(sm->regs_claim); 1314 err3: 1315 pci_disable_device(dev); 1316 err2: 1317 pci_set_drvdata(dev, NULL); 1318 kfree(sm); 1319 err1: 1320 return err; 1321 } 1322 1323 static void sm501_remove_sub(struct sm501_devdata *sm, 1324 struct sm501_device *smdev) 1325 { 1326 list_del(&smdev->list); 1327 platform_device_unregister(&smdev->pdev); 1328 } 1329 1330 static void sm501_dev_remove(struct sm501_devdata *sm) 1331 { 1332 struct sm501_device *smdev, *tmp; 1333 1334 list_for_each_entry_safe(smdev, tmp, &sm->devices, list) 1335 sm501_remove_sub(sm, smdev); 1336 1337 device_remove_file(sm->dev, &dev_attr_dbg_regs); 1338 } 1339 1340 static void sm501_pci_remove(struct pci_dev *dev) 1341 { 1342 struct sm501_devdata *sm = pci_get_drvdata(dev); 1343 1344 sm501_dev_remove(sm); 1345 iounmap(sm->regs); 1346 1347 release_resource(sm->regs_claim); 1348 kfree(sm->regs_claim); 1349 1350 pci_set_drvdata(dev, NULL); 1351 pci_disable_device(dev); 1352 } 1353 1354 static int sm501_plat_remove(struct platform_device *dev) 1355 { 1356 struct sm501_devdata *sm = platform_get_drvdata(dev); 1357 1358 sm501_dev_remove(sm); 1359 iounmap(sm->regs); 1360 1361 release_resource(sm->regs_claim); 1362 kfree(sm->regs_claim); 1363 1364 return 0; 1365 } 1366 1367 static struct pci_device_id sm501_pci_tbl[] = { 1368 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1369 { 0, }, 1370 }; 1371 1372 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); 1373 1374 static struct pci_driver sm501_pci_drv = { 1375 .name = "sm501", 1376 .id_table = sm501_pci_tbl, 1377 .probe = sm501_pci_probe, 1378 .remove = sm501_pci_remove, 1379 }; 1380 1381 static struct platform_driver sm501_plat_drv = { 1382 .driver = { 1383 .name = "sm501", 1384 .owner = THIS_MODULE, 1385 }, 1386 .probe = sm501_plat_probe, 1387 .remove = sm501_plat_remove, 1388 .suspend = sm501_plat_suspend, 1389 .resume = sm501_plat_resume, 1390 }; 1391 1392 static int __init sm501_base_init(void) 1393 { 1394 platform_driver_register(&sm501_plat_drv); 1395 return pci_register_driver(&sm501_pci_drv); 1396 } 1397 1398 static void __exit sm501_base_exit(void) 1399 { 1400 platform_driver_unregister(&sm501_plat_drv); 1401 pci_unregister_driver(&sm501_pci_drv); 1402 } 1403 1404 module_init(sm501_base_init); 1405 module_exit(sm501_base_exit); 1406 1407 MODULE_DESCRIPTION("SM501 Core Driver"); 1408 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders"); 1409 MODULE_LICENSE("GPL v2"); 1410