xref: /openbmc/linux/drivers/mfd/sm501.c (revision 4800cd83)
1 /* linux/drivers/mfd/sm501.c
2  *
3  * Copyright (C) 2006 Simtec Electronics
4  *	Ben Dooks <ben@simtec.co.uk>
5  *	Vincent Sanders <vince@simtec.co.uk>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * SM501 MFD driver
12 */
13 
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/list.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pci.h>
22 #include <linux/i2c-gpio.h>
23 #include <linux/slab.h>
24 
25 #include <linux/sm501.h>
26 #include <linux/sm501-regs.h>
27 #include <linux/serial_8250.h>
28 
29 #include <linux/io.h>
30 
31 struct sm501_device {
32 	struct list_head		list;
33 	struct platform_device		pdev;
34 };
35 
36 struct sm501_gpio;
37 
38 #ifdef CONFIG_MFD_SM501_GPIO
39 #include <linux/gpio.h>
40 
41 struct sm501_gpio_chip {
42 	struct gpio_chip	gpio;
43 	struct sm501_gpio	*ourgpio;	/* to get back to parent. */
44 	void __iomem		*regbase;
45 	void __iomem		*control;	/* address of control reg. */
46 };
47 
48 struct sm501_gpio {
49 	struct sm501_gpio_chip	low;
50 	struct sm501_gpio_chip	high;
51 	spinlock_t		lock;
52 
53 	unsigned int		 registered : 1;
54 	void __iomem		*regs;
55 	struct resource		*regs_res;
56 };
57 #else
58 struct sm501_gpio {
59 	/* no gpio support, empty definition for sm501_devdata. */
60 };
61 #endif
62 
63 struct sm501_devdata {
64 	spinlock_t			 reg_lock;
65 	struct mutex			 clock_lock;
66 	struct list_head		 devices;
67 	struct sm501_gpio		 gpio;
68 
69 	struct device			*dev;
70 	struct resource			*io_res;
71 	struct resource			*mem_res;
72 	struct resource			*regs_claim;
73 	struct sm501_platdata		*platdata;
74 
75 
76 	unsigned int			 in_suspend;
77 	unsigned long			 pm_misc;
78 
79 	int				 unit_power[20];
80 	unsigned int			 pdev_id;
81 	unsigned int			 irq;
82 	void __iomem			*regs;
83 	unsigned int			 rev;
84 };
85 
86 
87 #define MHZ (1000 * 1000)
88 
89 #ifdef DEBUG
90 static const unsigned int div_tab[] = {
91 	[0]		= 1,
92 	[1]		= 2,
93 	[2]		= 4,
94 	[3]		= 8,
95 	[4]		= 16,
96 	[5]		= 32,
97 	[6]		= 64,
98 	[7]		= 128,
99 	[8]		= 3,
100 	[9]		= 6,
101 	[10]	        = 12,
102 	[11]		= 24,
103 	[12]		= 48,
104 	[13]		= 96,
105 	[14]		= 192,
106 	[15]		= 384,
107 	[16]		= 5,
108 	[17]		= 10,
109 	[18]		= 20,
110 	[19]		= 40,
111 	[20]		= 80,
112 	[21]		= 160,
113 	[22]		= 320,
114 	[23]		= 604,
115 };
116 
117 static unsigned long decode_div(unsigned long pll2, unsigned long val,
118 				unsigned int lshft, unsigned int selbit,
119 				unsigned long mask)
120 {
121 	if (val & selbit)
122 		pll2 = 288 * MHZ;
123 
124 	return pll2 / div_tab[(val >> lshft) & mask];
125 }
126 
127 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
128 
129 /* sm501_dump_clk
130  *
131  * Print out the current clock configuration for the device
132 */
133 
134 static void sm501_dump_clk(struct sm501_devdata *sm)
135 {
136 	unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
137 	unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
138 	unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
139 	unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
140 	unsigned long sdclk0, sdclk1;
141 	unsigned long pll2 = 0;
142 
143 	switch (misct & 0x30) {
144 	case 0x00:
145 		pll2 = 336 * MHZ;
146 		break;
147 	case 0x10:
148 		pll2 = 288 * MHZ;
149 		break;
150 	case 0x20:
151 		pll2 = 240 * MHZ;
152 		break;
153 	case 0x30:
154 		pll2 = 192 * MHZ;
155 		break;
156 	}
157 
158 	sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
159 	sdclk0 /= div_tab[((misct >> 8) & 0xf)];
160 
161 	sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
162 	sdclk1 /= div_tab[((misct >> 16) & 0xf)];
163 
164 	dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
165 		misct, pm0, pm1);
166 
167 	dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
168 		fmt_freq(pll2), sdclk0, sdclk1);
169 
170 	dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
171 
172 	dev_dbg(sm->dev, "PM0[%c]: "
173 		 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
174 		 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
175 		 (pmc & 3 ) == 0 ? '*' : '-',
176 		 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
177 		 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
178 		 fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
179 		 fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
180 
181 	dev_dbg(sm->dev, "PM1[%c]: "
182 		"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
183 		"M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
184 		(pmc & 3 ) == 1 ? '*' : '-',
185 		fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
186 		fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
187 		fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
188 		fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
189 }
190 
191 static void sm501_dump_regs(struct sm501_devdata *sm)
192 {
193 	void __iomem *regs = sm->regs;
194 
195 	dev_info(sm->dev, "System Control   %08x\n",
196 			readl(regs + SM501_SYSTEM_CONTROL));
197 	dev_info(sm->dev, "Misc Control     %08x\n",
198 			readl(regs + SM501_MISC_CONTROL));
199 	dev_info(sm->dev, "GPIO Control Low %08x\n",
200 			readl(regs + SM501_GPIO31_0_CONTROL));
201 	dev_info(sm->dev, "GPIO Control Hi  %08x\n",
202 			readl(regs + SM501_GPIO63_32_CONTROL));
203 	dev_info(sm->dev, "DRAM Control     %08x\n",
204 			readl(regs + SM501_DRAM_CONTROL));
205 	dev_info(sm->dev, "Arbitration Ctrl %08x\n",
206 			readl(regs + SM501_ARBTRTN_CONTROL));
207 	dev_info(sm->dev, "Misc Timing      %08x\n",
208 			readl(regs + SM501_MISC_TIMING));
209 }
210 
211 static void sm501_dump_gate(struct sm501_devdata *sm)
212 {
213 	dev_info(sm->dev, "CurrentGate      %08x\n",
214 			readl(sm->regs + SM501_CURRENT_GATE));
215 	dev_info(sm->dev, "CurrentClock     %08x\n",
216 			readl(sm->regs + SM501_CURRENT_CLOCK));
217 	dev_info(sm->dev, "PowerModeControl %08x\n",
218 			readl(sm->regs + SM501_POWER_MODE_CONTROL));
219 }
220 
221 #else
222 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
223 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
224 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
225 #endif
226 
227 /* sm501_sync_regs
228  *
229  * ensure the
230 */
231 
232 static void sm501_sync_regs(struct sm501_devdata *sm)
233 {
234 	readl(sm->regs);
235 }
236 
237 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
238 {
239 	/* during suspend/resume, we are currently not allowed to sleep,
240 	 * so change to using mdelay() instead of msleep() if we
241 	 * are in one of these paths */
242 
243 	if (sm->in_suspend)
244 		mdelay(delay);
245 	else
246 		msleep(delay);
247 }
248 
249 /* sm501_misc_control
250  *
251  * alters the miscellaneous control parameters
252 */
253 
254 int sm501_misc_control(struct device *dev,
255 		       unsigned long set, unsigned long clear)
256 {
257 	struct sm501_devdata *sm = dev_get_drvdata(dev);
258 	unsigned long misc;
259 	unsigned long save;
260 	unsigned long to;
261 
262 	spin_lock_irqsave(&sm->reg_lock, save);
263 
264 	misc = readl(sm->regs + SM501_MISC_CONTROL);
265 	to = (misc & ~clear) | set;
266 
267 	if (to != misc) {
268 		writel(to, sm->regs + SM501_MISC_CONTROL);
269 		sm501_sync_regs(sm);
270 
271 		dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
272 	}
273 
274 	spin_unlock_irqrestore(&sm->reg_lock, save);
275 	return to;
276 }
277 
278 EXPORT_SYMBOL_GPL(sm501_misc_control);
279 
280 /* sm501_modify_reg
281  *
282  * Modify a register in the SM501 which may be shared with other
283  * drivers.
284 */
285 
286 unsigned long sm501_modify_reg(struct device *dev,
287 			       unsigned long reg,
288 			       unsigned long set,
289 			       unsigned long clear)
290 {
291 	struct sm501_devdata *sm = dev_get_drvdata(dev);
292 	unsigned long data;
293 	unsigned long save;
294 
295 	spin_lock_irqsave(&sm->reg_lock, save);
296 
297 	data = readl(sm->regs + reg);
298 	data |= set;
299 	data &= ~clear;
300 
301 	writel(data, sm->regs + reg);
302 	sm501_sync_regs(sm);
303 
304 	spin_unlock_irqrestore(&sm->reg_lock, save);
305 
306 	return data;
307 }
308 
309 EXPORT_SYMBOL_GPL(sm501_modify_reg);
310 
311 /* sm501_unit_power
312  *
313  * alters the power active gate to set specific units on or off
314  */
315 
316 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
317 {
318 	struct sm501_devdata *sm = dev_get_drvdata(dev);
319 	unsigned long mode;
320 	unsigned long gate;
321 	unsigned long clock;
322 
323 	mutex_lock(&sm->clock_lock);
324 
325 	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
326 	gate = readl(sm->regs + SM501_CURRENT_GATE);
327 	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
328 
329 	mode &= 3;		/* get current power mode */
330 
331 	if (unit >= ARRAY_SIZE(sm->unit_power)) {
332 		dev_err(dev, "%s: bad unit %d\n", __func__, unit);
333 		goto already;
334 	}
335 
336 	dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
337 		sm->unit_power[unit], to);
338 
339 	if (to == 0 && sm->unit_power[unit] == 0) {
340 		dev_err(sm->dev, "unit %d is already shutdown\n", unit);
341 		goto already;
342 	}
343 
344 	sm->unit_power[unit] += to ? 1 : -1;
345 	to = sm->unit_power[unit] ? 1 : 0;
346 
347 	if (to) {
348 		if (gate & (1 << unit))
349 			goto already;
350 		gate |= (1 << unit);
351 	} else {
352 		if (!(gate & (1 << unit)))
353 			goto already;
354 		gate &= ~(1 << unit);
355 	}
356 
357 	switch (mode) {
358 	case 1:
359 		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
360 		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
361 		mode = 0;
362 		break;
363 	case 2:
364 	case 0:
365 		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
366 		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
367 		mode = 1;
368 		break;
369 
370 	default:
371 		gate = -1;
372 		goto already;
373 	}
374 
375 	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
376 	sm501_sync_regs(sm);
377 
378 	dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
379 		gate, clock, mode);
380 
381 	sm501_mdelay(sm, 16);
382 
383  already:
384 	mutex_unlock(&sm->clock_lock);
385 	return gate;
386 }
387 
388 EXPORT_SYMBOL_GPL(sm501_unit_power);
389 
390 
391 /* Perform a rounded division. */
392 static long sm501fb_round_div(long num, long denom)
393 {
394         /* n / d + 1 / 2 = (2n + d) / 2d */
395         return (2 * num + denom) / (2 * denom);
396 }
397 
398 /* clock value structure. */
399 struct sm501_clock {
400 	unsigned long mclk;
401 	int divider;
402 	int shift;
403 	unsigned int m, n, k;
404 };
405 
406 /* sm501_calc_clock
407  *
408  * Calculates the nearest discrete clock frequency that
409  * can be achieved with the specified input clock.
410  *   the maximum divisor is 3 or 5
411  */
412 
413 static int sm501_calc_clock(unsigned long freq,
414 			    struct sm501_clock *clock,
415 			    int max_div,
416 			    unsigned long mclk,
417 			    long *best_diff)
418 {
419 	int ret = 0;
420 	int divider;
421 	int shift;
422 	long diff;
423 
424 	/* try dividers 1 and 3 for CRT and for panel,
425 	   try divider 5 for panel only.*/
426 
427 	for (divider = 1; divider <= max_div; divider += 2) {
428 		/* try all 8 shift values.*/
429 		for (shift = 0; shift < 8; shift++) {
430 			/* Calculate difference to requested clock */
431 			diff = sm501fb_round_div(mclk, divider << shift) - freq;
432 			if (diff < 0)
433 				diff = -diff;
434 
435 			/* If it is less than the current, use it */
436 			if (diff < *best_diff) {
437 				*best_diff = diff;
438 
439 				clock->mclk = mclk;
440 				clock->divider = divider;
441 				clock->shift = shift;
442 				ret = 1;
443 			}
444 		}
445 	}
446 
447 	return ret;
448 }
449 
450 /* sm501_calc_pll
451  *
452  * Calculates the nearest discrete clock frequency that can be
453  * achieved using the programmable PLL.
454  *   the maximum divisor is 3 or 5
455  */
456 
457 static unsigned long sm501_calc_pll(unsigned long freq,
458 					struct sm501_clock *clock,
459 					int max_div)
460 {
461 	unsigned long mclk;
462 	unsigned int m, n, k;
463 	long best_diff = 999999999;
464 
465 	/*
466 	 * The SM502 datasheet doesn't specify the min/max values for M and N.
467 	 * N = 1 at least doesn't work in practice.
468 	 */
469 	for (m = 2; m <= 255; m++) {
470 		for (n = 2; n <= 127; n++) {
471 			for (k = 0; k <= 1; k++) {
472 				mclk = (24000000UL * m / n) >> k;
473 
474 				if (sm501_calc_clock(freq, clock, max_div,
475 						     mclk, &best_diff)) {
476 					clock->m = m;
477 					clock->n = n;
478 					clock->k = k;
479 				}
480 			}
481 		}
482 	}
483 
484 	/* Return best clock. */
485 	return clock->mclk / (clock->divider << clock->shift);
486 }
487 
488 /* sm501_select_clock
489  *
490  * Calculates the nearest discrete clock frequency that can be
491  * achieved using the 288MHz and 336MHz PLLs.
492  *   the maximum divisor is 3 or 5
493  */
494 
495 static unsigned long sm501_select_clock(unsigned long freq,
496 					struct sm501_clock *clock,
497 					int max_div)
498 {
499 	unsigned long mclk;
500 	long best_diff = 999999999;
501 
502 	/* Try 288MHz and 336MHz clocks. */
503 	for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
504 		sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
505 	}
506 
507 	/* Return best clock. */
508 	return clock->mclk / (clock->divider << clock->shift);
509 }
510 
511 /* sm501_set_clock
512  *
513  * set one of the four clock sources to the closest available frequency to
514  *  the one specified
515 */
516 
517 unsigned long sm501_set_clock(struct device *dev,
518 			      int clksrc,
519 			      unsigned long req_freq)
520 {
521 	struct sm501_devdata *sm = dev_get_drvdata(dev);
522 	unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
523 	unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
524 	unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
525 	unsigned char reg;
526 	unsigned int pll_reg = 0;
527 	unsigned long sm501_freq; /* the actual frequency achieved */
528 
529 	struct sm501_clock to;
530 
531 	/* find achivable discrete frequency and setup register value
532 	 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
533 	 * has an extra bit for the divider */
534 
535 	switch (clksrc) {
536 	case SM501_CLOCK_P2XCLK:
537 		/* This clock is divided in half so to achieve the
538 		 * requested frequency the value must be multiplied by
539 		 * 2. This clock also has an additional pre divisor */
540 
541 		if (sm->rev >= 0xC0) {
542 			/* SM502 -> use the programmable PLL */
543 			sm501_freq = (sm501_calc_pll(2 * req_freq,
544 						     &to, 5) / 2);
545 			reg = to.shift & 0x07;/* bottom 3 bits are shift */
546 			if (to.divider == 3)
547 				reg |= 0x08; /* /3 divider required */
548 			else if (to.divider == 5)
549 				reg |= 0x10; /* /5 divider required */
550 			reg |= 0x40; /* select the programmable PLL */
551 			pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
552 		} else {
553 			sm501_freq = (sm501_select_clock(2 * req_freq,
554 							 &to, 5) / 2);
555 			reg = to.shift & 0x07;/* bottom 3 bits are shift */
556 			if (to.divider == 3)
557 				reg |= 0x08; /* /3 divider required */
558 			else if (to.divider == 5)
559 				reg |= 0x10; /* /5 divider required */
560 			if (to.mclk != 288000000)
561 				reg |= 0x20; /* which mclk pll is source */
562 		}
563 		break;
564 
565 	case SM501_CLOCK_V2XCLK:
566 		/* This clock is divided in half so to achieve the
567 		 * requested frequency the value must be multiplied by 2. */
568 
569 		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
570 		reg=to.shift & 0x07;	/* bottom 3 bits are shift */
571 		if (to.divider == 3)
572 			reg |= 0x08;	/* /3 divider required */
573 		if (to.mclk != 288000000)
574 			reg |= 0x10;	/* which mclk pll is source */
575 		break;
576 
577 	case SM501_CLOCK_MCLK:
578 	case SM501_CLOCK_M1XCLK:
579 		/* These clocks are the same and not further divided */
580 
581 		sm501_freq = sm501_select_clock( req_freq, &to, 3);
582 		reg=to.shift & 0x07;	/* bottom 3 bits are shift */
583 		if (to.divider == 3)
584 			reg |= 0x08;	/* /3 divider required */
585 		if (to.mclk != 288000000)
586 			reg |= 0x10;	/* which mclk pll is source */
587 		break;
588 
589 	default:
590 		return 0; /* this is bad */
591 	}
592 
593 	mutex_lock(&sm->clock_lock);
594 
595 	mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
596 	gate = readl(sm->regs + SM501_CURRENT_GATE);
597 	clock = readl(sm->regs + SM501_CURRENT_CLOCK);
598 
599 	clock = clock & ~(0xFF << clksrc);
600 	clock |= reg<<clksrc;
601 
602 	mode &= 3;	/* find current mode */
603 
604 	switch (mode) {
605 	case 1:
606 		writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
607 		writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
608 		mode = 0;
609 		break;
610 	case 2:
611 	case 0:
612 		writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
613 		writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
614 		mode = 1;
615 		break;
616 
617 	default:
618 		mutex_unlock(&sm->clock_lock);
619 		return -1;
620 	}
621 
622 	writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
623 
624 	if (pll_reg)
625 		writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
626 
627 	sm501_sync_regs(sm);
628 
629 	dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
630 		gate, clock, mode);
631 
632 	sm501_mdelay(sm, 16);
633 	mutex_unlock(&sm->clock_lock);
634 
635 	sm501_dump_clk(sm);
636 
637 	return sm501_freq;
638 }
639 
640 EXPORT_SYMBOL_GPL(sm501_set_clock);
641 
642 /* sm501_find_clock
643  *
644  * finds the closest available frequency for a given clock
645 */
646 
647 unsigned long sm501_find_clock(struct device *dev,
648 			       int clksrc,
649 			       unsigned long req_freq)
650 {
651 	struct sm501_devdata *sm = dev_get_drvdata(dev);
652 	unsigned long sm501_freq; /* the frequency achieveable by the 501 */
653 	struct sm501_clock to;
654 
655 	switch (clksrc) {
656 	case SM501_CLOCK_P2XCLK:
657 		if (sm->rev >= 0xC0) {
658 			/* SM502 -> use the programmable PLL */
659 			sm501_freq = (sm501_calc_pll(2 * req_freq,
660 						     &to, 5) / 2);
661 		} else {
662 			sm501_freq = (sm501_select_clock(2 * req_freq,
663 							 &to, 5) / 2);
664 		}
665 		break;
666 
667 	case SM501_CLOCK_V2XCLK:
668 		sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
669 		break;
670 
671 	case SM501_CLOCK_MCLK:
672 	case SM501_CLOCK_M1XCLK:
673 		sm501_freq = sm501_select_clock(req_freq, &to, 3);
674 		break;
675 
676 	default:
677 		sm501_freq = 0;		/* error */
678 	}
679 
680 	return sm501_freq;
681 }
682 
683 EXPORT_SYMBOL_GPL(sm501_find_clock);
684 
685 static struct sm501_device *to_sm_device(struct platform_device *pdev)
686 {
687 	return container_of(pdev, struct sm501_device, pdev);
688 }
689 
690 /* sm501_device_release
691  *
692  * A release function for the platform devices we create to allow us to
693  * free any items we allocated
694 */
695 
696 static void sm501_device_release(struct device *dev)
697 {
698 	kfree(to_sm_device(to_platform_device(dev)));
699 }
700 
701 /* sm501_create_subdev
702  *
703  * Create a skeleton platform device with resources for passing to a
704  * sub-driver
705 */
706 
707 static struct platform_device *
708 sm501_create_subdev(struct sm501_devdata *sm, char *name,
709 		    unsigned int res_count, unsigned int platform_data_size)
710 {
711 	struct sm501_device *smdev;
712 
713 	smdev = kzalloc(sizeof(struct sm501_device) +
714 			(sizeof(struct resource) * res_count) +
715 			platform_data_size, GFP_KERNEL);
716 	if (!smdev)
717 		return NULL;
718 
719 	smdev->pdev.dev.release = sm501_device_release;
720 
721 	smdev->pdev.name = name;
722 	smdev->pdev.id = sm->pdev_id;
723 	smdev->pdev.dev.parent = sm->dev;
724 
725 	if (res_count) {
726 		smdev->pdev.resource = (struct resource *)(smdev+1);
727 		smdev->pdev.num_resources = res_count;
728 	}
729 	if (platform_data_size)
730 		smdev->pdev.dev.platform_data = (void *)(smdev+1);
731 
732 	return &smdev->pdev;
733 }
734 
735 /* sm501_register_device
736  *
737  * Register a platform device created with sm501_create_subdev()
738 */
739 
740 static int sm501_register_device(struct sm501_devdata *sm,
741 				 struct platform_device *pdev)
742 {
743 	struct sm501_device *smdev = to_sm_device(pdev);
744 	int ptr;
745 	int ret;
746 
747 	for (ptr = 0; ptr < pdev->num_resources; ptr++) {
748 		printk(KERN_DEBUG "%s[%d] %pR\n",
749 		       pdev->name, ptr, &pdev->resource[ptr]);
750 	}
751 
752 	ret = platform_device_register(pdev);
753 
754 	if (ret >= 0) {
755 		dev_dbg(sm->dev, "registered %s\n", pdev->name);
756 		list_add_tail(&smdev->list, &sm->devices);
757 	} else
758 		dev_err(sm->dev, "error registering %s (%d)\n",
759 			pdev->name, ret);
760 
761 	return ret;
762 }
763 
764 /* sm501_create_subio
765  *
766  * Fill in an IO resource for a sub device
767 */
768 
769 static void sm501_create_subio(struct sm501_devdata *sm,
770 			       struct resource *res,
771 			       resource_size_t offs,
772 			       resource_size_t size)
773 {
774 	res->flags = IORESOURCE_MEM;
775 	res->parent = sm->io_res;
776 	res->start = sm->io_res->start + offs;
777 	res->end = res->start + size - 1;
778 }
779 
780 /* sm501_create_mem
781  *
782  * Fill in an MEM resource for a sub device
783 */
784 
785 static void sm501_create_mem(struct sm501_devdata *sm,
786 			     struct resource *res,
787 			     resource_size_t *offs,
788 			     resource_size_t size)
789 {
790 	*offs -= size;		/* adjust memory size */
791 
792 	res->flags = IORESOURCE_MEM;
793 	res->parent = sm->mem_res;
794 	res->start = sm->mem_res->start + *offs;
795 	res->end = res->start + size - 1;
796 }
797 
798 /* sm501_create_irq
799  *
800  * Fill in an IRQ resource for a sub device
801 */
802 
803 static void sm501_create_irq(struct sm501_devdata *sm,
804 			     struct resource *res)
805 {
806 	res->flags = IORESOURCE_IRQ;
807 	res->parent = NULL;
808 	res->start = res->end = sm->irq;
809 }
810 
811 static int sm501_register_usbhost(struct sm501_devdata *sm,
812 				  resource_size_t *mem_avail)
813 {
814 	struct platform_device *pdev;
815 
816 	pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
817 	if (!pdev)
818 		return -ENOMEM;
819 
820 	sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
821 	sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
822 	sm501_create_irq(sm, &pdev->resource[2]);
823 
824 	return sm501_register_device(sm, pdev);
825 }
826 
827 static void sm501_setup_uart_data(struct sm501_devdata *sm,
828 				  struct plat_serial8250_port *uart_data,
829 				  unsigned int offset)
830 {
831 	uart_data->membase = sm->regs + offset;
832 	uart_data->mapbase = sm->io_res->start + offset;
833 	uart_data->iotype = UPIO_MEM;
834 	uart_data->irq = sm->irq;
835 	uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
836 	uart_data->regshift = 2;
837 	uart_data->uartclk = (9600 * 16);
838 }
839 
840 static int sm501_register_uart(struct sm501_devdata *sm, int devices)
841 {
842 	struct platform_device *pdev;
843 	struct plat_serial8250_port *uart_data;
844 
845 	pdev = sm501_create_subdev(sm, "serial8250", 0,
846 				   sizeof(struct plat_serial8250_port) * 3);
847 	if (!pdev)
848 		return -ENOMEM;
849 
850 	uart_data = pdev->dev.platform_data;
851 
852 	if (devices & SM501_USE_UART0) {
853 		sm501_setup_uart_data(sm, uart_data++, 0x30000);
854 		sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
855 		sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
856 		sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
857 	}
858 	if (devices & SM501_USE_UART1) {
859 		sm501_setup_uart_data(sm, uart_data++, 0x30020);
860 		sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
861 		sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
862 		sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
863 	}
864 
865 	pdev->id = PLAT8250_DEV_SM501;
866 
867 	return sm501_register_device(sm, pdev);
868 }
869 
870 static int sm501_register_display(struct sm501_devdata *sm,
871 				  resource_size_t *mem_avail)
872 {
873 	struct platform_device *pdev;
874 
875 	pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
876 	if (!pdev)
877 		return -ENOMEM;
878 
879 	sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
880 	sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
881 	sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
882 	sm501_create_irq(sm, &pdev->resource[3]);
883 
884 	return sm501_register_device(sm, pdev);
885 }
886 
887 #ifdef CONFIG_MFD_SM501_GPIO
888 
889 static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
890 {
891 	return container_of(gc, struct sm501_gpio_chip, gpio);
892 }
893 
894 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
895 {
896 	return container_of(gpio, struct sm501_devdata, gpio);
897 }
898 
899 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
900 
901 {
902 	struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
903 	unsigned long result;
904 
905 	result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
906 	result >>= offset;
907 
908 	return result & 1UL;
909 }
910 
911 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
912 				   unsigned long bit)
913 {
914 	unsigned long ctrl;
915 
916 	/* check and modify if this pin is not set as gpio. */
917 
918 	if (readl(smchip->control) & bit) {
919 		dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
920 			 "changing mode of gpio, bit %08lx\n", bit);
921 
922 		ctrl = readl(smchip->control);
923 		ctrl &= ~bit;
924 		writel(ctrl, smchip->control);
925 
926 		sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
927 	}
928 }
929 
930 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
931 
932 {
933 	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
934 	struct sm501_gpio *smgpio = smchip->ourgpio;
935 	unsigned long bit = 1 << offset;
936 	void __iomem *regs = smchip->regbase;
937 	unsigned long save;
938 	unsigned long val;
939 
940 	dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
941 		__func__, chip, offset);
942 
943 	spin_lock_irqsave(&smgpio->lock, save);
944 
945 	val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
946 	if (value)
947 		val |= bit;
948 	writel(val, regs);
949 
950 	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
951 	sm501_gpio_ensure_gpio(smchip, bit);
952 
953 	spin_unlock_irqrestore(&smgpio->lock, save);
954 }
955 
956 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
957 {
958 	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
959 	struct sm501_gpio *smgpio = smchip->ourgpio;
960 	void __iomem *regs = smchip->regbase;
961 	unsigned long bit = 1 << offset;
962 	unsigned long save;
963 	unsigned long ddr;
964 
965 	dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
966 		__func__, chip, offset);
967 
968 	spin_lock_irqsave(&smgpio->lock, save);
969 
970 	ddr = readl(regs + SM501_GPIO_DDR_LOW);
971 	writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
972 
973 	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
974 	sm501_gpio_ensure_gpio(smchip, bit);
975 
976 	spin_unlock_irqrestore(&smgpio->lock, save);
977 
978 	return 0;
979 }
980 
981 static int sm501_gpio_output(struct gpio_chip *chip,
982 			     unsigned offset, int value)
983 {
984 	struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
985 	struct sm501_gpio *smgpio = smchip->ourgpio;
986 	unsigned long bit = 1 << offset;
987 	void __iomem *regs = smchip->regbase;
988 	unsigned long save;
989 	unsigned long val;
990 	unsigned long ddr;
991 
992 	dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
993 		__func__, chip, offset, value);
994 
995 	spin_lock_irqsave(&smgpio->lock, save);
996 
997 	val = readl(regs + SM501_GPIO_DATA_LOW);
998 	if (value)
999 		val |= bit;
1000 	else
1001 		val &= ~bit;
1002 	writel(val, regs);
1003 
1004 	ddr = readl(regs + SM501_GPIO_DDR_LOW);
1005 	writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
1006 
1007 	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1008 	writel(val, regs + SM501_GPIO_DATA_LOW);
1009 
1010 	sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1011 	spin_unlock_irqrestore(&smgpio->lock, save);
1012 
1013 	return 0;
1014 }
1015 
1016 static struct gpio_chip gpio_chip_template = {
1017 	.ngpio			= 32,
1018 	.direction_input	= sm501_gpio_input,
1019 	.direction_output	= sm501_gpio_output,
1020 	.set			= sm501_gpio_set,
1021 	.get			= sm501_gpio_get,
1022 };
1023 
1024 static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm,
1025 					      struct sm501_gpio *gpio,
1026 					      struct sm501_gpio_chip *chip)
1027 {
1028 	struct sm501_platdata *pdata = sm->platdata;
1029 	struct gpio_chip *gchip = &chip->gpio;
1030 	int base = pdata->gpio_base;
1031 
1032 	chip->gpio = gpio_chip_template;
1033 
1034 	if (chip == &gpio->high) {
1035 		if (base > 0)
1036 			base += 32;
1037 		chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1038 		chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1039 		gchip->label  = "SM501-HIGH";
1040 	} else {
1041 		chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1042 		chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1043 		gchip->label  = "SM501-LOW";
1044 	}
1045 
1046 	gchip->base   = base;
1047 	chip->ourgpio = gpio;
1048 
1049 	return gpiochip_add(gchip);
1050 }
1051 
1052 static int __devinit sm501_register_gpio(struct sm501_devdata *sm)
1053 {
1054 	struct sm501_gpio *gpio = &sm->gpio;
1055 	resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1056 	int ret;
1057 	int tmp;
1058 
1059 	dev_dbg(sm->dev, "registering gpio block %08llx\n",
1060 		(unsigned long long)iobase);
1061 
1062 	spin_lock_init(&gpio->lock);
1063 
1064 	gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1065 	if (gpio->regs_res == NULL) {
1066 		dev_err(sm->dev, "gpio: failed to request region\n");
1067 		return -ENXIO;
1068 	}
1069 
1070 	gpio->regs = ioremap(iobase, 0x20);
1071 	if (gpio->regs == NULL) {
1072 		dev_err(sm->dev, "gpio: failed to remap registers\n");
1073 		ret = -ENXIO;
1074 		goto err_claimed;
1075 	}
1076 
1077 	/* Register both our chips. */
1078 
1079 	ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1080 	if (ret) {
1081 		dev_err(sm->dev, "failed to add low chip\n");
1082 		goto err_mapped;
1083 	}
1084 
1085 	ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1086 	if (ret) {
1087 		dev_err(sm->dev, "failed to add high chip\n");
1088 		goto err_low_chip;
1089 	}
1090 
1091 	gpio->registered = 1;
1092 
1093 	return 0;
1094 
1095  err_low_chip:
1096 	tmp = gpiochip_remove(&gpio->low.gpio);
1097 	if (tmp) {
1098 		dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1099 		return ret;
1100 	}
1101 
1102  err_mapped:
1103 	iounmap(gpio->regs);
1104 
1105  err_claimed:
1106 	release_resource(gpio->regs_res);
1107 	kfree(gpio->regs_res);
1108 
1109 	return ret;
1110 }
1111 
1112 static void sm501_gpio_remove(struct sm501_devdata *sm)
1113 {
1114 	struct sm501_gpio *gpio = &sm->gpio;
1115 	int ret;
1116 
1117 	if (!sm->gpio.registered)
1118 		return;
1119 
1120 	ret = gpiochip_remove(&gpio->low.gpio);
1121 	if (ret)
1122 		dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1123 
1124 	ret = gpiochip_remove(&gpio->high.gpio);
1125 	if (ret)
1126 		dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
1127 
1128 	iounmap(gpio->regs);
1129 	release_resource(gpio->regs_res);
1130 	kfree(gpio->regs_res);
1131 }
1132 
1133 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1134 {
1135 	struct sm501_gpio *gpio = &sm->gpio;
1136 	int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1137 
1138 	return (pin % 32) + base;
1139 }
1140 
1141 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1142 {
1143 	return sm->gpio.registered;
1144 }
1145 #else
1146 static inline int sm501_register_gpio(struct sm501_devdata *sm)
1147 {
1148 	return 0;
1149 }
1150 
1151 static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1152 {
1153 }
1154 
1155 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1156 {
1157 	return -1;
1158 }
1159 
1160 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1161 {
1162 	return 0;
1163 }
1164 #endif
1165 
1166 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1167 					    struct sm501_platdata_gpio_i2c *iic)
1168 {
1169 	struct i2c_gpio_platform_data *icd;
1170 	struct platform_device *pdev;
1171 
1172 	pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1173 				   sizeof(struct i2c_gpio_platform_data));
1174 	if (!pdev)
1175 		return -ENOMEM;
1176 
1177 	icd = pdev->dev.platform_data;
1178 
1179 	/* We keep the pin_sda and pin_scl fields relative in case the
1180 	 * same platform data is passed to >1 SM501.
1181 	 */
1182 
1183 	icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1184 	icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1185 	icd->timeout = iic->timeout;
1186 	icd->udelay = iic->udelay;
1187 
1188 	/* note, we can't use either of the pin numbers, as the i2c-gpio
1189 	 * driver uses the platform.id field to generate the bus number
1190 	 * to register with the i2c core; The i2c core doesn't have enough
1191 	 * entries to deal with anything we currently use.
1192 	*/
1193 
1194 	pdev->id = iic->bus_num;
1195 
1196 	dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1197 		 iic->bus_num,
1198 		 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1199 
1200 	return sm501_register_device(sm, pdev);
1201 }
1202 
1203 static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1204 				   struct sm501_platdata *pdata)
1205 {
1206 	struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1207 	int index;
1208 	int ret;
1209 
1210 	for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1211 		ret = sm501_register_gpio_i2c_instance(sm, iic);
1212 		if (ret < 0)
1213 			return ret;
1214 	}
1215 
1216 	return 0;
1217 }
1218 
1219 /* sm501_dbg_regs
1220  *
1221  * Debug attribute to attach to parent device to show core registers
1222 */
1223 
1224 static ssize_t sm501_dbg_regs(struct device *dev,
1225 			      struct device_attribute *attr, char *buff)
1226 {
1227 	struct sm501_devdata *sm = dev_get_drvdata(dev)	;
1228 	unsigned int reg;
1229 	char *ptr = buff;
1230 	int ret;
1231 
1232 	for (reg = 0x00; reg < 0x70; reg += 4) {
1233 		ret = sprintf(ptr, "%08x = %08x\n",
1234 			      reg, readl(sm->regs + reg));
1235 		ptr += ret;
1236 	}
1237 
1238 	return ptr - buff;
1239 }
1240 
1241 
1242 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
1243 
1244 /* sm501_init_reg
1245  *
1246  * Helper function for the init code to setup a register
1247  *
1248  * clear the bits which are set in r->mask, and then set
1249  * the bits set in r->set.
1250 */
1251 
1252 static inline void sm501_init_reg(struct sm501_devdata *sm,
1253 				  unsigned long reg,
1254 				  struct sm501_reg_init *r)
1255 {
1256 	unsigned long tmp;
1257 
1258 	tmp = readl(sm->regs + reg);
1259 	tmp &= ~r->mask;
1260 	tmp |= r->set;
1261 	writel(tmp, sm->regs + reg);
1262 }
1263 
1264 /* sm501_init_regs
1265  *
1266  * Setup core register values
1267 */
1268 
1269 static void sm501_init_regs(struct sm501_devdata *sm,
1270 			    struct sm501_initdata *init)
1271 {
1272 	sm501_misc_control(sm->dev,
1273 			   init->misc_control.set,
1274 			   init->misc_control.mask);
1275 
1276 	sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1277 	sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1278 	sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1279 
1280 	if (init->m1xclk) {
1281 		dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1282 		sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1283 	}
1284 
1285 	if (init->mclk) {
1286 		dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1287 		sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1288 	}
1289 
1290 }
1291 
1292 /* Check the PLL sources for the M1CLK and M1XCLK
1293  *
1294  * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1295  * there is a risk (see errata AB-5) that the SM501 will cease proper
1296  * function. If this happens, then it is likely the SM501 will
1297  * hang the system.
1298 */
1299 
1300 static int sm501_check_clocks(struct sm501_devdata *sm)
1301 {
1302 	unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
1303 	unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1304 	unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1305 
1306 	return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1307 }
1308 
1309 static unsigned int sm501_mem_local[] = {
1310 	[0]	= 4*1024*1024,
1311 	[1]	= 8*1024*1024,
1312 	[2]	= 16*1024*1024,
1313 	[3]	= 32*1024*1024,
1314 	[4]	= 64*1024*1024,
1315 	[5]	= 2*1024*1024,
1316 };
1317 
1318 /* sm501_init_dev
1319  *
1320  * Common init code for an SM501
1321 */
1322 
1323 static int __devinit sm501_init_dev(struct sm501_devdata *sm)
1324 {
1325 	struct sm501_initdata *idata;
1326 	struct sm501_platdata *pdata;
1327 	resource_size_t mem_avail;
1328 	unsigned long dramctrl;
1329 	unsigned long devid;
1330 	int ret;
1331 
1332 	mutex_init(&sm->clock_lock);
1333 	spin_lock_init(&sm->reg_lock);
1334 
1335 	INIT_LIST_HEAD(&sm->devices);
1336 
1337 	devid = readl(sm->regs + SM501_DEVICEID);
1338 
1339 	if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1340 		dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1341 		return -EINVAL;
1342 	}
1343 
1344 	/* disable irqs */
1345 	writel(0, sm->regs + SM501_IRQ_MASK);
1346 
1347 	dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
1348 	mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1349 
1350 	dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1351 		 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1352 
1353 	sm->rev = devid & SM501_DEVICEID_REVMASK;
1354 
1355 	sm501_dump_gate(sm);
1356 
1357 	ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1358 	if (ret)
1359 		dev_err(sm->dev, "failed to create debug regs file\n");
1360 
1361 	sm501_dump_clk(sm);
1362 
1363 	/* check to see if we have some device initialisation */
1364 
1365 	pdata = sm->platdata;
1366 	idata = pdata ? pdata->init : NULL;
1367 
1368 	if (idata) {
1369 		sm501_init_regs(sm, idata);
1370 
1371 		if (idata->devices & SM501_USE_USB_HOST)
1372 			sm501_register_usbhost(sm, &mem_avail);
1373 		if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1374 			sm501_register_uart(sm, idata->devices);
1375 		if (idata->devices & SM501_USE_GPIO)
1376 			sm501_register_gpio(sm);
1377 	}
1378 
1379 	if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
1380 		if (!sm501_gpio_isregistered(sm))
1381 			dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1382 		else
1383 			sm501_register_gpio_i2c(sm, pdata);
1384 	}
1385 
1386 	ret = sm501_check_clocks(sm);
1387 	if (ret) {
1388 		dev_err(sm->dev, "M1X and M clocks sourced from different "
1389 					"PLLs\n");
1390 		return -EINVAL;
1391 	}
1392 
1393 	/* always create a framebuffer */
1394 	sm501_register_display(sm, &mem_avail);
1395 
1396 	return 0;
1397 }
1398 
1399 static int __devinit sm501_plat_probe(struct platform_device *dev)
1400 {
1401 	struct sm501_devdata *sm;
1402 	int ret;
1403 
1404 	sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1405 	if (sm == NULL) {
1406 		dev_err(&dev->dev, "no memory for device data\n");
1407 		ret = -ENOMEM;
1408 		goto err1;
1409 	}
1410 
1411 	sm->dev = &dev->dev;
1412 	sm->pdev_id = dev->id;
1413 	sm->platdata = dev->dev.platform_data;
1414 
1415 	ret = platform_get_irq(dev, 0);
1416 	if (ret < 0) {
1417 		dev_err(&dev->dev, "failed to get irq resource\n");
1418 		goto err_res;
1419 	}
1420 	sm->irq = ret;
1421 
1422 	sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1423 	sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1424 	if (sm->io_res == NULL || sm->mem_res == NULL) {
1425 		dev_err(&dev->dev, "failed to get IO resource\n");
1426 		ret = -ENOENT;
1427 		goto err_res;
1428 	}
1429 
1430 	sm->regs_claim = request_mem_region(sm->io_res->start,
1431 					    0x100, "sm501");
1432 
1433 	if (sm->regs_claim == NULL) {
1434 		dev_err(&dev->dev, "cannot claim registers\n");
1435 		ret = -EBUSY;
1436 		goto err_res;
1437 	}
1438 
1439 	platform_set_drvdata(dev, sm);
1440 
1441 	sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1442 
1443 	if (sm->regs == NULL) {
1444 		dev_err(&dev->dev, "cannot remap registers\n");
1445 		ret = -EIO;
1446 		goto err_claim;
1447 	}
1448 
1449 	return sm501_init_dev(sm);
1450 
1451  err_claim:
1452 	release_resource(sm->regs_claim);
1453 	kfree(sm->regs_claim);
1454  err_res:
1455 	kfree(sm);
1456  err1:
1457 	return ret;
1458 
1459 }
1460 
1461 #ifdef CONFIG_PM
1462 
1463 /* power management support */
1464 
1465 static void sm501_set_power(struct sm501_devdata *sm, int on)
1466 {
1467 	struct sm501_platdata *pd = sm->platdata;
1468 
1469 	if (pd == NULL)
1470 		return;
1471 
1472 	if (pd->get_power) {
1473 		if (pd->get_power(sm->dev) == on) {
1474 			dev_dbg(sm->dev, "is already %d\n", on);
1475 			return;
1476 		}
1477 	}
1478 
1479 	if (pd->set_power) {
1480 		dev_dbg(sm->dev, "setting power to %d\n", on);
1481 
1482 		pd->set_power(sm->dev, on);
1483 		sm501_mdelay(sm, 10);
1484 	}
1485 }
1486 
1487 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1488 {
1489 	struct sm501_devdata *sm = platform_get_drvdata(pdev);
1490 
1491 	sm->in_suspend = 1;
1492 	sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
1493 
1494 	sm501_dump_regs(sm);
1495 
1496 	if (sm->platdata) {
1497 		if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1498 			sm501_set_power(sm, 0);
1499 	}
1500 
1501 	return 0;
1502 }
1503 
1504 static int sm501_plat_resume(struct platform_device *pdev)
1505 {
1506 	struct sm501_devdata *sm = platform_get_drvdata(pdev);
1507 
1508 	sm501_set_power(sm, 1);
1509 
1510 	sm501_dump_regs(sm);
1511 	sm501_dump_gate(sm);
1512 	sm501_dump_clk(sm);
1513 
1514 	/* check to see if we are in the same state as when suspended */
1515 
1516 	if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1517 		dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1518 		writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1519 
1520 		/* our suspend causes the controller state to change,
1521 		 * either by something attempting setup, power loss,
1522 		 * or an external reset event on power change */
1523 
1524 		if (sm->platdata && sm->platdata->init) {
1525 			sm501_init_regs(sm, sm->platdata->init);
1526 		}
1527 	}
1528 
1529 	/* dump our state from resume */
1530 
1531 	sm501_dump_regs(sm);
1532 	sm501_dump_clk(sm);
1533 
1534 	sm->in_suspend = 0;
1535 
1536 	return 0;
1537 }
1538 #else
1539 #define sm501_plat_suspend NULL
1540 #define sm501_plat_resume NULL
1541 #endif
1542 
1543 /* Initialisation data for PCI devices */
1544 
1545 static struct sm501_initdata sm501_pci_initdata = {
1546 	.gpio_high	= {
1547 		.set	= 0x3F000000,		/* 24bit panel */
1548 		.mask	= 0x0,
1549 	},
1550 	.misc_timing	= {
1551 		.set	= 0x010100,		/* SDRAM timing */
1552 		.mask	= 0x1F1F00,
1553 	},
1554 	.misc_control	= {
1555 		.set	= SM501_MISC_PNL_24BIT,
1556 		.mask	= 0,
1557 	},
1558 
1559 	.devices	= SM501_USE_ALL,
1560 
1561 	/* Errata AB-3 says that 72MHz is the fastest available
1562 	 * for 33MHZ PCI with proper bus-mastering operation */
1563 
1564 	.mclk		= 72 * MHZ,
1565 	.m1xclk		= 144 * MHZ,
1566 };
1567 
1568 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1569 	.flags		= (SM501FB_FLAG_USE_INIT_MODE |
1570 			   SM501FB_FLAG_USE_HWCURSOR |
1571 			   SM501FB_FLAG_USE_HWACCEL |
1572 			   SM501FB_FLAG_DISABLE_AT_EXIT),
1573 };
1574 
1575 static struct sm501_platdata_fb sm501_fb_pdata = {
1576 	.fb_route	= SM501_FB_OWN,
1577 	.fb_crt		= &sm501_pdata_fbsub,
1578 	.fb_pnl		= &sm501_pdata_fbsub,
1579 };
1580 
1581 static struct sm501_platdata sm501_pci_platdata = {
1582 	.init		= &sm501_pci_initdata,
1583 	.fb		= &sm501_fb_pdata,
1584 	.gpio_base	= -1,
1585 };
1586 
1587 static int __devinit sm501_pci_probe(struct pci_dev *dev,
1588 				     const struct pci_device_id *id)
1589 {
1590 	struct sm501_devdata *sm;
1591 	int err;
1592 
1593 	sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1594 	if (sm == NULL) {
1595 		dev_err(&dev->dev, "no memory for device data\n");
1596 		err = -ENOMEM;
1597 		goto err1;
1598 	}
1599 
1600 	/* set a default set of platform data */
1601 	dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1602 
1603 	/* set a hopefully unique id for our child platform devices */
1604 	sm->pdev_id = 32 + dev->devfn;
1605 
1606 	pci_set_drvdata(dev, sm);
1607 
1608 	err = pci_enable_device(dev);
1609 	if (err) {
1610 		dev_err(&dev->dev, "cannot enable device\n");
1611 		goto err2;
1612 	}
1613 
1614 	sm->dev = &dev->dev;
1615 	sm->irq = dev->irq;
1616 
1617 #ifdef __BIG_ENDIAN
1618 	/* if the system is big-endian, we most probably have a
1619 	 * translation in the IO layer making the PCI bus little endian
1620 	 * so make the framebuffer swapped pixels */
1621 
1622 	sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1623 #endif
1624 
1625 	/* check our resources */
1626 
1627 	if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1628 		dev_err(&dev->dev, "region #0 is not memory?\n");
1629 		err = -EINVAL;
1630 		goto err3;
1631 	}
1632 
1633 	if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1634 		dev_err(&dev->dev, "region #1 is not memory?\n");
1635 		err = -EINVAL;
1636 		goto err3;
1637 	}
1638 
1639 	/* make our resources ready for sharing */
1640 
1641 	sm->io_res = &dev->resource[1];
1642 	sm->mem_res = &dev->resource[0];
1643 
1644 	sm->regs_claim = request_mem_region(sm->io_res->start,
1645 					    0x100, "sm501");
1646 	if (sm->regs_claim == NULL) {
1647 		dev_err(&dev->dev, "cannot claim registers\n");
1648 		err= -EBUSY;
1649 		goto err3;
1650 	}
1651 
1652 	sm->regs = pci_ioremap_bar(dev, 1);
1653 
1654 	if (sm->regs == NULL) {
1655 		dev_err(&dev->dev, "cannot remap registers\n");
1656 		err = -EIO;
1657 		goto err4;
1658 	}
1659 
1660 	sm501_init_dev(sm);
1661 	return 0;
1662 
1663  err4:
1664 	release_resource(sm->regs_claim);
1665 	kfree(sm->regs_claim);
1666  err3:
1667 	pci_disable_device(dev);
1668  err2:
1669 	pci_set_drvdata(dev, NULL);
1670 	kfree(sm);
1671  err1:
1672 	return err;
1673 }
1674 
1675 static void sm501_remove_sub(struct sm501_devdata *sm,
1676 			     struct sm501_device *smdev)
1677 {
1678 	list_del(&smdev->list);
1679 	platform_device_unregister(&smdev->pdev);
1680 }
1681 
1682 static void sm501_dev_remove(struct sm501_devdata *sm)
1683 {
1684 	struct sm501_device *smdev, *tmp;
1685 
1686 	list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1687 		sm501_remove_sub(sm, smdev);
1688 
1689 	device_remove_file(sm->dev, &dev_attr_dbg_regs);
1690 
1691 	sm501_gpio_remove(sm);
1692 }
1693 
1694 static void __devexit sm501_pci_remove(struct pci_dev *dev)
1695 {
1696 	struct sm501_devdata *sm = pci_get_drvdata(dev);
1697 
1698 	sm501_dev_remove(sm);
1699 	iounmap(sm->regs);
1700 
1701 	release_resource(sm->regs_claim);
1702 	kfree(sm->regs_claim);
1703 
1704 	pci_set_drvdata(dev, NULL);
1705 	pci_disable_device(dev);
1706 }
1707 
1708 static int sm501_plat_remove(struct platform_device *dev)
1709 {
1710 	struct sm501_devdata *sm = platform_get_drvdata(dev);
1711 
1712 	sm501_dev_remove(sm);
1713 	iounmap(sm->regs);
1714 
1715 	release_resource(sm->regs_claim);
1716 	kfree(sm->regs_claim);
1717 
1718 	return 0;
1719 }
1720 
1721 static struct pci_device_id sm501_pci_tbl[] = {
1722 	{ 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1723 	{ 0, },
1724 };
1725 
1726 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1727 
1728 static struct pci_driver sm501_pci_driver = {
1729 	.name		= "sm501",
1730 	.id_table	= sm501_pci_tbl,
1731 	.probe		= sm501_pci_probe,
1732 	.remove		= __devexit_p(sm501_pci_remove),
1733 };
1734 
1735 MODULE_ALIAS("platform:sm501");
1736 
1737 static struct platform_driver sm501_plat_driver = {
1738 	.driver		= {
1739 		.name	= "sm501",
1740 		.owner	= THIS_MODULE,
1741 	},
1742 	.probe		= sm501_plat_probe,
1743 	.remove		= sm501_plat_remove,
1744 	.suspend	= sm501_plat_suspend,
1745 	.resume		= sm501_plat_resume,
1746 };
1747 
1748 static int __init sm501_base_init(void)
1749 {
1750 	platform_driver_register(&sm501_plat_driver);
1751 	return pci_register_driver(&sm501_pci_driver);
1752 }
1753 
1754 static void __exit sm501_base_exit(void)
1755 {
1756 	platform_driver_unregister(&sm501_plat_driver);
1757 	pci_unregister_driver(&sm501_pci_driver);
1758 }
1759 
1760 module_init(sm501_base_init);
1761 module_exit(sm501_base_exit);
1762 
1763 MODULE_DESCRIPTION("SM501 Core Driver");
1764 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1765 MODULE_LICENSE("GPL v2");
1766