1 /* linux/drivers/mfd/sm501.c 2 * 3 * Copyright (C) 2006 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * Vincent Sanders <vince@simtec.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * SM501 MFD driver 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/init.h> 18 #include <linux/list.h> 19 #include <linux/device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pci.h> 22 #include <linux/platform_data/i2c-gpio.h> 23 #include <linux/gpio/machine.h> 24 #include <linux/slab.h> 25 26 #include <linux/sm501.h> 27 #include <linux/sm501-regs.h> 28 #include <linux/serial_8250.h> 29 30 #include <linux/io.h> 31 32 struct sm501_device { 33 struct list_head list; 34 struct platform_device pdev; 35 }; 36 37 struct sm501_gpio; 38 39 #ifdef CONFIG_MFD_SM501_GPIO 40 #include <linux/gpio.h> 41 42 struct sm501_gpio_chip { 43 struct gpio_chip gpio; 44 struct sm501_gpio *ourgpio; /* to get back to parent. */ 45 void __iomem *regbase; 46 void __iomem *control; /* address of control reg. */ 47 }; 48 49 struct sm501_gpio { 50 struct sm501_gpio_chip low; 51 struct sm501_gpio_chip high; 52 spinlock_t lock; 53 54 unsigned int registered : 1; 55 void __iomem *regs; 56 struct resource *regs_res; 57 }; 58 #else 59 struct sm501_gpio { 60 /* no gpio support, empty definition for sm501_devdata. */ 61 }; 62 #endif 63 64 struct sm501_devdata { 65 spinlock_t reg_lock; 66 struct mutex clock_lock; 67 struct list_head devices; 68 struct sm501_gpio gpio; 69 70 struct device *dev; 71 struct resource *io_res; 72 struct resource *mem_res; 73 struct resource *regs_claim; 74 struct sm501_platdata *platdata; 75 76 77 unsigned int in_suspend; 78 unsigned long pm_misc; 79 80 int unit_power[20]; 81 unsigned int pdev_id; 82 unsigned int irq; 83 void __iomem *regs; 84 unsigned int rev; 85 }; 86 87 88 #define MHZ (1000 * 1000) 89 90 #ifdef DEBUG 91 static const unsigned int div_tab[] = { 92 [0] = 1, 93 [1] = 2, 94 [2] = 4, 95 [3] = 8, 96 [4] = 16, 97 [5] = 32, 98 [6] = 64, 99 [7] = 128, 100 [8] = 3, 101 [9] = 6, 102 [10] = 12, 103 [11] = 24, 104 [12] = 48, 105 [13] = 96, 106 [14] = 192, 107 [15] = 384, 108 [16] = 5, 109 [17] = 10, 110 [18] = 20, 111 [19] = 40, 112 [20] = 80, 113 [21] = 160, 114 [22] = 320, 115 [23] = 604, 116 }; 117 118 static unsigned long decode_div(unsigned long pll2, unsigned long val, 119 unsigned int lshft, unsigned int selbit, 120 unsigned long mask) 121 { 122 if (val & selbit) 123 pll2 = 288 * MHZ; 124 125 return pll2 / div_tab[(val >> lshft) & mask]; 126 } 127 128 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x) 129 130 /* sm501_dump_clk 131 * 132 * Print out the current clock configuration for the device 133 */ 134 135 static void sm501_dump_clk(struct sm501_devdata *sm) 136 { 137 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); 138 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); 139 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); 140 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 141 unsigned long sdclk0, sdclk1; 142 unsigned long pll2 = 0; 143 144 switch (misct & 0x30) { 145 case 0x00: 146 pll2 = 336 * MHZ; 147 break; 148 case 0x10: 149 pll2 = 288 * MHZ; 150 break; 151 case 0x20: 152 pll2 = 240 * MHZ; 153 break; 154 case 0x30: 155 pll2 = 192 * MHZ; 156 break; 157 } 158 159 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; 160 sdclk0 /= div_tab[((misct >> 8) & 0xf)]; 161 162 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; 163 sdclk1 /= div_tab[((misct >> 16) & 0xf)]; 164 165 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", 166 misct, pm0, pm1); 167 168 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", 169 fmt_freq(pll2), sdclk0, sdclk1); 170 171 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); 172 173 dev_dbg(sm->dev, "PM0[%c]: " 174 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 175 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 176 (pmc & 3 ) == 0 ? '*' : '-', 177 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), 178 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), 179 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), 180 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); 181 182 dev_dbg(sm->dev, "PM1[%c]: " 183 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 184 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 185 (pmc & 3 ) == 1 ? '*' : '-', 186 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), 187 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), 188 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), 189 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); 190 } 191 192 static void sm501_dump_regs(struct sm501_devdata *sm) 193 { 194 void __iomem *regs = sm->regs; 195 196 dev_info(sm->dev, "System Control %08x\n", 197 smc501_readl(regs + SM501_SYSTEM_CONTROL)); 198 dev_info(sm->dev, "Misc Control %08x\n", 199 smc501_readl(regs + SM501_MISC_CONTROL)); 200 dev_info(sm->dev, "GPIO Control Low %08x\n", 201 smc501_readl(regs + SM501_GPIO31_0_CONTROL)); 202 dev_info(sm->dev, "GPIO Control Hi %08x\n", 203 smc501_readl(regs + SM501_GPIO63_32_CONTROL)); 204 dev_info(sm->dev, "DRAM Control %08x\n", 205 smc501_readl(regs + SM501_DRAM_CONTROL)); 206 dev_info(sm->dev, "Arbitration Ctrl %08x\n", 207 smc501_readl(regs + SM501_ARBTRTN_CONTROL)); 208 dev_info(sm->dev, "Misc Timing %08x\n", 209 smc501_readl(regs + SM501_MISC_TIMING)); 210 } 211 212 static void sm501_dump_gate(struct sm501_devdata *sm) 213 { 214 dev_info(sm->dev, "CurrentGate %08x\n", 215 smc501_readl(sm->regs + SM501_CURRENT_GATE)); 216 dev_info(sm->dev, "CurrentClock %08x\n", 217 smc501_readl(sm->regs + SM501_CURRENT_CLOCK)); 218 dev_info(sm->dev, "PowerModeControl %08x\n", 219 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL)); 220 } 221 222 #else 223 static inline void sm501_dump_gate(struct sm501_devdata *sm) { } 224 static inline void sm501_dump_regs(struct sm501_devdata *sm) { } 225 static inline void sm501_dump_clk(struct sm501_devdata *sm) { } 226 #endif 227 228 /* sm501_sync_regs 229 * 230 * ensure the 231 */ 232 233 static void sm501_sync_regs(struct sm501_devdata *sm) 234 { 235 smc501_readl(sm->regs); 236 } 237 238 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) 239 { 240 /* during suspend/resume, we are currently not allowed to sleep, 241 * so change to using mdelay() instead of msleep() if we 242 * are in one of these paths */ 243 244 if (sm->in_suspend) 245 mdelay(delay); 246 else 247 msleep(delay); 248 } 249 250 /* sm501_misc_control 251 * 252 * alters the miscellaneous control parameters 253 */ 254 255 int sm501_misc_control(struct device *dev, 256 unsigned long set, unsigned long clear) 257 { 258 struct sm501_devdata *sm = dev_get_drvdata(dev); 259 unsigned long misc; 260 unsigned long save; 261 unsigned long to; 262 263 spin_lock_irqsave(&sm->reg_lock, save); 264 265 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 266 to = (misc & ~clear) | set; 267 268 if (to != misc) { 269 smc501_writel(to, sm->regs + SM501_MISC_CONTROL); 270 sm501_sync_regs(sm); 271 272 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); 273 } 274 275 spin_unlock_irqrestore(&sm->reg_lock, save); 276 return to; 277 } 278 279 EXPORT_SYMBOL_GPL(sm501_misc_control); 280 281 /* sm501_modify_reg 282 * 283 * Modify a register in the SM501 which may be shared with other 284 * drivers. 285 */ 286 287 unsigned long sm501_modify_reg(struct device *dev, 288 unsigned long reg, 289 unsigned long set, 290 unsigned long clear) 291 { 292 struct sm501_devdata *sm = dev_get_drvdata(dev); 293 unsigned long data; 294 unsigned long save; 295 296 spin_lock_irqsave(&sm->reg_lock, save); 297 298 data = smc501_readl(sm->regs + reg); 299 data |= set; 300 data &= ~clear; 301 302 smc501_writel(data, sm->regs + reg); 303 sm501_sync_regs(sm); 304 305 spin_unlock_irqrestore(&sm->reg_lock, save); 306 307 return data; 308 } 309 310 EXPORT_SYMBOL_GPL(sm501_modify_reg); 311 312 /* sm501_unit_power 313 * 314 * alters the power active gate to set specific units on or off 315 */ 316 317 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) 318 { 319 struct sm501_devdata *sm = dev_get_drvdata(dev); 320 unsigned long mode; 321 unsigned long gate; 322 unsigned long clock; 323 324 mutex_lock(&sm->clock_lock); 325 326 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 327 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 328 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 329 330 mode &= 3; /* get current power mode */ 331 332 if (unit >= ARRAY_SIZE(sm->unit_power)) { 333 dev_err(dev, "%s: bad unit %d\n", __func__, unit); 334 goto already; 335 } 336 337 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit, 338 sm->unit_power[unit], to); 339 340 if (to == 0 && sm->unit_power[unit] == 0) { 341 dev_err(sm->dev, "unit %d is already shutdown\n", unit); 342 goto already; 343 } 344 345 sm->unit_power[unit] += to ? 1 : -1; 346 to = sm->unit_power[unit] ? 1 : 0; 347 348 if (to) { 349 if (gate & (1 << unit)) 350 goto already; 351 gate |= (1 << unit); 352 } else { 353 if (!(gate & (1 << unit))) 354 goto already; 355 gate &= ~(1 << unit); 356 } 357 358 switch (mode) { 359 case 1: 360 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 361 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 362 mode = 0; 363 break; 364 case 2: 365 case 0: 366 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 367 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 368 mode = 1; 369 break; 370 371 default: 372 gate = -1; 373 goto already; 374 } 375 376 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 377 sm501_sync_regs(sm); 378 379 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 380 gate, clock, mode); 381 382 sm501_mdelay(sm, 16); 383 384 already: 385 mutex_unlock(&sm->clock_lock); 386 return gate; 387 } 388 389 EXPORT_SYMBOL_GPL(sm501_unit_power); 390 391 /* clock value structure. */ 392 struct sm501_clock { 393 unsigned long mclk; 394 int divider; 395 int shift; 396 unsigned int m, n, k; 397 }; 398 399 /* sm501_calc_clock 400 * 401 * Calculates the nearest discrete clock frequency that 402 * can be achieved with the specified input clock. 403 * the maximum divisor is 3 or 5 404 */ 405 406 static int sm501_calc_clock(unsigned long freq, 407 struct sm501_clock *clock, 408 int max_div, 409 unsigned long mclk, 410 long *best_diff) 411 { 412 int ret = 0; 413 int divider; 414 int shift; 415 long diff; 416 417 /* try dividers 1 and 3 for CRT and for panel, 418 try divider 5 for panel only.*/ 419 420 for (divider = 1; divider <= max_div; divider += 2) { 421 /* try all 8 shift values.*/ 422 for (shift = 0; shift < 8; shift++) { 423 /* Calculate difference to requested clock */ 424 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; 425 if (diff < 0) 426 diff = -diff; 427 428 /* If it is less than the current, use it */ 429 if (diff < *best_diff) { 430 *best_diff = diff; 431 432 clock->mclk = mclk; 433 clock->divider = divider; 434 clock->shift = shift; 435 ret = 1; 436 } 437 } 438 } 439 440 return ret; 441 } 442 443 /* sm501_calc_pll 444 * 445 * Calculates the nearest discrete clock frequency that can be 446 * achieved using the programmable PLL. 447 * the maximum divisor is 3 or 5 448 */ 449 450 static unsigned long sm501_calc_pll(unsigned long freq, 451 struct sm501_clock *clock, 452 int max_div) 453 { 454 unsigned long mclk; 455 unsigned int m, n, k; 456 long best_diff = 999999999; 457 458 /* 459 * The SM502 datasheet doesn't specify the min/max values for M and N. 460 * N = 1 at least doesn't work in practice. 461 */ 462 for (m = 2; m <= 255; m++) { 463 for (n = 2; n <= 127; n++) { 464 for (k = 0; k <= 1; k++) { 465 mclk = (24000000UL * m / n) >> k; 466 467 if (sm501_calc_clock(freq, clock, max_div, 468 mclk, &best_diff)) { 469 clock->m = m; 470 clock->n = n; 471 clock->k = k; 472 } 473 } 474 } 475 } 476 477 /* Return best clock. */ 478 return clock->mclk / (clock->divider << clock->shift); 479 } 480 481 /* sm501_select_clock 482 * 483 * Calculates the nearest discrete clock frequency that can be 484 * achieved using the 288MHz and 336MHz PLLs. 485 * the maximum divisor is 3 or 5 486 */ 487 488 static unsigned long sm501_select_clock(unsigned long freq, 489 struct sm501_clock *clock, 490 int max_div) 491 { 492 unsigned long mclk; 493 long best_diff = 999999999; 494 495 /* Try 288MHz and 336MHz clocks. */ 496 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { 497 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); 498 } 499 500 /* Return best clock. */ 501 return clock->mclk / (clock->divider << clock->shift); 502 } 503 504 /* sm501_set_clock 505 * 506 * set one of the four clock sources to the closest available frequency to 507 * the one specified 508 */ 509 510 unsigned long sm501_set_clock(struct device *dev, 511 int clksrc, 512 unsigned long req_freq) 513 { 514 struct sm501_devdata *sm = dev_get_drvdata(dev); 515 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 516 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 517 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 518 unsigned int pll_reg = 0; 519 unsigned long sm501_freq; /* the actual frequency achieved */ 520 u64 reg; 521 522 struct sm501_clock to; 523 524 /* find achivable discrete frequency and setup register value 525 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK 526 * has an extra bit for the divider */ 527 528 switch (clksrc) { 529 case SM501_CLOCK_P2XCLK: 530 /* This clock is divided in half so to achieve the 531 * requested frequency the value must be multiplied by 532 * 2. This clock also has an additional pre divisor */ 533 534 if (sm->rev >= 0xC0) { 535 /* SM502 -> use the programmable PLL */ 536 sm501_freq = (sm501_calc_pll(2 * req_freq, 537 &to, 5) / 2); 538 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 539 if (to.divider == 3) 540 reg |= 0x08; /* /3 divider required */ 541 else if (to.divider == 5) 542 reg |= 0x10; /* /5 divider required */ 543 reg |= 0x40; /* select the programmable PLL */ 544 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; 545 } else { 546 sm501_freq = (sm501_select_clock(2 * req_freq, 547 &to, 5) / 2); 548 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 549 if (to.divider == 3) 550 reg |= 0x08; /* /3 divider required */ 551 else if (to.divider == 5) 552 reg |= 0x10; /* /5 divider required */ 553 if (to.mclk != 288000000) 554 reg |= 0x20; /* which mclk pll is source */ 555 } 556 break; 557 558 case SM501_CLOCK_V2XCLK: 559 /* This clock is divided in half so to achieve the 560 * requested frequency the value must be multiplied by 2. */ 561 562 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 563 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 564 if (to.divider == 3) 565 reg |= 0x08; /* /3 divider required */ 566 if (to.mclk != 288000000) 567 reg |= 0x10; /* which mclk pll is source */ 568 break; 569 570 case SM501_CLOCK_MCLK: 571 case SM501_CLOCK_M1XCLK: 572 /* These clocks are the same and not further divided */ 573 574 sm501_freq = sm501_select_clock( req_freq, &to, 3); 575 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 576 if (to.divider == 3) 577 reg |= 0x08; /* /3 divider required */ 578 if (to.mclk != 288000000) 579 reg |= 0x10; /* which mclk pll is source */ 580 break; 581 582 default: 583 return 0; /* this is bad */ 584 } 585 586 mutex_lock(&sm->clock_lock); 587 588 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 589 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 590 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 591 592 clock = clock & ~(0xFF << clksrc); 593 clock |= reg<<clksrc; 594 595 mode &= 3; /* find current mode */ 596 597 switch (mode) { 598 case 1: 599 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 600 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 601 mode = 0; 602 break; 603 case 2: 604 case 0: 605 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 606 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 607 mode = 1; 608 break; 609 610 default: 611 mutex_unlock(&sm->clock_lock); 612 return -1; 613 } 614 615 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 616 617 if (pll_reg) 618 smc501_writel(pll_reg, 619 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); 620 621 sm501_sync_regs(sm); 622 623 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 624 gate, clock, mode); 625 626 sm501_mdelay(sm, 16); 627 mutex_unlock(&sm->clock_lock); 628 629 sm501_dump_clk(sm); 630 631 return sm501_freq; 632 } 633 634 EXPORT_SYMBOL_GPL(sm501_set_clock); 635 636 /* sm501_find_clock 637 * 638 * finds the closest available frequency for a given clock 639 */ 640 641 unsigned long sm501_find_clock(struct device *dev, 642 int clksrc, 643 unsigned long req_freq) 644 { 645 struct sm501_devdata *sm = dev_get_drvdata(dev); 646 unsigned long sm501_freq; /* the frequency achieveable by the 501 */ 647 struct sm501_clock to; 648 649 switch (clksrc) { 650 case SM501_CLOCK_P2XCLK: 651 if (sm->rev >= 0xC0) { 652 /* SM502 -> use the programmable PLL */ 653 sm501_freq = (sm501_calc_pll(2 * req_freq, 654 &to, 5) / 2); 655 } else { 656 sm501_freq = (sm501_select_clock(2 * req_freq, 657 &to, 5) / 2); 658 } 659 break; 660 661 case SM501_CLOCK_V2XCLK: 662 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 663 break; 664 665 case SM501_CLOCK_MCLK: 666 case SM501_CLOCK_M1XCLK: 667 sm501_freq = sm501_select_clock(req_freq, &to, 3); 668 break; 669 670 default: 671 sm501_freq = 0; /* error */ 672 } 673 674 return sm501_freq; 675 } 676 677 EXPORT_SYMBOL_GPL(sm501_find_clock); 678 679 static struct sm501_device *to_sm_device(struct platform_device *pdev) 680 { 681 return container_of(pdev, struct sm501_device, pdev); 682 } 683 684 /* sm501_device_release 685 * 686 * A release function for the platform devices we create to allow us to 687 * free any items we allocated 688 */ 689 690 static void sm501_device_release(struct device *dev) 691 { 692 kfree(to_sm_device(to_platform_device(dev))); 693 } 694 695 /* sm501_create_subdev 696 * 697 * Create a skeleton platform device with resources for passing to a 698 * sub-driver 699 */ 700 701 static struct platform_device * 702 sm501_create_subdev(struct sm501_devdata *sm, char *name, 703 unsigned int res_count, unsigned int platform_data_size) 704 { 705 struct sm501_device *smdev; 706 707 smdev = kzalloc(sizeof(struct sm501_device) + 708 (sizeof(struct resource) * res_count) + 709 platform_data_size, GFP_KERNEL); 710 if (!smdev) 711 return NULL; 712 713 smdev->pdev.dev.release = sm501_device_release; 714 715 smdev->pdev.name = name; 716 smdev->pdev.id = sm->pdev_id; 717 smdev->pdev.dev.parent = sm->dev; 718 smdev->pdev.dev.coherent_dma_mask = 0xffffffff; 719 720 if (res_count) { 721 smdev->pdev.resource = (struct resource *)(smdev+1); 722 smdev->pdev.num_resources = res_count; 723 } 724 if (platform_data_size) 725 smdev->pdev.dev.platform_data = (void *)(smdev+1); 726 727 return &smdev->pdev; 728 } 729 730 /* sm501_register_device 731 * 732 * Register a platform device created with sm501_create_subdev() 733 */ 734 735 static int sm501_register_device(struct sm501_devdata *sm, 736 struct platform_device *pdev) 737 { 738 struct sm501_device *smdev = to_sm_device(pdev); 739 int ptr; 740 int ret; 741 742 for (ptr = 0; ptr < pdev->num_resources; ptr++) { 743 printk(KERN_DEBUG "%s[%d] %pR\n", 744 pdev->name, ptr, &pdev->resource[ptr]); 745 } 746 747 ret = platform_device_register(pdev); 748 749 if (ret >= 0) { 750 dev_dbg(sm->dev, "registered %s\n", pdev->name); 751 list_add_tail(&smdev->list, &sm->devices); 752 } else 753 dev_err(sm->dev, "error registering %s (%d)\n", 754 pdev->name, ret); 755 756 return ret; 757 } 758 759 /* sm501_create_subio 760 * 761 * Fill in an IO resource for a sub device 762 */ 763 764 static void sm501_create_subio(struct sm501_devdata *sm, 765 struct resource *res, 766 resource_size_t offs, 767 resource_size_t size) 768 { 769 res->flags = IORESOURCE_MEM; 770 res->parent = sm->io_res; 771 res->start = sm->io_res->start + offs; 772 res->end = res->start + size - 1; 773 } 774 775 /* sm501_create_mem 776 * 777 * Fill in an MEM resource for a sub device 778 */ 779 780 static void sm501_create_mem(struct sm501_devdata *sm, 781 struct resource *res, 782 resource_size_t *offs, 783 resource_size_t size) 784 { 785 *offs -= size; /* adjust memory size */ 786 787 res->flags = IORESOURCE_MEM; 788 res->parent = sm->mem_res; 789 res->start = sm->mem_res->start + *offs; 790 res->end = res->start + size - 1; 791 } 792 793 /* sm501_create_irq 794 * 795 * Fill in an IRQ resource for a sub device 796 */ 797 798 static void sm501_create_irq(struct sm501_devdata *sm, 799 struct resource *res) 800 { 801 res->flags = IORESOURCE_IRQ; 802 res->parent = NULL; 803 res->start = res->end = sm->irq; 804 } 805 806 static int sm501_register_usbhost(struct sm501_devdata *sm, 807 resource_size_t *mem_avail) 808 { 809 struct platform_device *pdev; 810 811 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0); 812 if (!pdev) 813 return -ENOMEM; 814 815 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000); 816 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024); 817 sm501_create_irq(sm, &pdev->resource[2]); 818 819 return sm501_register_device(sm, pdev); 820 } 821 822 static void sm501_setup_uart_data(struct sm501_devdata *sm, 823 struct plat_serial8250_port *uart_data, 824 unsigned int offset) 825 { 826 uart_data->membase = sm->regs + offset; 827 uart_data->mapbase = sm->io_res->start + offset; 828 uart_data->iotype = UPIO_MEM; 829 uart_data->irq = sm->irq; 830 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 831 uart_data->regshift = 2; 832 uart_data->uartclk = (9600 * 16); 833 } 834 835 static int sm501_register_uart(struct sm501_devdata *sm, int devices) 836 { 837 struct platform_device *pdev; 838 struct plat_serial8250_port *uart_data; 839 840 pdev = sm501_create_subdev(sm, "serial8250", 0, 841 sizeof(struct plat_serial8250_port) * 3); 842 if (!pdev) 843 return -ENOMEM; 844 845 uart_data = dev_get_platdata(&pdev->dev); 846 847 if (devices & SM501_USE_UART0) { 848 sm501_setup_uart_data(sm, uart_data++, 0x30000); 849 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1); 850 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0); 851 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0); 852 } 853 if (devices & SM501_USE_UART1) { 854 sm501_setup_uart_data(sm, uart_data++, 0x30020); 855 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1); 856 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0); 857 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0); 858 } 859 860 pdev->id = PLAT8250_DEV_SM501; 861 862 return sm501_register_device(sm, pdev); 863 } 864 865 static int sm501_register_display(struct sm501_devdata *sm, 866 resource_size_t *mem_avail) 867 { 868 struct platform_device *pdev; 869 870 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0); 871 if (!pdev) 872 return -ENOMEM; 873 874 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000); 875 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000); 876 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail); 877 sm501_create_irq(sm, &pdev->resource[3]); 878 879 return sm501_register_device(sm, pdev); 880 } 881 882 #ifdef CONFIG_MFD_SM501_GPIO 883 884 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio) 885 { 886 return container_of(gpio, struct sm501_devdata, gpio); 887 } 888 889 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) 890 891 { 892 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip); 893 unsigned long result; 894 895 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW); 896 result >>= offset; 897 898 return result & 1UL; 899 } 900 901 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, 902 unsigned long bit) 903 { 904 unsigned long ctrl; 905 906 /* check and modify if this pin is not set as gpio. */ 907 908 if (smc501_readl(smchip->control) & bit) { 909 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, 910 "changing mode of gpio, bit %08lx\n", bit); 911 912 ctrl = smc501_readl(smchip->control); 913 ctrl &= ~bit; 914 smc501_writel(ctrl, smchip->control); 915 916 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); 917 } 918 } 919 920 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 921 922 { 923 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 924 struct sm501_gpio *smgpio = smchip->ourgpio; 925 unsigned long bit = 1 << offset; 926 void __iomem *regs = smchip->regbase; 927 unsigned long save; 928 unsigned long val; 929 930 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 931 __func__, chip, offset); 932 933 spin_lock_irqsave(&smgpio->lock, save); 934 935 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit; 936 if (value) 937 val |= bit; 938 smc501_writel(val, regs); 939 940 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 941 sm501_gpio_ensure_gpio(smchip, bit); 942 943 spin_unlock_irqrestore(&smgpio->lock, save); 944 } 945 946 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) 947 { 948 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 949 struct sm501_gpio *smgpio = smchip->ourgpio; 950 void __iomem *regs = smchip->regbase; 951 unsigned long bit = 1 << offset; 952 unsigned long save; 953 unsigned long ddr; 954 955 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 956 __func__, chip, offset); 957 958 spin_lock_irqsave(&smgpio->lock, save); 959 960 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 961 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); 962 963 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 964 sm501_gpio_ensure_gpio(smchip, bit); 965 966 spin_unlock_irqrestore(&smgpio->lock, save); 967 968 return 0; 969 } 970 971 static int sm501_gpio_output(struct gpio_chip *chip, 972 unsigned offset, int value) 973 { 974 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 975 struct sm501_gpio *smgpio = smchip->ourgpio; 976 unsigned long bit = 1 << offset; 977 void __iomem *regs = smchip->regbase; 978 unsigned long save; 979 unsigned long val; 980 unsigned long ddr; 981 982 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n", 983 __func__, chip, offset, value); 984 985 spin_lock_irqsave(&smgpio->lock, save); 986 987 val = smc501_readl(regs + SM501_GPIO_DATA_LOW); 988 if (value) 989 val |= bit; 990 else 991 val &= ~bit; 992 smc501_writel(val, regs); 993 994 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 995 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); 996 997 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 998 smc501_writel(val, regs + SM501_GPIO_DATA_LOW); 999 1000 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 1001 spin_unlock_irqrestore(&smgpio->lock, save); 1002 1003 return 0; 1004 } 1005 1006 static const struct gpio_chip gpio_chip_template = { 1007 .ngpio = 32, 1008 .direction_input = sm501_gpio_input, 1009 .direction_output = sm501_gpio_output, 1010 .set = sm501_gpio_set, 1011 .get = sm501_gpio_get, 1012 }; 1013 1014 static int sm501_gpio_register_chip(struct sm501_devdata *sm, 1015 struct sm501_gpio *gpio, 1016 struct sm501_gpio_chip *chip) 1017 { 1018 struct sm501_platdata *pdata = sm->platdata; 1019 struct gpio_chip *gchip = &chip->gpio; 1020 int base = pdata->gpio_base; 1021 1022 chip->gpio = gpio_chip_template; 1023 1024 if (chip == &gpio->high) { 1025 if (base > 0) 1026 base += 32; 1027 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; 1028 chip->control = sm->regs + SM501_GPIO63_32_CONTROL; 1029 gchip->label = "SM501-HIGH"; 1030 } else { 1031 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; 1032 chip->control = sm->regs + SM501_GPIO31_0_CONTROL; 1033 gchip->label = "SM501-LOW"; 1034 } 1035 1036 gchip->base = base; 1037 chip->ourgpio = gpio; 1038 1039 return gpiochip_add_data(gchip, chip); 1040 } 1041 1042 static int sm501_register_gpio(struct sm501_devdata *sm) 1043 { 1044 struct sm501_gpio *gpio = &sm->gpio; 1045 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1046 int ret; 1047 1048 dev_dbg(sm->dev, "registering gpio block %08llx\n", 1049 (unsigned long long)iobase); 1050 1051 spin_lock_init(&gpio->lock); 1052 1053 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio"); 1054 if (!gpio->regs_res) { 1055 dev_err(sm->dev, "gpio: failed to request region\n"); 1056 return -ENXIO; 1057 } 1058 1059 gpio->regs = ioremap(iobase, 0x20); 1060 if (!gpio->regs) { 1061 dev_err(sm->dev, "gpio: failed to remap registers\n"); 1062 ret = -ENXIO; 1063 goto err_claimed; 1064 } 1065 1066 /* Register both our chips. */ 1067 1068 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low); 1069 if (ret) { 1070 dev_err(sm->dev, "failed to add low chip\n"); 1071 goto err_mapped; 1072 } 1073 1074 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high); 1075 if (ret) { 1076 dev_err(sm->dev, "failed to add high chip\n"); 1077 goto err_low_chip; 1078 } 1079 1080 gpio->registered = 1; 1081 1082 return 0; 1083 1084 err_low_chip: 1085 gpiochip_remove(&gpio->low.gpio); 1086 1087 err_mapped: 1088 iounmap(gpio->regs); 1089 1090 err_claimed: 1091 release_resource(gpio->regs_res); 1092 kfree(gpio->regs_res); 1093 1094 return ret; 1095 } 1096 1097 static void sm501_gpio_remove(struct sm501_devdata *sm) 1098 { 1099 struct sm501_gpio *gpio = &sm->gpio; 1100 1101 if (!sm->gpio.registered) 1102 return; 1103 1104 gpiochip_remove(&gpio->low.gpio); 1105 gpiochip_remove(&gpio->high.gpio); 1106 1107 iounmap(gpio->regs); 1108 release_resource(gpio->regs_res); 1109 kfree(gpio->regs_res); 1110 } 1111 1112 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1113 { 1114 return sm->gpio.registered; 1115 } 1116 #else 1117 static inline int sm501_register_gpio(struct sm501_devdata *sm) 1118 { 1119 return 0; 1120 } 1121 1122 static inline void sm501_gpio_remove(struct sm501_devdata *sm) 1123 { 1124 } 1125 1126 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1127 { 1128 return 0; 1129 } 1130 #endif 1131 1132 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm, 1133 struct sm501_platdata_gpio_i2c *iic) 1134 { 1135 struct i2c_gpio_platform_data *icd; 1136 struct platform_device *pdev; 1137 struct gpiod_lookup_table *lookup; 1138 1139 pdev = sm501_create_subdev(sm, "i2c-gpio", 0, 1140 sizeof(struct i2c_gpio_platform_data)); 1141 if (!pdev) 1142 return -ENOMEM; 1143 1144 /* Create a gpiod lookup using gpiochip-local offsets */ 1145 lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3), 1146 GFP_KERNEL); 1147 if (!lookup) 1148 return -ENOMEM; 1149 1150 lookup->dev_id = "i2c-gpio"; 1151 if (iic->pin_sda < 32) 1152 lookup->table[0].chip_label = "SM501-LOW"; 1153 else 1154 lookup->table[0].chip_label = "SM501-HIGH"; 1155 lookup->table[0].chip_hwnum = iic->pin_sda % 32; 1156 lookup->table[0].con_id = NULL; 1157 lookup->table[0].idx = 0; 1158 lookup->table[0].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN; 1159 if (iic->pin_scl < 32) 1160 lookup->table[1].chip_label = "SM501-LOW"; 1161 else 1162 lookup->table[1].chip_label = "SM501-HIGH"; 1163 lookup->table[1].chip_hwnum = iic->pin_scl % 32; 1164 lookup->table[1].con_id = NULL; 1165 lookup->table[1].idx = 1; 1166 lookup->table[1].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN; 1167 gpiod_add_lookup_table(lookup); 1168 1169 icd = dev_get_platdata(&pdev->dev); 1170 icd->timeout = iic->timeout; 1171 icd->udelay = iic->udelay; 1172 1173 /* note, we can't use either of the pin numbers, as the i2c-gpio 1174 * driver uses the platform.id field to generate the bus number 1175 * to register with the i2c core; The i2c core doesn't have enough 1176 * entries to deal with anything we currently use. 1177 */ 1178 1179 pdev->id = iic->bus_num; 1180 1181 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n", 1182 iic->bus_num, 1183 iic->pin_sda, iic->pin_scl); 1184 1185 return sm501_register_device(sm, pdev); 1186 } 1187 1188 static int sm501_register_gpio_i2c(struct sm501_devdata *sm, 1189 struct sm501_platdata *pdata) 1190 { 1191 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c; 1192 int index; 1193 int ret; 1194 1195 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) { 1196 ret = sm501_register_gpio_i2c_instance(sm, iic); 1197 if (ret < 0) 1198 return ret; 1199 } 1200 1201 return 0; 1202 } 1203 1204 /* sm501_dbg_regs 1205 * 1206 * Debug attribute to attach to parent device to show core registers 1207 */ 1208 1209 static ssize_t sm501_dbg_regs(struct device *dev, 1210 struct device_attribute *attr, char *buff) 1211 { 1212 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 1213 unsigned int reg; 1214 char *ptr = buff; 1215 int ret; 1216 1217 for (reg = 0x00; reg < 0x70; reg += 4) { 1218 ret = sprintf(ptr, "%08x = %08x\n", 1219 reg, smc501_readl(sm->regs + reg)); 1220 ptr += ret; 1221 } 1222 1223 return ptr - buff; 1224 } 1225 1226 1227 static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL); 1228 1229 /* sm501_init_reg 1230 * 1231 * Helper function for the init code to setup a register 1232 * 1233 * clear the bits which are set in r->mask, and then set 1234 * the bits set in r->set. 1235 */ 1236 1237 static inline void sm501_init_reg(struct sm501_devdata *sm, 1238 unsigned long reg, 1239 struct sm501_reg_init *r) 1240 { 1241 unsigned long tmp; 1242 1243 tmp = smc501_readl(sm->regs + reg); 1244 tmp &= ~r->mask; 1245 tmp |= r->set; 1246 smc501_writel(tmp, sm->regs + reg); 1247 } 1248 1249 /* sm501_init_regs 1250 * 1251 * Setup core register values 1252 */ 1253 1254 static void sm501_init_regs(struct sm501_devdata *sm, 1255 struct sm501_initdata *init) 1256 { 1257 sm501_misc_control(sm->dev, 1258 init->misc_control.set, 1259 init->misc_control.mask); 1260 1261 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing); 1262 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low); 1263 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high); 1264 1265 if (init->m1xclk) { 1266 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk); 1267 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk); 1268 } 1269 1270 if (init->mclk) { 1271 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); 1272 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); 1273 } 1274 1275 } 1276 1277 /* Check the PLL sources for the M1CLK and M1XCLK 1278 * 1279 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then 1280 * there is a risk (see errata AB-5) that the SM501 will cease proper 1281 * function. If this happens, then it is likely the SM501 will 1282 * hang the system. 1283 */ 1284 1285 static int sm501_check_clocks(struct sm501_devdata *sm) 1286 { 1287 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 1288 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); 1289 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); 1290 1291 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0)); 1292 } 1293 1294 static unsigned int sm501_mem_local[] = { 1295 [0] = 4*1024*1024, 1296 [1] = 8*1024*1024, 1297 [2] = 16*1024*1024, 1298 [3] = 32*1024*1024, 1299 [4] = 64*1024*1024, 1300 [5] = 2*1024*1024, 1301 }; 1302 1303 /* sm501_init_dev 1304 * 1305 * Common init code for an SM501 1306 */ 1307 1308 static int sm501_init_dev(struct sm501_devdata *sm) 1309 { 1310 struct sm501_initdata *idata; 1311 struct sm501_platdata *pdata; 1312 resource_size_t mem_avail; 1313 unsigned long dramctrl; 1314 unsigned long devid; 1315 int ret; 1316 1317 mutex_init(&sm->clock_lock); 1318 spin_lock_init(&sm->reg_lock); 1319 1320 INIT_LIST_HEAD(&sm->devices); 1321 1322 devid = smc501_readl(sm->regs + SM501_DEVICEID); 1323 1324 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { 1325 dev_err(sm->dev, "incorrect device id %08lx\n", devid); 1326 return -EINVAL; 1327 } 1328 1329 /* disable irqs */ 1330 smc501_writel(0, sm->regs + SM501_IRQ_MASK); 1331 1332 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL); 1333 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; 1334 1335 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", 1336 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq); 1337 1338 sm->rev = devid & SM501_DEVICEID_REVMASK; 1339 1340 sm501_dump_gate(sm); 1341 1342 ret = device_create_file(sm->dev, &dev_attr_dbg_regs); 1343 if (ret) 1344 dev_err(sm->dev, "failed to create debug regs file\n"); 1345 1346 sm501_dump_clk(sm); 1347 1348 /* check to see if we have some device initialisation */ 1349 1350 pdata = sm->platdata; 1351 idata = pdata ? pdata->init : NULL; 1352 1353 if (idata) { 1354 sm501_init_regs(sm, idata); 1355 1356 if (idata->devices & SM501_USE_USB_HOST) 1357 sm501_register_usbhost(sm, &mem_avail); 1358 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1)) 1359 sm501_register_uart(sm, idata->devices); 1360 if (idata->devices & SM501_USE_GPIO) 1361 sm501_register_gpio(sm); 1362 } 1363 1364 if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) { 1365 if (!sm501_gpio_isregistered(sm)) 1366 dev_err(sm->dev, "no gpio available for i2c gpio.\n"); 1367 else 1368 sm501_register_gpio_i2c(sm, pdata); 1369 } 1370 1371 ret = sm501_check_clocks(sm); 1372 if (ret) { 1373 dev_err(sm->dev, "M1X and M clocks sourced from different " 1374 "PLLs\n"); 1375 return -EINVAL; 1376 } 1377 1378 /* always create a framebuffer */ 1379 sm501_register_display(sm, &mem_avail); 1380 1381 return 0; 1382 } 1383 1384 static int sm501_plat_probe(struct platform_device *dev) 1385 { 1386 struct sm501_devdata *sm; 1387 int ret; 1388 1389 sm = kzalloc(sizeof(*sm), GFP_KERNEL); 1390 if (!sm) { 1391 ret = -ENOMEM; 1392 goto err1; 1393 } 1394 1395 sm->dev = &dev->dev; 1396 sm->pdev_id = dev->id; 1397 sm->platdata = dev_get_platdata(&dev->dev); 1398 1399 ret = platform_get_irq(dev, 0); 1400 if (ret < 0) { 1401 dev_err(&dev->dev, "failed to get irq resource\n"); 1402 goto err_res; 1403 } 1404 sm->irq = ret; 1405 1406 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 1407 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1408 if (!sm->io_res || !sm->mem_res) { 1409 dev_err(&dev->dev, "failed to get IO resource\n"); 1410 ret = -ENOENT; 1411 goto err_res; 1412 } 1413 1414 sm->regs_claim = request_mem_region(sm->io_res->start, 1415 0x100, "sm501"); 1416 if (!sm->regs_claim) { 1417 dev_err(&dev->dev, "cannot claim registers\n"); 1418 ret = -EBUSY; 1419 goto err_res; 1420 } 1421 1422 platform_set_drvdata(dev, sm); 1423 1424 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res)); 1425 if (!sm->regs) { 1426 dev_err(&dev->dev, "cannot remap registers\n"); 1427 ret = -EIO; 1428 goto err_claim; 1429 } 1430 1431 return sm501_init_dev(sm); 1432 1433 err_claim: 1434 release_resource(sm->regs_claim); 1435 kfree(sm->regs_claim); 1436 err_res: 1437 kfree(sm); 1438 err1: 1439 return ret; 1440 1441 } 1442 1443 #ifdef CONFIG_PM 1444 1445 /* power management support */ 1446 1447 static void sm501_set_power(struct sm501_devdata *sm, int on) 1448 { 1449 struct sm501_platdata *pd = sm->platdata; 1450 1451 if (!pd) 1452 return; 1453 1454 if (pd->get_power) { 1455 if (pd->get_power(sm->dev) == on) { 1456 dev_dbg(sm->dev, "is already %d\n", on); 1457 return; 1458 } 1459 } 1460 1461 if (pd->set_power) { 1462 dev_dbg(sm->dev, "setting power to %d\n", on); 1463 1464 pd->set_power(sm->dev, on); 1465 sm501_mdelay(sm, 10); 1466 } 1467 } 1468 1469 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) 1470 { 1471 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1472 1473 sm->in_suspend = 1; 1474 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 1475 1476 sm501_dump_regs(sm); 1477 1478 if (sm->platdata) { 1479 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF) 1480 sm501_set_power(sm, 0); 1481 } 1482 1483 return 0; 1484 } 1485 1486 static int sm501_plat_resume(struct platform_device *pdev) 1487 { 1488 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1489 1490 sm501_set_power(sm, 1); 1491 1492 sm501_dump_regs(sm); 1493 sm501_dump_gate(sm); 1494 sm501_dump_clk(sm); 1495 1496 /* check to see if we are in the same state as when suspended */ 1497 1498 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { 1499 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); 1500 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); 1501 1502 /* our suspend causes the controller state to change, 1503 * either by something attempting setup, power loss, 1504 * or an external reset event on power change */ 1505 1506 if (sm->platdata && sm->platdata->init) { 1507 sm501_init_regs(sm, sm->platdata->init); 1508 } 1509 } 1510 1511 /* dump our state from resume */ 1512 1513 sm501_dump_regs(sm); 1514 sm501_dump_clk(sm); 1515 1516 sm->in_suspend = 0; 1517 1518 return 0; 1519 } 1520 #else 1521 #define sm501_plat_suspend NULL 1522 #define sm501_plat_resume NULL 1523 #endif 1524 1525 /* Initialisation data for PCI devices */ 1526 1527 static struct sm501_initdata sm501_pci_initdata = { 1528 .gpio_high = { 1529 .set = 0x3F000000, /* 24bit panel */ 1530 .mask = 0x0, 1531 }, 1532 .misc_timing = { 1533 .set = 0x010100, /* SDRAM timing */ 1534 .mask = 0x1F1F00, 1535 }, 1536 .misc_control = { 1537 .set = SM501_MISC_PNL_24BIT, 1538 .mask = 0, 1539 }, 1540 1541 .devices = SM501_USE_ALL, 1542 1543 /* Errata AB-3 says that 72MHz is the fastest available 1544 * for 33MHZ PCI with proper bus-mastering operation */ 1545 1546 .mclk = 72 * MHZ, 1547 .m1xclk = 144 * MHZ, 1548 }; 1549 1550 static struct sm501_platdata_fbsub sm501_pdata_fbsub = { 1551 .flags = (SM501FB_FLAG_USE_INIT_MODE | 1552 SM501FB_FLAG_USE_HWCURSOR | 1553 SM501FB_FLAG_USE_HWACCEL | 1554 SM501FB_FLAG_DISABLE_AT_EXIT), 1555 }; 1556 1557 static struct sm501_platdata_fb sm501_fb_pdata = { 1558 .fb_route = SM501_FB_OWN, 1559 .fb_crt = &sm501_pdata_fbsub, 1560 .fb_pnl = &sm501_pdata_fbsub, 1561 }; 1562 1563 static struct sm501_platdata sm501_pci_platdata = { 1564 .init = &sm501_pci_initdata, 1565 .fb = &sm501_fb_pdata, 1566 .gpio_base = -1, 1567 }; 1568 1569 static int sm501_pci_probe(struct pci_dev *dev, 1570 const struct pci_device_id *id) 1571 { 1572 struct sm501_devdata *sm; 1573 int err; 1574 1575 sm = kzalloc(sizeof(*sm), GFP_KERNEL); 1576 if (!sm) { 1577 err = -ENOMEM; 1578 goto err1; 1579 } 1580 1581 /* set a default set of platform data */ 1582 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata; 1583 1584 /* set a hopefully unique id for our child platform devices */ 1585 sm->pdev_id = 32 + dev->devfn; 1586 1587 pci_set_drvdata(dev, sm); 1588 1589 err = pci_enable_device(dev); 1590 if (err) { 1591 dev_err(&dev->dev, "cannot enable device\n"); 1592 goto err2; 1593 } 1594 1595 sm->dev = &dev->dev; 1596 sm->irq = dev->irq; 1597 1598 #ifdef __BIG_ENDIAN 1599 /* if the system is big-endian, we most probably have a 1600 * translation in the IO layer making the PCI bus little endian 1601 * so make the framebuffer swapped pixels */ 1602 1603 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN; 1604 #endif 1605 1606 /* check our resources */ 1607 1608 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) { 1609 dev_err(&dev->dev, "region #0 is not memory?\n"); 1610 err = -EINVAL; 1611 goto err3; 1612 } 1613 1614 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) { 1615 dev_err(&dev->dev, "region #1 is not memory?\n"); 1616 err = -EINVAL; 1617 goto err3; 1618 } 1619 1620 /* make our resources ready for sharing */ 1621 1622 sm->io_res = &dev->resource[1]; 1623 sm->mem_res = &dev->resource[0]; 1624 1625 sm->regs_claim = request_mem_region(sm->io_res->start, 1626 0x100, "sm501"); 1627 if (!sm->regs_claim) { 1628 dev_err(&dev->dev, "cannot claim registers\n"); 1629 err= -EBUSY; 1630 goto err3; 1631 } 1632 1633 sm->regs = pci_ioremap_bar(dev, 1); 1634 if (!sm->regs) { 1635 dev_err(&dev->dev, "cannot remap registers\n"); 1636 err = -EIO; 1637 goto err4; 1638 } 1639 1640 sm501_init_dev(sm); 1641 return 0; 1642 1643 err4: 1644 release_resource(sm->regs_claim); 1645 kfree(sm->regs_claim); 1646 err3: 1647 pci_disable_device(dev); 1648 err2: 1649 kfree(sm); 1650 err1: 1651 return err; 1652 } 1653 1654 static void sm501_remove_sub(struct sm501_devdata *sm, 1655 struct sm501_device *smdev) 1656 { 1657 list_del(&smdev->list); 1658 platform_device_unregister(&smdev->pdev); 1659 } 1660 1661 static void sm501_dev_remove(struct sm501_devdata *sm) 1662 { 1663 struct sm501_device *smdev, *tmp; 1664 1665 list_for_each_entry_safe(smdev, tmp, &sm->devices, list) 1666 sm501_remove_sub(sm, smdev); 1667 1668 device_remove_file(sm->dev, &dev_attr_dbg_regs); 1669 1670 sm501_gpio_remove(sm); 1671 } 1672 1673 static void sm501_pci_remove(struct pci_dev *dev) 1674 { 1675 struct sm501_devdata *sm = pci_get_drvdata(dev); 1676 1677 sm501_dev_remove(sm); 1678 iounmap(sm->regs); 1679 1680 release_resource(sm->regs_claim); 1681 kfree(sm->regs_claim); 1682 1683 pci_disable_device(dev); 1684 } 1685 1686 static int sm501_plat_remove(struct platform_device *dev) 1687 { 1688 struct sm501_devdata *sm = platform_get_drvdata(dev); 1689 1690 sm501_dev_remove(sm); 1691 iounmap(sm->regs); 1692 1693 release_resource(sm->regs_claim); 1694 kfree(sm->regs_claim); 1695 1696 return 0; 1697 } 1698 1699 static const struct pci_device_id sm501_pci_tbl[] = { 1700 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1701 { 0, }, 1702 }; 1703 1704 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); 1705 1706 static struct pci_driver sm501_pci_driver = { 1707 .name = "sm501", 1708 .id_table = sm501_pci_tbl, 1709 .probe = sm501_pci_probe, 1710 .remove = sm501_pci_remove, 1711 }; 1712 1713 MODULE_ALIAS("platform:sm501"); 1714 1715 static const struct of_device_id of_sm501_match_tbl[] = { 1716 { .compatible = "smi,sm501", }, 1717 { /* end */ } 1718 }; 1719 MODULE_DEVICE_TABLE(of, of_sm501_match_tbl); 1720 1721 static struct platform_driver sm501_plat_driver = { 1722 .driver = { 1723 .name = "sm501", 1724 .of_match_table = of_sm501_match_tbl, 1725 }, 1726 .probe = sm501_plat_probe, 1727 .remove = sm501_plat_remove, 1728 .suspend = sm501_plat_suspend, 1729 .resume = sm501_plat_resume, 1730 }; 1731 1732 static int __init sm501_base_init(void) 1733 { 1734 platform_driver_register(&sm501_plat_driver); 1735 return pci_register_driver(&sm501_pci_driver); 1736 } 1737 1738 static void __exit sm501_base_exit(void) 1739 { 1740 platform_driver_unregister(&sm501_plat_driver); 1741 pci_unregister_driver(&sm501_pci_driver); 1742 } 1743 1744 module_init(sm501_base_init); 1745 module_exit(sm501_base_exit); 1746 1747 MODULE_DESCRIPTION("SM501 Core Driver"); 1748 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders"); 1749 MODULE_LICENSE("GPL v2"); 1750