1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * MFD internals for Renesas RZ/G2L MTU3 Core driver 4 * 5 * Copyright (C) 2023 Renesas Electronics Corporation 6 */ 7 8 #ifndef RZ_MTU3_MFD_H 9 #define RZ_MTU3_MFD_H 10 11 #define MTU_8BIT_CH_0(_tier, _nfcr, _tcr, _tcr2, _tmdr1, _tiorh, _tiorl, _tbtm) \ 12 { \ 13 [RZ_MTU3_TIER] = _tier, \ 14 [RZ_MTU3_NFCR] = _nfcr, \ 15 [RZ_MTU3_TCR] = _tcr, \ 16 [RZ_MTU3_TCR2] = _tcr2, \ 17 [RZ_MTU3_TMDR1] = _tmdr1, \ 18 [RZ_MTU3_TIORH] = _tiorh, \ 19 [RZ_MTU3_TIORL] = _tiorl, \ 20 [RZ_MTU3_TBTM] = _tbtm \ 21 } 22 23 #define MTU_8BIT_CH_1_2(_tier, _nfcr, _tsr, _tcr, _tcr2, _tmdr1, _tior) \ 24 { \ 25 [RZ_MTU3_TIER] = _tier, \ 26 [RZ_MTU3_NFCR] = _nfcr, \ 27 [RZ_MTU3_TSR] = _tsr, \ 28 [RZ_MTU3_TCR] = _tcr, \ 29 [RZ_MTU3_TCR2] = _tcr2, \ 30 [RZ_MTU3_TMDR1] = _tmdr1, \ 31 [RZ_MTU3_TIOR] = _tior \ 32 } \ 33 34 #define MTU_8BIT_CH_3_4_6_7(_tier, _nfcr, _tsr, _tcr, _tcr2, _tmdr1, _tiorh, _tiorl, _tbtm) \ 35 { \ 36 [RZ_MTU3_TIER] = _tier, \ 37 [RZ_MTU3_NFCR] = _nfcr, \ 38 [RZ_MTU3_TSR] = _tsr, \ 39 [RZ_MTU3_TCR] = _tcr, \ 40 [RZ_MTU3_TCR2] = _tcr2, \ 41 [RZ_MTU3_TMDR1] = _tmdr1, \ 42 [RZ_MTU3_TIORH] = _tiorh, \ 43 [RZ_MTU3_TIORL] = _tiorl, \ 44 [RZ_MTU3_TBTM] = _tbtm \ 45 } \ 46 47 #define MTU_8BIT_CH_5(_tier, _nfcr, _tstr, _tcntcmpclr, _tcru, _tcr2u, _tioru, \ 48 _tcrv, _tcr2v, _tiorv, _tcrw, _tcr2w, _tiorw) \ 49 { \ 50 [RZ_MTU3_TIER] = _tier, \ 51 [RZ_MTU3_NFCR] = _nfcr, \ 52 [RZ_MTU3_TSTR] = _tstr, \ 53 [RZ_MTU3_TCNTCMPCLR] = _tcntcmpclr, \ 54 [RZ_MTU3_TCRU] = _tcru, \ 55 [RZ_MTU3_TCR2U] = _tcr2u, \ 56 [RZ_MTU3_TIORU] = _tioru, \ 57 [RZ_MTU3_TCRV] = _tcrv, \ 58 [RZ_MTU3_TCR2V] = _tcr2v, \ 59 [RZ_MTU3_TIORV] = _tiorv, \ 60 [RZ_MTU3_TCRW] = _tcrw, \ 61 [RZ_MTU3_TCR2W] = _tcr2w, \ 62 [RZ_MTU3_TIORW] = _tiorw \ 63 } \ 64 65 #define MTU_8BIT_CH_8(_tier, _nfcr, _tcr, _tcr2, _tmdr1, _tiorh, _tiorl) \ 66 { \ 67 [RZ_MTU3_TIER] = _tier, \ 68 [RZ_MTU3_NFCR] = _nfcr, \ 69 [RZ_MTU3_TCR] = _tcr, \ 70 [RZ_MTU3_TCR2] = _tcr2, \ 71 [RZ_MTU3_TMDR1] = _tmdr1, \ 72 [RZ_MTU3_TIORH] = _tiorh, \ 73 [RZ_MTU3_TIORL] = _tiorl \ 74 } \ 75 76 #define MTU_16BIT_CH_0(_tcnt, _tgra, _tgrb, _tgrc, _tgrd, _tgre, _tgrf) \ 77 { \ 78 [RZ_MTU3_TCNT] = _tcnt, \ 79 [RZ_MTU3_TGRA] = _tgra, \ 80 [RZ_MTU3_TGRB] = _tgrb, \ 81 [RZ_MTU3_TGRC] = _tgrc, \ 82 [RZ_MTU3_TGRD] = _tgrd, \ 83 [RZ_MTU3_TGRE] = _tgre, \ 84 [RZ_MTU3_TGRF] = _tgrf \ 85 } 86 87 #define MTU_16BIT_CH_1_2(_tcnt, _tgra, _tgrb) \ 88 { \ 89 [RZ_MTU3_TCNT] = _tcnt, \ 90 [RZ_MTU3_TGRA] = _tgra, \ 91 [RZ_MTU3_TGRB] = _tgrb \ 92 } 93 94 #define MTU_16BIT_CH_3_6(_tcnt, _tgra, _tgrb, _tgrc, _tgrd, _tgre) \ 95 { \ 96 [RZ_MTU3_TCNT] = _tcnt, \ 97 [RZ_MTU3_TGRA] = _tgra, \ 98 [RZ_MTU3_TGRB] = _tgrb, \ 99 [RZ_MTU3_TGRC] = _tgrc, \ 100 [RZ_MTU3_TGRD] = _tgrd, \ 101 [RZ_MTU3_TGRE] = _tgre \ 102 } 103 104 #define MTU_16BIT_CH_4_7(_tcnt, _tgra, _tgrb, _tgrc, _tgrd, _tgre, _tgrf, \ 105 _tadcr, _tadcora, _tadcorb, _tadcobra, _tadcobrb) \ 106 { \ 107 [RZ_MTU3_TCNT] = _tcnt, \ 108 [RZ_MTU3_TGRA] = _tgra, \ 109 [RZ_MTU3_TGRB] = _tgrb, \ 110 [RZ_MTU3_TGRC] = _tgrc, \ 111 [RZ_MTU3_TGRD] = _tgrd, \ 112 [RZ_MTU3_TGRE] = _tgre, \ 113 [RZ_MTU3_TGRF] = _tgrf, \ 114 [RZ_MTU3_TADCR] = _tadcr, \ 115 [RZ_MTU3_TADCORA] = _tadcora, \ 116 [RZ_MTU3_TADCORB] = _tadcorb, \ 117 [RZ_MTU3_TADCOBRA] = _tadcobra, \ 118 [RZ_MTU3_TADCOBRB] = _tadcobrb \ 119 } 120 121 #define MTU_16BIT_CH_5(_tcntu, _tgru, _tcntv, _tgrv, _tcntw, _tgrw) \ 122 { \ 123 [RZ_MTU3_TCNTU] = _tcntu, \ 124 [RZ_MTU3_TGRU] = _tgru, \ 125 [RZ_MTU3_TCNTV] = _tcntv, \ 126 [RZ_MTU3_TGRV] = _tgrv, \ 127 [RZ_MTU3_TCNTW] = _tcntw, \ 128 [RZ_MTU3_TGRW] = _tgrw \ 129 } 130 131 #define MTU_32BIT_CH_1(_tcntlw, _tgralw, _tgrblw) \ 132 { \ 133 [RZ_MTU3_TCNTLW] = _tcntlw, \ 134 [RZ_MTU3_TGRALW] = _tgralw, \ 135 [RZ_MTU3_TGRBLW] = _tgrblw \ 136 } 137 138 #define MTU_32BIT_CH_8(_tcnt, _tgra, _tgrb, _tgrc, _tgrd) \ 139 { \ 140 [RZ_MTU3_TCNT] = _tcnt, \ 141 [RZ_MTU3_TGRA] = _tgra, \ 142 [RZ_MTU3_TGRB] = _tgrb, \ 143 [RZ_MTU3_TGRC] = _tgrc, \ 144 [RZ_MTU3_TGRD] = _tgrd \ 145 } 146 147 #endif 148