1 /* 2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #define pr_fmt(fmt) "%s: " fmt, __func__ 15 16 #include <linux/kernel.h> 17 #include <linux/interrupt.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/err.h> 25 #include <linux/ssbi.h> 26 #include <linux/regmap.h> 27 #include <linux/of_platform.h> 28 #include <linux/mfd/core.h> 29 30 #define SSBI_REG_ADDR_IRQ_BASE 0x1BB 31 32 #define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0) 33 #define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1) 34 #define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2) 35 #define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3) 36 #define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4) 37 #define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5) 38 #define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6) 39 #define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7) 40 #define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8) 41 42 #define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100 43 #define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30) 44 #define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0) 45 #define PM8821_SSBI_REG(m, b, offset) \ 46 ((m == 0) ? \ 47 (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \ 48 (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset)) 49 #define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0) 50 #define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01) 51 #define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08) 52 #define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f) 53 54 #define PM8821_BLOCKS_PER_MASTER 7 55 56 #define PM_IRQF_LVL_SEL 0x01 /* level select */ 57 #define PM_IRQF_MASK_FE 0x02 /* mask falling edge */ 58 #define PM_IRQF_MASK_RE 0x04 /* mask rising edge */ 59 #define PM_IRQF_CLR 0x08 /* clear interrupt */ 60 #define PM_IRQF_BITS_MASK 0x70 61 #define PM_IRQF_BITS_SHIFT 4 62 #define PM_IRQF_WRITE 0x80 63 64 #define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \ 65 PM_IRQF_MASK_RE) 66 67 #define REG_HWREV 0x002 /* PMIC4 revision */ 68 #define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */ 69 70 #define PM8XXX_NR_IRQS 256 71 #define PM8821_NR_IRQS 112 72 73 struct pm_irq_data { 74 int num_irqs; 75 struct irq_chip *irq_chip; 76 void (*irq_handler)(struct irq_desc *desc); 77 }; 78 79 struct pm_irq_chip { 80 struct regmap *regmap; 81 spinlock_t pm_irq_lock; 82 struct irq_domain *irqdomain; 83 unsigned int num_blocks; 84 unsigned int num_masters; 85 const struct pm_irq_data *pm_irq_data; 86 /* MUST BE AT THE END OF THIS STRUCT */ 87 u8 config[0]; 88 }; 89 90 static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp, 91 unsigned int *ip) 92 { 93 int rc; 94 95 spin_lock(&chip->pm_irq_lock); 96 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp); 97 if (rc) { 98 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc); 99 goto bail; 100 } 101 102 rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip); 103 if (rc) 104 pr_err("Failed Reading Status rc=%d\n", rc); 105 bail: 106 spin_unlock(&chip->pm_irq_lock); 107 return rc; 108 } 109 110 static int 111 pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp) 112 { 113 int rc; 114 115 spin_lock(&chip->pm_irq_lock); 116 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp); 117 if (rc) { 118 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc); 119 goto bail; 120 } 121 122 cp |= PM_IRQF_WRITE; 123 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp); 124 if (rc) 125 pr_err("Failed Configuring IRQ rc=%d\n", rc); 126 bail: 127 spin_unlock(&chip->pm_irq_lock); 128 return rc; 129 } 130 131 static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block) 132 { 133 int pmirq, irq, i, ret = 0; 134 unsigned int bits; 135 136 ret = pm8xxx_read_block_irq(chip, block, &bits); 137 if (ret) { 138 pr_err("Failed reading %d block ret=%d", block, ret); 139 return ret; 140 } 141 if (!bits) { 142 pr_err("block bit set in master but no irqs: %d", block); 143 return 0; 144 } 145 146 /* Check IRQ bits */ 147 for (i = 0; i < 8; i++) { 148 if (bits & (1 << i)) { 149 pmirq = block * 8 + i; 150 irq = irq_find_mapping(chip->irqdomain, pmirq); 151 generic_handle_irq(irq); 152 } 153 } 154 return 0; 155 } 156 157 static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master) 158 { 159 unsigned int blockbits; 160 int block_number, i, ret = 0; 161 162 ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master, 163 &blockbits); 164 if (ret) { 165 pr_err("Failed to read master %d ret=%d\n", master, ret); 166 return ret; 167 } 168 if (!blockbits) { 169 pr_err("master bit set in root but no blocks: %d", master); 170 return 0; 171 } 172 173 for (i = 0; i < 8; i++) 174 if (blockbits & (1 << i)) { 175 block_number = master * 8 + i; /* block # */ 176 ret |= pm8xxx_irq_block_handler(chip, block_number); 177 } 178 return ret; 179 } 180 181 static void pm8xxx_irq_handler(struct irq_desc *desc) 182 { 183 struct pm_irq_chip *chip = irq_desc_get_handler_data(desc); 184 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 185 unsigned int root; 186 int i, ret, masters = 0; 187 188 chained_irq_enter(irq_chip, desc); 189 190 ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root); 191 if (ret) { 192 pr_err("Can't read root status ret=%d\n", ret); 193 return; 194 } 195 196 /* on pm8xxx series masters start from bit 1 of the root */ 197 masters = root >> 1; 198 199 /* Read allowed masters for blocks. */ 200 for (i = 0; i < chip->num_masters; i++) 201 if (masters & (1 << i)) 202 pm8xxx_irq_master_handler(chip, i); 203 204 chained_irq_exit(irq_chip, desc); 205 } 206 207 static void pm8821_irq_block_handler(struct pm_irq_chip *chip, 208 int master, int block) 209 { 210 int pmirq, irq, i, ret; 211 unsigned int bits; 212 213 ret = regmap_read(chip->regmap, 214 PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits); 215 if (ret) { 216 pr_err("Reading block %d failed ret=%d", block, ret); 217 return; 218 } 219 220 /* Convert block offset to global block number */ 221 block += (master * PM8821_BLOCKS_PER_MASTER) - 1; 222 223 /* Check IRQ bits */ 224 for (i = 0; i < 8; i++) { 225 if (bits & BIT(i)) { 226 pmirq = block * 8 + i; 227 irq = irq_find_mapping(chip->irqdomain, pmirq); 228 generic_handle_irq(irq); 229 } 230 } 231 } 232 233 static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip, 234 int master, u8 master_val) 235 { 236 int block; 237 238 for (block = 1; block < 8; block++) 239 if (master_val & BIT(block)) 240 pm8821_irq_block_handler(chip, master, block); 241 } 242 243 static void pm8821_irq_handler(struct irq_desc *desc) 244 { 245 struct pm_irq_chip *chip = irq_desc_get_handler_data(desc); 246 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 247 unsigned int master; 248 int ret; 249 250 chained_irq_enter(irq_chip, desc); 251 ret = regmap_read(chip->regmap, 252 PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master); 253 if (ret) { 254 pr_err("Failed to read master 0 ret=%d\n", ret); 255 goto done; 256 } 257 258 /* bits 1 through 7 marks the first 7 blocks in master 0 */ 259 if (master & GENMASK(7, 1)) 260 pm8821_irq_master_handler(chip, 0, master); 261 262 /* bit 0 marks if master 1 contains any bits */ 263 if (!(master & BIT(0))) 264 goto done; 265 266 ret = regmap_read(chip->regmap, 267 PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master); 268 if (ret) { 269 pr_err("Failed to read master 1 ret=%d\n", ret); 270 goto done; 271 } 272 273 pm8821_irq_master_handler(chip, 1, master); 274 275 done: 276 chained_irq_exit(irq_chip, desc); 277 } 278 279 static void pm8xxx_irq_mask_ack(struct irq_data *d) 280 { 281 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); 282 unsigned int pmirq = irqd_to_hwirq(d); 283 u8 block, config; 284 285 block = pmirq / 8; 286 287 config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR; 288 pm8xxx_config_irq(chip, block, config); 289 } 290 291 static void pm8xxx_irq_unmask(struct irq_data *d) 292 { 293 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); 294 unsigned int pmirq = irqd_to_hwirq(d); 295 u8 block, config; 296 297 block = pmirq / 8; 298 299 config = chip->config[pmirq]; 300 pm8xxx_config_irq(chip, block, config); 301 } 302 303 static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 304 { 305 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); 306 unsigned int pmirq = irqd_to_hwirq(d); 307 int irq_bit; 308 u8 block, config; 309 310 block = pmirq / 8; 311 irq_bit = pmirq % 8; 312 313 chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT) 314 | PM_IRQF_MASK_ALL; 315 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 316 if (flow_type & IRQF_TRIGGER_RISING) 317 chip->config[pmirq] &= ~PM_IRQF_MASK_RE; 318 if (flow_type & IRQF_TRIGGER_FALLING) 319 chip->config[pmirq] &= ~PM_IRQF_MASK_FE; 320 } else { 321 chip->config[pmirq] |= PM_IRQF_LVL_SEL; 322 323 if (flow_type & IRQF_TRIGGER_HIGH) 324 chip->config[pmirq] &= ~PM_IRQF_MASK_RE; 325 else 326 chip->config[pmirq] &= ~PM_IRQF_MASK_FE; 327 } 328 329 config = chip->config[pmirq] | PM_IRQF_CLR; 330 return pm8xxx_config_irq(chip, block, config); 331 } 332 333 static int pm8xxx_irq_get_irqchip_state(struct irq_data *d, 334 enum irqchip_irq_state which, 335 bool *state) 336 { 337 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); 338 unsigned int pmirq = irqd_to_hwirq(d); 339 unsigned int bits; 340 int irq_bit; 341 u8 block; 342 int rc; 343 344 if (which != IRQCHIP_STATE_LINE_LEVEL) 345 return -EINVAL; 346 347 block = pmirq / 8; 348 irq_bit = pmirq % 8; 349 350 spin_lock(&chip->pm_irq_lock); 351 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block); 352 if (rc) { 353 pr_err("Failed Selecting Block %d rc=%d\n", block, rc); 354 goto bail; 355 } 356 357 rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits); 358 if (rc) { 359 pr_err("Failed Reading Status rc=%d\n", rc); 360 goto bail; 361 } 362 363 *state = !!(bits & BIT(irq_bit)); 364 bail: 365 spin_unlock(&chip->pm_irq_lock); 366 367 return rc; 368 } 369 370 static struct irq_chip pm8xxx_irq_chip = { 371 .name = "pm8xxx", 372 .irq_mask_ack = pm8xxx_irq_mask_ack, 373 .irq_unmask = pm8xxx_irq_unmask, 374 .irq_set_type = pm8xxx_irq_set_type, 375 .irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state, 376 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, 377 }; 378 379 static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip, 380 struct irq_domain *domain, unsigned int irq, 381 irq_hw_number_t hwirq, unsigned int type) 382 { 383 irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip, 384 chip, handle_level_irq, NULL, NULL); 385 irq_set_noprobe(irq); 386 } 387 388 static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 389 unsigned int nr_irqs, void *data) 390 { 391 struct pm_irq_chip *chip = domain->host_data; 392 struct irq_fwspec *fwspec = data; 393 irq_hw_number_t hwirq; 394 unsigned int type; 395 int ret, i; 396 397 ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); 398 if (ret) 399 return ret; 400 401 for (i = 0; i < nr_irqs; i++) 402 pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type); 403 404 return 0; 405 } 406 407 static const struct irq_domain_ops pm8xxx_irq_domain_ops = { 408 .alloc = pm8xxx_irq_domain_alloc, 409 .free = irq_domain_free_irqs_common, 410 .translate = irq_domain_translate_twocell, 411 }; 412 413 static void pm8821_irq_mask_ack(struct irq_data *d) 414 { 415 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); 416 unsigned int pmirq = irqd_to_hwirq(d); 417 u8 block, master; 418 int irq_bit, rc; 419 420 block = pmirq / 8; 421 master = block / PM8821_BLOCKS_PER_MASTER; 422 irq_bit = pmirq % 8; 423 block %= PM8821_BLOCKS_PER_MASTER; 424 425 rc = regmap_update_bits(chip->regmap, 426 PM8821_SSBI_ADDR_IRQ_MASK(master, block), 427 BIT(irq_bit), BIT(irq_bit)); 428 if (rc) { 429 pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc); 430 return; 431 } 432 433 rc = regmap_update_bits(chip->regmap, 434 PM8821_SSBI_ADDR_IRQ_CLEAR(master, block), 435 BIT(irq_bit), BIT(irq_bit)); 436 if (rc) 437 pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc); 438 } 439 440 static void pm8821_irq_unmask(struct irq_data *d) 441 { 442 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); 443 unsigned int pmirq = irqd_to_hwirq(d); 444 int irq_bit, rc; 445 u8 block, master; 446 447 block = pmirq / 8; 448 master = block / PM8821_BLOCKS_PER_MASTER; 449 irq_bit = pmirq % 8; 450 block %= PM8821_BLOCKS_PER_MASTER; 451 452 rc = regmap_update_bits(chip->regmap, 453 PM8821_SSBI_ADDR_IRQ_MASK(master, block), 454 BIT(irq_bit), ~BIT(irq_bit)); 455 if (rc) 456 pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc); 457 458 } 459 460 static int pm8821_irq_get_irqchip_state(struct irq_data *d, 461 enum irqchip_irq_state which, 462 bool *state) 463 { 464 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); 465 int rc, pmirq = irqd_to_hwirq(d); 466 u8 block, irq_bit, master; 467 unsigned int bits; 468 469 block = pmirq / 8; 470 master = block / PM8821_BLOCKS_PER_MASTER; 471 irq_bit = pmirq % 8; 472 block %= PM8821_BLOCKS_PER_MASTER; 473 474 rc = regmap_read(chip->regmap, 475 PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits); 476 if (rc) { 477 pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc); 478 return rc; 479 } 480 481 *state = !!(bits & BIT(irq_bit)); 482 483 return rc; 484 } 485 486 static struct irq_chip pm8821_irq_chip = { 487 .name = "pm8821", 488 .irq_mask_ack = pm8821_irq_mask_ack, 489 .irq_unmask = pm8821_irq_unmask, 490 .irq_get_irqchip_state = pm8821_irq_get_irqchip_state, 491 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, 492 }; 493 494 static const struct regmap_config ssbi_regmap_config = { 495 .reg_bits = 16, 496 .val_bits = 8, 497 .max_register = 0x3ff, 498 .fast_io = true, 499 .reg_read = ssbi_reg_read, 500 .reg_write = ssbi_reg_write 501 }; 502 503 static const struct pm_irq_data pm8xxx_data = { 504 .num_irqs = PM8XXX_NR_IRQS, 505 .irq_chip = &pm8xxx_irq_chip, 506 .irq_handler = pm8xxx_irq_handler, 507 }; 508 509 static const struct pm_irq_data pm8821_data = { 510 .num_irqs = PM8821_NR_IRQS, 511 .irq_chip = &pm8821_irq_chip, 512 .irq_handler = pm8821_irq_handler, 513 }; 514 515 static const struct of_device_id pm8xxx_id_table[] = { 516 { .compatible = "qcom,pm8018", .data = &pm8xxx_data}, 517 { .compatible = "qcom,pm8058", .data = &pm8xxx_data}, 518 { .compatible = "qcom,pm8821", .data = &pm8821_data}, 519 { .compatible = "qcom,pm8921", .data = &pm8xxx_data}, 520 { } 521 }; 522 MODULE_DEVICE_TABLE(of, pm8xxx_id_table); 523 524 static int pm8xxx_probe(struct platform_device *pdev) 525 { 526 const struct pm_irq_data *data; 527 struct regmap *regmap; 528 int irq, rc; 529 unsigned int val; 530 u32 rev; 531 struct pm_irq_chip *chip; 532 533 data = of_device_get_match_data(&pdev->dev); 534 if (!data) { 535 dev_err(&pdev->dev, "No matching driver data found\n"); 536 return -EINVAL; 537 } 538 539 irq = platform_get_irq(pdev, 0); 540 if (irq < 0) 541 return irq; 542 543 regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent, 544 &ssbi_regmap_config); 545 if (IS_ERR(regmap)) 546 return PTR_ERR(regmap); 547 548 /* Read PMIC chip revision */ 549 rc = regmap_read(regmap, REG_HWREV, &val); 550 if (rc) { 551 pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc); 552 return rc; 553 } 554 pr_info("PMIC revision 1: %02X\n", val); 555 rev = val; 556 557 /* Read PMIC chip revision 2 */ 558 rc = regmap_read(regmap, REG_HWREV_2, &val); 559 if (rc) { 560 pr_err("Failed to read hw rev 2 reg %d:rc=%d\n", 561 REG_HWREV_2, rc); 562 return rc; 563 } 564 pr_info("PMIC revision 2: %02X\n", val); 565 rev |= val << BITS_PER_BYTE; 566 567 chip = devm_kzalloc(&pdev->dev, 568 struct_size(chip, config, data->num_irqs), 569 GFP_KERNEL); 570 if (!chip) 571 return -ENOMEM; 572 573 platform_set_drvdata(pdev, chip); 574 chip->regmap = regmap; 575 chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8); 576 chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8); 577 chip->pm_irq_data = data; 578 spin_lock_init(&chip->pm_irq_lock); 579 580 chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, 581 data->num_irqs, 582 &pm8xxx_irq_domain_ops, 583 chip); 584 if (!chip->irqdomain) 585 return -ENODEV; 586 587 irq_set_chained_handler_and_data(irq, data->irq_handler, chip); 588 irq_set_irq_wake(irq, 1); 589 590 rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 591 if (rc) { 592 irq_set_chained_handler_and_data(irq, NULL, NULL); 593 irq_domain_remove(chip->irqdomain); 594 } 595 596 return rc; 597 } 598 599 static int pm8xxx_remove_child(struct device *dev, void *unused) 600 { 601 platform_device_unregister(to_platform_device(dev)); 602 return 0; 603 } 604 605 static int pm8xxx_remove(struct platform_device *pdev) 606 { 607 int irq = platform_get_irq(pdev, 0); 608 struct pm_irq_chip *chip = platform_get_drvdata(pdev); 609 610 device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child); 611 irq_set_chained_handler_and_data(irq, NULL, NULL); 612 irq_domain_remove(chip->irqdomain); 613 614 return 0; 615 } 616 617 static struct platform_driver pm8xxx_driver = { 618 .probe = pm8xxx_probe, 619 .remove = pm8xxx_remove, 620 .driver = { 621 .name = "pm8xxx-core", 622 .of_match_table = pm8xxx_id_table, 623 }, 624 }; 625 626 static int __init pm8xxx_init(void) 627 { 628 return platform_driver_register(&pm8xxx_driver); 629 } 630 subsys_initcall(pm8xxx_init); 631 632 static void __exit pm8xxx_exit(void) 633 { 634 platform_driver_unregister(&pm8xxx_driver); 635 } 636 module_exit(pm8xxx_exit); 637 638 MODULE_LICENSE("GPL v2"); 639 MODULE_DESCRIPTION("PMIC 8xxx core driver"); 640 MODULE_VERSION("1.0"); 641 MODULE_ALIAS("platform:pm8xxx-core"); 642