197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
240a3a0f2SLinus Walleij /*
340a3a0f2SLinus Walleij * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
440a3a0f2SLinus Walleij */
540a3a0f2SLinus Walleij
640a3a0f2SLinus Walleij #define pr_fmt(fmt) "%s: " fmt, __func__
740a3a0f2SLinus Walleij
840a3a0f2SLinus Walleij #include <linux/kernel.h>
940a3a0f2SLinus Walleij #include <linux/interrupt.h>
1040a3a0f2SLinus Walleij #include <linux/irqchip/chained_irq.h>
1140a3a0f2SLinus Walleij #include <linux/irq.h>
1240a3a0f2SLinus Walleij #include <linux/irqdomain.h>
1340a3a0f2SLinus Walleij #include <linux/module.h>
1440a3a0f2SLinus Walleij #include <linux/platform_device.h>
1540a3a0f2SLinus Walleij #include <linux/slab.h>
1640a3a0f2SLinus Walleij #include <linux/err.h>
1740a3a0f2SLinus Walleij #include <linux/ssbi.h>
1840a3a0f2SLinus Walleij #include <linux/regmap.h>
1940a3a0f2SLinus Walleij #include <linux/of_platform.h>
2040a3a0f2SLinus Walleij #include <linux/mfd/core.h>
2140a3a0f2SLinus Walleij
2240a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_BASE 0x1BB
2340a3a0f2SLinus Walleij
2440a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
2540a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
2640a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
2740a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
2840a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
2940a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
3040a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
3140a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
3240a3a0f2SLinus Walleij #define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
3340a3a0f2SLinus Walleij
34953f432bSSrinivas Kandagatla #define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
35953f432bSSrinivas Kandagatla #define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
36953f432bSSrinivas Kandagatla #define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
37953f432bSSrinivas Kandagatla #define PM8821_SSBI_REG(m, b, offset) \
38953f432bSSrinivas Kandagatla ((m == 0) ? \
39953f432bSSrinivas Kandagatla (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
40953f432bSSrinivas Kandagatla (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
41953f432bSSrinivas Kandagatla #define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
42953f432bSSrinivas Kandagatla #define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
43953f432bSSrinivas Kandagatla #define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
44953f432bSSrinivas Kandagatla #define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
45953f432bSSrinivas Kandagatla
46953f432bSSrinivas Kandagatla #define PM8821_BLOCKS_PER_MASTER 7
47953f432bSSrinivas Kandagatla
4840a3a0f2SLinus Walleij #define PM_IRQF_LVL_SEL 0x01 /* level select */
4940a3a0f2SLinus Walleij #define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
5040a3a0f2SLinus Walleij #define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
5140a3a0f2SLinus Walleij #define PM_IRQF_CLR 0x08 /* clear interrupt */
5240a3a0f2SLinus Walleij #define PM_IRQF_BITS_MASK 0x70
5340a3a0f2SLinus Walleij #define PM_IRQF_BITS_SHIFT 4
5440a3a0f2SLinus Walleij #define PM_IRQF_WRITE 0x80
5540a3a0f2SLinus Walleij
5640a3a0f2SLinus Walleij #define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
5740a3a0f2SLinus Walleij PM_IRQF_MASK_RE)
5840a3a0f2SLinus Walleij
5940a3a0f2SLinus Walleij #define REG_HWREV 0x002 /* PMIC4 revision */
6040a3a0f2SLinus Walleij #define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
6140a3a0f2SLinus Walleij
6240a3a0f2SLinus Walleij #define PM8XXX_NR_IRQS 256
63953f432bSSrinivas Kandagatla #define PM8821_NR_IRQS 112
6440a3a0f2SLinus Walleij
653324a7c1SBrian Masney struct pm_irq_data {
663324a7c1SBrian Masney int num_irqs;
673324a7c1SBrian Masney struct irq_chip *irq_chip;
68d3546ccdSDmitry Baryshkov irq_handler_t irq_handler;
693324a7c1SBrian Masney };
703324a7c1SBrian Masney
7140a3a0f2SLinus Walleij struct pm_irq_chip {
7240a3a0f2SLinus Walleij struct regmap *regmap;
7340a3a0f2SLinus Walleij spinlock_t pm_irq_lock;
7440a3a0f2SLinus Walleij struct irq_domain *irqdomain;
7540a3a0f2SLinus Walleij unsigned int num_blocks;
7640a3a0f2SLinus Walleij unsigned int num_masters;
773324a7c1SBrian Masney const struct pm_irq_data *pm_irq_data;
783324a7c1SBrian Masney /* MUST BE AT THE END OF THIS STRUCT */
797235d9e4SGustavo A. R. Silva u8 config[];
8040a3a0f2SLinus Walleij };
8140a3a0f2SLinus Walleij
pm8xxx_read_block_irq(struct pm_irq_chip * chip,unsigned int bp,unsigned int * ip)8240a3a0f2SLinus Walleij static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
8340a3a0f2SLinus Walleij unsigned int *ip)
8440a3a0f2SLinus Walleij {
8540a3a0f2SLinus Walleij int rc;
8640a3a0f2SLinus Walleij
8740a3a0f2SLinus Walleij spin_lock(&chip->pm_irq_lock);
8840a3a0f2SLinus Walleij rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
8940a3a0f2SLinus Walleij if (rc) {
9040a3a0f2SLinus Walleij pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
9140a3a0f2SLinus Walleij goto bail;
9240a3a0f2SLinus Walleij }
9340a3a0f2SLinus Walleij
9440a3a0f2SLinus Walleij rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
9540a3a0f2SLinus Walleij if (rc)
9640a3a0f2SLinus Walleij pr_err("Failed Reading Status rc=%d\n", rc);
9740a3a0f2SLinus Walleij bail:
9840a3a0f2SLinus Walleij spin_unlock(&chip->pm_irq_lock);
9940a3a0f2SLinus Walleij return rc;
10040a3a0f2SLinus Walleij }
10140a3a0f2SLinus Walleij
10240a3a0f2SLinus Walleij static int
pm8xxx_config_irq(struct pm_irq_chip * chip,unsigned int bp,unsigned int cp)10340a3a0f2SLinus Walleij pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
10440a3a0f2SLinus Walleij {
10540a3a0f2SLinus Walleij int rc;
106*f1a63db6SChengfeng Ye unsigned long flags;
10740a3a0f2SLinus Walleij
108*f1a63db6SChengfeng Ye spin_lock_irqsave(&chip->pm_irq_lock, flags);
10940a3a0f2SLinus Walleij rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
11040a3a0f2SLinus Walleij if (rc) {
11140a3a0f2SLinus Walleij pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
11240a3a0f2SLinus Walleij goto bail;
11340a3a0f2SLinus Walleij }
11440a3a0f2SLinus Walleij
11540a3a0f2SLinus Walleij cp |= PM_IRQF_WRITE;
11640a3a0f2SLinus Walleij rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
11740a3a0f2SLinus Walleij if (rc)
11840a3a0f2SLinus Walleij pr_err("Failed Configuring IRQ rc=%d\n", rc);
11940a3a0f2SLinus Walleij bail:
120*f1a63db6SChengfeng Ye spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
12140a3a0f2SLinus Walleij return rc;
12240a3a0f2SLinus Walleij }
12340a3a0f2SLinus Walleij
pm8xxx_irq_block_handler(struct pm_irq_chip * chip,int block)12440a3a0f2SLinus Walleij static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
12540a3a0f2SLinus Walleij {
1263b0cccefSMarc Zyngier int pmirq, i, ret = 0;
12740a3a0f2SLinus Walleij unsigned int bits;
12840a3a0f2SLinus Walleij
12940a3a0f2SLinus Walleij ret = pm8xxx_read_block_irq(chip, block, &bits);
13040a3a0f2SLinus Walleij if (ret) {
13140a3a0f2SLinus Walleij pr_err("Failed reading %d block ret=%d", block, ret);
13240a3a0f2SLinus Walleij return ret;
13340a3a0f2SLinus Walleij }
13440a3a0f2SLinus Walleij if (!bits) {
13540a3a0f2SLinus Walleij pr_err("block bit set in master but no irqs: %d", block);
13640a3a0f2SLinus Walleij return 0;
13740a3a0f2SLinus Walleij }
13840a3a0f2SLinus Walleij
13940a3a0f2SLinus Walleij /* Check IRQ bits */
14040a3a0f2SLinus Walleij for (i = 0; i < 8; i++) {
14140a3a0f2SLinus Walleij if (bits & (1 << i)) {
14240a3a0f2SLinus Walleij pmirq = block * 8 + i;
1433b0cccefSMarc Zyngier generic_handle_domain_irq(chip->irqdomain, pmirq);
14440a3a0f2SLinus Walleij }
14540a3a0f2SLinus Walleij }
14640a3a0f2SLinus Walleij return 0;
14740a3a0f2SLinus Walleij }
14840a3a0f2SLinus Walleij
pm8xxx_irq_master_handler(struct pm_irq_chip * chip,int master)14940a3a0f2SLinus Walleij static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
15040a3a0f2SLinus Walleij {
15140a3a0f2SLinus Walleij unsigned int blockbits;
15240a3a0f2SLinus Walleij int block_number, i, ret = 0;
15340a3a0f2SLinus Walleij
15440a3a0f2SLinus Walleij ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
15540a3a0f2SLinus Walleij &blockbits);
15640a3a0f2SLinus Walleij if (ret) {
15740a3a0f2SLinus Walleij pr_err("Failed to read master %d ret=%d\n", master, ret);
15840a3a0f2SLinus Walleij return ret;
15940a3a0f2SLinus Walleij }
16040a3a0f2SLinus Walleij if (!blockbits) {
16140a3a0f2SLinus Walleij pr_err("master bit set in root but no blocks: %d", master);
16240a3a0f2SLinus Walleij return 0;
16340a3a0f2SLinus Walleij }
16440a3a0f2SLinus Walleij
16540a3a0f2SLinus Walleij for (i = 0; i < 8; i++)
16640a3a0f2SLinus Walleij if (blockbits & (1 << i)) {
16740a3a0f2SLinus Walleij block_number = master * 8 + i; /* block # */
16840a3a0f2SLinus Walleij ret |= pm8xxx_irq_block_handler(chip, block_number);
16940a3a0f2SLinus Walleij }
17040a3a0f2SLinus Walleij return ret;
17140a3a0f2SLinus Walleij }
17240a3a0f2SLinus Walleij
pm8xxx_irq_handler(int irq,void * data)173d3546ccdSDmitry Baryshkov static irqreturn_t pm8xxx_irq_handler(int irq, void *data)
17440a3a0f2SLinus Walleij {
175d3546ccdSDmitry Baryshkov struct pm_irq_chip *chip = data;
17640a3a0f2SLinus Walleij unsigned int root;
17740a3a0f2SLinus Walleij int i, ret, masters = 0;
17840a3a0f2SLinus Walleij
17940a3a0f2SLinus Walleij ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
18040a3a0f2SLinus Walleij if (ret) {
18140a3a0f2SLinus Walleij pr_err("Can't read root status ret=%d\n", ret);
182d3546ccdSDmitry Baryshkov return IRQ_NONE;
18340a3a0f2SLinus Walleij }
18440a3a0f2SLinus Walleij
18540a3a0f2SLinus Walleij /* on pm8xxx series masters start from bit 1 of the root */
18640a3a0f2SLinus Walleij masters = root >> 1;
18740a3a0f2SLinus Walleij
18840a3a0f2SLinus Walleij /* Read allowed masters for blocks. */
18940a3a0f2SLinus Walleij for (i = 0; i < chip->num_masters; i++)
19040a3a0f2SLinus Walleij if (masters & (1 << i))
19140a3a0f2SLinus Walleij pm8xxx_irq_master_handler(chip, i);
19240a3a0f2SLinus Walleij
193d3546ccdSDmitry Baryshkov return IRQ_HANDLED;
19440a3a0f2SLinus Walleij }
19540a3a0f2SLinus Walleij
pm8821_irq_block_handler(struct pm_irq_chip * chip,int master,int block)196953f432bSSrinivas Kandagatla static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
197953f432bSSrinivas Kandagatla int master, int block)
198953f432bSSrinivas Kandagatla {
1993b0cccefSMarc Zyngier int pmirq, i, ret;
200953f432bSSrinivas Kandagatla unsigned int bits;
201953f432bSSrinivas Kandagatla
202953f432bSSrinivas Kandagatla ret = regmap_read(chip->regmap,
203953f432bSSrinivas Kandagatla PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
204953f432bSSrinivas Kandagatla if (ret) {
205953f432bSSrinivas Kandagatla pr_err("Reading block %d failed ret=%d", block, ret);
206953f432bSSrinivas Kandagatla return;
207953f432bSSrinivas Kandagatla }
208953f432bSSrinivas Kandagatla
209953f432bSSrinivas Kandagatla /* Convert block offset to global block number */
210953f432bSSrinivas Kandagatla block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
211953f432bSSrinivas Kandagatla
212953f432bSSrinivas Kandagatla /* Check IRQ bits */
213953f432bSSrinivas Kandagatla for (i = 0; i < 8; i++) {
214953f432bSSrinivas Kandagatla if (bits & BIT(i)) {
215953f432bSSrinivas Kandagatla pmirq = block * 8 + i;
2163b0cccefSMarc Zyngier generic_handle_domain_irq(chip->irqdomain, pmirq);
217953f432bSSrinivas Kandagatla }
218953f432bSSrinivas Kandagatla }
219953f432bSSrinivas Kandagatla }
220953f432bSSrinivas Kandagatla
pm8821_irq_master_handler(struct pm_irq_chip * chip,int master,u8 master_val)221953f432bSSrinivas Kandagatla static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
222953f432bSSrinivas Kandagatla int master, u8 master_val)
223953f432bSSrinivas Kandagatla {
224953f432bSSrinivas Kandagatla int block;
225953f432bSSrinivas Kandagatla
226953f432bSSrinivas Kandagatla for (block = 1; block < 8; block++)
227953f432bSSrinivas Kandagatla if (master_val & BIT(block))
228953f432bSSrinivas Kandagatla pm8821_irq_block_handler(chip, master, block);
229953f432bSSrinivas Kandagatla }
230953f432bSSrinivas Kandagatla
pm8821_irq_handler(int irq,void * data)231d3546ccdSDmitry Baryshkov static irqreturn_t pm8821_irq_handler(int irq, void *data)
232953f432bSSrinivas Kandagatla {
233d3546ccdSDmitry Baryshkov struct pm_irq_chip *chip = data;
234953f432bSSrinivas Kandagatla unsigned int master;
235953f432bSSrinivas Kandagatla int ret;
236953f432bSSrinivas Kandagatla
237953f432bSSrinivas Kandagatla ret = regmap_read(chip->regmap,
238953f432bSSrinivas Kandagatla PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
239953f432bSSrinivas Kandagatla if (ret) {
240953f432bSSrinivas Kandagatla pr_err("Failed to read master 0 ret=%d\n", ret);
241d3546ccdSDmitry Baryshkov return IRQ_NONE;
242953f432bSSrinivas Kandagatla }
243953f432bSSrinivas Kandagatla
244953f432bSSrinivas Kandagatla /* bits 1 through 7 marks the first 7 blocks in master 0 */
245953f432bSSrinivas Kandagatla if (master & GENMASK(7, 1))
246953f432bSSrinivas Kandagatla pm8821_irq_master_handler(chip, 0, master);
247953f432bSSrinivas Kandagatla
248953f432bSSrinivas Kandagatla /* bit 0 marks if master 1 contains any bits */
249953f432bSSrinivas Kandagatla if (!(master & BIT(0)))
250d3546ccdSDmitry Baryshkov return IRQ_NONE;
251953f432bSSrinivas Kandagatla
252953f432bSSrinivas Kandagatla ret = regmap_read(chip->regmap,
253953f432bSSrinivas Kandagatla PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
254953f432bSSrinivas Kandagatla if (ret) {
255953f432bSSrinivas Kandagatla pr_err("Failed to read master 1 ret=%d\n", ret);
256d3546ccdSDmitry Baryshkov return IRQ_NONE;
257953f432bSSrinivas Kandagatla }
258953f432bSSrinivas Kandagatla
259953f432bSSrinivas Kandagatla pm8821_irq_master_handler(chip, 1, master);
260953f432bSSrinivas Kandagatla
261d3546ccdSDmitry Baryshkov return IRQ_HANDLED;
262953f432bSSrinivas Kandagatla }
263953f432bSSrinivas Kandagatla
pm8xxx_irq_mask_ack(struct irq_data * d)26440a3a0f2SLinus Walleij static void pm8xxx_irq_mask_ack(struct irq_data *d)
26540a3a0f2SLinus Walleij {
26640a3a0f2SLinus Walleij struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
26740a3a0f2SLinus Walleij unsigned int pmirq = irqd_to_hwirq(d);
26840a3a0f2SLinus Walleij u8 block, config;
26940a3a0f2SLinus Walleij
27040a3a0f2SLinus Walleij block = pmirq / 8;
27140a3a0f2SLinus Walleij
27240a3a0f2SLinus Walleij config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
27340a3a0f2SLinus Walleij pm8xxx_config_irq(chip, block, config);
27440a3a0f2SLinus Walleij }
27540a3a0f2SLinus Walleij
pm8xxx_irq_unmask(struct irq_data * d)27640a3a0f2SLinus Walleij static void pm8xxx_irq_unmask(struct irq_data *d)
27740a3a0f2SLinus Walleij {
27840a3a0f2SLinus Walleij struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
27940a3a0f2SLinus Walleij unsigned int pmirq = irqd_to_hwirq(d);
28040a3a0f2SLinus Walleij u8 block, config;
28140a3a0f2SLinus Walleij
28240a3a0f2SLinus Walleij block = pmirq / 8;
28340a3a0f2SLinus Walleij
28440a3a0f2SLinus Walleij config = chip->config[pmirq];
28540a3a0f2SLinus Walleij pm8xxx_config_irq(chip, block, config);
28640a3a0f2SLinus Walleij }
28740a3a0f2SLinus Walleij
pm8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)28840a3a0f2SLinus Walleij static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
28940a3a0f2SLinus Walleij {
29040a3a0f2SLinus Walleij struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
29140a3a0f2SLinus Walleij unsigned int pmirq = irqd_to_hwirq(d);
29240a3a0f2SLinus Walleij int irq_bit;
29340a3a0f2SLinus Walleij u8 block, config;
29440a3a0f2SLinus Walleij
29540a3a0f2SLinus Walleij block = pmirq / 8;
29640a3a0f2SLinus Walleij irq_bit = pmirq % 8;
29740a3a0f2SLinus Walleij
29840a3a0f2SLinus Walleij chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
29940a3a0f2SLinus Walleij | PM_IRQF_MASK_ALL;
30040a3a0f2SLinus Walleij if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
30140a3a0f2SLinus Walleij if (flow_type & IRQF_TRIGGER_RISING)
30240a3a0f2SLinus Walleij chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
30340a3a0f2SLinus Walleij if (flow_type & IRQF_TRIGGER_FALLING)
30440a3a0f2SLinus Walleij chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
30540a3a0f2SLinus Walleij } else {
30640a3a0f2SLinus Walleij chip->config[pmirq] |= PM_IRQF_LVL_SEL;
30740a3a0f2SLinus Walleij
30840a3a0f2SLinus Walleij if (flow_type & IRQF_TRIGGER_HIGH)
30940a3a0f2SLinus Walleij chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
31040a3a0f2SLinus Walleij else
31140a3a0f2SLinus Walleij chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
31240a3a0f2SLinus Walleij }
31340a3a0f2SLinus Walleij
31440a3a0f2SLinus Walleij config = chip->config[pmirq] | PM_IRQF_CLR;
31540a3a0f2SLinus Walleij return pm8xxx_config_irq(chip, block, config);
31640a3a0f2SLinus Walleij }
31740a3a0f2SLinus Walleij
pm8xxx_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * state)31840a3a0f2SLinus Walleij static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
31940a3a0f2SLinus Walleij enum irqchip_irq_state which,
32040a3a0f2SLinus Walleij bool *state)
32140a3a0f2SLinus Walleij {
32240a3a0f2SLinus Walleij struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
32340a3a0f2SLinus Walleij unsigned int pmirq = irqd_to_hwirq(d);
32440a3a0f2SLinus Walleij unsigned int bits;
325*f1a63db6SChengfeng Ye unsigned long flags;
32640a3a0f2SLinus Walleij int irq_bit;
32740a3a0f2SLinus Walleij u8 block;
32840a3a0f2SLinus Walleij int rc;
32940a3a0f2SLinus Walleij
33040a3a0f2SLinus Walleij if (which != IRQCHIP_STATE_LINE_LEVEL)
33140a3a0f2SLinus Walleij return -EINVAL;
33240a3a0f2SLinus Walleij
33340a3a0f2SLinus Walleij block = pmirq / 8;
33440a3a0f2SLinus Walleij irq_bit = pmirq % 8;
33540a3a0f2SLinus Walleij
336*f1a63db6SChengfeng Ye spin_lock_irqsave(&chip->pm_irq_lock, flags);
33740a3a0f2SLinus Walleij rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
33840a3a0f2SLinus Walleij if (rc) {
33940a3a0f2SLinus Walleij pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
34040a3a0f2SLinus Walleij goto bail;
34140a3a0f2SLinus Walleij }
34240a3a0f2SLinus Walleij
34340a3a0f2SLinus Walleij rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
34440a3a0f2SLinus Walleij if (rc) {
34540a3a0f2SLinus Walleij pr_err("Failed Reading Status rc=%d\n", rc);
34640a3a0f2SLinus Walleij goto bail;
34740a3a0f2SLinus Walleij }
34840a3a0f2SLinus Walleij
34940a3a0f2SLinus Walleij *state = !!(bits & BIT(irq_bit));
35040a3a0f2SLinus Walleij bail:
351*f1a63db6SChengfeng Ye spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
35240a3a0f2SLinus Walleij
35340a3a0f2SLinus Walleij return rc;
35440a3a0f2SLinus Walleij }
35540a3a0f2SLinus Walleij
35640a3a0f2SLinus Walleij static struct irq_chip pm8xxx_irq_chip = {
35740a3a0f2SLinus Walleij .name = "pm8xxx",
35840a3a0f2SLinus Walleij .irq_mask_ack = pm8xxx_irq_mask_ack,
35940a3a0f2SLinus Walleij .irq_unmask = pm8xxx_irq_unmask,
36040a3a0f2SLinus Walleij .irq_set_type = pm8xxx_irq_set_type,
36140a3a0f2SLinus Walleij .irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
36240a3a0f2SLinus Walleij .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
36340a3a0f2SLinus Walleij };
36440a3a0f2SLinus Walleij
pm8xxx_irq_domain_map(struct pm_irq_chip * chip,struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq,unsigned int type)3653324a7c1SBrian Masney static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
3663324a7c1SBrian Masney struct irq_domain *domain, unsigned int irq,
3673324a7c1SBrian Masney irq_hw_number_t hwirq, unsigned int type)
36840a3a0f2SLinus Walleij {
3693324a7c1SBrian Masney irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
3703324a7c1SBrian Masney chip, handle_level_irq, NULL, NULL);
37140a3a0f2SLinus Walleij irq_set_noprobe(irq);
3723324a7c1SBrian Masney }
3733324a7c1SBrian Masney
pm8xxx_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)3743324a7c1SBrian Masney static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3753324a7c1SBrian Masney unsigned int nr_irqs, void *data)
3763324a7c1SBrian Masney {
3773324a7c1SBrian Masney struct pm_irq_chip *chip = domain->host_data;
3783324a7c1SBrian Masney struct irq_fwspec *fwspec = data;
3793324a7c1SBrian Masney irq_hw_number_t hwirq;
3803324a7c1SBrian Masney unsigned int type;
3813324a7c1SBrian Masney int ret, i;
3823324a7c1SBrian Masney
3833324a7c1SBrian Masney ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
3843324a7c1SBrian Masney if (ret)
3853324a7c1SBrian Masney return ret;
3863324a7c1SBrian Masney
3873324a7c1SBrian Masney for (i = 0; i < nr_irqs; i++)
3883324a7c1SBrian Masney pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
38940a3a0f2SLinus Walleij
39040a3a0f2SLinus Walleij return 0;
39140a3a0f2SLinus Walleij }
39240a3a0f2SLinus Walleij
39340a3a0f2SLinus Walleij static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
3943324a7c1SBrian Masney .alloc = pm8xxx_irq_domain_alloc,
3953324a7c1SBrian Masney .free = irq_domain_free_irqs_common,
3963324a7c1SBrian Masney .translate = irq_domain_translate_twocell,
39740a3a0f2SLinus Walleij };
39840a3a0f2SLinus Walleij
pm8821_irq_mask_ack(struct irq_data * d)399953f432bSSrinivas Kandagatla static void pm8821_irq_mask_ack(struct irq_data *d)
400953f432bSSrinivas Kandagatla {
401953f432bSSrinivas Kandagatla struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
402953f432bSSrinivas Kandagatla unsigned int pmirq = irqd_to_hwirq(d);
403953f432bSSrinivas Kandagatla u8 block, master;
404953f432bSSrinivas Kandagatla int irq_bit, rc;
405953f432bSSrinivas Kandagatla
406953f432bSSrinivas Kandagatla block = pmirq / 8;
407953f432bSSrinivas Kandagatla master = block / PM8821_BLOCKS_PER_MASTER;
408953f432bSSrinivas Kandagatla irq_bit = pmirq % 8;
409953f432bSSrinivas Kandagatla block %= PM8821_BLOCKS_PER_MASTER;
410953f432bSSrinivas Kandagatla
411953f432bSSrinivas Kandagatla rc = regmap_update_bits(chip->regmap,
412953f432bSSrinivas Kandagatla PM8821_SSBI_ADDR_IRQ_MASK(master, block),
413953f432bSSrinivas Kandagatla BIT(irq_bit), BIT(irq_bit));
414953f432bSSrinivas Kandagatla if (rc) {
415953f432bSSrinivas Kandagatla pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
416953f432bSSrinivas Kandagatla return;
417953f432bSSrinivas Kandagatla }
418953f432bSSrinivas Kandagatla
419953f432bSSrinivas Kandagatla rc = regmap_update_bits(chip->regmap,
420953f432bSSrinivas Kandagatla PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
421953f432bSSrinivas Kandagatla BIT(irq_bit), BIT(irq_bit));
422953f432bSSrinivas Kandagatla if (rc)
423953f432bSSrinivas Kandagatla pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
424953f432bSSrinivas Kandagatla }
425953f432bSSrinivas Kandagatla
pm8821_irq_unmask(struct irq_data * d)426953f432bSSrinivas Kandagatla static void pm8821_irq_unmask(struct irq_data *d)
427953f432bSSrinivas Kandagatla {
428953f432bSSrinivas Kandagatla struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
429953f432bSSrinivas Kandagatla unsigned int pmirq = irqd_to_hwirq(d);
430953f432bSSrinivas Kandagatla int irq_bit, rc;
431953f432bSSrinivas Kandagatla u8 block, master;
432953f432bSSrinivas Kandagatla
433953f432bSSrinivas Kandagatla block = pmirq / 8;
434953f432bSSrinivas Kandagatla master = block / PM8821_BLOCKS_PER_MASTER;
435953f432bSSrinivas Kandagatla irq_bit = pmirq % 8;
436953f432bSSrinivas Kandagatla block %= PM8821_BLOCKS_PER_MASTER;
437953f432bSSrinivas Kandagatla
438953f432bSSrinivas Kandagatla rc = regmap_update_bits(chip->regmap,
439953f432bSSrinivas Kandagatla PM8821_SSBI_ADDR_IRQ_MASK(master, block),
440953f432bSSrinivas Kandagatla BIT(irq_bit), ~BIT(irq_bit));
441953f432bSSrinivas Kandagatla if (rc)
442953f432bSSrinivas Kandagatla pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
443953f432bSSrinivas Kandagatla
444953f432bSSrinivas Kandagatla }
445953f432bSSrinivas Kandagatla
pm8821_irq_get_irqchip_state(struct irq_data * d,enum irqchip_irq_state which,bool * state)446953f432bSSrinivas Kandagatla static int pm8821_irq_get_irqchip_state(struct irq_data *d,
447953f432bSSrinivas Kandagatla enum irqchip_irq_state which,
448953f432bSSrinivas Kandagatla bool *state)
449953f432bSSrinivas Kandagatla {
450953f432bSSrinivas Kandagatla struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
451953f432bSSrinivas Kandagatla int rc, pmirq = irqd_to_hwirq(d);
452953f432bSSrinivas Kandagatla u8 block, irq_bit, master;
453953f432bSSrinivas Kandagatla unsigned int bits;
454953f432bSSrinivas Kandagatla
455953f432bSSrinivas Kandagatla block = pmirq / 8;
456953f432bSSrinivas Kandagatla master = block / PM8821_BLOCKS_PER_MASTER;
457953f432bSSrinivas Kandagatla irq_bit = pmirq % 8;
458953f432bSSrinivas Kandagatla block %= PM8821_BLOCKS_PER_MASTER;
459953f432bSSrinivas Kandagatla
460953f432bSSrinivas Kandagatla rc = regmap_read(chip->regmap,
461953f432bSSrinivas Kandagatla PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
462953f432bSSrinivas Kandagatla if (rc) {
463953f432bSSrinivas Kandagatla pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
464953f432bSSrinivas Kandagatla return rc;
465953f432bSSrinivas Kandagatla }
466953f432bSSrinivas Kandagatla
467953f432bSSrinivas Kandagatla *state = !!(bits & BIT(irq_bit));
468953f432bSSrinivas Kandagatla
469953f432bSSrinivas Kandagatla return rc;
470953f432bSSrinivas Kandagatla }
471953f432bSSrinivas Kandagatla
472953f432bSSrinivas Kandagatla static struct irq_chip pm8821_irq_chip = {
473953f432bSSrinivas Kandagatla .name = "pm8821",
474953f432bSSrinivas Kandagatla .irq_mask_ack = pm8821_irq_mask_ack,
475953f432bSSrinivas Kandagatla .irq_unmask = pm8821_irq_unmask,
476953f432bSSrinivas Kandagatla .irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
477953f432bSSrinivas Kandagatla .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
478953f432bSSrinivas Kandagatla };
479953f432bSSrinivas Kandagatla
48040a3a0f2SLinus Walleij static const struct regmap_config ssbi_regmap_config = {
48140a3a0f2SLinus Walleij .reg_bits = 16,
48240a3a0f2SLinus Walleij .val_bits = 8,
48340a3a0f2SLinus Walleij .max_register = 0x3ff,
48440a3a0f2SLinus Walleij .fast_io = true,
48540a3a0f2SLinus Walleij .reg_read = ssbi_reg_read,
48640a3a0f2SLinus Walleij .reg_write = ssbi_reg_write
48740a3a0f2SLinus Walleij };
48840a3a0f2SLinus Walleij
489953f432bSSrinivas Kandagatla static const struct pm_irq_data pm8xxx_data = {
490953f432bSSrinivas Kandagatla .num_irqs = PM8XXX_NR_IRQS,
4913324a7c1SBrian Masney .irq_chip = &pm8xxx_irq_chip,
492953f432bSSrinivas Kandagatla .irq_handler = pm8xxx_irq_handler,
493953f432bSSrinivas Kandagatla };
494953f432bSSrinivas Kandagatla
495953f432bSSrinivas Kandagatla static const struct pm_irq_data pm8821_data = {
496953f432bSSrinivas Kandagatla .num_irqs = PM8821_NR_IRQS,
4973324a7c1SBrian Masney .irq_chip = &pm8821_irq_chip,
498953f432bSSrinivas Kandagatla .irq_handler = pm8821_irq_handler,
499953f432bSSrinivas Kandagatla };
500953f432bSSrinivas Kandagatla
50140a3a0f2SLinus Walleij static const struct of_device_id pm8xxx_id_table[] = {
502953f432bSSrinivas Kandagatla { .compatible = "qcom,pm8058", .data = &pm8xxx_data},
503953f432bSSrinivas Kandagatla { .compatible = "qcom,pm8821", .data = &pm8821_data},
504953f432bSSrinivas Kandagatla { .compatible = "qcom,pm8921", .data = &pm8xxx_data},
50540a3a0f2SLinus Walleij { }
50640a3a0f2SLinus Walleij };
50740a3a0f2SLinus Walleij MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
50840a3a0f2SLinus Walleij
pm8xxx_probe(struct platform_device * pdev)50940a3a0f2SLinus Walleij static int pm8xxx_probe(struct platform_device *pdev)
51040a3a0f2SLinus Walleij {
511953f432bSSrinivas Kandagatla const struct pm_irq_data *data;
51240a3a0f2SLinus Walleij struct regmap *regmap;
51340a3a0f2SLinus Walleij int irq, rc;
51440a3a0f2SLinus Walleij unsigned int val;
51540a3a0f2SLinus Walleij struct pm_irq_chip *chip;
516953f432bSSrinivas Kandagatla
517953f432bSSrinivas Kandagatla data = of_device_get_match_data(&pdev->dev);
518953f432bSSrinivas Kandagatla if (!data) {
519953f432bSSrinivas Kandagatla dev_err(&pdev->dev, "No matching driver data found\n");
520953f432bSSrinivas Kandagatla return -EINVAL;
521953f432bSSrinivas Kandagatla }
52240a3a0f2SLinus Walleij
52340a3a0f2SLinus Walleij irq = platform_get_irq(pdev, 0);
52440a3a0f2SLinus Walleij if (irq < 0)
52540a3a0f2SLinus Walleij return irq;
52640a3a0f2SLinus Walleij
52740a3a0f2SLinus Walleij regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
52840a3a0f2SLinus Walleij &ssbi_regmap_config);
52940a3a0f2SLinus Walleij if (IS_ERR(regmap))
53040a3a0f2SLinus Walleij return PTR_ERR(regmap);
53140a3a0f2SLinus Walleij
53240a3a0f2SLinus Walleij /* Read PMIC chip revision */
53340a3a0f2SLinus Walleij rc = regmap_read(regmap, REG_HWREV, &val);
53440a3a0f2SLinus Walleij if (rc) {
53540a3a0f2SLinus Walleij pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
53640a3a0f2SLinus Walleij return rc;
53740a3a0f2SLinus Walleij }
53840a3a0f2SLinus Walleij pr_info("PMIC revision 1: %02X\n", val);
53940a3a0f2SLinus Walleij
54040a3a0f2SLinus Walleij /* Read PMIC chip revision 2 */
54140a3a0f2SLinus Walleij rc = regmap_read(regmap, REG_HWREV_2, &val);
54240a3a0f2SLinus Walleij if (rc) {
54340a3a0f2SLinus Walleij pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
54440a3a0f2SLinus Walleij REG_HWREV_2, rc);
54540a3a0f2SLinus Walleij return rc;
54640a3a0f2SLinus Walleij }
54740a3a0f2SLinus Walleij pr_info("PMIC revision 2: %02X\n", val);
54840a3a0f2SLinus Walleij
5490ed2dd03SKees Cook chip = devm_kzalloc(&pdev->dev,
5500ed2dd03SKees Cook struct_size(chip, config, data->num_irqs),
55140a3a0f2SLinus Walleij GFP_KERNEL);
55240a3a0f2SLinus Walleij if (!chip)
55340a3a0f2SLinus Walleij return -ENOMEM;
55440a3a0f2SLinus Walleij
55540a3a0f2SLinus Walleij platform_set_drvdata(pdev, chip);
55640a3a0f2SLinus Walleij chip->regmap = regmap;
5573324a7c1SBrian Masney chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
55840a3a0f2SLinus Walleij chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
5593324a7c1SBrian Masney chip->pm_irq_data = data;
56040a3a0f2SLinus Walleij spin_lock_init(&chip->pm_irq_lock);
56140a3a0f2SLinus Walleij
562953f432bSSrinivas Kandagatla chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
563953f432bSSrinivas Kandagatla data->num_irqs,
5643324a7c1SBrian Masney &pm8xxx_irq_domain_ops,
56540a3a0f2SLinus Walleij chip);
56640a3a0f2SLinus Walleij if (!chip->irqdomain)
56740a3a0f2SLinus Walleij return -ENODEV;
56840a3a0f2SLinus Walleij
569d3546ccdSDmitry Baryshkov rc = devm_request_irq(&pdev->dev, irq, data->irq_handler, 0, dev_name(&pdev->dev), chip);
570d3546ccdSDmitry Baryshkov if (rc)
571d3546ccdSDmitry Baryshkov return rc;
572d3546ccdSDmitry Baryshkov
57340a3a0f2SLinus Walleij irq_set_irq_wake(irq, 1);
57440a3a0f2SLinus Walleij
57540a3a0f2SLinus Walleij rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
576d3546ccdSDmitry Baryshkov if (rc)
57740a3a0f2SLinus Walleij irq_domain_remove(chip->irqdomain);
57840a3a0f2SLinus Walleij
57940a3a0f2SLinus Walleij return rc;
58040a3a0f2SLinus Walleij }
58140a3a0f2SLinus Walleij
pm8xxx_remove_child(struct device * dev,void * unused)58240a3a0f2SLinus Walleij static int pm8xxx_remove_child(struct device *dev, void *unused)
58340a3a0f2SLinus Walleij {
58440a3a0f2SLinus Walleij platform_device_unregister(to_platform_device(dev));
58540a3a0f2SLinus Walleij return 0;
58640a3a0f2SLinus Walleij }
58740a3a0f2SLinus Walleij
pm8xxx_remove(struct platform_device * pdev)58840a3a0f2SLinus Walleij static int pm8xxx_remove(struct platform_device *pdev)
58940a3a0f2SLinus Walleij {
59040a3a0f2SLinus Walleij struct pm_irq_chip *chip = platform_get_drvdata(pdev);
59140a3a0f2SLinus Walleij
59240a3a0f2SLinus Walleij device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
59340a3a0f2SLinus Walleij irq_domain_remove(chip->irqdomain);
59440a3a0f2SLinus Walleij
59540a3a0f2SLinus Walleij return 0;
59640a3a0f2SLinus Walleij }
59740a3a0f2SLinus Walleij
59840a3a0f2SLinus Walleij static struct platform_driver pm8xxx_driver = {
59940a3a0f2SLinus Walleij .probe = pm8xxx_probe,
60040a3a0f2SLinus Walleij .remove = pm8xxx_remove,
60140a3a0f2SLinus Walleij .driver = {
60240a3a0f2SLinus Walleij .name = "pm8xxx-core",
60340a3a0f2SLinus Walleij .of_match_table = pm8xxx_id_table,
60440a3a0f2SLinus Walleij },
60540a3a0f2SLinus Walleij };
60640a3a0f2SLinus Walleij
pm8xxx_init(void)60740a3a0f2SLinus Walleij static int __init pm8xxx_init(void)
60840a3a0f2SLinus Walleij {
60940a3a0f2SLinus Walleij return platform_driver_register(&pm8xxx_driver);
61040a3a0f2SLinus Walleij }
61140a3a0f2SLinus Walleij subsys_initcall(pm8xxx_init);
61240a3a0f2SLinus Walleij
pm8xxx_exit(void)61340a3a0f2SLinus Walleij static void __exit pm8xxx_exit(void)
61440a3a0f2SLinus Walleij {
61540a3a0f2SLinus Walleij platform_driver_unregister(&pm8xxx_driver);
61640a3a0f2SLinus Walleij }
61740a3a0f2SLinus Walleij module_exit(pm8xxx_exit);
61840a3a0f2SLinus Walleij
61940a3a0f2SLinus Walleij MODULE_LICENSE("GPL v2");
62040a3a0f2SLinus Walleij MODULE_DESCRIPTION("PMIC 8xxx core driver");
62140a3a0f2SLinus Walleij MODULE_VERSION("1.0");
62240a3a0f2SLinus Walleij MODULE_ALIAS("platform:pm8xxx-core");
623