1 /* 2 * TI Palmas MFD Driver 3 * 4 * Copyright 2011-2012 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/slab.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/irq.h> 22 #include <linux/regmap.h> 23 #include <linux/err.h> 24 #include <linux/mfd/core.h> 25 #include <linux/mfd/palmas.h> 26 #include <linux/of_device.h> 27 28 static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = { 29 { 30 .reg_bits = 8, 31 .val_bits = 8, 32 .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE, 33 PALMAS_PRIMARY_SECONDARY_PAD3), 34 }, 35 { 36 .reg_bits = 8, 37 .val_bits = 8, 38 .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE, 39 PALMAS_GPADC_SMPS_VSEL_MONITORING), 40 }, 41 { 42 .reg_bits = 8, 43 .val_bits = 8, 44 .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE, 45 PALMAS_GPADC_TRIM16), 46 }, 47 }; 48 49 static const struct regmap_irq tps65917_irqs[] = { 50 /* INT1 IRQs */ 51 [TPS65917_RESERVED1] = { 52 .mask = TPS65917_RESERVED, 53 }, 54 [TPS65917_PWRON_IRQ] = { 55 .mask = TPS65917_INT1_STATUS_PWRON, 56 }, 57 [TPS65917_LONG_PRESS_KEY_IRQ] = { 58 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY, 59 }, 60 [TPS65917_RESERVED2] = { 61 .mask = TPS65917_RESERVED, 62 }, 63 [TPS65917_PWRDOWN_IRQ] = { 64 .mask = TPS65917_INT1_STATUS_PWRDOWN, 65 }, 66 [TPS65917_HOTDIE_IRQ] = { 67 .mask = TPS65917_INT1_STATUS_HOTDIE, 68 }, 69 [TPS65917_VSYS_MON_IRQ] = { 70 .mask = TPS65917_INT1_STATUS_VSYS_MON, 71 }, 72 [TPS65917_RESERVED3] = { 73 .mask = TPS65917_RESERVED, 74 }, 75 /* INT2 IRQs*/ 76 [TPS65917_RESERVED4] = { 77 .mask = TPS65917_RESERVED, 78 .reg_offset = 1, 79 }, 80 [TPS65917_OTP_ERROR_IRQ] = { 81 .mask = TPS65917_INT2_STATUS_OTP_ERROR, 82 .reg_offset = 1, 83 }, 84 [TPS65917_WDT_IRQ] = { 85 .mask = TPS65917_INT2_STATUS_WDT, 86 .reg_offset = 1, 87 }, 88 [TPS65917_RESERVED5] = { 89 .mask = TPS65917_RESERVED, 90 .reg_offset = 1, 91 }, 92 [TPS65917_RESET_IN_IRQ] = { 93 .mask = TPS65917_INT2_STATUS_RESET_IN, 94 .reg_offset = 1, 95 }, 96 [TPS65917_FSD_IRQ] = { 97 .mask = TPS65917_INT2_STATUS_FSD, 98 .reg_offset = 1, 99 }, 100 [TPS65917_SHORT_IRQ] = { 101 .mask = TPS65917_INT2_STATUS_SHORT, 102 .reg_offset = 1, 103 }, 104 [TPS65917_RESERVED6] = { 105 .mask = TPS65917_RESERVED, 106 .reg_offset = 1, 107 }, 108 /* INT3 IRQs */ 109 [TPS65917_GPADC_AUTO_0_IRQ] = { 110 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0, 111 .reg_offset = 2, 112 }, 113 [TPS65917_GPADC_AUTO_1_IRQ] = { 114 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1, 115 .reg_offset = 2, 116 }, 117 [TPS65917_GPADC_EOC_SW_IRQ] = { 118 .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW, 119 .reg_offset = 2, 120 }, 121 [TPS65917_RESREVED6] = { 122 .mask = TPS65917_RESERVED6, 123 .reg_offset = 2, 124 }, 125 [TPS65917_RESERVED7] = { 126 .mask = TPS65917_RESERVED, 127 .reg_offset = 2, 128 }, 129 [TPS65917_RESERVED8] = { 130 .mask = TPS65917_RESERVED, 131 .reg_offset = 2, 132 }, 133 [TPS65917_RESERVED9] = { 134 .mask = TPS65917_RESERVED, 135 .reg_offset = 2, 136 }, 137 [TPS65917_VBUS_IRQ] = { 138 .mask = TPS65917_INT3_STATUS_VBUS, 139 .reg_offset = 2, 140 }, 141 /* INT4 IRQs */ 142 [TPS65917_GPIO_0_IRQ] = { 143 .mask = TPS65917_INT4_STATUS_GPIO_0, 144 .reg_offset = 3, 145 }, 146 [TPS65917_GPIO_1_IRQ] = { 147 .mask = TPS65917_INT4_STATUS_GPIO_1, 148 .reg_offset = 3, 149 }, 150 [TPS65917_GPIO_2_IRQ] = { 151 .mask = TPS65917_INT4_STATUS_GPIO_2, 152 .reg_offset = 3, 153 }, 154 [TPS65917_GPIO_3_IRQ] = { 155 .mask = TPS65917_INT4_STATUS_GPIO_3, 156 .reg_offset = 3, 157 }, 158 [TPS65917_GPIO_4_IRQ] = { 159 .mask = TPS65917_INT4_STATUS_GPIO_4, 160 .reg_offset = 3, 161 }, 162 [TPS65917_GPIO_5_IRQ] = { 163 .mask = TPS65917_INT4_STATUS_GPIO_5, 164 .reg_offset = 3, 165 }, 166 [TPS65917_GPIO_6_IRQ] = { 167 .mask = TPS65917_INT4_STATUS_GPIO_6, 168 .reg_offset = 3, 169 }, 170 [TPS65917_RESERVED10] = { 171 .mask = TPS65917_RESERVED10, 172 .reg_offset = 3, 173 }, 174 }; 175 176 static const struct regmap_irq palmas_irqs[] = { 177 /* INT1 IRQs */ 178 [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = { 179 .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV, 180 }, 181 [PALMAS_PWRON_IRQ] = { 182 .mask = PALMAS_INT1_STATUS_PWRON, 183 }, 184 [PALMAS_LONG_PRESS_KEY_IRQ] = { 185 .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY, 186 }, 187 [PALMAS_RPWRON_IRQ] = { 188 .mask = PALMAS_INT1_STATUS_RPWRON, 189 }, 190 [PALMAS_PWRDOWN_IRQ] = { 191 .mask = PALMAS_INT1_STATUS_PWRDOWN, 192 }, 193 [PALMAS_HOTDIE_IRQ] = { 194 .mask = PALMAS_INT1_STATUS_HOTDIE, 195 }, 196 [PALMAS_VSYS_MON_IRQ] = { 197 .mask = PALMAS_INT1_STATUS_VSYS_MON, 198 }, 199 [PALMAS_VBAT_MON_IRQ] = { 200 .mask = PALMAS_INT1_STATUS_VBAT_MON, 201 }, 202 /* INT2 IRQs*/ 203 [PALMAS_RTC_ALARM_IRQ] = { 204 .mask = PALMAS_INT2_STATUS_RTC_ALARM, 205 .reg_offset = 1, 206 }, 207 [PALMAS_RTC_TIMER_IRQ] = { 208 .mask = PALMAS_INT2_STATUS_RTC_TIMER, 209 .reg_offset = 1, 210 }, 211 [PALMAS_WDT_IRQ] = { 212 .mask = PALMAS_INT2_STATUS_WDT, 213 .reg_offset = 1, 214 }, 215 [PALMAS_BATREMOVAL_IRQ] = { 216 .mask = PALMAS_INT2_STATUS_BATREMOVAL, 217 .reg_offset = 1, 218 }, 219 [PALMAS_RESET_IN_IRQ] = { 220 .mask = PALMAS_INT2_STATUS_RESET_IN, 221 .reg_offset = 1, 222 }, 223 [PALMAS_FBI_BB_IRQ] = { 224 .mask = PALMAS_INT2_STATUS_FBI_BB, 225 .reg_offset = 1, 226 }, 227 [PALMAS_SHORT_IRQ] = { 228 .mask = PALMAS_INT2_STATUS_SHORT, 229 .reg_offset = 1, 230 }, 231 [PALMAS_VAC_ACOK_IRQ] = { 232 .mask = PALMAS_INT2_STATUS_VAC_ACOK, 233 .reg_offset = 1, 234 }, 235 /* INT3 IRQs */ 236 [PALMAS_GPADC_AUTO_0_IRQ] = { 237 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0, 238 .reg_offset = 2, 239 }, 240 [PALMAS_GPADC_AUTO_1_IRQ] = { 241 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1, 242 .reg_offset = 2, 243 }, 244 [PALMAS_GPADC_EOC_SW_IRQ] = { 245 .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW, 246 .reg_offset = 2, 247 }, 248 [PALMAS_GPADC_EOC_RT_IRQ] = { 249 .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT, 250 .reg_offset = 2, 251 }, 252 [PALMAS_ID_OTG_IRQ] = { 253 .mask = PALMAS_INT3_STATUS_ID_OTG, 254 .reg_offset = 2, 255 }, 256 [PALMAS_ID_IRQ] = { 257 .mask = PALMAS_INT3_STATUS_ID, 258 .reg_offset = 2, 259 }, 260 [PALMAS_VBUS_OTG_IRQ] = { 261 .mask = PALMAS_INT3_STATUS_VBUS_OTG, 262 .reg_offset = 2, 263 }, 264 [PALMAS_VBUS_IRQ] = { 265 .mask = PALMAS_INT3_STATUS_VBUS, 266 .reg_offset = 2, 267 }, 268 /* INT4 IRQs */ 269 [PALMAS_GPIO_0_IRQ] = { 270 .mask = PALMAS_INT4_STATUS_GPIO_0, 271 .reg_offset = 3, 272 }, 273 [PALMAS_GPIO_1_IRQ] = { 274 .mask = PALMAS_INT4_STATUS_GPIO_1, 275 .reg_offset = 3, 276 }, 277 [PALMAS_GPIO_2_IRQ] = { 278 .mask = PALMAS_INT4_STATUS_GPIO_2, 279 .reg_offset = 3, 280 }, 281 [PALMAS_GPIO_3_IRQ] = { 282 .mask = PALMAS_INT4_STATUS_GPIO_3, 283 .reg_offset = 3, 284 }, 285 [PALMAS_GPIO_4_IRQ] = { 286 .mask = PALMAS_INT4_STATUS_GPIO_4, 287 .reg_offset = 3, 288 }, 289 [PALMAS_GPIO_5_IRQ] = { 290 .mask = PALMAS_INT4_STATUS_GPIO_5, 291 .reg_offset = 3, 292 }, 293 [PALMAS_GPIO_6_IRQ] = { 294 .mask = PALMAS_INT4_STATUS_GPIO_6, 295 .reg_offset = 3, 296 }, 297 [PALMAS_GPIO_7_IRQ] = { 298 .mask = PALMAS_INT4_STATUS_GPIO_7, 299 .reg_offset = 3, 300 }, 301 }; 302 303 static struct regmap_irq_chip palmas_irq_chip = { 304 .name = "palmas", 305 .irqs = palmas_irqs, 306 .num_irqs = ARRAY_SIZE(palmas_irqs), 307 308 .num_regs = 4, 309 .irq_reg_stride = 5, 310 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, 311 PALMAS_INT1_STATUS), 312 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, 313 PALMAS_INT1_MASK), 314 }; 315 316 static struct regmap_irq_chip tps65917_irq_chip = { 317 .name = "tps65917", 318 .irqs = tps65917_irqs, 319 .num_irqs = ARRAY_SIZE(tps65917_irqs), 320 321 .num_regs = 4, 322 .irq_reg_stride = 5, 323 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, 324 PALMAS_INT1_STATUS), 325 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, 326 PALMAS_INT1_MASK), 327 }; 328 329 int palmas_ext_control_req_config(struct palmas *palmas, 330 enum palmas_external_requestor_id id, int ext_ctrl, bool enable) 331 { 332 struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata; 333 int preq_mask_bit = 0; 334 int reg_add = 0; 335 int bit_pos, ret; 336 337 if (!(ext_ctrl & PALMAS_EXT_REQ)) 338 return 0; 339 340 if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX) 341 return 0; 342 343 if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) { 344 reg_add = PALMAS_NSLEEP_RES_ASSIGN; 345 preq_mask_bit = 0; 346 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) { 347 reg_add = PALMAS_ENABLE1_RES_ASSIGN; 348 preq_mask_bit = 1; 349 } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) { 350 reg_add = PALMAS_ENABLE2_RES_ASSIGN; 351 preq_mask_bit = 2; 352 } 353 354 bit_pos = pmic_ddata->sleep_req_info[id].bit_pos; 355 reg_add += pmic_ddata->sleep_req_info[id].reg_offset; 356 if (enable) 357 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, 358 reg_add, BIT(bit_pos), BIT(bit_pos)); 359 else 360 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, 361 reg_add, BIT(bit_pos), 0); 362 if (ret < 0) { 363 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n", 364 reg_add, ret); 365 return ret; 366 } 367 368 /* Unmask the PREQ */ 369 ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE, 370 PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0); 371 if (ret < 0) { 372 dev_err(palmas->dev, "POWER_CTRL register update failed %d\n", 373 ret); 374 return ret; 375 } 376 return ret; 377 } 378 EXPORT_SYMBOL_GPL(palmas_ext_control_req_config); 379 380 static int palmas_set_pdata_irq_flag(struct i2c_client *i2c, 381 struct palmas_platform_data *pdata) 382 { 383 struct irq_data *irq_data = irq_get_irq_data(i2c->irq); 384 if (!irq_data) { 385 dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq); 386 return -EINVAL; 387 } 388 389 pdata->irq_flags = irqd_get_trigger_type(irq_data); 390 dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags); 391 return 0; 392 } 393 394 static void palmas_dt_to_pdata(struct i2c_client *i2c, 395 struct palmas_platform_data *pdata) 396 { 397 struct device_node *node = i2c->dev.of_node; 398 int ret; 399 u32 prop; 400 401 ret = of_property_read_u32(node, "ti,mux-pad1", &prop); 402 if (!ret) { 403 pdata->mux_from_pdata = 1; 404 pdata->pad1 = prop; 405 } 406 407 ret = of_property_read_u32(node, "ti,mux-pad2", &prop); 408 if (!ret) { 409 pdata->mux_from_pdata = 1; 410 pdata->pad2 = prop; 411 } 412 413 /* The default for this register is all masked */ 414 ret = of_property_read_u32(node, "ti,power-ctrl", &prop); 415 if (!ret) 416 pdata->power_ctrl = prop; 417 else 418 pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK | 419 PALMAS_POWER_CTRL_ENABLE1_MASK | 420 PALMAS_POWER_CTRL_ENABLE2_MASK; 421 if (i2c->irq) 422 palmas_set_pdata_irq_flag(i2c, pdata); 423 424 pdata->pm_off = of_property_read_bool(node, 425 "ti,system-power-controller"); 426 } 427 428 static struct palmas *palmas_dev; 429 static void palmas_power_off(void) 430 { 431 unsigned int addr; 432 int ret, slave; 433 434 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE); 435 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL); 436 437 ret = regmap_update_bits( 438 palmas_dev->regmap[slave], 439 addr, 440 PALMAS_DEV_CTRL_DEV_ON, 441 0); 442 443 if (ret) 444 pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n", 445 __func__, ret); 446 } 447 448 static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST; 449 static unsigned int tps659038_features; 450 451 struct palmas_driver_data { 452 unsigned int *features; 453 struct regmap_irq_chip *irq_chip; 454 }; 455 456 static struct palmas_driver_data palmas_data = { 457 .features = &palmas_features, 458 .irq_chip = &palmas_irq_chip, 459 }; 460 461 static struct palmas_driver_data tps659038_data = { 462 .features = &tps659038_features, 463 .irq_chip = &palmas_irq_chip, 464 }; 465 466 static struct palmas_driver_data tps65917_data = { 467 .features = &tps659038_features, 468 .irq_chip = &tps65917_irq_chip, 469 }; 470 471 static const struct of_device_id of_palmas_match_tbl[] = { 472 { 473 .compatible = "ti,palmas", 474 .data = &palmas_data, 475 }, 476 { 477 .compatible = "ti,tps659038", 478 .data = &tps659038_data, 479 }, 480 { 481 .compatible = "ti,tps65917", 482 .data = &tps65917_data, 483 }, 484 { }, 485 }; 486 MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); 487 488 static int palmas_i2c_probe(struct i2c_client *i2c, 489 const struct i2c_device_id *id) 490 { 491 struct palmas *palmas; 492 struct palmas_platform_data *pdata; 493 struct palmas_driver_data *driver_data; 494 struct device_node *node = i2c->dev.of_node; 495 int ret = 0, i; 496 unsigned int reg, addr; 497 int slave; 498 const struct of_device_id *match; 499 500 pdata = dev_get_platdata(&i2c->dev); 501 502 if (node && !pdata) { 503 pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL); 504 505 if (!pdata) 506 return -ENOMEM; 507 508 palmas_dt_to_pdata(i2c, pdata); 509 } 510 511 if (!pdata) 512 return -EINVAL; 513 514 palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL); 515 if (palmas == NULL) 516 return -ENOMEM; 517 518 i2c_set_clientdata(i2c, palmas); 519 palmas->dev = &i2c->dev; 520 palmas->irq = i2c->irq; 521 522 match = of_match_device(of_palmas_match_tbl, &i2c->dev); 523 524 if (!match) 525 return -ENODATA; 526 527 driver_data = (struct palmas_driver_data *)match->data; 528 palmas->features = *driver_data->features; 529 530 for (i = 0; i < PALMAS_NUM_CLIENTS; i++) { 531 if (i == 0) 532 palmas->i2c_clients[i] = i2c; 533 else { 534 palmas->i2c_clients[i] = 535 i2c_new_dummy(i2c->adapter, 536 i2c->addr + i); 537 if (!palmas->i2c_clients[i]) { 538 dev_err(palmas->dev, 539 "can't attach client %d\n", i); 540 ret = -ENOMEM; 541 goto err_i2c; 542 } 543 palmas->i2c_clients[i]->dev.of_node = of_node_get(node); 544 } 545 palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i], 546 &palmas_regmap_config[i]); 547 if (IS_ERR(palmas->regmap[i])) { 548 ret = PTR_ERR(palmas->regmap[i]); 549 dev_err(palmas->dev, 550 "Failed to allocate regmap %d, err: %d\n", 551 i, ret); 552 goto err_i2c; 553 } 554 } 555 556 if (!palmas->irq) { 557 dev_warn(palmas->dev, "IRQ missing: skipping irq request\n"); 558 goto no_irq; 559 } 560 561 /* Change interrupt line output polarity */ 562 if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH) 563 reg = PALMAS_POLARITY_CTRL_INT_POLARITY; 564 else 565 reg = 0; 566 ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE, 567 PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY, 568 reg); 569 if (ret < 0) { 570 dev_err(palmas->dev, "POLARITY_CTRL updat failed: %d\n", ret); 571 goto err_i2c; 572 } 573 574 /* Change IRQ into clear on read mode for efficiency */ 575 slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE); 576 addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL); 577 reg = PALMAS_INT_CTRL_INT_CLEAR; 578 579 regmap_write(palmas->regmap[slave], addr, reg); 580 581 ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq, 582 IRQF_ONESHOT | pdata->irq_flags, 0, 583 driver_data->irq_chip, &palmas->irq_data); 584 if (ret < 0) 585 goto err_i2c; 586 587 no_irq: 588 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE); 589 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE, 590 PALMAS_PRIMARY_SECONDARY_PAD1); 591 592 if (pdata->mux_from_pdata) { 593 reg = pdata->pad1; 594 ret = regmap_write(palmas->regmap[slave], addr, reg); 595 if (ret) 596 goto err_irq; 597 } else { 598 ret = regmap_read(palmas->regmap[slave], addr, ®); 599 if (ret) 600 goto err_irq; 601 } 602 603 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0)) 604 palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED; 605 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK)) 606 palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED; 607 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) == 608 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT)) 609 palmas->led_muxed |= PALMAS_LED1_MUXED; 610 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) == 611 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT)) 612 palmas->pwm_muxed |= PALMAS_PWM1_MUXED; 613 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK)) 614 palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED; 615 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) == 616 (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT)) 617 palmas->led_muxed |= PALMAS_LED2_MUXED; 618 else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) == 619 (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT)) 620 palmas->pwm_muxed |= PALMAS_PWM2_MUXED; 621 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3)) 622 palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED; 623 624 addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE, 625 PALMAS_PRIMARY_SECONDARY_PAD2); 626 627 if (pdata->mux_from_pdata) { 628 reg = pdata->pad2; 629 ret = regmap_write(palmas->regmap[slave], addr, reg); 630 if (ret) 631 goto err_irq; 632 } else { 633 ret = regmap_read(palmas->regmap[slave], addr, ®); 634 if (ret) 635 goto err_irq; 636 } 637 638 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4)) 639 palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED; 640 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK)) 641 palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED; 642 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6)) 643 palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED; 644 if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK)) 645 palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED; 646 647 dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n", 648 palmas->gpio_muxed, palmas->pwm_muxed, 649 palmas->led_muxed); 650 651 reg = pdata->power_ctrl; 652 653 slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE); 654 addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL); 655 656 ret = regmap_write(palmas->regmap[slave], addr, reg); 657 if (ret) 658 goto err_irq; 659 660 /* 661 * If we are probing with DT do this the DT way and return here 662 * otherwise continue and add devices using mfd helpers. 663 */ 664 if (node) { 665 ret = of_platform_populate(node, NULL, NULL, &i2c->dev); 666 if (ret < 0) { 667 goto err_irq; 668 } else if (pdata->pm_off && !pm_power_off) { 669 palmas_dev = palmas; 670 pm_power_off = palmas_power_off; 671 } 672 } 673 674 return ret; 675 676 err_irq: 677 regmap_del_irq_chip(palmas->irq, palmas->irq_data); 678 err_i2c: 679 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) { 680 if (palmas->i2c_clients[i]) 681 i2c_unregister_device(palmas->i2c_clients[i]); 682 } 683 return ret; 684 } 685 686 static int palmas_i2c_remove(struct i2c_client *i2c) 687 { 688 struct palmas *palmas = i2c_get_clientdata(i2c); 689 int i; 690 691 regmap_del_irq_chip(palmas->irq, palmas->irq_data); 692 693 for (i = 1; i < PALMAS_NUM_CLIENTS; i++) { 694 if (palmas->i2c_clients[i]) 695 i2c_unregister_device(palmas->i2c_clients[i]); 696 } 697 698 if (palmas == palmas_dev) { 699 pm_power_off = NULL; 700 palmas_dev = NULL; 701 } 702 703 return 0; 704 } 705 706 static const struct i2c_device_id palmas_i2c_id[] = { 707 { "palmas", }, 708 { "twl6035", }, 709 { "twl6037", }, 710 { "tps65913", }, 711 { /* end */ } 712 }; 713 MODULE_DEVICE_TABLE(i2c, palmas_i2c_id); 714 715 static struct i2c_driver palmas_i2c_driver = { 716 .driver = { 717 .name = "palmas", 718 .of_match_table = of_palmas_match_tbl, 719 }, 720 .probe = palmas_i2c_probe, 721 .remove = palmas_i2c_remove, 722 .id_table = palmas_i2c_id, 723 }; 724 725 static int __init palmas_i2c_init(void) 726 { 727 return i2c_add_driver(&palmas_i2c_driver); 728 } 729 /* init early so consumer devices can complete system boot */ 730 subsys_initcall(palmas_i2c_init); 731 732 static void __exit palmas_i2c_exit(void) 733 { 734 i2c_del_driver(&palmas_i2c_driver); 735 } 736 module_exit(palmas_i2c_exit); 737 738 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); 739 MODULE_DESCRIPTION("Palmas chip family multi-function driver"); 740 MODULE_LICENSE("GPL"); 741