1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap-usb-tll.c - The USB TLL driver for OMAP EHCI & OHCI 4 * 5 * Copyright (C) 2012-2013 Texas Instruments Incorporated - https://www.ti.com 6 * Author: Keshava Munegowda <keshava_mgowda@ti.com> 7 * Author: Roger Quadros <rogerq@ti.com> 8 */ 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/types.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/platform_device.h> 15 #include <linux/clk.h> 16 #include <linux/io.h> 17 #include <linux/err.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/platform_data/usb-omap.h> 20 #include <linux/of.h> 21 22 #include "omap-usb.h" 23 24 #define USBTLL_DRIVER_NAME "usbhs_tll" 25 26 /* TLL Register Set */ 27 #define OMAP_USBTLL_REVISION (0x00) 28 #define OMAP_USBTLL_SYSCONFIG (0x10) 29 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) 30 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) 31 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) 32 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) 33 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) 34 35 #define OMAP_USBTLL_SYSSTATUS (0x14) 36 #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) 37 38 #define OMAP_USBTLL_IRQSTATUS (0x18) 39 #define OMAP_USBTLL_IRQENABLE (0x1C) 40 41 #define OMAP_TLL_SHARED_CONF (0x30) 42 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) 43 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) 44 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) 45 #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) 46 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) 47 48 #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) 49 #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 50 #define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16) 51 #define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15) 52 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) 53 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) 54 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) 55 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) 56 #define OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI (2 << 1) 57 #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1) 58 #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) 59 60 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0 61 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1 62 #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2 63 #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3 64 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4 65 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5 66 #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6 67 #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7 68 #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA 69 #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB 70 71 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) 72 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) 73 #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) 74 #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) 75 #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) 76 #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) 77 #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) 78 #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) 79 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) 80 81 #define OMAP_REV2_TLL_CHANNEL_COUNT 2 82 #define OMAP_TLL_CHANNEL_COUNT 3 83 #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0) 84 #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1) 85 #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2) 86 87 /* Values of USBTLL_REVISION - Note: these are not given in the TRM */ 88 #define OMAP_USBTLL_REV1 0x00000015 /* OMAP3 */ 89 #define OMAP_USBTLL_REV2 0x00000018 /* OMAP 3630 */ 90 #define OMAP_USBTLL_REV3 0x00000004 /* OMAP4 */ 91 #define OMAP_USBTLL_REV4 0x00000006 /* OMAP5 */ 92 93 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL) 94 95 /* only PHY and UNUSED modes don't need TLL */ 96 #define omap_usb_mode_needs_tll(x) ((x) != OMAP_USBHS_PORT_MODE_UNUSED &&\ 97 (x) != OMAP_EHCI_PORT_MODE_PHY) 98 99 struct usbtll_omap { 100 void __iomem *base; 101 int nch; /* num. of channels */ 102 struct clk *ch_clk[]; /* must be the last member */ 103 }; 104 105 /*-------------------------------------------------------------------------*/ 106 107 static const char usbtll_driver_name[] = USBTLL_DRIVER_NAME; 108 static struct device *tll_dev; 109 static DEFINE_SPINLOCK(tll_lock); /* serialize access to tll_dev */ 110 111 /*-------------------------------------------------------------------------*/ 112 113 static inline void usbtll_write(void __iomem *base, u32 reg, u32 val) 114 { 115 writel_relaxed(val, base + reg); 116 } 117 118 static inline u32 usbtll_read(void __iomem *base, u32 reg) 119 { 120 return readl_relaxed(base + reg); 121 } 122 123 static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val) 124 { 125 writeb_relaxed(val, base + reg); 126 } 127 128 /*-------------------------------------------------------------------------*/ 129 130 static bool is_ohci_port(enum usbhs_omap_port_mode pmode) 131 { 132 switch (pmode) { 133 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: 134 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: 135 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: 136 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: 137 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: 138 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: 139 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: 140 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: 141 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: 142 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: 143 return true; 144 145 default: 146 return false; 147 } 148 } 149 150 /* 151 * convert the port-mode enum to a value we can use in the FSLSMODE 152 * field of USBTLL_CHANNEL_CONF 153 */ 154 static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode) 155 { 156 switch (mode) { 157 case OMAP_USBHS_PORT_MODE_UNUSED: 158 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: 159 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; 160 161 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: 162 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM; 163 164 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: 165 return OMAP_TLL_FSLSMODE_3PIN_PHY; 166 167 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: 168 return OMAP_TLL_FSLSMODE_4PIN_PHY; 169 170 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: 171 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0; 172 173 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: 174 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM; 175 176 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: 177 return OMAP_TLL_FSLSMODE_3PIN_TLL; 178 179 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: 180 return OMAP_TLL_FSLSMODE_4PIN_TLL; 181 182 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: 183 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0; 184 185 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: 186 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM; 187 default: 188 pr_warn("Invalid port mode, using default\n"); 189 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; 190 } 191 } 192 193 /** 194 * usbtll_omap_probe - initialize TI-based HCDs 195 * 196 * Allocates basic resources for this USB host controller. 197 * 198 * @pdev: Pointer to this device's platform device structure 199 */ 200 static int usbtll_omap_probe(struct platform_device *pdev) 201 { 202 struct device *dev = &pdev->dev; 203 struct usbtll_omap *tll; 204 void __iomem *base; 205 int i, nch, ver; 206 207 dev_dbg(dev, "starting TI HSUSB TLL Controller\n"); 208 209 base = devm_platform_ioremap_resource(pdev, 0); 210 if (IS_ERR(base)) 211 return PTR_ERR(base); 212 213 pm_runtime_enable(dev); 214 pm_runtime_get_sync(dev); 215 216 ver = usbtll_read(base, OMAP_USBTLL_REVISION); 217 switch (ver) { 218 case OMAP_USBTLL_REV1: 219 case OMAP_USBTLL_REV4: 220 nch = OMAP_TLL_CHANNEL_COUNT; 221 break; 222 case OMAP_USBTLL_REV2: 223 case OMAP_USBTLL_REV3: 224 nch = OMAP_REV2_TLL_CHANNEL_COUNT; 225 break; 226 default: 227 nch = OMAP_TLL_CHANNEL_COUNT; 228 dev_dbg(dev, "rev 0x%x not recognized, assuming %d channels\n", 229 ver, nch); 230 break; 231 } 232 233 tll = devm_kzalloc(dev, struct_size(tll, ch_clk, nch), GFP_KERNEL); 234 if (!tll) { 235 pm_runtime_put_sync(dev); 236 pm_runtime_disable(dev); 237 return -ENOMEM; 238 } 239 240 tll->base = base; 241 tll->nch = nch; 242 platform_set_drvdata(pdev, tll); 243 244 for (i = 0; i < nch; i++) { 245 char clkname[] = "usb_tll_hs_usb_chx_clk"; 246 247 snprintf(clkname, sizeof(clkname), 248 "usb_tll_hs_usb_ch%d_clk", i); 249 tll->ch_clk[i] = clk_get(dev, clkname); 250 251 if (IS_ERR(tll->ch_clk[i])) 252 dev_dbg(dev, "can't get clock : %s\n", clkname); 253 else 254 clk_prepare(tll->ch_clk[i]); 255 } 256 257 pm_runtime_put_sync(dev); 258 /* only after this can omap_tll_enable/disable work */ 259 spin_lock(&tll_lock); 260 tll_dev = dev; 261 spin_unlock(&tll_lock); 262 263 return 0; 264 } 265 266 /** 267 * usbtll_omap_remove - shutdown processing for UHH & TLL HCDs 268 * @pdev: USB Host Controller being removed 269 * 270 * Reverses the effect of usbtll_omap_probe(). 271 */ 272 static int usbtll_omap_remove(struct platform_device *pdev) 273 { 274 struct usbtll_omap *tll = platform_get_drvdata(pdev); 275 int i; 276 277 spin_lock(&tll_lock); 278 tll_dev = NULL; 279 spin_unlock(&tll_lock); 280 281 for (i = 0; i < tll->nch; i++) { 282 if (!IS_ERR(tll->ch_clk[i])) { 283 clk_unprepare(tll->ch_clk[i]); 284 clk_put(tll->ch_clk[i]); 285 } 286 } 287 288 pm_runtime_disable(&pdev->dev); 289 return 0; 290 } 291 292 static const struct of_device_id usbtll_omap_dt_ids[] = { 293 { .compatible = "ti,usbhs-tll" }, 294 { } 295 }; 296 297 MODULE_DEVICE_TABLE(of, usbtll_omap_dt_ids); 298 299 static struct platform_driver usbtll_omap_driver = { 300 .driver = { 301 .name = usbtll_driver_name, 302 .of_match_table = usbtll_omap_dt_ids, 303 }, 304 .probe = usbtll_omap_probe, 305 .remove = usbtll_omap_remove, 306 }; 307 308 int omap_tll_init(struct usbhs_omap_platform_data *pdata) 309 { 310 int i; 311 bool needs_tll; 312 unsigned reg; 313 struct usbtll_omap *tll; 314 315 if (!tll_dev) 316 return -ENODEV; 317 318 pm_runtime_get_sync(tll_dev); 319 320 spin_lock(&tll_lock); 321 tll = dev_get_drvdata(tll_dev); 322 needs_tll = false; 323 for (i = 0; i < tll->nch; i++) 324 needs_tll |= omap_usb_mode_needs_tll(pdata->port_mode[i]); 325 326 if (needs_tll) { 327 void __iomem *base = tll->base; 328 329 /* Program Common TLL register */ 330 reg = usbtll_read(base, OMAP_TLL_SHARED_CONF); 331 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON 332 | OMAP_TLL_SHARED_CONF_USB_DIVRATION); 333 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; 334 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; 335 336 usbtll_write(base, OMAP_TLL_SHARED_CONF, reg); 337 338 /* Enable channels now */ 339 for (i = 0; i < tll->nch; i++) { 340 reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i)); 341 342 if (is_ohci_port(pdata->port_mode[i])) { 343 reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) 344 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; 345 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; 346 } else if (pdata->port_mode[i] == 347 OMAP_EHCI_PORT_MODE_TLL) { 348 /* 349 * Disable UTMI AutoIdle, BitStuffing 350 * and use SDR Mode. Enable ULPI AutoIdle. 351 */ 352 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE 353 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); 354 reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF; 355 reg |= OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE; 356 } else if (pdata->port_mode[i] == 357 OMAP_EHCI_PORT_MODE_HSIC) { 358 /* 359 * HSIC Mode requires UTMI port configurations 360 */ 361 reg |= OMAP_TLL_CHANNEL_CONF_DRVVBUS 362 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS 363 | OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI 364 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF; 365 } else { 366 continue; 367 } 368 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; 369 usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg); 370 371 usbtll_writeb(base, 372 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 373 0xbe); 374 } 375 } 376 377 spin_unlock(&tll_lock); 378 pm_runtime_put_sync(tll_dev); 379 380 return 0; 381 } 382 EXPORT_SYMBOL_GPL(omap_tll_init); 383 384 int omap_tll_enable(struct usbhs_omap_platform_data *pdata) 385 { 386 int i; 387 struct usbtll_omap *tll; 388 389 if (!tll_dev) 390 return -ENODEV; 391 392 pm_runtime_get_sync(tll_dev); 393 394 spin_lock(&tll_lock); 395 tll = dev_get_drvdata(tll_dev); 396 397 for (i = 0; i < tll->nch; i++) { 398 if (omap_usb_mode_needs_tll(pdata->port_mode[i])) { 399 int r; 400 401 if (IS_ERR(tll->ch_clk[i])) 402 continue; 403 404 r = clk_enable(tll->ch_clk[i]); 405 if (r) { 406 dev_err(tll_dev, 407 "Error enabling ch %d clock: %d\n", i, r); 408 } 409 } 410 } 411 412 spin_unlock(&tll_lock); 413 414 return 0; 415 } 416 EXPORT_SYMBOL_GPL(omap_tll_enable); 417 418 int omap_tll_disable(struct usbhs_omap_platform_data *pdata) 419 { 420 int i; 421 struct usbtll_omap *tll; 422 423 if (!tll_dev) 424 return -ENODEV; 425 426 spin_lock(&tll_lock); 427 tll = dev_get_drvdata(tll_dev); 428 429 for (i = 0; i < tll->nch; i++) { 430 if (omap_usb_mode_needs_tll(pdata->port_mode[i])) { 431 if (!IS_ERR(tll->ch_clk[i])) 432 clk_disable(tll->ch_clk[i]); 433 } 434 } 435 436 spin_unlock(&tll_lock); 437 pm_runtime_put_sync(tll_dev); 438 439 return 0; 440 } 441 EXPORT_SYMBOL_GPL(omap_tll_disable); 442 443 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>"); 444 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); 445 MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers"); 446 447 static int __init omap_usbtll_drvinit(void) 448 { 449 return platform_driver_register(&usbtll_omap_driver); 450 } 451 452 /* 453 * init before usbhs core driver; 454 * The usbtll driver should be initialized before 455 * the usbhs core driver probe function is called. 456 */ 457 fs_initcall(omap_usbtll_drvinit); 458 459 static void __exit omap_usbtll_drvexit(void) 460 { 461 platform_driver_unregister(&usbtll_omap_driver); 462 } 463 module_exit(omap_usbtll_drvexit); 464