xref: /openbmc/linux/drivers/mfd/mt6397-irq.c (revision a4872e80)
1a4872e80SHsin-Hsiung Wang // SPDX-License-Identifier: GPL-2.0
2a4872e80SHsin-Hsiung Wang //
3a4872e80SHsin-Hsiung Wang // Copyright (c) 2019 MediaTek Inc.
4a4872e80SHsin-Hsiung Wang 
5a4872e80SHsin-Hsiung Wang #include <linux/interrupt.h>
6a4872e80SHsin-Hsiung Wang #include <linux/module.h>
7a4872e80SHsin-Hsiung Wang #include <linux/of.h>
8a4872e80SHsin-Hsiung Wang #include <linux/of_device.h>
9a4872e80SHsin-Hsiung Wang #include <linux/of_irq.h>
10a4872e80SHsin-Hsiung Wang #include <linux/platform_device.h>
11a4872e80SHsin-Hsiung Wang #include <linux/regmap.h>
12a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6323/core.h>
13a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6323/registers.h>
14a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6397/core.h>
15a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6397/registers.h>
16a4872e80SHsin-Hsiung Wang 
17a4872e80SHsin-Hsiung Wang static void mt6397_irq_lock(struct irq_data *data)
18a4872e80SHsin-Hsiung Wang {
19a4872e80SHsin-Hsiung Wang 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
20a4872e80SHsin-Hsiung Wang 
21a4872e80SHsin-Hsiung Wang 	mutex_lock(&mt6397->irqlock);
22a4872e80SHsin-Hsiung Wang }
23a4872e80SHsin-Hsiung Wang 
24a4872e80SHsin-Hsiung Wang static void mt6397_irq_sync_unlock(struct irq_data *data)
25a4872e80SHsin-Hsiung Wang {
26a4872e80SHsin-Hsiung Wang 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
27a4872e80SHsin-Hsiung Wang 
28a4872e80SHsin-Hsiung Wang 	regmap_write(mt6397->regmap, mt6397->int_con[0],
29a4872e80SHsin-Hsiung Wang 		     mt6397->irq_masks_cur[0]);
30a4872e80SHsin-Hsiung Wang 	regmap_write(mt6397->regmap, mt6397->int_con[1],
31a4872e80SHsin-Hsiung Wang 		     mt6397->irq_masks_cur[1]);
32a4872e80SHsin-Hsiung Wang 
33a4872e80SHsin-Hsiung Wang 	mutex_unlock(&mt6397->irqlock);
34a4872e80SHsin-Hsiung Wang }
35a4872e80SHsin-Hsiung Wang 
36a4872e80SHsin-Hsiung Wang static void mt6397_irq_disable(struct irq_data *data)
37a4872e80SHsin-Hsiung Wang {
38a4872e80SHsin-Hsiung Wang 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
39a4872e80SHsin-Hsiung Wang 	int shift = data->hwirq & 0xf;
40a4872e80SHsin-Hsiung Wang 	int reg = data->hwirq >> 4;
41a4872e80SHsin-Hsiung Wang 
42a4872e80SHsin-Hsiung Wang 	mt6397->irq_masks_cur[reg] &= ~BIT(shift);
43a4872e80SHsin-Hsiung Wang }
44a4872e80SHsin-Hsiung Wang 
45a4872e80SHsin-Hsiung Wang static void mt6397_irq_enable(struct irq_data *data)
46a4872e80SHsin-Hsiung Wang {
47a4872e80SHsin-Hsiung Wang 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
48a4872e80SHsin-Hsiung Wang 	int shift = data->hwirq & 0xf;
49a4872e80SHsin-Hsiung Wang 	int reg = data->hwirq >> 4;
50a4872e80SHsin-Hsiung Wang 
51a4872e80SHsin-Hsiung Wang 	mt6397->irq_masks_cur[reg] |= BIT(shift);
52a4872e80SHsin-Hsiung Wang }
53a4872e80SHsin-Hsiung Wang 
54a4872e80SHsin-Hsiung Wang #ifdef CONFIG_PM_SLEEP
55a4872e80SHsin-Hsiung Wang static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
56a4872e80SHsin-Hsiung Wang {
57a4872e80SHsin-Hsiung Wang 	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
58a4872e80SHsin-Hsiung Wang 	int shift = irq_data->hwirq & 0xf;
59a4872e80SHsin-Hsiung Wang 	int reg = irq_data->hwirq >> 4;
60a4872e80SHsin-Hsiung Wang 
61a4872e80SHsin-Hsiung Wang 	if (on)
62a4872e80SHsin-Hsiung Wang 		mt6397->wake_mask[reg] |= BIT(shift);
63a4872e80SHsin-Hsiung Wang 	else
64a4872e80SHsin-Hsiung Wang 		mt6397->wake_mask[reg] &= ~BIT(shift);
65a4872e80SHsin-Hsiung Wang 
66a4872e80SHsin-Hsiung Wang 	return 0;
67a4872e80SHsin-Hsiung Wang }
68a4872e80SHsin-Hsiung Wang #else
69a4872e80SHsin-Hsiung Wang #define mt6397_irq_set_wake NULL
70a4872e80SHsin-Hsiung Wang #endif
71a4872e80SHsin-Hsiung Wang 
72a4872e80SHsin-Hsiung Wang static struct irq_chip mt6397_irq_chip = {
73a4872e80SHsin-Hsiung Wang 	.name = "mt6397-irq",
74a4872e80SHsin-Hsiung Wang 	.irq_bus_lock = mt6397_irq_lock,
75a4872e80SHsin-Hsiung Wang 	.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
76a4872e80SHsin-Hsiung Wang 	.irq_enable = mt6397_irq_enable,
77a4872e80SHsin-Hsiung Wang 	.irq_disable = mt6397_irq_disable,
78a4872e80SHsin-Hsiung Wang 	.irq_set_wake = mt6397_irq_set_wake,
79a4872e80SHsin-Hsiung Wang };
80a4872e80SHsin-Hsiung Wang 
81a4872e80SHsin-Hsiung Wang static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
82a4872e80SHsin-Hsiung Wang 				  int irqbase)
83a4872e80SHsin-Hsiung Wang {
84a4872e80SHsin-Hsiung Wang 	unsigned int status;
85a4872e80SHsin-Hsiung Wang 	int i, irq, ret;
86a4872e80SHsin-Hsiung Wang 
87a4872e80SHsin-Hsiung Wang 	ret = regmap_read(mt6397->regmap, reg, &status);
88a4872e80SHsin-Hsiung Wang 	if (ret) {
89a4872e80SHsin-Hsiung Wang 		dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
90a4872e80SHsin-Hsiung Wang 		return;
91a4872e80SHsin-Hsiung Wang 	}
92a4872e80SHsin-Hsiung Wang 
93a4872e80SHsin-Hsiung Wang 	for (i = 0; i < 16; i++) {
94a4872e80SHsin-Hsiung Wang 		if (status & BIT(i)) {
95a4872e80SHsin-Hsiung Wang 			irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
96a4872e80SHsin-Hsiung Wang 			if (irq)
97a4872e80SHsin-Hsiung Wang 				handle_nested_irq(irq);
98a4872e80SHsin-Hsiung Wang 		}
99a4872e80SHsin-Hsiung Wang 	}
100a4872e80SHsin-Hsiung Wang 
101a4872e80SHsin-Hsiung Wang 	regmap_write(mt6397->regmap, reg, status);
102a4872e80SHsin-Hsiung Wang }
103a4872e80SHsin-Hsiung Wang 
104a4872e80SHsin-Hsiung Wang static irqreturn_t mt6397_irq_thread(int irq, void *data)
105a4872e80SHsin-Hsiung Wang {
106a4872e80SHsin-Hsiung Wang 	struct mt6397_chip *mt6397 = data;
107a4872e80SHsin-Hsiung Wang 
108a4872e80SHsin-Hsiung Wang 	mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
109a4872e80SHsin-Hsiung Wang 	mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
110a4872e80SHsin-Hsiung Wang 
111a4872e80SHsin-Hsiung Wang 	return IRQ_HANDLED;
112a4872e80SHsin-Hsiung Wang }
113a4872e80SHsin-Hsiung Wang 
114a4872e80SHsin-Hsiung Wang static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
115a4872e80SHsin-Hsiung Wang 				 irq_hw_number_t hw)
116a4872e80SHsin-Hsiung Wang {
117a4872e80SHsin-Hsiung Wang 	struct mt6397_chip *mt6397 = d->host_data;
118a4872e80SHsin-Hsiung Wang 
119a4872e80SHsin-Hsiung Wang 	irq_set_chip_data(irq, mt6397);
120a4872e80SHsin-Hsiung Wang 	irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
121a4872e80SHsin-Hsiung Wang 	irq_set_nested_thread(irq, 1);
122a4872e80SHsin-Hsiung Wang 	irq_set_noprobe(irq);
123a4872e80SHsin-Hsiung Wang 
124a4872e80SHsin-Hsiung Wang 	return 0;
125a4872e80SHsin-Hsiung Wang }
126a4872e80SHsin-Hsiung Wang 
127a4872e80SHsin-Hsiung Wang static const struct irq_domain_ops mt6397_irq_domain_ops = {
128a4872e80SHsin-Hsiung Wang 	.map = mt6397_irq_domain_map,
129a4872e80SHsin-Hsiung Wang };
130a4872e80SHsin-Hsiung Wang 
131a4872e80SHsin-Hsiung Wang int mt6397_irq_init(struct mt6397_chip *chip)
132a4872e80SHsin-Hsiung Wang {
133a4872e80SHsin-Hsiung Wang 	int ret;
134a4872e80SHsin-Hsiung Wang 
135a4872e80SHsin-Hsiung Wang 	mutex_init(&chip->irqlock);
136a4872e80SHsin-Hsiung Wang 
137a4872e80SHsin-Hsiung Wang 	switch (chip->chip_id) {
138a4872e80SHsin-Hsiung Wang 	case MT6323_CHIP_ID:
139a4872e80SHsin-Hsiung Wang 		chip->int_con[0] = MT6323_INT_CON0;
140a4872e80SHsin-Hsiung Wang 		chip->int_con[1] = MT6323_INT_CON1;
141a4872e80SHsin-Hsiung Wang 		chip->int_status[0] = MT6323_INT_STATUS0;
142a4872e80SHsin-Hsiung Wang 		chip->int_status[1] = MT6323_INT_STATUS1;
143a4872e80SHsin-Hsiung Wang 		break;
144a4872e80SHsin-Hsiung Wang 
145a4872e80SHsin-Hsiung Wang 	case MT6391_CHIP_ID:
146a4872e80SHsin-Hsiung Wang 	case MT6397_CHIP_ID:
147a4872e80SHsin-Hsiung Wang 		chip->int_con[0] = MT6397_INT_CON0;
148a4872e80SHsin-Hsiung Wang 		chip->int_con[1] = MT6397_INT_CON1;
149a4872e80SHsin-Hsiung Wang 		chip->int_status[0] = MT6397_INT_STATUS0;
150a4872e80SHsin-Hsiung Wang 		chip->int_status[1] = MT6397_INT_STATUS1;
151a4872e80SHsin-Hsiung Wang 		break;
152a4872e80SHsin-Hsiung Wang 
153a4872e80SHsin-Hsiung Wang 	default:
154a4872e80SHsin-Hsiung Wang 		dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
155a4872e80SHsin-Hsiung Wang 		return -ENODEV;
156a4872e80SHsin-Hsiung Wang 	}
157a4872e80SHsin-Hsiung Wang 
158a4872e80SHsin-Hsiung Wang 	/* Mask all interrupt sources */
159a4872e80SHsin-Hsiung Wang 	regmap_write(chip->regmap, chip->int_con[0], 0x0);
160a4872e80SHsin-Hsiung Wang 	regmap_write(chip->regmap, chip->int_con[1], 0x0);
161a4872e80SHsin-Hsiung Wang 
162a4872e80SHsin-Hsiung Wang 	chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
163a4872e80SHsin-Hsiung Wang 						 MT6397_IRQ_NR,
164a4872e80SHsin-Hsiung Wang 						 &mt6397_irq_domain_ops,
165a4872e80SHsin-Hsiung Wang 						 chip);
166a4872e80SHsin-Hsiung Wang 	if (!chip->irq_domain) {
167a4872e80SHsin-Hsiung Wang 		dev_err(chip->dev, "could not create irq domain\n");
168a4872e80SHsin-Hsiung Wang 		return -ENOMEM;
169a4872e80SHsin-Hsiung Wang 	}
170a4872e80SHsin-Hsiung Wang 
171a4872e80SHsin-Hsiung Wang 	ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
172a4872e80SHsin-Hsiung Wang 					mt6397_irq_thread, IRQF_ONESHOT,
173a4872e80SHsin-Hsiung Wang 					"mt6397-pmic", chip);
174a4872e80SHsin-Hsiung Wang 	if (ret) {
175a4872e80SHsin-Hsiung Wang 		dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
176a4872e80SHsin-Hsiung Wang 			chip->irq, ret);
177a4872e80SHsin-Hsiung Wang 		return ret;
178a4872e80SHsin-Hsiung Wang 	}
179a4872e80SHsin-Hsiung Wang 
180a4872e80SHsin-Hsiung Wang 	return 0;
181a4872e80SHsin-Hsiung Wang }
182