1a4872e80SHsin-Hsiung Wang // SPDX-License-Identifier: GPL-2.0
2a4872e80SHsin-Hsiung Wang //
3a4872e80SHsin-Hsiung Wang // Copyright (c) 2019 MediaTek Inc.
4a4872e80SHsin-Hsiung Wang
5a4872e80SHsin-Hsiung Wang #include <linux/interrupt.h>
6*dc0c386eSRob Herring #include <linux/irq.h>
7*dc0c386eSRob Herring #include <linux/irqdomain.h>
8a4872e80SHsin-Hsiung Wang #include <linux/module.h>
9a4872e80SHsin-Hsiung Wang #include <linux/platform_device.h>
10a4872e80SHsin-Hsiung Wang #include <linux/regmap.h>
114e2e7cfeSHsin-Hsiung Wang #include <linux/suspend.h>
12a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6323/core.h>
13a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6323/registers.h>
14d9cd0bc6SAngeloGioacchino Del Regno #include <linux/mfd/mt6331/core.h>
15d9cd0bc6SAngeloGioacchino Del Regno #include <linux/mfd/mt6331/registers.h>
16a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6397/core.h>
17a4872e80SHsin-Hsiung Wang #include <linux/mfd/mt6397/registers.h>
18a4872e80SHsin-Hsiung Wang
mt6397_irq_lock(struct irq_data * data)19a4872e80SHsin-Hsiung Wang static void mt6397_irq_lock(struct irq_data *data)
20a4872e80SHsin-Hsiung Wang {
21a4872e80SHsin-Hsiung Wang struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
22a4872e80SHsin-Hsiung Wang
23a4872e80SHsin-Hsiung Wang mutex_lock(&mt6397->irqlock);
24a4872e80SHsin-Hsiung Wang }
25a4872e80SHsin-Hsiung Wang
mt6397_irq_sync_unlock(struct irq_data * data)26a4872e80SHsin-Hsiung Wang static void mt6397_irq_sync_unlock(struct irq_data *data)
27a4872e80SHsin-Hsiung Wang {
28a4872e80SHsin-Hsiung Wang struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
29a4872e80SHsin-Hsiung Wang
30a4872e80SHsin-Hsiung Wang regmap_write(mt6397->regmap, mt6397->int_con[0],
31a4872e80SHsin-Hsiung Wang mt6397->irq_masks_cur[0]);
32a4872e80SHsin-Hsiung Wang regmap_write(mt6397->regmap, mt6397->int_con[1],
33a4872e80SHsin-Hsiung Wang mt6397->irq_masks_cur[1]);
34a4872e80SHsin-Hsiung Wang
35a4872e80SHsin-Hsiung Wang mutex_unlock(&mt6397->irqlock);
36a4872e80SHsin-Hsiung Wang }
37a4872e80SHsin-Hsiung Wang
mt6397_irq_disable(struct irq_data * data)38a4872e80SHsin-Hsiung Wang static void mt6397_irq_disable(struct irq_data *data)
39a4872e80SHsin-Hsiung Wang {
40a4872e80SHsin-Hsiung Wang struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
41a4872e80SHsin-Hsiung Wang int shift = data->hwirq & 0xf;
42a4872e80SHsin-Hsiung Wang int reg = data->hwirq >> 4;
43a4872e80SHsin-Hsiung Wang
44a4872e80SHsin-Hsiung Wang mt6397->irq_masks_cur[reg] &= ~BIT(shift);
45a4872e80SHsin-Hsiung Wang }
46a4872e80SHsin-Hsiung Wang
mt6397_irq_enable(struct irq_data * data)47a4872e80SHsin-Hsiung Wang static void mt6397_irq_enable(struct irq_data *data)
48a4872e80SHsin-Hsiung Wang {
49a4872e80SHsin-Hsiung Wang struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
50a4872e80SHsin-Hsiung Wang int shift = data->hwirq & 0xf;
51a4872e80SHsin-Hsiung Wang int reg = data->hwirq >> 4;
52a4872e80SHsin-Hsiung Wang
53a4872e80SHsin-Hsiung Wang mt6397->irq_masks_cur[reg] |= BIT(shift);
54a4872e80SHsin-Hsiung Wang }
55a4872e80SHsin-Hsiung Wang
mt6397_irq_set_wake(struct irq_data * irq_data,unsigned int on)56a4872e80SHsin-Hsiung Wang static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
57a4872e80SHsin-Hsiung Wang {
58a4872e80SHsin-Hsiung Wang struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
59a4872e80SHsin-Hsiung Wang int shift = irq_data->hwirq & 0xf;
60a4872e80SHsin-Hsiung Wang int reg = irq_data->hwirq >> 4;
61a4872e80SHsin-Hsiung Wang
62a4872e80SHsin-Hsiung Wang if (on)
63a4872e80SHsin-Hsiung Wang mt6397->wake_mask[reg] |= BIT(shift);
64a4872e80SHsin-Hsiung Wang else
65a4872e80SHsin-Hsiung Wang mt6397->wake_mask[reg] &= ~BIT(shift);
66a4872e80SHsin-Hsiung Wang
67a4872e80SHsin-Hsiung Wang return 0;
68a4872e80SHsin-Hsiung Wang }
69a4872e80SHsin-Hsiung Wang
70a4872e80SHsin-Hsiung Wang static struct irq_chip mt6397_irq_chip = {
71a4872e80SHsin-Hsiung Wang .name = "mt6397-irq",
72a4872e80SHsin-Hsiung Wang .irq_bus_lock = mt6397_irq_lock,
73a4872e80SHsin-Hsiung Wang .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
74a4872e80SHsin-Hsiung Wang .irq_enable = mt6397_irq_enable,
75a4872e80SHsin-Hsiung Wang .irq_disable = mt6397_irq_disable,
76e1243e0dSPaul Cercueil .irq_set_wake = pm_sleep_ptr(mt6397_irq_set_wake),
77a4872e80SHsin-Hsiung Wang };
78a4872e80SHsin-Hsiung Wang
mt6397_irq_handle_reg(struct mt6397_chip * mt6397,int reg,int irqbase)79a4872e80SHsin-Hsiung Wang static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
80a4872e80SHsin-Hsiung Wang int irqbase)
81a4872e80SHsin-Hsiung Wang {
824e2e7cfeSHsin-Hsiung Wang unsigned int status = 0;
83a4872e80SHsin-Hsiung Wang int i, irq, ret;
84a4872e80SHsin-Hsiung Wang
85a4872e80SHsin-Hsiung Wang ret = regmap_read(mt6397->regmap, reg, &status);
86a4872e80SHsin-Hsiung Wang if (ret) {
87a4872e80SHsin-Hsiung Wang dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
88a4872e80SHsin-Hsiung Wang return;
89a4872e80SHsin-Hsiung Wang }
90a4872e80SHsin-Hsiung Wang
91a4872e80SHsin-Hsiung Wang for (i = 0; i < 16; i++) {
92a4872e80SHsin-Hsiung Wang if (status & BIT(i)) {
93a4872e80SHsin-Hsiung Wang irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
94a4872e80SHsin-Hsiung Wang if (irq)
95a4872e80SHsin-Hsiung Wang handle_nested_irq(irq);
96a4872e80SHsin-Hsiung Wang }
97a4872e80SHsin-Hsiung Wang }
98a4872e80SHsin-Hsiung Wang
99a4872e80SHsin-Hsiung Wang regmap_write(mt6397->regmap, reg, status);
100a4872e80SHsin-Hsiung Wang }
101a4872e80SHsin-Hsiung Wang
mt6397_irq_thread(int irq,void * data)102a4872e80SHsin-Hsiung Wang static irqreturn_t mt6397_irq_thread(int irq, void *data)
103a4872e80SHsin-Hsiung Wang {
104a4872e80SHsin-Hsiung Wang struct mt6397_chip *mt6397 = data;
105a4872e80SHsin-Hsiung Wang
106a4872e80SHsin-Hsiung Wang mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
107a4872e80SHsin-Hsiung Wang mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
108a4872e80SHsin-Hsiung Wang
109a4872e80SHsin-Hsiung Wang return IRQ_HANDLED;
110a4872e80SHsin-Hsiung Wang }
111a4872e80SHsin-Hsiung Wang
mt6397_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)112a4872e80SHsin-Hsiung Wang static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
113a4872e80SHsin-Hsiung Wang irq_hw_number_t hw)
114a4872e80SHsin-Hsiung Wang {
115a4872e80SHsin-Hsiung Wang struct mt6397_chip *mt6397 = d->host_data;
116a4872e80SHsin-Hsiung Wang
117a4872e80SHsin-Hsiung Wang irq_set_chip_data(irq, mt6397);
118a4872e80SHsin-Hsiung Wang irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
119a4872e80SHsin-Hsiung Wang irq_set_nested_thread(irq, 1);
120a4872e80SHsin-Hsiung Wang irq_set_noprobe(irq);
121a4872e80SHsin-Hsiung Wang
122a4872e80SHsin-Hsiung Wang return 0;
123a4872e80SHsin-Hsiung Wang }
124a4872e80SHsin-Hsiung Wang
125a4872e80SHsin-Hsiung Wang static const struct irq_domain_ops mt6397_irq_domain_ops = {
126a4872e80SHsin-Hsiung Wang .map = mt6397_irq_domain_map,
127a4872e80SHsin-Hsiung Wang };
128a4872e80SHsin-Hsiung Wang
mt6397_irq_pm_notifier(struct notifier_block * notifier,unsigned long pm_event,void * unused)1294e2e7cfeSHsin-Hsiung Wang static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
1304e2e7cfeSHsin-Hsiung Wang unsigned long pm_event, void *unused)
1314e2e7cfeSHsin-Hsiung Wang {
1324e2e7cfeSHsin-Hsiung Wang struct mt6397_chip *chip =
1334e2e7cfeSHsin-Hsiung Wang container_of(notifier, struct mt6397_chip, pm_nb);
1344e2e7cfeSHsin-Hsiung Wang
1354e2e7cfeSHsin-Hsiung Wang switch (pm_event) {
1364e2e7cfeSHsin-Hsiung Wang case PM_SUSPEND_PREPARE:
1374e2e7cfeSHsin-Hsiung Wang regmap_write(chip->regmap,
1384e2e7cfeSHsin-Hsiung Wang chip->int_con[0], chip->wake_mask[0]);
1394e2e7cfeSHsin-Hsiung Wang regmap_write(chip->regmap,
1404e2e7cfeSHsin-Hsiung Wang chip->int_con[1], chip->wake_mask[1]);
1414e2e7cfeSHsin-Hsiung Wang enable_irq_wake(chip->irq);
1424e2e7cfeSHsin-Hsiung Wang break;
1434e2e7cfeSHsin-Hsiung Wang
1444e2e7cfeSHsin-Hsiung Wang case PM_POST_SUSPEND:
1454e2e7cfeSHsin-Hsiung Wang regmap_write(chip->regmap,
1464e2e7cfeSHsin-Hsiung Wang chip->int_con[0], chip->irq_masks_cur[0]);
1474e2e7cfeSHsin-Hsiung Wang regmap_write(chip->regmap,
1484e2e7cfeSHsin-Hsiung Wang chip->int_con[1], chip->irq_masks_cur[1]);
1494e2e7cfeSHsin-Hsiung Wang disable_irq_wake(chip->irq);
1504e2e7cfeSHsin-Hsiung Wang break;
1514e2e7cfeSHsin-Hsiung Wang
1524e2e7cfeSHsin-Hsiung Wang default:
1534e2e7cfeSHsin-Hsiung Wang break;
1544e2e7cfeSHsin-Hsiung Wang }
1554e2e7cfeSHsin-Hsiung Wang
1564e2e7cfeSHsin-Hsiung Wang return NOTIFY_DONE;
1574e2e7cfeSHsin-Hsiung Wang }
1584e2e7cfeSHsin-Hsiung Wang
mt6397_irq_init(struct mt6397_chip * chip)159a4872e80SHsin-Hsiung Wang int mt6397_irq_init(struct mt6397_chip *chip)
160a4872e80SHsin-Hsiung Wang {
161a4872e80SHsin-Hsiung Wang int ret;
162a4872e80SHsin-Hsiung Wang
163a4872e80SHsin-Hsiung Wang mutex_init(&chip->irqlock);
164a4872e80SHsin-Hsiung Wang
165a4872e80SHsin-Hsiung Wang switch (chip->chip_id) {
166a4872e80SHsin-Hsiung Wang case MT6323_CHIP_ID:
167a4872e80SHsin-Hsiung Wang chip->int_con[0] = MT6323_INT_CON0;
168a4872e80SHsin-Hsiung Wang chip->int_con[1] = MT6323_INT_CON1;
169a4872e80SHsin-Hsiung Wang chip->int_status[0] = MT6323_INT_STATUS0;
170a4872e80SHsin-Hsiung Wang chip->int_status[1] = MT6323_INT_STATUS1;
171a4872e80SHsin-Hsiung Wang break;
172d9cd0bc6SAngeloGioacchino Del Regno case MT6331_CHIP_ID:
173d9cd0bc6SAngeloGioacchino Del Regno chip->int_con[0] = MT6331_INT_CON0;
174d9cd0bc6SAngeloGioacchino Del Regno chip->int_con[1] = MT6331_INT_CON1;
175d9cd0bc6SAngeloGioacchino Del Regno chip->int_status[0] = MT6331_INT_STATUS_CON0;
176d9cd0bc6SAngeloGioacchino Del Regno chip->int_status[1] = MT6331_INT_STATUS_CON1;
177d9cd0bc6SAngeloGioacchino Del Regno break;
178a4872e80SHsin-Hsiung Wang case MT6391_CHIP_ID:
179a4872e80SHsin-Hsiung Wang case MT6397_CHIP_ID:
180a4872e80SHsin-Hsiung Wang chip->int_con[0] = MT6397_INT_CON0;
181a4872e80SHsin-Hsiung Wang chip->int_con[1] = MT6397_INT_CON1;
182a4872e80SHsin-Hsiung Wang chip->int_status[0] = MT6397_INT_STATUS0;
183a4872e80SHsin-Hsiung Wang chip->int_status[1] = MT6397_INT_STATUS1;
184a4872e80SHsin-Hsiung Wang break;
185a4872e80SHsin-Hsiung Wang
186a4872e80SHsin-Hsiung Wang default:
187a4872e80SHsin-Hsiung Wang dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
188a4872e80SHsin-Hsiung Wang return -ENODEV;
189a4872e80SHsin-Hsiung Wang }
190a4872e80SHsin-Hsiung Wang
191a4872e80SHsin-Hsiung Wang /* Mask all interrupt sources */
192a4872e80SHsin-Hsiung Wang regmap_write(chip->regmap, chip->int_con[0], 0x0);
193a4872e80SHsin-Hsiung Wang regmap_write(chip->regmap, chip->int_con[1], 0x0);
194a4872e80SHsin-Hsiung Wang
1954e2e7cfeSHsin-Hsiung Wang chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
196a4872e80SHsin-Hsiung Wang chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
197a4872e80SHsin-Hsiung Wang MT6397_IRQ_NR,
198a4872e80SHsin-Hsiung Wang &mt6397_irq_domain_ops,
199a4872e80SHsin-Hsiung Wang chip);
200a4872e80SHsin-Hsiung Wang if (!chip->irq_domain) {
201a4872e80SHsin-Hsiung Wang dev_err(chip->dev, "could not create irq domain\n");
202a4872e80SHsin-Hsiung Wang return -ENOMEM;
203a4872e80SHsin-Hsiung Wang }
204a4872e80SHsin-Hsiung Wang
205a4872e80SHsin-Hsiung Wang ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
206a4872e80SHsin-Hsiung Wang mt6397_irq_thread, IRQF_ONESHOT,
207a4872e80SHsin-Hsiung Wang "mt6397-pmic", chip);
208a4872e80SHsin-Hsiung Wang if (ret) {
209a4872e80SHsin-Hsiung Wang dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
210a4872e80SHsin-Hsiung Wang chip->irq, ret);
211a4872e80SHsin-Hsiung Wang return ret;
212a4872e80SHsin-Hsiung Wang }
213a4872e80SHsin-Hsiung Wang
2144e2e7cfeSHsin-Hsiung Wang register_pm_notifier(&chip->pm_nb);
215a4872e80SHsin-Hsiung Wang return 0;
216a4872e80SHsin-Hsiung Wang }
217