17edd3634SGene Chen // SPDX-License-Identifier: GPL-2.0 27edd3634SGene Chen /* 37edd3634SGene Chen * Copyright (c) 2020 MediaTek Inc. 47edd3634SGene Chen * 57edd3634SGene Chen * Author: Gene Chen <gene_chen@richtek.com> 67edd3634SGene Chen */ 77edd3634SGene Chen 8137871bcSGene Chen #include <linux/crc8.h> 97edd3634SGene Chen #include <linux/i2c.h> 107edd3634SGene Chen #include <linux/init.h> 117edd3634SGene Chen #include <linux/interrupt.h> 127edd3634SGene Chen #include <linux/kernel.h> 137edd3634SGene Chen #include <linux/mfd/core.h> 147edd3634SGene Chen #include <linux/module.h> 15137871bcSGene Chen #include <linux/regmap.h> 16137871bcSGene Chen #include <linux/slab.h> 177edd3634SGene Chen 18b042c085SGene Chen enum { 19b042c085SGene Chen MT6360_SLAVE_TCPC = 0, 20b042c085SGene Chen MT6360_SLAVE_PMIC, 21b042c085SGene Chen MT6360_SLAVE_LDO, 22b042c085SGene Chen MT6360_SLAVE_PMU, 23b042c085SGene Chen MT6360_SLAVE_MAX, 24b042c085SGene Chen }; 25b042c085SGene Chen 26b042c085SGene Chen struct mt6360_ddata { 27b042c085SGene Chen struct i2c_client *i2c[MT6360_SLAVE_MAX]; 28b042c085SGene Chen struct device *dev; 29b042c085SGene Chen struct regmap *regmap; 30b042c085SGene Chen struct regmap_irq_chip_data *irq_data; 31b042c085SGene Chen unsigned int chip_rev; 32b042c085SGene Chen u8 crc8_tbl[CRC8_TABLE_SIZE]; 33b042c085SGene Chen }; 34b042c085SGene Chen 35b042c085SGene Chen #define MT6360_TCPC_SLAVEID 0x4E 36b042c085SGene Chen #define MT6360_PMIC_SLAVEID 0x1A 37b042c085SGene Chen #define MT6360_LDO_SLAVEID 0x64 38b042c085SGene Chen #define MT6360_PMU_SLAVEID 0x34 39b042c085SGene Chen 40b042c085SGene Chen #define MT6360_REG_TCPCSTART 0x00 41b042c085SGene Chen #define MT6360_REG_TCPCEND 0xFF 42b042c085SGene Chen #define MT6360_REG_PMICSTART 0x100 43b042c085SGene Chen #define MT6360_REG_PMICEND 0x13B 44b042c085SGene Chen #define MT6360_REG_LDOSTART 0x200 45b042c085SGene Chen #define MT6360_REG_LDOEND 0x21C 46b042c085SGene Chen #define MT6360_REG_PMUSTART 0x300 47b042c085SGene Chen #define MT6360_PMU_DEV_INFO 0x300 48b042c085SGene Chen #define MT6360_PMU_CHG_IRQ1 0x3D0 49b042c085SGene Chen #define MT6360_PMU_CHG_MASK1 0x3F0 50b042c085SGene Chen #define MT6360_REG_PMUEND 0x3FF 51b042c085SGene Chen 52b042c085SGene Chen #define MT6360_PMU_IRQ_REGNUM 16 53b042c085SGene Chen 54b042c085SGene Chen #define CHIP_VEN_MASK 0xF0 55b042c085SGene Chen #define CHIP_VEN_MT6360 0x50 56b042c085SGene Chen #define CHIP_REV_MASK 0x0F 57b042c085SGene Chen 58b042c085SGene Chen #define MT6360_ADDRESS_MASK 0x3F 59b042c085SGene Chen #define MT6360_DATA_SIZE_1_BYTE 0x00 60b042c085SGene Chen #define MT6360_DATA_SIZE_2_BYTES 0x40 61b042c085SGene Chen #define MT6360_DATA_SIZE_3_BYTES 0x80 62b042c085SGene Chen #define MT6360_DATA_SIZE_4_BYTES 0xC0 63b042c085SGene Chen 64b042c085SGene Chen #define MT6360_CRC8_POLYNOMIAL 0x7 657edd3634SGene Chen 663b085044SGene Chen #define MT6360_CRC_I2C_ADDR_SIZE 1 673b085044SGene Chen #define MT6360_CRC_REG_ADDR_SIZE 1 683b085044SGene Chen /* prealloca read size = i2c device addr + i2c reg addr + val ... + crc8 */ 693b085044SGene Chen #define MT6360_ALLOC_READ_SIZE(_size) (_size + 3) 703b085044SGene Chen /* prealloca write size = i2c device addr + i2c reg addr + val ... + crc8 + dummy byte */ 713b085044SGene Chen #define MT6360_ALLOC_WRITE_SIZE(_size) (_size + 4) 723b085044SGene Chen #define MT6360_CRC_PREDATA_OFFSET (MT6360_CRC_I2C_ADDR_SIZE + MT6360_CRC_REG_ADDR_SIZE) 733b085044SGene Chen #define MT6360_CRC_CRC8_SIZE 1 743b085044SGene Chen #define MT6360_CRC_DUMMY_BYTE_SIZE 1 753b085044SGene Chen #define MT6360_REGMAP_REG_BYTE_SIZE 2 763b085044SGene Chen #define I2C_ADDR_XLATE_8BIT(_addr, _rw) (((_addr & 0x7F) << 1) + _rw) 773b085044SGene Chen 787edd3634SGene Chen /* reg 0 -> 0 ~ 7 */ 7950e89312SGene Chen #define MT6360_CHG_TREG_EVT 4 8050e89312SGene Chen #define MT6360_CHG_AICR_EVT 5 8150e89312SGene Chen #define MT6360_CHG_MIVR_EVT 6 8250e89312SGene Chen #define MT6360_PWR_RDY_EVT 7 837edd3634SGene Chen /* REG 1 -> 8 ~ 15 */ 8450e89312SGene Chen #define MT6360_CHG_BATSYSUV_EVT 9 8550e89312SGene Chen #define MT6360_FLED_CHG_VINOVP_EVT 11 8650e89312SGene Chen #define MT6360_CHG_VSYSUV_EVT 12 8750e89312SGene Chen #define MT6360_CHG_VSYSOV_EVT 13 8850e89312SGene Chen #define MT6360_CHG_VBATOV_EVT 14 8950e89312SGene Chen #define MT6360_CHG_VBUSOV_EVT 15 907edd3634SGene Chen /* REG 2 -> 16 ~ 23 */ 917edd3634SGene Chen /* REG 3 -> 24 ~ 31 */ 9250e89312SGene Chen #define MT6360_WD_PMU_DET 25 9350e89312SGene Chen #define MT6360_WD_PMU_DONE 26 9450e89312SGene Chen #define MT6360_CHG_TMRI 27 9550e89312SGene Chen #define MT6360_CHG_ADPBADI 29 9650e89312SGene Chen #define MT6360_CHG_RVPI 30 9750e89312SGene Chen #define MT6360_OTPI 31 987edd3634SGene Chen /* REG 4 -> 32 ~ 39 */ 9950e89312SGene Chen #define MT6360_CHG_AICCMEASL 32 10050e89312SGene Chen #define MT6360_CHGDET_DONEI 34 10150e89312SGene Chen #define MT6360_WDTMRI 35 10250e89312SGene Chen #define MT6360_SSFINISHI 36 10350e89312SGene Chen #define MT6360_CHG_RECHGI 37 10450e89312SGene Chen #define MT6360_CHG_TERMI 38 10550e89312SGene Chen #define MT6360_CHG_IEOCI 39 1067edd3634SGene Chen /* REG 5 -> 40 ~ 47 */ 10750e89312SGene Chen #define MT6360_PUMPX_DONEI 40 10850e89312SGene Chen #define MT6360_BAT_OVP_ADC_EVT 41 10950e89312SGene Chen #define MT6360_TYPEC_OTP_EVT 42 11050e89312SGene Chen #define MT6360_ADC_WAKEUP_EVT 43 11150e89312SGene Chen #define MT6360_ADC_DONEI 44 11250e89312SGene Chen #define MT6360_BST_BATUVI 45 11350e89312SGene Chen #define MT6360_BST_VBUSOVI 46 11450e89312SGene Chen #define MT6360_BST_OLPI 47 1157edd3634SGene Chen /* REG 6 -> 48 ~ 55 */ 11650e89312SGene Chen #define MT6360_ATTACH_I 48 11750e89312SGene Chen #define MT6360_DETACH_I 49 11850e89312SGene Chen #define MT6360_QC30_STPDONE 51 11950e89312SGene Chen #define MT6360_QC_VBUSDET_DONE 52 12050e89312SGene Chen #define MT6360_HVDCP_DET 53 12150e89312SGene Chen #define MT6360_CHGDETI 54 12250e89312SGene Chen #define MT6360_DCDTI 55 1237edd3634SGene Chen /* REG 7 -> 56 ~ 63 */ 12450e89312SGene Chen #define MT6360_FOD_DONE_EVT 56 12550e89312SGene Chen #define MT6360_FOD_OV_EVT 57 12650e89312SGene Chen #define MT6360_CHRDET_UVP_EVT 58 12750e89312SGene Chen #define MT6360_CHRDET_OVP_EVT 59 12850e89312SGene Chen #define MT6360_CHRDET_EXT_EVT 60 12950e89312SGene Chen #define MT6360_FOD_LR_EVT 61 13050e89312SGene Chen #define MT6360_FOD_HR_EVT 62 13150e89312SGene Chen #define MT6360_FOD_DISCHG_FAIL_EVT 63 1327edd3634SGene Chen /* REG 8 -> 64 ~ 71 */ 13350e89312SGene Chen #define MT6360_USBID_EVT 64 13450e89312SGene Chen #define MT6360_APWDTRST_EVT 65 13550e89312SGene Chen #define MT6360_EN_EVT 66 13650e89312SGene Chen #define MT6360_QONB_RST_EVT 67 13750e89312SGene Chen #define MT6360_MRSTB_EVT 68 13850e89312SGene Chen #define MT6360_OTP_EVT 69 13950e89312SGene Chen #define MT6360_VDDAOV_EVT 70 14050e89312SGene Chen #define MT6360_SYSUV_EVT 71 1417edd3634SGene Chen /* REG 9 -> 72 ~ 79 */ 14250e89312SGene Chen #define MT6360_FLED_STRBPIN_EVT 72 14350e89312SGene Chen #define MT6360_FLED_TORPIN_EVT 73 14450e89312SGene Chen #define MT6360_FLED_TX_EVT 74 14550e89312SGene Chen #define MT6360_FLED_LVF_EVT 75 14650e89312SGene Chen #define MT6360_FLED2_SHORT_EVT 78 14750e89312SGene Chen #define MT6360_FLED1_SHORT_EVT 79 1487edd3634SGene Chen /* REG 10 -> 80 ~ 87 */ 14950e89312SGene Chen #define MT6360_FLED2_STRB_EVT 80 15050e89312SGene Chen #define MT6360_FLED1_STRB_EVT 81 15150e89312SGene Chen #define MT6360_FLED2_STRB_TO_EVT 82 15250e89312SGene Chen #define MT6360_FLED1_STRB_TO_EVT 83 15350e89312SGene Chen #define MT6360_FLED2_TOR_EVT 84 15450e89312SGene Chen #define MT6360_FLED1_TOR_EVT 85 1557edd3634SGene Chen /* REG 11 -> 88 ~ 95 */ 1567edd3634SGene Chen /* REG 12 -> 96 ~ 103 */ 15750e89312SGene Chen #define MT6360_BUCK1_PGB_EVT 96 15850e89312SGene Chen #define MT6360_BUCK1_OC_EVT 100 15950e89312SGene Chen #define MT6360_BUCK1_OV_EVT 101 16050e89312SGene Chen #define MT6360_BUCK1_UV_EVT 102 1617edd3634SGene Chen /* REG 13 -> 104 ~ 111 */ 16250e89312SGene Chen #define MT6360_BUCK2_PGB_EVT 104 16350e89312SGene Chen #define MT6360_BUCK2_OC_EVT 108 16450e89312SGene Chen #define MT6360_BUCK2_OV_EVT 109 16550e89312SGene Chen #define MT6360_BUCK2_UV_EVT 110 1667edd3634SGene Chen /* REG 14 -> 112 ~ 119 */ 16750e89312SGene Chen #define MT6360_LDO1_OC_EVT 113 16850e89312SGene Chen #define MT6360_LDO2_OC_EVT 114 16950e89312SGene Chen #define MT6360_LDO3_OC_EVT 115 17050e89312SGene Chen #define MT6360_LDO5_OC_EVT 117 17150e89312SGene Chen #define MT6360_LDO6_OC_EVT 118 17250e89312SGene Chen #define MT6360_LDO7_OC_EVT 119 1737edd3634SGene Chen /* REG 15 -> 120 ~ 127 */ 17450e89312SGene Chen #define MT6360_LDO1_PGB_EVT 121 17550e89312SGene Chen #define MT6360_LDO2_PGB_EVT 122 17650e89312SGene Chen #define MT6360_LDO3_PGB_EVT 123 17750e89312SGene Chen #define MT6360_LDO5_PGB_EVT 125 17850e89312SGene Chen #define MT6360_LDO6_PGB_EVT 126 17950e89312SGene Chen #define MT6360_LDO7_PGB_EVT 127 1807edd3634SGene Chen 18160a90b35SGene Chen static const struct regmap_irq mt6360_irqs[] = { 1827edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8), 1837edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8), 1847edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8), 1857edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_PWR_RDY_EVT, 8), 1867edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_BATSYSUV_EVT, 8), 1877edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_CHG_VINOVP_EVT, 8), 1887edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSUV_EVT, 8), 1897edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSOV_EVT, 8), 1907edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VBATOV_EVT, 8), 1917edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VBUSOV_EVT, 8), 1927edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DET, 8), 1937edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DONE, 8), 1947edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_TMRI, 8), 1957edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_ADPBADI, 8), 1967edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_RVPI, 8), 1977edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_OTPI, 8), 1987edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_AICCMEASL, 8), 1997edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHGDET_DONEI, 8), 2007edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_WDTMRI, 8), 2017edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_SSFINISHI, 8), 2027edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_RECHGI, 8), 2037edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_TERMI, 8), 2047edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_IEOCI, 8), 2057edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_PUMPX_DONEI, 8), 2067edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BAT_OVP_ADC_EVT, 8), 2077edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_TYPEC_OTP_EVT, 8), 2087edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_ADC_WAKEUP_EVT, 8), 2097edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_ADC_DONEI, 8), 2107edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BST_BATUVI, 8), 2117edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BST_VBUSOVI, 8), 2127edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BST_OLPI, 8), 2137edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_ATTACH_I, 8), 2147edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_DETACH_I, 8), 2157edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_QC30_STPDONE, 8), 2167edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_QC_VBUSDET_DONE, 8), 2177edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_HVDCP_DET, 8), 2187edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHGDETI, 8), 2197edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_DCDTI, 8), 2207edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_DONE_EVT, 8), 2217edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_OV_EVT, 8), 2227edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHRDET_UVP_EVT, 8), 2237edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHRDET_OVP_EVT, 8), 2247edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHRDET_EXT_EVT, 8), 2257edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_LR_EVT, 8), 2267edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_HR_EVT, 8), 2277edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_DISCHG_FAIL_EVT, 8), 2287edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_USBID_EVT, 8), 2297edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_APWDTRST_EVT, 8), 2307edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_EN_EVT, 8), 2317edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_QONB_RST_EVT, 8), 2327edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_MRSTB_EVT, 8), 2337edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_OTP_EVT, 8), 2347edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_VDDAOV_EVT, 8), 2357edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_SYSUV_EVT, 8), 2367edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_STRBPIN_EVT, 8), 2377edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_TORPIN_EVT, 8), 2387edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_TX_EVT, 8), 2397edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_LVF_EVT, 8), 2407edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_SHORT_EVT, 8), 2417edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_SHORT_EVT, 8), 2427edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_EVT, 8), 2437edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_EVT, 8), 2447edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_TO_EVT, 8), 2457edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_TO_EVT, 8), 2467edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_TOR_EVT, 8), 2477edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_TOR_EVT, 8), 2487edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_PGB_EVT, 8), 2497edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OC_EVT, 8), 2507edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OV_EVT, 8), 2517edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_UV_EVT, 8), 2527edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_PGB_EVT, 8), 2537edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OC_EVT, 8), 2547edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OV_EVT, 8), 2557edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_UV_EVT, 8), 2567edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO1_OC_EVT, 8), 2577edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO2_OC_EVT, 8), 2587edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO3_OC_EVT, 8), 2597edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO5_OC_EVT, 8), 2607edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO6_OC_EVT, 8), 2617edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO7_OC_EVT, 8), 2627edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO1_PGB_EVT, 8), 2637edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO2_PGB_EVT, 8), 2647edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO3_PGB_EVT, 8), 2657edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO5_PGB_EVT, 8), 2667edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO6_PGB_EVT, 8), 2677edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8), 2687edd3634SGene Chen }; 2697edd3634SGene Chen 270a75a2d56SGene Chen static const struct regmap_irq_chip mt6360_irq_chip = { 271a75a2d56SGene Chen .name = "mt6360_irqs", 27260a90b35SGene Chen .irqs = mt6360_irqs, 27360a90b35SGene Chen .num_irqs = ARRAY_SIZE(mt6360_irqs), 2747edd3634SGene Chen .num_regs = MT6360_PMU_IRQ_REGNUM, 2757edd3634SGene Chen .mask_base = MT6360_PMU_CHG_MASK1, 2767edd3634SGene Chen .status_base = MT6360_PMU_CHG_IRQ1, 2777edd3634SGene Chen .ack_base = MT6360_PMU_CHG_IRQ1, 2787edd3634SGene Chen .init_ack_masked = true, 2797edd3634SGene Chen .use_ack = true, 2807edd3634SGene Chen }; 2817edd3634SGene Chen 2827edd3634SGene Chen static const struct resource mt6360_adc_resources[] = { 2837edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"), 2847edd3634SGene Chen }; 2857edd3634SGene Chen 2867edd3634SGene Chen static const struct resource mt6360_chg_resources[] = { 2877edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"), 2887edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"), 2897edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, "chg_batsysuv_evt"), 2907edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"), 2917edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"), 2927edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"), 2937edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"), 2947edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"), 2957edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"), 2967edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"), 2977edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"), 2987edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"), 2997edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"), 3007edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"), 3017edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"), 3027edd3634SGene Chen }; 3037edd3634SGene Chen 3047edd3634SGene Chen static const struct resource mt6360_led_resources[] = { 3057edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, "fled_chg_vinovp_evt"), 3067edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"), 3077edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"), 3087edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"), 3097edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, "fled2_strb_to_evt"), 3107edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"), 3117edd3634SGene Chen }; 3127edd3634SGene Chen 3134ee06e10SGene Chen static const struct resource mt6360_regulator_resources[] = { 3147edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"), 3157edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"), 3167edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"), 3177edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"), 3187edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"), 3197edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"), 3207edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"), 3217edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"), 3227edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), 3237edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), 3247edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), 3257edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"), 326*84742a98SFei Shao DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"), 327*84742a98SFei Shao DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), 3287edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"), 3297edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"), 3307edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"), 3317edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"), 332*84742a98SFei Shao DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), 333*84742a98SFei Shao DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), 3347edd3634SGene Chen }; 3357edd3634SGene Chen 3367edd3634SGene Chen static const struct mfd_cell mt6360_devs[] = { 33712f3f131SGene Chen MFD_CELL_OF("mt6360-adc", mt6360_adc_resources, 33812f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-adc"), 33912f3f131SGene Chen MFD_CELL_OF("mt6360-chg", mt6360_chg_resources, 34012f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-chg"), 34112f3f131SGene Chen MFD_CELL_OF("mt6360-led", mt6360_led_resources, 34212f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-led"), 3434ee06e10SGene Chen MFD_CELL_RES("mt6360-regulator", mt6360_regulator_resources), 34412f3f131SGene Chen MFD_CELL_OF("mt6360-tcpc", NULL, 34512f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-tcpc"), 3467edd3634SGene Chen }; 3477edd3634SGene Chen 348e8470294SGene Chen static int mt6360_check_vendor_info(struct mt6360_ddata *ddata) 349e8470294SGene Chen { 350e8470294SGene Chen u32 info; 351e8470294SGene Chen int ret; 352e8470294SGene Chen 353e8470294SGene Chen ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, &info); 354e8470294SGene Chen if (ret < 0) 355e8470294SGene Chen return ret; 356e8470294SGene Chen 357e8470294SGene Chen if ((info & CHIP_VEN_MASK) != CHIP_VEN_MT6360) { 358e8470294SGene Chen dev_err(ddata->dev, "Device not supported\n"); 359e8470294SGene Chen return -ENODEV; 360e8470294SGene Chen } 361e8470294SGene Chen 362e8470294SGene Chen ddata->chip_rev = info & CHIP_REV_MASK; 363e8470294SGene Chen 364e8470294SGene Chen return 0; 365e8470294SGene Chen } 366e8470294SGene Chen 3677edd3634SGene Chen static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { 3683b085044SGene Chen MT6360_TCPC_SLAVEID, 3697edd3634SGene Chen MT6360_PMIC_SLAVEID, 3707edd3634SGene Chen MT6360_LDO_SLAVEID, 3713b085044SGene Chen MT6360_PMU_SLAVEID, 3723b085044SGene Chen }; 3733b085044SGene Chen 3743b085044SGene Chen static int mt6360_xlate_pmicldo_addr(u8 *addr, int rw_size) 3753b085044SGene Chen { 3763b085044SGene Chen /* Address is already in encoded [5:0] */ 3773b085044SGene Chen *addr &= MT6360_ADDRESS_MASK; 3783b085044SGene Chen 3793b085044SGene Chen switch (rw_size) { 3803b085044SGene Chen case 1: 3813b085044SGene Chen *addr |= MT6360_DATA_SIZE_1_BYTE; 3823b085044SGene Chen break; 3833b085044SGene Chen case 2: 3843b085044SGene Chen *addr |= MT6360_DATA_SIZE_2_BYTES; 3853b085044SGene Chen break; 3863b085044SGene Chen case 3: 3873b085044SGene Chen *addr |= MT6360_DATA_SIZE_3_BYTES; 3883b085044SGene Chen break; 3893b085044SGene Chen case 4: 3903b085044SGene Chen *addr |= MT6360_DATA_SIZE_4_BYTES; 3913b085044SGene Chen break; 3923b085044SGene Chen default: 3933b085044SGene Chen return -EINVAL; 3943b085044SGene Chen } 3953b085044SGene Chen 3963b085044SGene Chen return 0; 3973b085044SGene Chen } 3983b085044SGene Chen 3993b085044SGene Chen static int mt6360_regmap_read(void *context, const void *reg, size_t reg_size, 4003b085044SGene Chen void *val, size_t val_size) 4013b085044SGene Chen { 4023b085044SGene Chen struct mt6360_ddata *ddata = context; 4033b085044SGene Chen u8 bank = *(u8 *)reg; 4043b085044SGene Chen u8 reg_addr = *(u8 *)(reg + 1); 4053b085044SGene Chen struct i2c_client *i2c = ddata->i2c[bank]; 4063b085044SGene Chen bool crc_needed = false; 4073b085044SGene Chen u8 *buf; 4083b085044SGene Chen int buf_len = MT6360_ALLOC_READ_SIZE(val_size); 4093b085044SGene Chen int read_size = val_size; 4103b085044SGene Chen u8 crc; 4113b085044SGene Chen int ret; 4123b085044SGene Chen 4133b085044SGene Chen if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) { 4143b085044SGene Chen crc_needed = true; 4153b085044SGene Chen ret = mt6360_xlate_pmicldo_addr(®_addr, val_size); 4163b085044SGene Chen if (ret < 0) 4173b085044SGene Chen return ret; 4183b085044SGene Chen read_size += MT6360_CRC_CRC8_SIZE; 4193b085044SGene Chen } 4203b085044SGene Chen 4213b085044SGene Chen buf = kzalloc(buf_len, GFP_KERNEL); 4223b085044SGene Chen if (!buf) 4233b085044SGene Chen return -ENOMEM; 4243b085044SGene Chen 4253b085044SGene Chen buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_READ); 4263b085044SGene Chen buf[1] = reg_addr; 4273b085044SGene Chen 4283b085044SGene Chen ret = i2c_smbus_read_i2c_block_data(i2c, reg_addr, read_size, 4293b085044SGene Chen buf + MT6360_CRC_PREDATA_OFFSET); 4303b085044SGene Chen if (ret < 0) 4313b085044SGene Chen goto out; 4323b085044SGene Chen else if (ret != read_size) { 4333b085044SGene Chen ret = -EIO; 4343b085044SGene Chen goto out; 4353b085044SGene Chen } 4363b085044SGene Chen 4373b085044SGene Chen if (crc_needed) { 4383b085044SGene Chen crc = crc8(ddata->crc8_tbl, buf, val_size + MT6360_CRC_PREDATA_OFFSET, 0); 4393b085044SGene Chen if (crc != buf[val_size + MT6360_CRC_PREDATA_OFFSET]) { 4403b085044SGene Chen ret = -EIO; 4413b085044SGene Chen goto out; 4423b085044SGene Chen } 4433b085044SGene Chen } 4443b085044SGene Chen 4453b085044SGene Chen memcpy(val, buf + MT6360_CRC_PREDATA_OFFSET, val_size); 4463b085044SGene Chen out: 4473b085044SGene Chen kfree(buf); 4483b085044SGene Chen return (ret < 0) ? ret : 0; 4493b085044SGene Chen } 4503b085044SGene Chen 4513b085044SGene Chen static int mt6360_regmap_write(void *context, const void *val, size_t val_size) 4523b085044SGene Chen { 4533b085044SGene Chen struct mt6360_ddata *ddata = context; 4543b085044SGene Chen u8 bank = *(u8 *)val; 4553b085044SGene Chen u8 reg_addr = *(u8 *)(val + 1); 4563b085044SGene Chen struct i2c_client *i2c = ddata->i2c[bank]; 4573b085044SGene Chen bool crc_needed = false; 4583b085044SGene Chen u8 *buf; 4593b085044SGene Chen int buf_len = MT6360_ALLOC_WRITE_SIZE(val_size); 4603b085044SGene Chen int write_size = val_size - MT6360_REGMAP_REG_BYTE_SIZE; 4613b085044SGene Chen int ret; 4623b085044SGene Chen 4633b085044SGene Chen if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) { 4643b085044SGene Chen crc_needed = true; 4653b085044SGene Chen ret = mt6360_xlate_pmicldo_addr(®_addr, val_size - MT6360_REGMAP_REG_BYTE_SIZE); 4663b085044SGene Chen if (ret < 0) 4673b085044SGene Chen return ret; 4683b085044SGene Chen } 4693b085044SGene Chen 4703b085044SGene Chen buf = kzalloc(buf_len, GFP_KERNEL); 4713b085044SGene Chen if (!buf) 4723b085044SGene Chen return -ENOMEM; 4733b085044SGene Chen 4743b085044SGene Chen buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_WRITE); 4753b085044SGene Chen buf[1] = reg_addr; 4763b085044SGene Chen memcpy(buf + MT6360_CRC_PREDATA_OFFSET, val + MT6360_REGMAP_REG_BYTE_SIZE, write_size); 4773b085044SGene Chen 4783b085044SGene Chen if (crc_needed) { 4793b085044SGene Chen buf[val_size] = crc8(ddata->crc8_tbl, buf, val_size, 0); 4803b085044SGene Chen write_size += (MT6360_CRC_CRC8_SIZE + MT6360_CRC_DUMMY_BYTE_SIZE); 4813b085044SGene Chen } 4823b085044SGene Chen 4833b085044SGene Chen ret = i2c_smbus_write_i2c_block_data(i2c, reg_addr, write_size, 4843b085044SGene Chen buf + MT6360_CRC_PREDATA_OFFSET); 4853b085044SGene Chen 4863b085044SGene Chen kfree(buf); 4873b085044SGene Chen return ret; 4883b085044SGene Chen } 4893b085044SGene Chen 4903b085044SGene Chen static const struct regmap_bus mt6360_regmap_bus = { 4913b085044SGene Chen .read = mt6360_regmap_read, 4923b085044SGene Chen .write = mt6360_regmap_write, 4933b085044SGene Chen 4943b085044SGene Chen /* Due to PMIC and LDO CRC access size limit */ 4953b085044SGene Chen .max_raw_read = 4, 4963b085044SGene Chen .max_raw_write = 4, 4973b085044SGene Chen }; 4983b085044SGene Chen 4993b085044SGene Chen static bool mt6360_is_readwrite_reg(struct device *dev, unsigned int reg) 5003b085044SGene Chen { 5013b085044SGene Chen switch (reg) { 5023b085044SGene Chen case MT6360_REG_TCPCSTART ... MT6360_REG_TCPCEND: 5033b085044SGene Chen fallthrough; 5043b085044SGene Chen case MT6360_REG_PMICSTART ... MT6360_REG_PMICEND: 5053b085044SGene Chen fallthrough; 5063b085044SGene Chen case MT6360_REG_LDOSTART ... MT6360_REG_LDOEND: 5073b085044SGene Chen fallthrough; 5083b085044SGene Chen case MT6360_REG_PMUSTART ... MT6360_REG_PMUEND: 5093b085044SGene Chen return true; 5103b085044SGene Chen } 5113b085044SGene Chen 5123b085044SGene Chen return false; 5133b085044SGene Chen } 5143b085044SGene Chen 5153b085044SGene Chen static const struct regmap_config mt6360_regmap_config = { 5163b085044SGene Chen .reg_bits = 16, 5173b085044SGene Chen .val_bits = 8, 5183b085044SGene Chen .reg_format_endian = REGMAP_ENDIAN_BIG, 5193b085044SGene Chen .max_register = MT6360_REG_PMUEND, 5203b085044SGene Chen .writeable_reg = mt6360_is_readwrite_reg, 5213b085044SGene Chen .readable_reg = mt6360_is_readwrite_reg, 5227edd3634SGene Chen }; 5237edd3634SGene Chen 52460a90b35SGene Chen static int mt6360_probe(struct i2c_client *client) 5257edd3634SGene Chen { 526e63ce9a5SGene Chen struct mt6360_ddata *ddata; 5277edd3634SGene Chen int i, ret; 5287edd3634SGene Chen 529e63ce9a5SGene Chen ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL); 530e63ce9a5SGene Chen if (!ddata) 5317edd3634SGene Chen return -ENOMEM; 5327edd3634SGene Chen 533e63ce9a5SGene Chen ddata->dev = &client->dev; 534e63ce9a5SGene Chen i2c_set_clientdata(client, ddata); 5357edd3634SGene Chen 5363b085044SGene Chen for (i = 0; i < MT6360_SLAVE_MAX - 1; i++) { 5373b085044SGene Chen ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev, 5383b085044SGene Chen client->adapter, 5393b085044SGene Chen mt6360_slave_addr[i]); 5403b085044SGene Chen if (IS_ERR(ddata->i2c[i])) { 5413b085044SGene Chen dev_err(&client->dev, 5423b085044SGene Chen "Failed to get new dummy I2C device for address 0x%x", 5433b085044SGene Chen mt6360_slave_addr[i]); 5443b085044SGene Chen return PTR_ERR(ddata->i2c[i]); 5453b085044SGene Chen } 5463b085044SGene Chen } 5473b085044SGene Chen ddata->i2c[MT6360_SLAVE_MAX - 1] = client; 5483b085044SGene Chen 5493b085044SGene Chen crc8_populate_msb(ddata->crc8_tbl, MT6360_CRC8_POLYNOMIAL); 5503b085044SGene Chen ddata->regmap = devm_regmap_init(ddata->dev, &mt6360_regmap_bus, ddata, 5513b085044SGene Chen &mt6360_regmap_config); 552e63ce9a5SGene Chen if (IS_ERR(ddata->regmap)) { 5537edd3634SGene Chen dev_err(&client->dev, "Failed to register regmap\n"); 554e63ce9a5SGene Chen return PTR_ERR(ddata->regmap); 5557edd3634SGene Chen } 5567edd3634SGene Chen 557e8470294SGene Chen ret = mt6360_check_vendor_info(ddata); 558e8470294SGene Chen if (ret) 5597edd3634SGene Chen return ret; 5607edd3634SGene Chen 561e63ce9a5SGene Chen ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, 562a75a2d56SGene Chen 0, 0, &mt6360_irq_chip, 563a75a2d56SGene Chen &ddata->irq_data); 5647edd3634SGene Chen if (ret) { 5657edd3634SGene Chen dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); 5667edd3634SGene Chen return ret; 5677edd3634SGene Chen } 5687edd3634SGene Chen 5697edd3634SGene Chen ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 5707edd3634SGene Chen mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL, 571e63ce9a5SGene Chen 0, regmap_irq_get_domain(ddata->irq_data)); 5727edd3634SGene Chen if (ret) { 5737edd3634SGene Chen dev_err(&client->dev, 5747edd3634SGene Chen "Failed to register subordinate devices\n"); 5757edd3634SGene Chen return ret; 5767edd3634SGene Chen } 5777edd3634SGene Chen 5787edd3634SGene Chen return 0; 5797edd3634SGene Chen } 5807edd3634SGene Chen 58160a90b35SGene Chen static int __maybe_unused mt6360_suspend(struct device *dev) 5827edd3634SGene Chen { 5837edd3634SGene Chen struct i2c_client *i2c = to_i2c_client(dev); 5847edd3634SGene Chen 5857edd3634SGene Chen if (device_may_wakeup(dev)) 5867edd3634SGene Chen enable_irq_wake(i2c->irq); 5877edd3634SGene Chen 5887edd3634SGene Chen return 0; 5897edd3634SGene Chen } 5907edd3634SGene Chen 59160a90b35SGene Chen static int __maybe_unused mt6360_resume(struct device *dev) 5927edd3634SGene Chen { 5937edd3634SGene Chen 5947edd3634SGene Chen struct i2c_client *i2c = to_i2c_client(dev); 5957edd3634SGene Chen 5967edd3634SGene Chen if (device_may_wakeup(dev)) 5977edd3634SGene Chen disable_irq_wake(i2c->irq); 5987edd3634SGene Chen 5997edd3634SGene Chen return 0; 6007edd3634SGene Chen } 6017edd3634SGene Chen 60260a90b35SGene Chen static SIMPLE_DEV_PM_OPS(mt6360_pm_ops, mt6360_suspend, mt6360_resume); 6037edd3634SGene Chen 60460a90b35SGene Chen static const struct of_device_id __maybe_unused mt6360_of_id[] = { 60560a90b35SGene Chen { .compatible = "mediatek,mt6360", }, 6067edd3634SGene Chen {}, 6077edd3634SGene Chen }; 60860a90b35SGene Chen MODULE_DEVICE_TABLE(of, mt6360_of_id); 6097edd3634SGene Chen 61060a90b35SGene Chen static struct i2c_driver mt6360_driver = { 6117edd3634SGene Chen .driver = { 61260a90b35SGene Chen .name = "mt6360", 61360a90b35SGene Chen .pm = &mt6360_pm_ops, 61460a90b35SGene Chen .of_match_table = of_match_ptr(mt6360_of_id), 6157edd3634SGene Chen }, 61660a90b35SGene Chen .probe_new = mt6360_probe, 6177edd3634SGene Chen }; 61860a90b35SGene Chen module_i2c_driver(mt6360_driver); 6197edd3634SGene Chen 6207edd3634SGene Chen MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>"); 62160a90b35SGene Chen MODULE_DESCRIPTION("MT6360 I2C Driver"); 6227edd3634SGene Chen MODULE_LICENSE("GPL v2"); 623