17edd3634SGene Chen // SPDX-License-Identifier: GPL-2.0 27edd3634SGene Chen /* 37edd3634SGene Chen * Copyright (c) 2020 MediaTek Inc. 47edd3634SGene Chen * 57edd3634SGene Chen * Author: Gene Chen <gene_chen@richtek.com> 67edd3634SGene Chen */ 77edd3634SGene Chen 8137871bcSGene Chen #include <linux/crc8.h> 97edd3634SGene Chen #include <linux/i2c.h> 107edd3634SGene Chen #include <linux/init.h> 117edd3634SGene Chen #include <linux/interrupt.h> 127edd3634SGene Chen #include <linux/kernel.h> 137edd3634SGene Chen #include <linux/mfd/core.h> 147edd3634SGene Chen #include <linux/module.h> 15137871bcSGene Chen #include <linux/regmap.h> 16137871bcSGene Chen #include <linux/slab.h> 177edd3634SGene Chen 187edd3634SGene Chen #include <linux/mfd/mt6360.h> 197edd3634SGene Chen 207edd3634SGene Chen /* reg 0 -> 0 ~ 7 */ 2150e89312SGene Chen #define MT6360_CHG_TREG_EVT 4 2250e89312SGene Chen #define MT6360_CHG_AICR_EVT 5 2350e89312SGene Chen #define MT6360_CHG_MIVR_EVT 6 2450e89312SGene Chen #define MT6360_PWR_RDY_EVT 7 257edd3634SGene Chen /* REG 1 -> 8 ~ 15 */ 2650e89312SGene Chen #define MT6360_CHG_BATSYSUV_EVT 9 2750e89312SGene Chen #define MT6360_FLED_CHG_VINOVP_EVT 11 2850e89312SGene Chen #define MT6360_CHG_VSYSUV_EVT 12 2950e89312SGene Chen #define MT6360_CHG_VSYSOV_EVT 13 3050e89312SGene Chen #define MT6360_CHG_VBATOV_EVT 14 3150e89312SGene Chen #define MT6360_CHG_VBUSOV_EVT 15 327edd3634SGene Chen /* REG 2 -> 16 ~ 23 */ 337edd3634SGene Chen /* REG 3 -> 24 ~ 31 */ 3450e89312SGene Chen #define MT6360_WD_PMU_DET 25 3550e89312SGene Chen #define MT6360_WD_PMU_DONE 26 3650e89312SGene Chen #define MT6360_CHG_TMRI 27 3750e89312SGene Chen #define MT6360_CHG_ADPBADI 29 3850e89312SGene Chen #define MT6360_CHG_RVPI 30 3950e89312SGene Chen #define MT6360_OTPI 31 407edd3634SGene Chen /* REG 4 -> 32 ~ 39 */ 4150e89312SGene Chen #define MT6360_CHG_AICCMEASL 32 4250e89312SGene Chen #define MT6360_CHGDET_DONEI 34 4350e89312SGene Chen #define MT6360_WDTMRI 35 4450e89312SGene Chen #define MT6360_SSFINISHI 36 4550e89312SGene Chen #define MT6360_CHG_RECHGI 37 4650e89312SGene Chen #define MT6360_CHG_TERMI 38 4750e89312SGene Chen #define MT6360_CHG_IEOCI 39 487edd3634SGene Chen /* REG 5 -> 40 ~ 47 */ 4950e89312SGene Chen #define MT6360_PUMPX_DONEI 40 5050e89312SGene Chen #define MT6360_BAT_OVP_ADC_EVT 41 5150e89312SGene Chen #define MT6360_TYPEC_OTP_EVT 42 5250e89312SGene Chen #define MT6360_ADC_WAKEUP_EVT 43 5350e89312SGene Chen #define MT6360_ADC_DONEI 44 5450e89312SGene Chen #define MT6360_BST_BATUVI 45 5550e89312SGene Chen #define MT6360_BST_VBUSOVI 46 5650e89312SGene Chen #define MT6360_BST_OLPI 47 577edd3634SGene Chen /* REG 6 -> 48 ~ 55 */ 5850e89312SGene Chen #define MT6360_ATTACH_I 48 5950e89312SGene Chen #define MT6360_DETACH_I 49 6050e89312SGene Chen #define MT6360_QC30_STPDONE 51 6150e89312SGene Chen #define MT6360_QC_VBUSDET_DONE 52 6250e89312SGene Chen #define MT6360_HVDCP_DET 53 6350e89312SGene Chen #define MT6360_CHGDETI 54 6450e89312SGene Chen #define MT6360_DCDTI 55 657edd3634SGene Chen /* REG 7 -> 56 ~ 63 */ 6650e89312SGene Chen #define MT6360_FOD_DONE_EVT 56 6750e89312SGene Chen #define MT6360_FOD_OV_EVT 57 6850e89312SGene Chen #define MT6360_CHRDET_UVP_EVT 58 6950e89312SGene Chen #define MT6360_CHRDET_OVP_EVT 59 7050e89312SGene Chen #define MT6360_CHRDET_EXT_EVT 60 7150e89312SGene Chen #define MT6360_FOD_LR_EVT 61 7250e89312SGene Chen #define MT6360_FOD_HR_EVT 62 7350e89312SGene Chen #define MT6360_FOD_DISCHG_FAIL_EVT 63 747edd3634SGene Chen /* REG 8 -> 64 ~ 71 */ 7550e89312SGene Chen #define MT6360_USBID_EVT 64 7650e89312SGene Chen #define MT6360_APWDTRST_EVT 65 7750e89312SGene Chen #define MT6360_EN_EVT 66 7850e89312SGene Chen #define MT6360_QONB_RST_EVT 67 7950e89312SGene Chen #define MT6360_MRSTB_EVT 68 8050e89312SGene Chen #define MT6360_OTP_EVT 69 8150e89312SGene Chen #define MT6360_VDDAOV_EVT 70 8250e89312SGene Chen #define MT6360_SYSUV_EVT 71 837edd3634SGene Chen /* REG 9 -> 72 ~ 79 */ 8450e89312SGene Chen #define MT6360_FLED_STRBPIN_EVT 72 8550e89312SGene Chen #define MT6360_FLED_TORPIN_EVT 73 8650e89312SGene Chen #define MT6360_FLED_TX_EVT 74 8750e89312SGene Chen #define MT6360_FLED_LVF_EVT 75 8850e89312SGene Chen #define MT6360_FLED2_SHORT_EVT 78 8950e89312SGene Chen #define MT6360_FLED1_SHORT_EVT 79 907edd3634SGene Chen /* REG 10 -> 80 ~ 87 */ 9150e89312SGene Chen #define MT6360_FLED2_STRB_EVT 80 9250e89312SGene Chen #define MT6360_FLED1_STRB_EVT 81 9350e89312SGene Chen #define MT6360_FLED2_STRB_TO_EVT 82 9450e89312SGene Chen #define MT6360_FLED1_STRB_TO_EVT 83 9550e89312SGene Chen #define MT6360_FLED2_TOR_EVT 84 9650e89312SGene Chen #define MT6360_FLED1_TOR_EVT 85 977edd3634SGene Chen /* REG 11 -> 88 ~ 95 */ 987edd3634SGene Chen /* REG 12 -> 96 ~ 103 */ 9950e89312SGene Chen #define MT6360_BUCK1_PGB_EVT 96 10050e89312SGene Chen #define MT6360_BUCK1_OC_EVT 100 10150e89312SGene Chen #define MT6360_BUCK1_OV_EVT 101 10250e89312SGene Chen #define MT6360_BUCK1_UV_EVT 102 1037edd3634SGene Chen /* REG 13 -> 104 ~ 111 */ 10450e89312SGene Chen #define MT6360_BUCK2_PGB_EVT 104 10550e89312SGene Chen #define MT6360_BUCK2_OC_EVT 108 10650e89312SGene Chen #define MT6360_BUCK2_OV_EVT 109 10750e89312SGene Chen #define MT6360_BUCK2_UV_EVT 110 1087edd3634SGene Chen /* REG 14 -> 112 ~ 119 */ 10950e89312SGene Chen #define MT6360_LDO1_OC_EVT 113 11050e89312SGene Chen #define MT6360_LDO2_OC_EVT 114 11150e89312SGene Chen #define MT6360_LDO3_OC_EVT 115 11250e89312SGene Chen #define MT6360_LDO5_OC_EVT 117 11350e89312SGene Chen #define MT6360_LDO6_OC_EVT 118 11450e89312SGene Chen #define MT6360_LDO7_OC_EVT 119 1157edd3634SGene Chen /* REG 15 -> 120 ~ 127 */ 11650e89312SGene Chen #define MT6360_LDO1_PGB_EVT 121 11750e89312SGene Chen #define MT6360_LDO2_PGB_EVT 122 11850e89312SGene Chen #define MT6360_LDO3_PGB_EVT 123 11950e89312SGene Chen #define MT6360_LDO5_PGB_EVT 125 12050e89312SGene Chen #define MT6360_LDO6_PGB_EVT 126 12150e89312SGene Chen #define MT6360_LDO7_PGB_EVT 127 1227edd3634SGene Chen 123*60a90b35SGene Chen static const struct regmap_irq mt6360_irqs[] = { 1247edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8), 1257edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8), 1267edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8), 1277edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_PWR_RDY_EVT, 8), 1287edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_BATSYSUV_EVT, 8), 1297edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_CHG_VINOVP_EVT, 8), 1307edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSUV_EVT, 8), 1317edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSOV_EVT, 8), 1327edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VBATOV_EVT, 8), 1337edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_VBUSOV_EVT, 8), 1347edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DET, 8), 1357edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DONE, 8), 1367edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_TMRI, 8), 1377edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_ADPBADI, 8), 1387edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_RVPI, 8), 1397edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_OTPI, 8), 1407edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_AICCMEASL, 8), 1417edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHGDET_DONEI, 8), 1427edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_WDTMRI, 8), 1437edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_SSFINISHI, 8), 1447edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_RECHGI, 8), 1457edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_TERMI, 8), 1467edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHG_IEOCI, 8), 1477edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_PUMPX_DONEI, 8), 1487edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BAT_OVP_ADC_EVT, 8), 1497edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_TYPEC_OTP_EVT, 8), 1507edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_ADC_WAKEUP_EVT, 8), 1517edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_ADC_DONEI, 8), 1527edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BST_BATUVI, 8), 1537edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BST_VBUSOVI, 8), 1547edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BST_OLPI, 8), 1557edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_ATTACH_I, 8), 1567edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_DETACH_I, 8), 1577edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_QC30_STPDONE, 8), 1587edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_QC_VBUSDET_DONE, 8), 1597edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_HVDCP_DET, 8), 1607edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHGDETI, 8), 1617edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_DCDTI, 8), 1627edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_DONE_EVT, 8), 1637edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_OV_EVT, 8), 1647edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHRDET_UVP_EVT, 8), 1657edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHRDET_OVP_EVT, 8), 1667edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_CHRDET_EXT_EVT, 8), 1677edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_LR_EVT, 8), 1687edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_HR_EVT, 8), 1697edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FOD_DISCHG_FAIL_EVT, 8), 1707edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_USBID_EVT, 8), 1717edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_APWDTRST_EVT, 8), 1727edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_EN_EVT, 8), 1737edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_QONB_RST_EVT, 8), 1747edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_MRSTB_EVT, 8), 1757edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_OTP_EVT, 8), 1767edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_VDDAOV_EVT, 8), 1777edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_SYSUV_EVT, 8), 1787edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_STRBPIN_EVT, 8), 1797edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_TORPIN_EVT, 8), 1807edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_TX_EVT, 8), 1817edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED_LVF_EVT, 8), 1827edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_SHORT_EVT, 8), 1837edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_SHORT_EVT, 8), 1847edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_EVT, 8), 1857edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_EVT, 8), 1867edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_TO_EVT, 8), 1877edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_TO_EVT, 8), 1887edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED2_TOR_EVT, 8), 1897edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_FLED1_TOR_EVT, 8), 1907edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_PGB_EVT, 8), 1917edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OC_EVT, 8), 1927edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OV_EVT, 8), 1937edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK1_UV_EVT, 8), 1947edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_PGB_EVT, 8), 1957edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OC_EVT, 8), 1967edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OV_EVT, 8), 1977edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_BUCK2_UV_EVT, 8), 1987edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO1_OC_EVT, 8), 1997edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO2_OC_EVT, 8), 2007edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO3_OC_EVT, 8), 2017edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO5_OC_EVT, 8), 2027edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO6_OC_EVT, 8), 2037edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO7_OC_EVT, 8), 2047edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO1_PGB_EVT, 8), 2057edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO2_PGB_EVT, 8), 2067edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO3_PGB_EVT, 8), 2077edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO5_PGB_EVT, 8), 2087edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO6_PGB_EVT, 8), 2097edd3634SGene Chen REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8), 2107edd3634SGene Chen }; 2117edd3634SGene Chen 2127edd3634SGene Chen static int mt6360_pmu_handle_post_irq(void *irq_drv_data) 2137edd3634SGene Chen { 214e63ce9a5SGene Chen struct mt6360_ddata *ddata = irq_drv_data; 2157edd3634SGene Chen 216e63ce9a5SGene Chen return regmap_update_bits(ddata->regmap, 2177edd3634SGene Chen MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG); 2187edd3634SGene Chen } 2197edd3634SGene Chen 220*60a90b35SGene Chen static struct regmap_irq_chip mt6360_irq_chip = { 221*60a90b35SGene Chen .irqs = mt6360_irqs, 222*60a90b35SGene Chen .num_irqs = ARRAY_SIZE(mt6360_irqs), 2237edd3634SGene Chen .num_regs = MT6360_PMU_IRQ_REGNUM, 2247edd3634SGene Chen .mask_base = MT6360_PMU_CHG_MASK1, 2257edd3634SGene Chen .status_base = MT6360_PMU_CHG_IRQ1, 2267edd3634SGene Chen .ack_base = MT6360_PMU_CHG_IRQ1, 2277edd3634SGene Chen .init_ack_masked = true, 2287edd3634SGene Chen .use_ack = true, 2297edd3634SGene Chen .handle_post_irq = mt6360_pmu_handle_post_irq, 2307edd3634SGene Chen }; 2317edd3634SGene Chen 2327edd3634SGene Chen static const struct regmap_config mt6360_pmu_regmap_config = { 2337edd3634SGene Chen .reg_bits = 8, 2347edd3634SGene Chen .val_bits = 8, 2357edd3634SGene Chen .max_register = MT6360_PMU_MAXREG, 2367edd3634SGene Chen }; 2377edd3634SGene Chen 2387edd3634SGene Chen static const struct resource mt6360_adc_resources[] = { 2397edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"), 2407edd3634SGene Chen }; 2417edd3634SGene Chen 2427edd3634SGene Chen static const struct resource mt6360_chg_resources[] = { 2437edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"), 2447edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"), 2457edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, "chg_batsysuv_evt"), 2467edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"), 2477edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"), 2487edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"), 2497edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"), 2507edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"), 2517edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"), 2527edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"), 2537edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"), 2547edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"), 2557edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"), 2567edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"), 2577edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"), 2587edd3634SGene Chen }; 2597edd3634SGene Chen 2607edd3634SGene Chen static const struct resource mt6360_led_resources[] = { 2617edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, "fled_chg_vinovp_evt"), 2627edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"), 2637edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"), 2647edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"), 2657edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, "fled2_strb_to_evt"), 2667edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"), 2677edd3634SGene Chen }; 2687edd3634SGene Chen 2694ee06e10SGene Chen static const struct resource mt6360_regulator_resources[] = { 2707edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"), 2717edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"), 2727edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"), 2737edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"), 2747edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"), 2757edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"), 2767edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"), 2777edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"), 2787edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"), 2797edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), 2807edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), 2817edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), 2827edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), 2837edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), 2847edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), 2857edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"), 2867edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"), 2877edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"), 2887edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"), 2897edd3634SGene Chen DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"), 2907edd3634SGene Chen }; 2917edd3634SGene Chen 2927edd3634SGene Chen static const struct mfd_cell mt6360_devs[] = { 29312f3f131SGene Chen MFD_CELL_OF("mt6360-adc", mt6360_adc_resources, 29412f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-adc"), 29512f3f131SGene Chen MFD_CELL_OF("mt6360-chg", mt6360_chg_resources, 29612f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-chg"), 29712f3f131SGene Chen MFD_CELL_OF("mt6360-led", mt6360_led_resources, 29812f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-led"), 2994ee06e10SGene Chen MFD_CELL_RES("mt6360-regulator", mt6360_regulator_resources), 30012f3f131SGene Chen MFD_CELL_OF("mt6360-tcpc", NULL, 30112f3f131SGene Chen NULL, 0, 0, "mediatek,mt6360-tcpc"), 3027edd3634SGene Chen }; 3037edd3634SGene Chen 3047edd3634SGene Chen static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { 3057edd3634SGene Chen MT6360_PMU_SLAVEID, 3067edd3634SGene Chen MT6360_PMIC_SLAVEID, 3077edd3634SGene Chen MT6360_LDO_SLAVEID, 3087edd3634SGene Chen MT6360_TCPC_SLAVEID, 3097edd3634SGene Chen }; 3107edd3634SGene Chen 311*60a90b35SGene Chen static int mt6360_probe(struct i2c_client *client) 3127edd3634SGene Chen { 313e63ce9a5SGene Chen struct mt6360_ddata *ddata; 3147edd3634SGene Chen unsigned int reg_data; 3157edd3634SGene Chen int i, ret; 3167edd3634SGene Chen 317e63ce9a5SGene Chen ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL); 318e63ce9a5SGene Chen if (!ddata) 3197edd3634SGene Chen return -ENOMEM; 3207edd3634SGene Chen 321e63ce9a5SGene Chen ddata->dev = &client->dev; 322e63ce9a5SGene Chen i2c_set_clientdata(client, ddata); 3237edd3634SGene Chen 324e63ce9a5SGene Chen ddata->regmap = devm_regmap_init_i2c(client, &mt6360_pmu_regmap_config); 325e63ce9a5SGene Chen if (IS_ERR(ddata->regmap)) { 3267edd3634SGene Chen dev_err(&client->dev, "Failed to register regmap\n"); 327e63ce9a5SGene Chen return PTR_ERR(ddata->regmap); 3287edd3634SGene Chen } 3297edd3634SGene Chen 330e63ce9a5SGene Chen ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, ®_data); 3317edd3634SGene Chen if (ret) { 3327edd3634SGene Chen dev_err(&client->dev, "Device not found\n"); 3337edd3634SGene Chen return ret; 3347edd3634SGene Chen } 3357edd3634SGene Chen 336e63ce9a5SGene Chen ddata->chip_rev = reg_data & CHIP_REV_MASK; 337e63ce9a5SGene Chen if (ddata->chip_rev != CHIP_VEN_MT6360) { 3387edd3634SGene Chen dev_err(&client->dev, "Device not supported\n"); 3397edd3634SGene Chen return -ENODEV; 3407edd3634SGene Chen } 3417edd3634SGene Chen 342*60a90b35SGene Chen mt6360_irq_chip.irq_drv_data = ddata; 343e63ce9a5SGene Chen ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, 3447edd3634SGene Chen IRQF_TRIGGER_FALLING, 0, 345*60a90b35SGene Chen &mt6360_irq_chip, &ddata->irq_data); 3467edd3634SGene Chen if (ret) { 3477edd3634SGene Chen dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); 3487edd3634SGene Chen return ret; 3497edd3634SGene Chen } 3507edd3634SGene Chen 351e63ce9a5SGene Chen ddata->i2c[0] = client; 3527edd3634SGene Chen for (i = 1; i < MT6360_SLAVE_MAX; i++) { 353e63ce9a5SGene Chen ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev, 3547edd3634SGene Chen client->adapter, 3557edd3634SGene Chen mt6360_slave_addr[i]); 356e63ce9a5SGene Chen if (IS_ERR(ddata->i2c[i])) { 3577edd3634SGene Chen dev_err(&client->dev, 3587edd3634SGene Chen "Failed to get new dummy I2C device for address 0x%x", 3597edd3634SGene Chen mt6360_slave_addr[i]); 360e63ce9a5SGene Chen return PTR_ERR(ddata->i2c[i]); 3617edd3634SGene Chen } 362e63ce9a5SGene Chen i2c_set_clientdata(ddata->i2c[i], ddata); 3637edd3634SGene Chen } 3647edd3634SGene Chen 3657edd3634SGene Chen ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 3667edd3634SGene Chen mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL, 367e63ce9a5SGene Chen 0, regmap_irq_get_domain(ddata->irq_data)); 3687edd3634SGene Chen if (ret) { 3697edd3634SGene Chen dev_err(&client->dev, 3707edd3634SGene Chen "Failed to register subordinate devices\n"); 3717edd3634SGene Chen return ret; 3727edd3634SGene Chen } 3737edd3634SGene Chen 3747edd3634SGene Chen return 0; 3757edd3634SGene Chen } 3767edd3634SGene Chen 377*60a90b35SGene Chen static int __maybe_unused mt6360_suspend(struct device *dev) 3787edd3634SGene Chen { 3797edd3634SGene Chen struct i2c_client *i2c = to_i2c_client(dev); 3807edd3634SGene Chen 3817edd3634SGene Chen if (device_may_wakeup(dev)) 3827edd3634SGene Chen enable_irq_wake(i2c->irq); 3837edd3634SGene Chen 3847edd3634SGene Chen return 0; 3857edd3634SGene Chen } 3867edd3634SGene Chen 387*60a90b35SGene Chen static int __maybe_unused mt6360_resume(struct device *dev) 3887edd3634SGene Chen { 3897edd3634SGene Chen 3907edd3634SGene Chen struct i2c_client *i2c = to_i2c_client(dev); 3917edd3634SGene Chen 3927edd3634SGene Chen if (device_may_wakeup(dev)) 3937edd3634SGene Chen disable_irq_wake(i2c->irq); 3947edd3634SGene Chen 3957edd3634SGene Chen return 0; 3967edd3634SGene Chen } 3977edd3634SGene Chen 398*60a90b35SGene Chen static SIMPLE_DEV_PM_OPS(mt6360_pm_ops, mt6360_suspend, mt6360_resume); 3997edd3634SGene Chen 400*60a90b35SGene Chen static const struct of_device_id __maybe_unused mt6360_of_id[] = { 401*60a90b35SGene Chen { .compatible = "mediatek,mt6360", }, 4027edd3634SGene Chen {}, 4037edd3634SGene Chen }; 404*60a90b35SGene Chen MODULE_DEVICE_TABLE(of, mt6360_of_id); 4057edd3634SGene Chen 406*60a90b35SGene Chen static struct i2c_driver mt6360_driver = { 4077edd3634SGene Chen .driver = { 408*60a90b35SGene Chen .name = "mt6360", 409*60a90b35SGene Chen .pm = &mt6360_pm_ops, 410*60a90b35SGene Chen .of_match_table = of_match_ptr(mt6360_of_id), 4117edd3634SGene Chen }, 412*60a90b35SGene Chen .probe_new = mt6360_probe, 4137edd3634SGene Chen }; 414*60a90b35SGene Chen module_i2c_driver(mt6360_driver); 4157edd3634SGene Chen 4167edd3634SGene Chen MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>"); 417*60a90b35SGene Chen MODULE_DESCRIPTION("MT6360 I2C Driver"); 4187edd3634SGene Chen MODULE_LICENSE("GPL v2"); 419