1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2020 MediaTek Inc. 4 5 #include <linux/interrupt.h> 6 #include <linux/mfd/mt6358/core.h> 7 #include <linux/mfd/mt6358/registers.h> 8 #include <linux/mfd/mt6359/core.h> 9 #include <linux/mfd/mt6359/registers.h> 10 #include <linux/mfd/mt6397/core.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 18 #define MTK_PMIC_REG_WIDTH 16 19 20 static const struct irq_top_t mt6358_ints[] = { 21 MT6358_TOP_GEN(BUCK), 22 MT6358_TOP_GEN(LDO), 23 MT6358_TOP_GEN(PSC), 24 MT6358_TOP_GEN(SCK), 25 MT6358_TOP_GEN(BM), 26 MT6358_TOP_GEN(HK), 27 MT6358_TOP_GEN(AUD), 28 MT6358_TOP_GEN(MISC), 29 }; 30 31 static const struct irq_top_t mt6359_ints[] = { 32 MT6359_TOP_GEN(BUCK), 33 MT6359_TOP_GEN(LDO), 34 MT6359_TOP_GEN(PSC), 35 MT6359_TOP_GEN(SCK), 36 MT6359_TOP_GEN(BM), 37 MT6359_TOP_GEN(HK), 38 MT6359_TOP_GEN(AUD), 39 MT6359_TOP_GEN(MISC), 40 }; 41 42 static struct pmic_irq_data mt6358_irqd = { 43 .num_top = ARRAY_SIZE(mt6358_ints), 44 .num_pmic_irqs = MT6358_IRQ_NR, 45 .top_int_status_reg = MT6358_TOP_INT_STATUS0, 46 .pmic_ints = mt6358_ints, 47 }; 48 49 static struct pmic_irq_data mt6359_irqd = { 50 .num_top = ARRAY_SIZE(mt6359_ints), 51 .num_pmic_irqs = MT6359_IRQ_NR, 52 .top_int_status_reg = MT6359_TOP_INT_STATUS0, 53 .pmic_ints = mt6359_ints, 54 }; 55 56 static void pmic_irq_enable(struct irq_data *data) 57 { 58 unsigned int hwirq = irqd_to_hwirq(data); 59 struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); 60 struct pmic_irq_data *irqd = chip->irq_data; 61 62 irqd->enable_hwirq[hwirq] = true; 63 } 64 65 static void pmic_irq_disable(struct irq_data *data) 66 { 67 unsigned int hwirq = irqd_to_hwirq(data); 68 struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); 69 struct pmic_irq_data *irqd = chip->irq_data; 70 71 irqd->enable_hwirq[hwirq] = false; 72 } 73 74 static void pmic_irq_lock(struct irq_data *data) 75 { 76 struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); 77 78 mutex_lock(&chip->irqlock); 79 } 80 81 static void pmic_irq_sync_unlock(struct irq_data *data) 82 { 83 unsigned int i, top_gp, gp_offset, en_reg, int_regs, shift; 84 struct mt6397_chip *chip = irq_data_get_irq_chip_data(data); 85 struct pmic_irq_data *irqd = chip->irq_data; 86 87 for (i = 0; i < irqd->num_pmic_irqs; i++) { 88 if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i]) 89 continue; 90 91 /* Find out the IRQ group */ 92 top_gp = 0; 93 while ((top_gp + 1) < irqd->num_top && 94 i >= irqd->pmic_ints[top_gp + 1].hwirq_base) 95 top_gp++; 96 97 /* Find the IRQ registers */ 98 gp_offset = i - irqd->pmic_ints[top_gp].hwirq_base; 99 int_regs = gp_offset / MTK_PMIC_REG_WIDTH; 100 shift = gp_offset % MTK_PMIC_REG_WIDTH; 101 en_reg = irqd->pmic_ints[top_gp].en_reg + 102 (irqd->pmic_ints[top_gp].en_reg_shift * int_regs); 103 104 regmap_update_bits(chip->regmap, en_reg, BIT(shift), 105 irqd->enable_hwirq[i] << shift); 106 107 irqd->cache_hwirq[i] = irqd->enable_hwirq[i]; 108 } 109 mutex_unlock(&chip->irqlock); 110 } 111 112 static struct irq_chip mt6358_irq_chip = { 113 .name = "mt6358-irq", 114 .flags = IRQCHIP_SKIP_SET_WAKE, 115 .irq_enable = pmic_irq_enable, 116 .irq_disable = pmic_irq_disable, 117 .irq_bus_lock = pmic_irq_lock, 118 .irq_bus_sync_unlock = pmic_irq_sync_unlock, 119 }; 120 121 static void mt6358_irq_sp_handler(struct mt6397_chip *chip, 122 unsigned int top_gp) 123 { 124 unsigned int irq_status, sta_reg, status; 125 unsigned int hwirq, virq; 126 int i, j, ret; 127 struct pmic_irq_data *irqd = chip->irq_data; 128 129 for (i = 0; i < irqd->pmic_ints[top_gp].num_int_regs; i++) { 130 sta_reg = irqd->pmic_ints[top_gp].sta_reg + 131 irqd->pmic_ints[top_gp].sta_reg_shift * i; 132 133 ret = regmap_read(chip->regmap, sta_reg, &irq_status); 134 if (ret) { 135 dev_err(chip->dev, 136 "Failed to read IRQ status, ret=%d\n", ret); 137 return; 138 } 139 140 if (!irq_status) 141 continue; 142 143 status = irq_status; 144 do { 145 j = __ffs(status); 146 147 hwirq = irqd->pmic_ints[top_gp].hwirq_base + 148 MTK_PMIC_REG_WIDTH * i + j; 149 150 virq = irq_find_mapping(chip->irq_domain, hwirq); 151 if (virq) 152 handle_nested_irq(virq); 153 154 status &= ~BIT(j); 155 } while (status); 156 157 regmap_write(chip->regmap, sta_reg, irq_status); 158 } 159 } 160 161 static irqreturn_t mt6358_irq_handler(int irq, void *data) 162 { 163 struct mt6397_chip *chip = data; 164 struct pmic_irq_data *irqd = chip->irq_data; 165 unsigned int bit, i, top_irq_status = 0; 166 int ret; 167 168 ret = regmap_read(chip->regmap, 169 irqd->top_int_status_reg, 170 &top_irq_status); 171 if (ret) { 172 dev_err(chip->dev, 173 "Failed to read status from the device, ret=%d\n", ret); 174 return IRQ_NONE; 175 } 176 177 for (i = 0; i < irqd->num_top; i++) { 178 bit = BIT(irqd->pmic_ints[i].top_offset); 179 if (top_irq_status & bit) { 180 mt6358_irq_sp_handler(chip, i); 181 top_irq_status &= ~bit; 182 if (!top_irq_status) 183 break; 184 } 185 } 186 187 return IRQ_HANDLED; 188 } 189 190 static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq, 191 irq_hw_number_t hw) 192 { 193 struct mt6397_chip *mt6397 = d->host_data; 194 195 irq_set_chip_data(irq, mt6397); 196 irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq); 197 irq_set_nested_thread(irq, 1); 198 irq_set_noprobe(irq); 199 200 return 0; 201 } 202 203 static const struct irq_domain_ops mt6358_irq_domain_ops = { 204 .map = pmic_irq_domain_map, 205 .xlate = irq_domain_xlate_twocell, 206 }; 207 208 int mt6358_irq_init(struct mt6397_chip *chip) 209 { 210 int i, j, ret; 211 struct pmic_irq_data *irqd; 212 213 switch (chip->chip_id) { 214 case MT6358_CHIP_ID: 215 case MT6366_CHIP_ID: 216 chip->irq_data = &mt6358_irqd; 217 break; 218 219 case MT6359_CHIP_ID: 220 chip->irq_data = &mt6359_irqd; 221 break; 222 223 default: 224 dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id); 225 return -ENODEV; 226 } 227 228 mutex_init(&chip->irqlock); 229 irqd = chip->irq_data; 230 irqd->enable_hwirq = devm_kcalloc(chip->dev, 231 irqd->num_pmic_irqs, 232 sizeof(*irqd->enable_hwirq), 233 GFP_KERNEL); 234 if (!irqd->enable_hwirq) 235 return -ENOMEM; 236 237 irqd->cache_hwirq = devm_kcalloc(chip->dev, 238 irqd->num_pmic_irqs, 239 sizeof(*irqd->cache_hwirq), 240 GFP_KERNEL); 241 if (!irqd->cache_hwirq) 242 return -ENOMEM; 243 244 /* Disable all interrupts for initializing */ 245 for (i = 0; i < irqd->num_top; i++) { 246 for (j = 0; j < irqd->pmic_ints[i].num_int_regs; j++) 247 regmap_write(chip->regmap, 248 irqd->pmic_ints[i].en_reg + 249 irqd->pmic_ints[i].en_reg_shift * j, 0); 250 } 251 252 chip->irq_domain = irq_domain_add_linear(chip->dev->of_node, 253 irqd->num_pmic_irqs, 254 &mt6358_irq_domain_ops, chip); 255 if (!chip->irq_domain) { 256 dev_err(chip->dev, "Could not create IRQ domain\n"); 257 return -ENODEV; 258 } 259 260 ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL, 261 mt6358_irq_handler, IRQF_ONESHOT, 262 mt6358_irq_chip.name, chip); 263 if (ret) { 264 dev_err(chip->dev, "Failed to register IRQ=%d, ret=%d\n", 265 chip->irq, ret); 266 return ret; 267 } 268 269 enable_irq_wake(chip->irq); 270 return ret; 271 } 272