1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // max8997-irq.c - Interrupt controller support for MAX8997 4 // 5 // Copyright (C) 2011 Samsung Electronics Co.Ltd 6 // MyungJoo Ham <myungjoo.ham@samsung.com> 7 // 8 // This driver is based on max8998-irq.c 9 10 #include <linux/err.h> 11 #include <linux/irq.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/max8997.h> 14 #include <linux/mfd/max8997-private.h> 15 16 static const u8 max8997_mask_reg[] = { 17 [PMIC_INT1] = MAX8997_REG_INT1MSK, 18 [PMIC_INT2] = MAX8997_REG_INT2MSK, 19 [PMIC_INT3] = MAX8997_REG_INT3MSK, 20 [PMIC_INT4] = MAX8997_REG_INT4MSK, 21 [FUEL_GAUGE] = MAX8997_REG_INVALID, 22 [MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1, 23 [MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2, 24 [MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3, 25 [GPIO_LOW] = MAX8997_REG_INVALID, 26 [GPIO_HI] = MAX8997_REG_INVALID, 27 [FLASH_STATUS] = MAX8997_REG_INVALID, 28 }; 29 30 static struct i2c_client *get_i2c(struct max8997_dev *max8997, 31 enum max8997_irq_source src) 32 { 33 switch (src) { 34 case PMIC_INT1 ... PMIC_INT4: 35 return max8997->i2c; 36 case FUEL_GAUGE: 37 return NULL; 38 case MUIC_INT1 ... MUIC_INT3: 39 return max8997->muic; 40 case GPIO_LOW ... GPIO_HI: 41 return max8997->i2c; 42 case FLASH_STATUS: 43 return max8997->i2c; 44 default: 45 return ERR_PTR(-EINVAL); 46 } 47 } 48 49 struct max8997_irq_data { 50 int mask; 51 enum max8997_irq_source group; 52 }; 53 54 #define DECLARE_IRQ(idx, _group, _mask) \ 55 [(idx)] = { .group = (_group), .mask = (_mask) } 56 static const struct max8997_irq_data max8997_irqs[] = { 57 DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0), 58 DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1), 59 DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3), 60 DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4), 61 DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5), 62 DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6), 63 DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7), 64 65 DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0), 66 DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1), 67 DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2), 68 DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3), 69 DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4), 70 DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5), 71 DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6), 72 73 DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0), 74 DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM, PMIC_INT3, 1 << 1), 75 DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP, PMIC_INT3, 1 << 2), 76 DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR, PMIC_INT3, 1 << 3), 77 DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF, PMIC_INT3, 1 << 5), 78 DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD, PMIC_INT3, 1 << 7), 79 80 DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0), 81 DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1, PMIC_INT4, 1 << 1), 82 DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2, PMIC_INT4, 1 << 2), 83 DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT, PMIC_INT4, 1 << 3), 84 DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S, PMIC_INT4, 1 << 4), 85 DECLARE_IRQ(MAX8997_PMICIRQ_WTSR, PMIC_INT4, 1 << 5), 86 87 DECLARE_IRQ(MAX8997_MUICIRQ_ADCError, MUIC_INT1, 1 << 2), 88 DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1), 89 DECLARE_IRQ(MAX8997_MUICIRQ_ADC, MUIC_INT1, 1 << 0), 90 91 DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4), 92 DECLARE_IRQ(MAX8997_MUICIRQ_DBChg, MUIC_INT2, 1 << 3), 93 DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2), 94 DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun, MUIC_INT2, 1 << 1), 95 DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0), 96 97 DECLARE_IRQ(MAX8997_MUICIRQ_OVP, MUIC_INT3, 1 << 2), 98 }; 99 100 static void max8997_irq_lock(struct irq_data *data) 101 { 102 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 103 104 mutex_lock(&max8997->irqlock); 105 } 106 107 static void max8997_irq_sync_unlock(struct irq_data *data) 108 { 109 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 110 int i; 111 112 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) { 113 u8 mask_reg = max8997_mask_reg[i]; 114 struct i2c_client *i2c = get_i2c(max8997, i); 115 116 if (mask_reg == MAX8997_REG_INVALID || 117 IS_ERR_OR_NULL(i2c)) 118 continue; 119 max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i]; 120 121 max8997_write_reg(i2c, max8997_mask_reg[i], 122 max8997->irq_masks_cur[i]); 123 } 124 125 mutex_unlock(&max8997->irqlock); 126 } 127 128 inline static const struct max8997_irq_data * 129 irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data) 130 { 131 return &max8997_irqs[data->hwirq]; 132 } 133 134 static void max8997_irq_mask(struct irq_data *data) 135 { 136 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 137 const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997, 138 data); 139 140 max8997->irq_masks_cur[irq_data->group] |= irq_data->mask; 141 } 142 143 static void max8997_irq_unmask(struct irq_data *data) 144 { 145 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 146 const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997, 147 data); 148 149 max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask; 150 } 151 152 static struct irq_chip max8997_irq_chip = { 153 .name = "max8997", 154 .irq_bus_lock = max8997_irq_lock, 155 .irq_bus_sync_unlock = max8997_irq_sync_unlock, 156 .irq_mask = max8997_irq_mask, 157 .irq_unmask = max8997_irq_unmask, 158 }; 159 160 #define MAX8997_IRQSRC_PMIC (1 << 1) 161 #define MAX8997_IRQSRC_FUELGAUGE (1 << 2) 162 #define MAX8997_IRQSRC_MUIC (1 << 3) 163 #define MAX8997_IRQSRC_GPIO (1 << 4) 164 #define MAX8997_IRQSRC_FLASH (1 << 5) 165 static irqreturn_t max8997_irq_thread(int irq, void *data) 166 { 167 struct max8997_dev *max8997 = data; 168 u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {}; 169 u8 irq_src; 170 int ret; 171 int i, cur_irq; 172 173 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src); 174 if (ret < 0) { 175 dev_err(max8997->dev, "Failed to read interrupt source: %d\n", 176 ret); 177 return IRQ_NONE; 178 } 179 180 if (irq_src & MAX8997_IRQSRC_PMIC) { 181 /* PMIC INT1 ~ INT4 */ 182 max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4, 183 &irq_reg[PMIC_INT1]); 184 } 185 if (irq_src & MAX8997_IRQSRC_FUELGAUGE) { 186 /* 187 * TODO: FUEL GAUGE 188 * 189 * This is to be supported by Max17042 driver. When 190 * an interrupt incurs here, it should be relayed to a 191 * Max17042 device that is connected (probably by 192 * platform-data). However, we do not have interrupt 193 * handling in Max17042 driver currently. The Max17042 IRQ 194 * driver should be ready to be used as a stand-alone device and 195 * a Max8997-dependent device. Because it is not ready in 196 * Max17042-side and it is not too critical in operating 197 * Max8997, we do not implement this in initial releases. 198 */ 199 irq_reg[FUEL_GAUGE] = 0; 200 } 201 if (irq_src & MAX8997_IRQSRC_MUIC) { 202 /* MUIC INT1 ~ INT3 */ 203 max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3, 204 &irq_reg[MUIC_INT1]); 205 } 206 if (irq_src & MAX8997_IRQSRC_GPIO) { 207 /* GPIO Interrupt */ 208 u8 gpio_info[MAX8997_NUM_GPIO]; 209 210 irq_reg[GPIO_LOW] = 0; 211 irq_reg[GPIO_HI] = 0; 212 213 max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1, 214 MAX8997_NUM_GPIO, gpio_info); 215 for (i = 0; i < MAX8997_NUM_GPIO; i++) { 216 bool interrupt = false; 217 218 switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) { 219 case MAX8997_GPIO_INT_BOTH: 220 if (max8997->gpio_status[i] != gpio_info[i]) 221 interrupt = true; 222 break; 223 case MAX8997_GPIO_INT_RISE: 224 if ((max8997->gpio_status[i] != gpio_info[i]) && 225 (gpio_info[i] & MAX8997_GPIO_DATA_MASK)) 226 interrupt = true; 227 break; 228 case MAX8997_GPIO_INT_FALL: 229 if ((max8997->gpio_status[i] != gpio_info[i]) && 230 !(gpio_info[i] & MAX8997_GPIO_DATA_MASK)) 231 interrupt = true; 232 break; 233 default: 234 break; 235 } 236 237 if (interrupt) { 238 if (i < 8) 239 irq_reg[GPIO_LOW] |= (1 << i); 240 else 241 irq_reg[GPIO_HI] |= (1 << (i - 8)); 242 } 243 244 } 245 } 246 if (irq_src & MAX8997_IRQSRC_FLASH) { 247 /* Flash Status Interrupt */ 248 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS, 249 &irq_reg[FLASH_STATUS]); 250 } 251 252 /* Apply masking */ 253 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) 254 irq_reg[i] &= ~max8997->irq_masks_cur[i]; 255 256 /* Report */ 257 for (i = 0; i < MAX8997_IRQ_NR; i++) { 258 if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) { 259 cur_irq = irq_find_mapping(max8997->irq_domain, i); 260 if (cur_irq) 261 handle_nested_irq(cur_irq); 262 } 263 } 264 265 return IRQ_HANDLED; 266 } 267 268 int max8997_irq_resume(struct max8997_dev *max8997) 269 { 270 if (max8997->irq && max8997->irq_domain) 271 max8997_irq_thread(0, max8997); 272 return 0; 273 } 274 275 static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq, 276 irq_hw_number_t hw) 277 { 278 struct max8997_dev *max8997 = d->host_data; 279 280 irq_set_chip_data(irq, max8997); 281 irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq); 282 irq_set_nested_thread(irq, 1); 283 irq_set_noprobe(irq); 284 285 return 0; 286 } 287 288 static const struct irq_domain_ops max8997_irq_domain_ops = { 289 .map = max8997_irq_domain_map, 290 }; 291 292 int max8997_irq_init(struct max8997_dev *max8997) 293 { 294 struct irq_domain *domain; 295 int i; 296 int ret; 297 u8 val; 298 299 if (!max8997->irq) { 300 dev_warn(max8997->dev, "No interrupt specified.\n"); 301 return 0; 302 } 303 304 mutex_init(&max8997->irqlock); 305 306 /* Mask individual interrupt sources */ 307 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) { 308 struct i2c_client *i2c; 309 310 max8997->irq_masks_cur[i] = 0xff; 311 max8997->irq_masks_cache[i] = 0xff; 312 i2c = get_i2c(max8997, i); 313 314 if (IS_ERR_OR_NULL(i2c)) 315 continue; 316 if (max8997_mask_reg[i] == MAX8997_REG_INVALID) 317 continue; 318 319 max8997_write_reg(i2c, max8997_mask_reg[i], 0xff); 320 } 321 322 for (i = 0; i < MAX8997_NUM_GPIO; i++) { 323 max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c, 324 MAX8997_REG_GPIOCNTL1 + i, 325 &val) 326 & MAX8997_GPIO_DATA_MASK) ? 327 true : false; 328 } 329 330 domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR, 331 &max8997_irq_domain_ops, max8997); 332 if (!domain) { 333 dev_err(max8997->dev, "could not create irq domain\n"); 334 return -ENODEV; 335 } 336 max8997->irq_domain = domain; 337 338 ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread, 339 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 340 "max8997-irq", max8997); 341 342 if (ret) { 343 dev_err(max8997->dev, "Failed to request IRQ %d: %d\n", 344 max8997->irq, ret); 345 return ret; 346 } 347 348 if (!max8997->ono) 349 return 0; 350 351 ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread, 352 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | 353 IRQF_ONESHOT, "max8997-ono", max8997); 354 355 if (ret) 356 dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n", 357 max8997->ono, ret); 358 359 return 0; 360 } 361 362 void max8997_irq_exit(struct max8997_dev *max8997) 363 { 364 if (max8997->ono) 365 free_irq(max8997->ono, max8997); 366 367 if (max8997->irq) 368 free_irq(max8997->irq, max8997); 369 } 370