1 /* 2 * Maxim MAX77620 MFD Driver 3 * 4 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. 5 * 6 * Author: 7 * Laxman Dewangan <ldewangan@nvidia.com> 8 * Chaitanya Bandi <bandik@nvidia.com> 9 * Mallikarjun Kasoju <mkasoju@nvidia.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 /****************** Teminology used in driver ******************** 17 * Here are some terminology used from datasheet for quick reference: 18 * Flexible Power Sequence (FPS): 19 * The Flexible Power Sequencer (FPS) allows each regulator to power up under 20 * hardware or software control. Additionally, each regulator can power on 21 * independently or among a group of other regulators with an adjustable 22 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can 23 * be programmed to be part of a sequence allowing external regulators to be 24 * sequenced along with internal regulators. 32KHz clock can be programmed to 25 * be part of a sequence. 26 * There is 3 FPS confguration registers and all resources are configured to 27 * any of these FPS or no FPS. 28 */ 29 30 #include <linux/i2c.h> 31 #include <linux/interrupt.h> 32 #include <linux/mfd/core.h> 33 #include <linux/mfd/max77620.h> 34 #include <linux/init.h> 35 #include <linux/of.h> 36 #include <linux/of_device.h> 37 #include <linux/regmap.h> 38 #include <linux/slab.h> 39 40 static struct max77620_chip *max77620_scratch; 41 42 static const struct resource gpio_resources[] = { 43 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO), 44 }; 45 46 static const struct resource power_resources[] = { 47 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW), 48 }; 49 50 static const struct resource rtc_resources[] = { 51 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC), 52 }; 53 54 static const struct resource thermal_resources[] = { 55 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1), 56 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2), 57 }; 58 59 static const struct regmap_irq max77620_top_irqs[] = { 60 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK), 61 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK), 62 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK), 63 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK), 64 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK), 65 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK), 66 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK), 67 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK), 68 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK), 69 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK), 70 }; 71 72 static const struct mfd_cell max77620_children[] = { 73 { .name = "max77620-pinctrl", }, 74 { .name = "max77620-clock", }, 75 { .name = "max77620-pmic", }, 76 { .name = "max77620-watchdog", }, 77 { 78 .name = "max77620-gpio", 79 .resources = gpio_resources, 80 .num_resources = ARRAY_SIZE(gpio_resources), 81 }, { 82 .name = "max77620-rtc", 83 .resources = rtc_resources, 84 .num_resources = ARRAY_SIZE(rtc_resources), 85 }, { 86 .name = "max77620-power", 87 .resources = power_resources, 88 .num_resources = ARRAY_SIZE(power_resources), 89 }, { 90 .name = "max77620-thermal", 91 .resources = thermal_resources, 92 .num_resources = ARRAY_SIZE(thermal_resources), 93 }, 94 }; 95 96 static const struct mfd_cell max20024_children[] = { 97 { .name = "max20024-pinctrl", }, 98 { .name = "max77620-clock", }, 99 { .name = "max20024-pmic", }, 100 { .name = "max77620-watchdog", }, 101 { 102 .name = "max77620-gpio", 103 .resources = gpio_resources, 104 .num_resources = ARRAY_SIZE(gpio_resources), 105 }, { 106 .name = "max77620-rtc", 107 .resources = rtc_resources, 108 .num_resources = ARRAY_SIZE(rtc_resources), 109 }, { 110 .name = "max20024-power", 111 .resources = power_resources, 112 .num_resources = ARRAY_SIZE(power_resources), 113 }, 114 }; 115 116 static const struct mfd_cell max77663_children[] = { 117 { .name = "max77620-pinctrl", }, 118 { .name = "max77620-clock", }, 119 { .name = "max77663-pmic", }, 120 { .name = "max77620-watchdog", }, 121 { 122 .name = "max77620-gpio", 123 .resources = gpio_resources, 124 .num_resources = ARRAY_SIZE(gpio_resources), 125 }, { 126 .name = "max77620-rtc", 127 .resources = rtc_resources, 128 .num_resources = ARRAY_SIZE(rtc_resources), 129 }, { 130 .name = "max77663-power", 131 .resources = power_resources, 132 .num_resources = ARRAY_SIZE(power_resources), 133 }, 134 }; 135 136 static const struct regmap_range max77620_readable_ranges[] = { 137 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 138 }; 139 140 static const struct regmap_access_table max77620_readable_table = { 141 .yes_ranges = max77620_readable_ranges, 142 .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges), 143 }; 144 145 static const struct regmap_range max20024_readable_ranges[] = { 146 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 147 regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD), 148 }; 149 150 static const struct regmap_access_table max20024_readable_table = { 151 .yes_ranges = max20024_readable_ranges, 152 .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges), 153 }; 154 155 static const struct regmap_range max77620_writable_ranges[] = { 156 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 157 }; 158 159 static const struct regmap_access_table max77620_writable_table = { 160 .yes_ranges = max77620_writable_ranges, 161 .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges), 162 }; 163 164 static const struct regmap_range max77620_cacheable_ranges[] = { 165 regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3), 166 regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3), 167 }; 168 169 static const struct regmap_access_table max77620_volatile_table = { 170 .no_ranges = max77620_cacheable_ranges, 171 .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges), 172 }; 173 174 static const struct regmap_config max77620_regmap_config = { 175 .name = "power-slave", 176 .reg_bits = 8, 177 .val_bits = 8, 178 .max_register = MAX77620_REG_DVSSD4 + 1, 179 .cache_type = REGCACHE_RBTREE, 180 .rd_table = &max77620_readable_table, 181 .wr_table = &max77620_writable_table, 182 .volatile_table = &max77620_volatile_table, 183 }; 184 185 static const struct regmap_config max20024_regmap_config = { 186 .name = "power-slave", 187 .reg_bits = 8, 188 .val_bits = 8, 189 .max_register = MAX20024_REG_MAX_ADD + 1, 190 .cache_type = REGCACHE_RBTREE, 191 .rd_table = &max20024_readable_table, 192 .wr_table = &max77620_writable_table, 193 .volatile_table = &max77620_volatile_table, 194 }; 195 196 static const struct regmap_range max77663_readable_ranges[] = { 197 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5), 198 }; 199 200 static const struct regmap_access_table max77663_readable_table = { 201 .yes_ranges = max77663_readable_ranges, 202 .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges), 203 }; 204 205 static const struct regmap_range max77663_writable_ranges[] = { 206 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5), 207 }; 208 209 static const struct regmap_access_table max77663_writable_table = { 210 .yes_ranges = max77663_writable_ranges, 211 .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges), 212 }; 213 214 static const struct regmap_config max77663_regmap_config = { 215 .name = "power-slave", 216 .reg_bits = 8, 217 .val_bits = 8, 218 .max_register = MAX77620_REG_CID5 + 1, 219 .cache_type = REGCACHE_RBTREE, 220 .rd_table = &max77663_readable_table, 221 .wr_table = &max77663_writable_table, 222 .volatile_table = &max77620_volatile_table, 223 }; 224 225 /* 226 * MAX77620 and MAX20024 has the following steps of the interrupt handling 227 * for TOP interrupts: 228 * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM. 229 * 2. Read IRQTOP and service the interrupt. 230 * 3. Once all interrupts has been checked and serviced, the interrupt service 231 * routine un-masks the hardware interrupt line by clearing GLBLM. 232 */ 233 static int max77620_irq_global_mask(void *irq_drv_data) 234 { 235 struct max77620_chip *chip = irq_drv_data; 236 int ret; 237 238 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 239 MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK); 240 if (ret < 0) 241 dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret); 242 243 return ret; 244 } 245 246 static int max77620_irq_global_unmask(void *irq_drv_data) 247 { 248 struct max77620_chip *chip = irq_drv_data; 249 int ret; 250 251 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 252 MAX77620_GLBLM_MASK, 0); 253 if (ret < 0) 254 dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret); 255 256 return ret; 257 } 258 259 static struct regmap_irq_chip max77620_top_irq_chip = { 260 .name = "max77620-top", 261 .irqs = max77620_top_irqs, 262 .num_irqs = ARRAY_SIZE(max77620_top_irqs), 263 .num_regs = 2, 264 .status_base = MAX77620_REG_IRQTOP, 265 .mask_base = MAX77620_REG_IRQTOPM, 266 .handle_pre_irq = max77620_irq_global_mask, 267 .handle_post_irq = max77620_irq_global_unmask, 268 }; 269 270 /* max77620_get_fps_period_reg_value: Get FPS bit field value from 271 * requested periods. 272 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560 273 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80, 274 * 160, 320, 540, 1280 and 2560 microseconds. 275 * The FPS register has 3 bits field to set the FPS period as 276 * bits max77620 max20024 277 * 000 40 20 278 * 001 80 40 279 * ::: 280 */ 281 static int max77620_get_fps_period_reg_value(struct max77620_chip *chip, 282 int tperiod) 283 { 284 int fps_min_period; 285 int i; 286 287 switch (chip->chip_id) { 288 case MAX20024: 289 fps_min_period = MAX20024_FPS_PERIOD_MIN_US; 290 break; 291 case MAX77620: 292 fps_min_period = MAX77620_FPS_PERIOD_MIN_US; 293 break; 294 case MAX77663: 295 fps_min_period = MAX20024_FPS_PERIOD_MIN_US; 296 break; 297 default: 298 return -EINVAL; 299 } 300 301 for (i = 0; i < 7; i++) { 302 if (fps_min_period >= tperiod) 303 return i; 304 fps_min_period *= 2; 305 } 306 307 return i; 308 } 309 310 /* max77620_config_fps: Configure FPS configuration registers 311 * based on platform specific information. 312 */ 313 static int max77620_config_fps(struct max77620_chip *chip, 314 struct device_node *fps_np) 315 { 316 struct device *dev = chip->dev; 317 unsigned int mask = 0, config = 0; 318 u32 fps_max_period; 319 u32 param_val; 320 int tperiod, fps_id; 321 int ret; 322 char fps_name[10]; 323 324 switch (chip->chip_id) { 325 case MAX20024: 326 fps_max_period = MAX20024_FPS_PERIOD_MAX_US; 327 break; 328 case MAX77620: 329 fps_max_period = MAX77620_FPS_PERIOD_MAX_US; 330 break; 331 case MAX77663: 332 fps_max_period = MAX20024_FPS_PERIOD_MAX_US; 333 break; 334 default: 335 return -EINVAL; 336 } 337 338 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 339 sprintf(fps_name, "fps%d", fps_id); 340 if (of_node_name_eq(fps_np, fps_name)) 341 break; 342 } 343 344 if (fps_id == MAX77620_FPS_COUNT) { 345 dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np); 346 return -EINVAL; 347 } 348 349 ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us", 350 ¶m_val); 351 if (!ret) { 352 mask |= MAX77620_FPS_TIME_PERIOD_MASK; 353 chip->shutdown_fps_period[fps_id] = min(param_val, 354 fps_max_period); 355 tperiod = max77620_get_fps_period_reg_value(chip, 356 chip->shutdown_fps_period[fps_id]); 357 config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT; 358 } 359 360 ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us", 361 ¶m_val); 362 if (!ret) 363 chip->suspend_fps_period[fps_id] = min(param_val, 364 fps_max_period); 365 366 ret = of_property_read_u32(fps_np, "maxim,fps-event-source", 367 ¶m_val); 368 if (!ret) { 369 if (param_val > 2) { 370 dev_err(dev, "FPS%d event-source invalid\n", fps_id); 371 return -EINVAL; 372 } 373 mask |= MAX77620_FPS_EN_SRC_MASK; 374 config |= param_val << MAX77620_FPS_EN_SRC_SHIFT; 375 if (param_val == 2) { 376 mask |= MAX77620_FPS_ENFPS_SW_MASK; 377 config |= MAX77620_FPS_ENFPS_SW; 378 } 379 } 380 381 if (!chip->sleep_enable && !chip->enable_global_lpm) { 382 ret = of_property_read_u32(fps_np, 383 "maxim,device-state-on-disabled-event", 384 ¶m_val); 385 if (!ret) { 386 if (param_val == 0) 387 chip->sleep_enable = true; 388 else if (param_val == 1) 389 chip->enable_global_lpm = true; 390 } 391 } 392 393 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 394 mask, config); 395 if (ret < 0) { 396 dev_err(dev, "Failed to update FPS CFG: %d\n", ret); 397 return ret; 398 } 399 400 return 0; 401 } 402 403 static int max77620_initialise_fps(struct max77620_chip *chip) 404 { 405 struct device *dev = chip->dev; 406 struct device_node *fps_np, *fps_child; 407 u8 config; 408 int fps_id; 409 int ret; 410 411 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 412 chip->shutdown_fps_period[fps_id] = -1; 413 chip->suspend_fps_period[fps_id] = -1; 414 } 415 416 fps_np = of_get_child_by_name(dev->of_node, "fps"); 417 if (!fps_np) 418 goto skip_fps; 419 420 for_each_child_of_node(fps_np, fps_child) { 421 ret = max77620_config_fps(chip, fps_child); 422 if (ret < 0) 423 return ret; 424 } 425 426 config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0; 427 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 428 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config); 429 if (ret < 0) { 430 dev_err(dev, "Failed to update SLP_LPM: %d\n", ret); 431 return ret; 432 } 433 434 skip_fps: 435 if (chip->chip_id == MAX77663) 436 return 0; 437 438 /* Enable wake on EN0 pin */ 439 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 440 MAX77620_ONOFFCNFG2_WK_EN0, 441 MAX77620_ONOFFCNFG2_WK_EN0); 442 if (ret < 0) { 443 dev_err(dev, "Failed to update WK_EN0: %d\n", ret); 444 return ret; 445 } 446 447 /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */ 448 if ((chip->chip_id == MAX20024) && chip->sleep_enable) { 449 config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE; 450 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 451 config, config); 452 if (ret < 0) { 453 dev_err(dev, "Failed to update SLPEN: %d\n", ret); 454 return ret; 455 } 456 } 457 458 return 0; 459 } 460 461 static int max77620_read_es_version(struct max77620_chip *chip) 462 { 463 unsigned int val; 464 u8 cid_val[6]; 465 int i; 466 int ret; 467 468 for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) { 469 ret = regmap_read(chip->rmap, i, &val); 470 if (ret < 0) { 471 dev_err(chip->dev, "Failed to read CID: %d\n", ret); 472 return ret; 473 } 474 dev_dbg(chip->dev, "CID%d: 0x%02x\n", 475 i - MAX77620_REG_CID0, val); 476 cid_val[i - MAX77620_REG_CID0] = val; 477 } 478 479 /* CID4 is OTP Version and CID5 is ES version */ 480 dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n", 481 cid_val[4], MAX77620_CID5_DIDM(cid_val[5])); 482 483 return ret; 484 } 485 486 static void max77620_pm_power_off(void) 487 { 488 struct max77620_chip *chip = max77620_scratch; 489 490 regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 491 MAX77620_ONOFFCNFG1_SFT_RST, 492 MAX77620_ONOFFCNFG1_SFT_RST); 493 } 494 495 static int max77620_probe(struct i2c_client *client, 496 const struct i2c_device_id *id) 497 { 498 const struct regmap_config *rmap_config; 499 struct max77620_chip *chip; 500 const struct mfd_cell *mfd_cells; 501 int n_mfd_cells; 502 bool pm_off; 503 int ret; 504 505 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 506 if (!chip) 507 return -ENOMEM; 508 509 i2c_set_clientdata(client, chip); 510 chip->dev = &client->dev; 511 chip->irq_base = -1; 512 chip->chip_irq = client->irq; 513 chip->chip_id = (enum max77620_chip_id)id->driver_data; 514 515 switch (chip->chip_id) { 516 case MAX77620: 517 mfd_cells = max77620_children; 518 n_mfd_cells = ARRAY_SIZE(max77620_children); 519 rmap_config = &max77620_regmap_config; 520 break; 521 case MAX20024: 522 mfd_cells = max20024_children; 523 n_mfd_cells = ARRAY_SIZE(max20024_children); 524 rmap_config = &max20024_regmap_config; 525 break; 526 case MAX77663: 527 mfd_cells = max77663_children; 528 n_mfd_cells = ARRAY_SIZE(max77663_children); 529 rmap_config = &max77663_regmap_config; 530 break; 531 default: 532 dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id); 533 return -EINVAL; 534 } 535 536 chip->rmap = devm_regmap_init_i2c(client, rmap_config); 537 if (IS_ERR(chip->rmap)) { 538 ret = PTR_ERR(chip->rmap); 539 dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret); 540 return ret; 541 } 542 543 ret = max77620_read_es_version(chip); 544 if (ret < 0) 545 return ret; 546 547 max77620_top_irq_chip.irq_drv_data = chip; 548 ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq, 549 IRQF_ONESHOT | IRQF_SHARED, 550 chip->irq_base, &max77620_top_irq_chip, 551 &chip->top_irq_data); 552 if (ret < 0) { 553 dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret); 554 return ret; 555 } 556 557 ret = max77620_initialise_fps(chip); 558 if (ret < 0) 559 return ret; 560 561 ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, 562 mfd_cells, n_mfd_cells, NULL, 0, 563 regmap_irq_get_domain(chip->top_irq_data)); 564 if (ret < 0) { 565 dev_err(chip->dev, "Failed to add MFD children: %d\n", ret); 566 return ret; 567 } 568 569 pm_off = of_device_is_system_power_controller(client->dev.of_node); 570 if (pm_off && !pm_power_off) { 571 max77620_scratch = chip; 572 pm_power_off = max77620_pm_power_off; 573 } 574 575 return 0; 576 } 577 578 #ifdef CONFIG_PM_SLEEP 579 static int max77620_set_fps_period(struct max77620_chip *chip, 580 int fps_id, int time_period) 581 { 582 int period = max77620_get_fps_period_reg_value(chip, time_period); 583 int ret; 584 585 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 586 MAX77620_FPS_TIME_PERIOD_MASK, 587 period << MAX77620_FPS_TIME_PERIOD_SHIFT); 588 if (ret < 0) { 589 dev_err(chip->dev, "Failed to update FPS period: %d\n", ret); 590 return ret; 591 } 592 593 return 0; 594 } 595 596 static int max77620_i2c_suspend(struct device *dev) 597 { 598 struct max77620_chip *chip = dev_get_drvdata(dev); 599 struct i2c_client *client = to_i2c_client(dev); 600 unsigned int config; 601 int fps; 602 int ret; 603 604 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 605 if (chip->suspend_fps_period[fps] < 0) 606 continue; 607 608 ret = max77620_set_fps_period(chip, fps, 609 chip->suspend_fps_period[fps]); 610 if (ret < 0) 611 return ret; 612 } 613 614 /* 615 * For MAX20024: No need to configure SLPEN on suspend as 616 * it will be configured on Init. 617 */ 618 if (chip->chip_id == MAX20024) 619 goto out; 620 621 config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0; 622 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 623 MAX77620_ONOFFCNFG1_SLPEN, 624 config); 625 if (ret < 0) { 626 dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret); 627 return ret; 628 } 629 630 if (chip->chip_id == MAX77663) 631 goto out; 632 633 /* Disable WK_EN0 */ 634 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 635 MAX77620_ONOFFCNFG2_WK_EN0, 0); 636 if (ret < 0) { 637 dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret); 638 return ret; 639 } 640 641 out: 642 disable_irq(client->irq); 643 644 return 0; 645 } 646 647 static int max77620_i2c_resume(struct device *dev) 648 { 649 struct max77620_chip *chip = dev_get_drvdata(dev); 650 struct i2c_client *client = to_i2c_client(dev); 651 int ret; 652 int fps; 653 654 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 655 if (chip->shutdown_fps_period[fps] < 0) 656 continue; 657 658 ret = max77620_set_fps_period(chip, fps, 659 chip->shutdown_fps_period[fps]); 660 if (ret < 0) 661 return ret; 662 } 663 664 /* 665 * For MAX20024: No need to configure WKEN0 on resume as 666 * it is configured on Init. 667 */ 668 if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663) 669 goto out; 670 671 /* Enable WK_EN0 */ 672 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 673 MAX77620_ONOFFCNFG2_WK_EN0, 674 MAX77620_ONOFFCNFG2_WK_EN0); 675 if (ret < 0) { 676 dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret); 677 return ret; 678 } 679 680 out: 681 enable_irq(client->irq); 682 683 return 0; 684 } 685 #endif 686 687 static const struct i2c_device_id max77620_id[] = { 688 {"max77620", MAX77620}, 689 {"max20024", MAX20024}, 690 {"max77663", MAX77663}, 691 {}, 692 }; 693 694 static const struct dev_pm_ops max77620_pm_ops = { 695 SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume) 696 }; 697 698 static struct i2c_driver max77620_driver = { 699 .driver = { 700 .name = "max77620", 701 .pm = &max77620_pm_ops, 702 }, 703 .probe = max77620_probe, 704 .id_table = max77620_id, 705 }; 706 builtin_i2c_driver(max77620_driver); 707