1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Maxim MAX77620 MFD Driver 4 * 5 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. 6 * 7 * Author: 8 * Laxman Dewangan <ldewangan@nvidia.com> 9 * Chaitanya Bandi <bandik@nvidia.com> 10 * Mallikarjun Kasoju <mkasoju@nvidia.com> 11 */ 12 13 /****************** Teminology used in driver ******************** 14 * Here are some terminology used from datasheet for quick reference: 15 * Flexible Power Sequence (FPS): 16 * The Flexible Power Sequencer (FPS) allows each regulator to power up under 17 * hardware or software control. Additionally, each regulator can power on 18 * independently or among a group of other regulators with an adjustable 19 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can 20 * be programmed to be part of a sequence allowing external regulators to be 21 * sequenced along with internal regulators. 32KHz clock can be programmed to 22 * be part of a sequence. 23 * There is 3 FPS confguration registers and all resources are configured to 24 * any of these FPS or no FPS. 25 */ 26 27 #include <linux/i2c.h> 28 #include <linux/interrupt.h> 29 #include <linux/mfd/core.h> 30 #include <linux/mfd/max77620.h> 31 #include <linux/init.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/regmap.h> 35 #include <linux/slab.h> 36 37 static struct max77620_chip *max77620_scratch; 38 39 static const struct resource gpio_resources[] = { 40 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO), 41 }; 42 43 static const struct resource power_resources[] = { 44 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW), 45 }; 46 47 static const struct resource rtc_resources[] = { 48 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC), 49 }; 50 51 static const struct resource thermal_resources[] = { 52 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1), 53 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2), 54 }; 55 56 static const struct regmap_irq max77620_top_irqs[] = { 57 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK), 58 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK), 59 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK), 60 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK), 61 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK), 62 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK), 63 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK), 64 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK), 65 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK), 66 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK), 67 }; 68 69 static const struct mfd_cell max77620_children[] = { 70 { .name = "max77620-pinctrl", }, 71 { .name = "max77620-clock", }, 72 { .name = "max77620-pmic", }, 73 { .name = "max77620-watchdog", }, 74 { 75 .name = "max77620-gpio", 76 .resources = gpio_resources, 77 .num_resources = ARRAY_SIZE(gpio_resources), 78 }, { 79 .name = "max77620-rtc", 80 .resources = rtc_resources, 81 .num_resources = ARRAY_SIZE(rtc_resources), 82 }, { 83 .name = "max77620-power", 84 .resources = power_resources, 85 .num_resources = ARRAY_SIZE(power_resources), 86 }, { 87 .name = "max77620-thermal", 88 .resources = thermal_resources, 89 .num_resources = ARRAY_SIZE(thermal_resources), 90 }, 91 }; 92 93 static const struct mfd_cell max20024_children[] = { 94 { .name = "max20024-pinctrl", }, 95 { .name = "max77620-clock", }, 96 { .name = "max20024-pmic", }, 97 { .name = "max77620-watchdog", }, 98 { 99 .name = "max77620-gpio", 100 .resources = gpio_resources, 101 .num_resources = ARRAY_SIZE(gpio_resources), 102 }, { 103 .name = "max77620-rtc", 104 .resources = rtc_resources, 105 .num_resources = ARRAY_SIZE(rtc_resources), 106 }, { 107 .name = "max20024-power", 108 .resources = power_resources, 109 .num_resources = ARRAY_SIZE(power_resources), 110 }, 111 }; 112 113 static const struct mfd_cell max77663_children[] = { 114 { .name = "max77620-pinctrl", }, 115 { .name = "max77620-clock", }, 116 { .name = "max77663-pmic", }, 117 { .name = "max77620-watchdog", }, 118 { 119 .name = "max77620-gpio", 120 .resources = gpio_resources, 121 .num_resources = ARRAY_SIZE(gpio_resources), 122 }, { 123 .name = "max77620-rtc", 124 .resources = rtc_resources, 125 .num_resources = ARRAY_SIZE(rtc_resources), 126 }, { 127 .name = "max77663-power", 128 .resources = power_resources, 129 .num_resources = ARRAY_SIZE(power_resources), 130 }, 131 }; 132 133 static const struct regmap_range max77620_readable_ranges[] = { 134 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 135 }; 136 137 static const struct regmap_access_table max77620_readable_table = { 138 .yes_ranges = max77620_readable_ranges, 139 .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges), 140 }; 141 142 static const struct regmap_range max20024_readable_ranges[] = { 143 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 144 regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD), 145 }; 146 147 static const struct regmap_access_table max20024_readable_table = { 148 .yes_ranges = max20024_readable_ranges, 149 .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges), 150 }; 151 152 static const struct regmap_range max77620_writable_ranges[] = { 153 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 154 }; 155 156 static const struct regmap_access_table max77620_writable_table = { 157 .yes_ranges = max77620_writable_ranges, 158 .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges), 159 }; 160 161 static const struct regmap_range max77620_cacheable_ranges[] = { 162 regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3), 163 regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3), 164 }; 165 166 static const struct regmap_access_table max77620_volatile_table = { 167 .no_ranges = max77620_cacheable_ranges, 168 .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges), 169 }; 170 171 static const struct regmap_config max77620_regmap_config = { 172 .name = "power-slave", 173 .reg_bits = 8, 174 .val_bits = 8, 175 .max_register = MAX77620_REG_DVSSD4 + 1, 176 .cache_type = REGCACHE_RBTREE, 177 .rd_table = &max77620_readable_table, 178 .wr_table = &max77620_writable_table, 179 .volatile_table = &max77620_volatile_table, 180 }; 181 182 static const struct regmap_config max20024_regmap_config = { 183 .name = "power-slave", 184 .reg_bits = 8, 185 .val_bits = 8, 186 .max_register = MAX20024_REG_MAX_ADD + 1, 187 .cache_type = REGCACHE_RBTREE, 188 .rd_table = &max20024_readable_table, 189 .wr_table = &max77620_writable_table, 190 .volatile_table = &max77620_volatile_table, 191 }; 192 193 static const struct regmap_range max77663_readable_ranges[] = { 194 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5), 195 }; 196 197 static const struct regmap_access_table max77663_readable_table = { 198 .yes_ranges = max77663_readable_ranges, 199 .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges), 200 }; 201 202 static const struct regmap_range max77663_writable_ranges[] = { 203 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5), 204 }; 205 206 static const struct regmap_access_table max77663_writable_table = { 207 .yes_ranges = max77663_writable_ranges, 208 .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges), 209 }; 210 211 static const struct regmap_config max77663_regmap_config = { 212 .name = "power-slave", 213 .reg_bits = 8, 214 .val_bits = 8, 215 .max_register = MAX77620_REG_CID5 + 1, 216 .cache_type = REGCACHE_RBTREE, 217 .rd_table = &max77663_readable_table, 218 .wr_table = &max77663_writable_table, 219 .volatile_table = &max77620_volatile_table, 220 }; 221 222 /* 223 * MAX77620 and MAX20024 has the following steps of the interrupt handling 224 * for TOP interrupts: 225 * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM. 226 * 2. Read IRQTOP and service the interrupt. 227 * 3. Once all interrupts has been checked and serviced, the interrupt service 228 * routine un-masks the hardware interrupt line by clearing GLBLM. 229 */ 230 static int max77620_irq_global_mask(void *irq_drv_data) 231 { 232 struct max77620_chip *chip = irq_drv_data; 233 int ret; 234 235 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 236 MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK); 237 if (ret < 0) 238 dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret); 239 240 return ret; 241 } 242 243 static int max77620_irq_global_unmask(void *irq_drv_data) 244 { 245 struct max77620_chip *chip = irq_drv_data; 246 int ret; 247 248 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 249 MAX77620_GLBLM_MASK, 0); 250 if (ret < 0) 251 dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret); 252 253 return ret; 254 } 255 256 static struct regmap_irq_chip max77620_top_irq_chip = { 257 .name = "max77620-top", 258 .irqs = max77620_top_irqs, 259 .num_irqs = ARRAY_SIZE(max77620_top_irqs), 260 .num_regs = 2, 261 .status_base = MAX77620_REG_IRQTOP, 262 .mask_base = MAX77620_REG_IRQTOPM, 263 .handle_pre_irq = max77620_irq_global_mask, 264 .handle_post_irq = max77620_irq_global_unmask, 265 }; 266 267 /* max77620_get_fps_period_reg_value: Get FPS bit field value from 268 * requested periods. 269 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560 270 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80, 271 * 160, 320, 540, 1280 and 2560 microseconds. 272 * The FPS register has 3 bits field to set the FPS period as 273 * bits max77620 max20024 274 * 000 40 20 275 * 001 80 40 276 * ::: 277 */ 278 static int max77620_get_fps_period_reg_value(struct max77620_chip *chip, 279 int tperiod) 280 { 281 int fps_min_period; 282 int i; 283 284 switch (chip->chip_id) { 285 case MAX20024: 286 fps_min_period = MAX20024_FPS_PERIOD_MIN_US; 287 break; 288 case MAX77620: 289 fps_min_period = MAX77620_FPS_PERIOD_MIN_US; 290 break; 291 case MAX77663: 292 fps_min_period = MAX20024_FPS_PERIOD_MIN_US; 293 break; 294 default: 295 return -EINVAL; 296 } 297 298 for (i = 0; i < 7; i++) { 299 if (fps_min_period >= tperiod) 300 return i; 301 fps_min_period *= 2; 302 } 303 304 return i; 305 } 306 307 /* max77620_config_fps: Configure FPS configuration registers 308 * based on platform specific information. 309 */ 310 static int max77620_config_fps(struct max77620_chip *chip, 311 struct device_node *fps_np) 312 { 313 struct device *dev = chip->dev; 314 unsigned int mask = 0, config = 0; 315 u32 fps_max_period; 316 u32 param_val; 317 int tperiod, fps_id; 318 int ret; 319 char fps_name[10]; 320 321 switch (chip->chip_id) { 322 case MAX20024: 323 fps_max_period = MAX20024_FPS_PERIOD_MAX_US; 324 break; 325 case MAX77620: 326 fps_max_period = MAX77620_FPS_PERIOD_MAX_US; 327 break; 328 case MAX77663: 329 fps_max_period = MAX20024_FPS_PERIOD_MAX_US; 330 break; 331 default: 332 return -EINVAL; 333 } 334 335 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 336 sprintf(fps_name, "fps%d", fps_id); 337 if (of_node_name_eq(fps_np, fps_name)) 338 break; 339 } 340 341 if (fps_id == MAX77620_FPS_COUNT) { 342 dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np); 343 return -EINVAL; 344 } 345 346 ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us", 347 ¶m_val); 348 if (!ret) { 349 mask |= MAX77620_FPS_TIME_PERIOD_MASK; 350 chip->shutdown_fps_period[fps_id] = min(param_val, 351 fps_max_period); 352 tperiod = max77620_get_fps_period_reg_value(chip, 353 chip->shutdown_fps_period[fps_id]); 354 config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT; 355 } 356 357 ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us", 358 ¶m_val); 359 if (!ret) 360 chip->suspend_fps_period[fps_id] = min(param_val, 361 fps_max_period); 362 363 ret = of_property_read_u32(fps_np, "maxim,fps-event-source", 364 ¶m_val); 365 if (!ret) { 366 if (param_val > 2) { 367 dev_err(dev, "FPS%d event-source invalid\n", fps_id); 368 return -EINVAL; 369 } 370 mask |= MAX77620_FPS_EN_SRC_MASK; 371 config |= param_val << MAX77620_FPS_EN_SRC_SHIFT; 372 if (param_val == 2) { 373 mask |= MAX77620_FPS_ENFPS_SW_MASK; 374 config |= MAX77620_FPS_ENFPS_SW; 375 } 376 } 377 378 if (!chip->sleep_enable && !chip->enable_global_lpm) { 379 ret = of_property_read_u32(fps_np, 380 "maxim,device-state-on-disabled-event", 381 ¶m_val); 382 if (!ret) { 383 if (param_val == 0) 384 chip->sleep_enable = true; 385 else if (param_val == 1) 386 chip->enable_global_lpm = true; 387 } 388 } 389 390 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 391 mask, config); 392 if (ret < 0) { 393 dev_err(dev, "Failed to update FPS CFG: %d\n", ret); 394 return ret; 395 } 396 397 return 0; 398 } 399 400 static int max77620_initialise_fps(struct max77620_chip *chip) 401 { 402 struct device *dev = chip->dev; 403 struct device_node *fps_np, *fps_child; 404 u8 config; 405 int fps_id; 406 int ret; 407 408 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 409 chip->shutdown_fps_period[fps_id] = -1; 410 chip->suspend_fps_period[fps_id] = -1; 411 } 412 413 fps_np = of_get_child_by_name(dev->of_node, "fps"); 414 if (!fps_np) 415 goto skip_fps; 416 417 for_each_child_of_node(fps_np, fps_child) { 418 ret = max77620_config_fps(chip, fps_child); 419 if (ret < 0) { 420 of_node_put(fps_child); 421 return ret; 422 } 423 } 424 425 config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0; 426 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 427 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config); 428 if (ret < 0) { 429 dev_err(dev, "Failed to update SLP_LPM: %d\n", ret); 430 return ret; 431 } 432 433 skip_fps: 434 if (chip->chip_id == MAX77663) 435 return 0; 436 437 /* Enable wake on EN0 pin */ 438 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 439 MAX77620_ONOFFCNFG2_WK_EN0, 440 MAX77620_ONOFFCNFG2_WK_EN0); 441 if (ret < 0) { 442 dev_err(dev, "Failed to update WK_EN0: %d\n", ret); 443 return ret; 444 } 445 446 /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */ 447 if ((chip->chip_id == MAX20024) && chip->sleep_enable) { 448 config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE; 449 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 450 config, config); 451 if (ret < 0) { 452 dev_err(dev, "Failed to update SLPEN: %d\n", ret); 453 return ret; 454 } 455 } 456 457 return 0; 458 } 459 460 static int max77620_read_es_version(struct max77620_chip *chip) 461 { 462 unsigned int val; 463 u8 cid_val[6]; 464 int i; 465 int ret; 466 467 for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) { 468 ret = regmap_read(chip->rmap, i, &val); 469 if (ret < 0) { 470 dev_err(chip->dev, "Failed to read CID: %d\n", ret); 471 return ret; 472 } 473 dev_dbg(chip->dev, "CID%d: 0x%02x\n", 474 i - MAX77620_REG_CID0, val); 475 cid_val[i - MAX77620_REG_CID0] = val; 476 } 477 478 /* CID4 is OTP Version and CID5 is ES version */ 479 dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n", 480 cid_val[4], MAX77620_CID5_DIDM(cid_val[5])); 481 482 return ret; 483 } 484 485 static void max77620_pm_power_off(void) 486 { 487 struct max77620_chip *chip = max77620_scratch; 488 489 regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 490 MAX77620_ONOFFCNFG1_SFT_RST, 491 MAX77620_ONOFFCNFG1_SFT_RST); 492 } 493 494 static int max77620_probe(struct i2c_client *client, 495 const struct i2c_device_id *id) 496 { 497 const struct regmap_config *rmap_config; 498 struct max77620_chip *chip; 499 const struct mfd_cell *mfd_cells; 500 int n_mfd_cells; 501 bool pm_off; 502 int ret; 503 504 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 505 if (!chip) 506 return -ENOMEM; 507 508 i2c_set_clientdata(client, chip); 509 chip->dev = &client->dev; 510 chip->irq_base = -1; 511 chip->chip_irq = client->irq; 512 chip->chip_id = (enum max77620_chip_id)id->driver_data; 513 514 switch (chip->chip_id) { 515 case MAX77620: 516 mfd_cells = max77620_children; 517 n_mfd_cells = ARRAY_SIZE(max77620_children); 518 rmap_config = &max77620_regmap_config; 519 break; 520 case MAX20024: 521 mfd_cells = max20024_children; 522 n_mfd_cells = ARRAY_SIZE(max20024_children); 523 rmap_config = &max20024_regmap_config; 524 break; 525 case MAX77663: 526 mfd_cells = max77663_children; 527 n_mfd_cells = ARRAY_SIZE(max77663_children); 528 rmap_config = &max77663_regmap_config; 529 break; 530 default: 531 dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id); 532 return -EINVAL; 533 } 534 535 chip->rmap = devm_regmap_init_i2c(client, rmap_config); 536 if (IS_ERR(chip->rmap)) { 537 ret = PTR_ERR(chip->rmap); 538 dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret); 539 return ret; 540 } 541 542 ret = max77620_read_es_version(chip); 543 if (ret < 0) 544 return ret; 545 546 max77620_top_irq_chip.irq_drv_data = chip; 547 ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq, 548 IRQF_ONESHOT | IRQF_SHARED, 549 chip->irq_base, &max77620_top_irq_chip, 550 &chip->top_irq_data); 551 if (ret < 0) { 552 dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret); 553 return ret; 554 } 555 556 ret = max77620_initialise_fps(chip); 557 if (ret < 0) 558 return ret; 559 560 ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, 561 mfd_cells, n_mfd_cells, NULL, 0, 562 regmap_irq_get_domain(chip->top_irq_data)); 563 if (ret < 0) { 564 dev_err(chip->dev, "Failed to add MFD children: %d\n", ret); 565 return ret; 566 } 567 568 pm_off = of_device_is_system_power_controller(client->dev.of_node); 569 if (pm_off && !pm_power_off) { 570 max77620_scratch = chip; 571 pm_power_off = max77620_pm_power_off; 572 } 573 574 return 0; 575 } 576 577 #ifdef CONFIG_PM_SLEEP 578 static int max77620_set_fps_period(struct max77620_chip *chip, 579 int fps_id, int time_period) 580 { 581 int period = max77620_get_fps_period_reg_value(chip, time_period); 582 int ret; 583 584 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 585 MAX77620_FPS_TIME_PERIOD_MASK, 586 period << MAX77620_FPS_TIME_PERIOD_SHIFT); 587 if (ret < 0) { 588 dev_err(chip->dev, "Failed to update FPS period: %d\n", ret); 589 return ret; 590 } 591 592 return 0; 593 } 594 595 static int max77620_i2c_suspend(struct device *dev) 596 { 597 struct max77620_chip *chip = dev_get_drvdata(dev); 598 struct i2c_client *client = to_i2c_client(dev); 599 unsigned int config; 600 int fps; 601 int ret; 602 603 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 604 if (chip->suspend_fps_period[fps] < 0) 605 continue; 606 607 ret = max77620_set_fps_period(chip, fps, 608 chip->suspend_fps_period[fps]); 609 if (ret < 0) 610 return ret; 611 } 612 613 /* 614 * For MAX20024: No need to configure SLPEN on suspend as 615 * it will be configured on Init. 616 */ 617 if (chip->chip_id == MAX20024) 618 goto out; 619 620 config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0; 621 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 622 MAX77620_ONOFFCNFG1_SLPEN, 623 config); 624 if (ret < 0) { 625 dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret); 626 return ret; 627 } 628 629 if (chip->chip_id == MAX77663) 630 goto out; 631 632 /* Disable WK_EN0 */ 633 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 634 MAX77620_ONOFFCNFG2_WK_EN0, 0); 635 if (ret < 0) { 636 dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret); 637 return ret; 638 } 639 640 out: 641 disable_irq(client->irq); 642 643 return 0; 644 } 645 646 static int max77620_i2c_resume(struct device *dev) 647 { 648 struct max77620_chip *chip = dev_get_drvdata(dev); 649 struct i2c_client *client = to_i2c_client(dev); 650 int ret; 651 int fps; 652 653 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 654 if (chip->shutdown_fps_period[fps] < 0) 655 continue; 656 657 ret = max77620_set_fps_period(chip, fps, 658 chip->shutdown_fps_period[fps]); 659 if (ret < 0) 660 return ret; 661 } 662 663 /* 664 * For MAX20024: No need to configure WKEN0 on resume as 665 * it is configured on Init. 666 */ 667 if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663) 668 goto out; 669 670 /* Enable WK_EN0 */ 671 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 672 MAX77620_ONOFFCNFG2_WK_EN0, 673 MAX77620_ONOFFCNFG2_WK_EN0); 674 if (ret < 0) { 675 dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret); 676 return ret; 677 } 678 679 out: 680 enable_irq(client->irq); 681 682 return 0; 683 } 684 #endif 685 686 static const struct i2c_device_id max77620_id[] = { 687 {"max77620", MAX77620}, 688 {"max20024", MAX20024}, 689 {"max77663", MAX77663}, 690 {}, 691 }; 692 693 static const struct dev_pm_ops max77620_pm_ops = { 694 SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume) 695 }; 696 697 static struct i2c_driver max77620_driver = { 698 .driver = { 699 .name = "max77620", 700 .pm = &max77620_pm_ops, 701 }, 702 .probe = max77620_probe, 703 .id_table = max77620_id, 704 }; 705 builtin_i2c_driver(max77620_driver); 706