1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2327156c5SLaxman Dewangan /* 3327156c5SLaxman Dewangan * Maxim MAX77620 MFD Driver 4327156c5SLaxman Dewangan * 5327156c5SLaxman Dewangan * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. 6327156c5SLaxman Dewangan * 7327156c5SLaxman Dewangan * Author: 8327156c5SLaxman Dewangan * Laxman Dewangan <ldewangan@nvidia.com> 9327156c5SLaxman Dewangan * Chaitanya Bandi <bandik@nvidia.com> 10327156c5SLaxman Dewangan * Mallikarjun Kasoju <mkasoju@nvidia.com> 11327156c5SLaxman Dewangan */ 12327156c5SLaxman Dewangan 13327156c5SLaxman Dewangan /****************** Teminology used in driver ******************** 14327156c5SLaxman Dewangan * Here are some terminology used from datasheet for quick reference: 15327156c5SLaxman Dewangan * Flexible Power Sequence (FPS): 16327156c5SLaxman Dewangan * The Flexible Power Sequencer (FPS) allows each regulator to power up under 17327156c5SLaxman Dewangan * hardware or software control. Additionally, each regulator can power on 18327156c5SLaxman Dewangan * independently or among a group of other regulators with an adjustable 19327156c5SLaxman Dewangan * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can 20327156c5SLaxman Dewangan * be programmed to be part of a sequence allowing external regulators to be 21327156c5SLaxman Dewangan * sequenced along with internal regulators. 32KHz clock can be programmed to 22327156c5SLaxman Dewangan * be part of a sequence. 23327156c5SLaxman Dewangan * There is 3 FPS confguration registers and all resources are configured to 24327156c5SLaxman Dewangan * any of these FPS or no FPS. 25327156c5SLaxman Dewangan */ 26327156c5SLaxman Dewangan 27327156c5SLaxman Dewangan #include <linux/i2c.h> 28327156c5SLaxman Dewangan #include <linux/interrupt.h> 29327156c5SLaxman Dewangan #include <linux/mfd/core.h> 30327156c5SLaxman Dewangan #include <linux/mfd/max77620.h> 31c1fe7c45SPaul Gortmaker #include <linux/init.h> 32327156c5SLaxman Dewangan #include <linux/of.h> 33327156c5SLaxman Dewangan #include <linux/of_device.h> 34327156c5SLaxman Dewangan #include <linux/regmap.h> 35327156c5SLaxman Dewangan #include <linux/slab.h> 36327156c5SLaxman Dewangan 37744b1310SDmitry Osipenko static struct max77620_chip *max77620_scratch; 38744b1310SDmitry Osipenko 392be59755SAxel Lin static const struct resource gpio_resources[] = { 40327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO), 41327156c5SLaxman Dewangan }; 42327156c5SLaxman Dewangan 432be59755SAxel Lin static const struct resource power_resources[] = { 44327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW), 45327156c5SLaxman Dewangan }; 46327156c5SLaxman Dewangan 472be59755SAxel Lin static const struct resource rtc_resources[] = { 48327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC), 49327156c5SLaxman Dewangan }; 50327156c5SLaxman Dewangan 512be59755SAxel Lin static const struct resource thermal_resources[] = { 52327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1), 53327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2), 54327156c5SLaxman Dewangan }; 55327156c5SLaxman Dewangan 56327156c5SLaxman Dewangan static const struct regmap_irq max77620_top_irqs[] = { 57327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK), 58327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK), 59327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK), 60327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK), 61327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK), 62327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK), 63327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK), 64327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK), 65327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK), 66327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK), 67327156c5SLaxman Dewangan }; 68327156c5SLaxman Dewangan 69327156c5SLaxman Dewangan static const struct mfd_cell max77620_children[] = { 70327156c5SLaxman Dewangan { .name = "max77620-pinctrl", }, 71327156c5SLaxman Dewangan { .name = "max77620-clock", }, 72327156c5SLaxman Dewangan { .name = "max77620-pmic", }, 73327156c5SLaxman Dewangan { .name = "max77620-watchdog", }, 74327156c5SLaxman Dewangan { 75327156c5SLaxman Dewangan .name = "max77620-gpio", 76327156c5SLaxman Dewangan .resources = gpio_resources, 77327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(gpio_resources), 78327156c5SLaxman Dewangan }, { 79327156c5SLaxman Dewangan .name = "max77620-rtc", 80327156c5SLaxman Dewangan .resources = rtc_resources, 81327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(rtc_resources), 82327156c5SLaxman Dewangan }, { 83327156c5SLaxman Dewangan .name = "max77620-power", 84327156c5SLaxman Dewangan .resources = power_resources, 85327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(power_resources), 86327156c5SLaxman Dewangan }, { 87327156c5SLaxman Dewangan .name = "max77620-thermal", 88327156c5SLaxman Dewangan .resources = thermal_resources, 89327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(thermal_resources), 90327156c5SLaxman Dewangan }, 91327156c5SLaxman Dewangan }; 92327156c5SLaxman Dewangan 93327156c5SLaxman Dewangan static const struct mfd_cell max20024_children[] = { 94327156c5SLaxman Dewangan { .name = "max20024-pinctrl", }, 95327156c5SLaxman Dewangan { .name = "max77620-clock", }, 96327156c5SLaxman Dewangan { .name = "max20024-pmic", }, 97327156c5SLaxman Dewangan { .name = "max77620-watchdog", }, 98327156c5SLaxman Dewangan { 99327156c5SLaxman Dewangan .name = "max77620-gpio", 100327156c5SLaxman Dewangan .resources = gpio_resources, 101327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(gpio_resources), 102327156c5SLaxman Dewangan }, { 103327156c5SLaxman Dewangan .name = "max77620-rtc", 104327156c5SLaxman Dewangan .resources = rtc_resources, 105327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(rtc_resources), 106327156c5SLaxman Dewangan }, { 107327156c5SLaxman Dewangan .name = "max20024-power", 108327156c5SLaxman Dewangan .resources = power_resources, 109327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(power_resources), 110327156c5SLaxman Dewangan }, 111327156c5SLaxman Dewangan }; 112327156c5SLaxman Dewangan 1134c58f701SDmitry Osipenko static const struct mfd_cell max77663_children[] = { 1144c58f701SDmitry Osipenko { .name = "max77620-pinctrl", }, 1154c58f701SDmitry Osipenko { .name = "max77620-clock", }, 1164c58f701SDmitry Osipenko { .name = "max77663-pmic", }, 1174c58f701SDmitry Osipenko { .name = "max77620-watchdog", }, 1184c58f701SDmitry Osipenko { 1194c58f701SDmitry Osipenko .name = "max77620-gpio", 1204c58f701SDmitry Osipenko .resources = gpio_resources, 1214c58f701SDmitry Osipenko .num_resources = ARRAY_SIZE(gpio_resources), 1224c58f701SDmitry Osipenko }, { 1234c58f701SDmitry Osipenko .name = "max77620-rtc", 1244c58f701SDmitry Osipenko .resources = rtc_resources, 1254c58f701SDmitry Osipenko .num_resources = ARRAY_SIZE(rtc_resources), 1264c58f701SDmitry Osipenko }, { 1274c58f701SDmitry Osipenko .name = "max77663-power", 1284c58f701SDmitry Osipenko .resources = power_resources, 1294c58f701SDmitry Osipenko .num_resources = ARRAY_SIZE(power_resources), 1304c58f701SDmitry Osipenko }, 1314c58f701SDmitry Osipenko }; 1324c58f701SDmitry Osipenko 133327156c5SLaxman Dewangan static const struct regmap_range max77620_readable_ranges[] = { 134327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 135327156c5SLaxman Dewangan }; 136327156c5SLaxman Dewangan 137327156c5SLaxman Dewangan static const struct regmap_access_table max77620_readable_table = { 138327156c5SLaxman Dewangan .yes_ranges = max77620_readable_ranges, 139327156c5SLaxman Dewangan .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges), 140327156c5SLaxman Dewangan }; 141327156c5SLaxman Dewangan 142327156c5SLaxman Dewangan static const struct regmap_range max20024_readable_ranges[] = { 143327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 144327156c5SLaxman Dewangan regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD), 145327156c5SLaxman Dewangan }; 146327156c5SLaxman Dewangan 147327156c5SLaxman Dewangan static const struct regmap_access_table max20024_readable_table = { 148327156c5SLaxman Dewangan .yes_ranges = max20024_readable_ranges, 149327156c5SLaxman Dewangan .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges), 150327156c5SLaxman Dewangan }; 151327156c5SLaxman Dewangan 152327156c5SLaxman Dewangan static const struct regmap_range max77620_writable_ranges[] = { 153327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 154327156c5SLaxman Dewangan }; 155327156c5SLaxman Dewangan 156327156c5SLaxman Dewangan static const struct regmap_access_table max77620_writable_table = { 157327156c5SLaxman Dewangan .yes_ranges = max77620_writable_ranges, 158327156c5SLaxman Dewangan .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges), 159327156c5SLaxman Dewangan }; 160327156c5SLaxman Dewangan 161327156c5SLaxman Dewangan static const struct regmap_range max77620_cacheable_ranges[] = { 162327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3), 163327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3), 164327156c5SLaxman Dewangan }; 165327156c5SLaxman Dewangan 166327156c5SLaxman Dewangan static const struct regmap_access_table max77620_volatile_table = { 167327156c5SLaxman Dewangan .no_ranges = max77620_cacheable_ranges, 168327156c5SLaxman Dewangan .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges), 169327156c5SLaxman Dewangan }; 170327156c5SLaxman Dewangan 171327156c5SLaxman Dewangan static const struct regmap_config max77620_regmap_config = { 172327156c5SLaxman Dewangan .name = "power-slave", 173327156c5SLaxman Dewangan .reg_bits = 8, 174327156c5SLaxman Dewangan .val_bits = 8, 175327156c5SLaxman Dewangan .max_register = MAX77620_REG_DVSSD4 + 1, 176327156c5SLaxman Dewangan .cache_type = REGCACHE_RBTREE, 177327156c5SLaxman Dewangan .rd_table = &max77620_readable_table, 178327156c5SLaxman Dewangan .wr_table = &max77620_writable_table, 179327156c5SLaxman Dewangan .volatile_table = &max77620_volatile_table, 180327156c5SLaxman Dewangan }; 181327156c5SLaxman Dewangan 182327156c5SLaxman Dewangan static const struct regmap_config max20024_regmap_config = { 183327156c5SLaxman Dewangan .name = "power-slave", 184327156c5SLaxman Dewangan .reg_bits = 8, 185327156c5SLaxman Dewangan .val_bits = 8, 186327156c5SLaxman Dewangan .max_register = MAX20024_REG_MAX_ADD + 1, 187327156c5SLaxman Dewangan .cache_type = REGCACHE_RBTREE, 188327156c5SLaxman Dewangan .rd_table = &max20024_readable_table, 189327156c5SLaxman Dewangan .wr_table = &max77620_writable_table, 190327156c5SLaxman Dewangan .volatile_table = &max77620_volatile_table, 191327156c5SLaxman Dewangan }; 192327156c5SLaxman Dewangan 1934c58f701SDmitry Osipenko static const struct regmap_range max77663_readable_ranges[] = { 1944c58f701SDmitry Osipenko regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5), 1954c58f701SDmitry Osipenko }; 1964c58f701SDmitry Osipenko 1974c58f701SDmitry Osipenko static const struct regmap_access_table max77663_readable_table = { 1984c58f701SDmitry Osipenko .yes_ranges = max77663_readable_ranges, 1994c58f701SDmitry Osipenko .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges), 2004c58f701SDmitry Osipenko }; 2014c58f701SDmitry Osipenko 2024c58f701SDmitry Osipenko static const struct regmap_range max77663_writable_ranges[] = { 2034c58f701SDmitry Osipenko regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5), 2044c58f701SDmitry Osipenko }; 2054c58f701SDmitry Osipenko 2064c58f701SDmitry Osipenko static const struct regmap_access_table max77663_writable_table = { 2074c58f701SDmitry Osipenko .yes_ranges = max77663_writable_ranges, 2084c58f701SDmitry Osipenko .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges), 2094c58f701SDmitry Osipenko }; 2104c58f701SDmitry Osipenko 2114c58f701SDmitry Osipenko static const struct regmap_config max77663_regmap_config = { 2124c58f701SDmitry Osipenko .name = "power-slave", 2134c58f701SDmitry Osipenko .reg_bits = 8, 2144c58f701SDmitry Osipenko .val_bits = 8, 2154c58f701SDmitry Osipenko .max_register = MAX77620_REG_CID5 + 1, 2164c58f701SDmitry Osipenko .cache_type = REGCACHE_RBTREE, 2174c58f701SDmitry Osipenko .rd_table = &max77663_readable_table, 2184c58f701SDmitry Osipenko .wr_table = &max77663_writable_table, 2194c58f701SDmitry Osipenko .volatile_table = &max77620_volatile_table, 2204c58f701SDmitry Osipenko }; 2214c58f701SDmitry Osipenko 2223df140d1SLaxman Dewangan /* 2233df140d1SLaxman Dewangan * MAX77620 and MAX20024 has the following steps of the interrupt handling 2243df140d1SLaxman Dewangan * for TOP interrupts: 2253df140d1SLaxman Dewangan * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM. 2263df140d1SLaxman Dewangan * 2. Read IRQTOP and service the interrupt. 2273df140d1SLaxman Dewangan * 3. Once all interrupts has been checked and serviced, the interrupt service 2283df140d1SLaxman Dewangan * routine un-masks the hardware interrupt line by clearing GLBLM. 2293df140d1SLaxman Dewangan */ 2303df140d1SLaxman Dewangan static int max77620_irq_global_mask(void *irq_drv_data) 2313df140d1SLaxman Dewangan { 2323df140d1SLaxman Dewangan struct max77620_chip *chip = irq_drv_data; 2333df140d1SLaxman Dewangan int ret; 2343df140d1SLaxman Dewangan 2353df140d1SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 2363df140d1SLaxman Dewangan MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK); 2373df140d1SLaxman Dewangan if (ret < 0) 2383df140d1SLaxman Dewangan dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret); 2393df140d1SLaxman Dewangan 2403df140d1SLaxman Dewangan return ret; 2413df140d1SLaxman Dewangan } 2423df140d1SLaxman Dewangan 2433df140d1SLaxman Dewangan static int max77620_irq_global_unmask(void *irq_drv_data) 2443df140d1SLaxman Dewangan { 2453df140d1SLaxman Dewangan struct max77620_chip *chip = irq_drv_data; 2463df140d1SLaxman Dewangan int ret; 2473df140d1SLaxman Dewangan 2483df140d1SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 2493df140d1SLaxman Dewangan MAX77620_GLBLM_MASK, 0); 2503df140d1SLaxman Dewangan if (ret < 0) 2513df140d1SLaxman Dewangan dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret); 2523df140d1SLaxman Dewangan 2533df140d1SLaxman Dewangan return ret; 2543df140d1SLaxman Dewangan } 2553df140d1SLaxman Dewangan 2563df140d1SLaxman Dewangan static struct regmap_irq_chip max77620_top_irq_chip = { 2573df140d1SLaxman Dewangan .name = "max77620-top", 2583df140d1SLaxman Dewangan .irqs = max77620_top_irqs, 2593df140d1SLaxman Dewangan .num_irqs = ARRAY_SIZE(max77620_top_irqs), 2603df140d1SLaxman Dewangan .num_regs = 2, 2613df140d1SLaxman Dewangan .status_base = MAX77620_REG_IRQTOP, 2623df140d1SLaxman Dewangan .mask_base = MAX77620_REG_IRQTOPM, 2633df140d1SLaxman Dewangan .handle_pre_irq = max77620_irq_global_mask, 2643df140d1SLaxman Dewangan .handle_post_irq = max77620_irq_global_unmask, 2653df140d1SLaxman Dewangan }; 2663df140d1SLaxman Dewangan 267327156c5SLaxman Dewangan /* max77620_get_fps_period_reg_value: Get FPS bit field value from 268327156c5SLaxman Dewangan * requested periods. 269327156c5SLaxman Dewangan * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560 270327156c5SLaxman Dewangan * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80, 271327156c5SLaxman Dewangan * 160, 320, 540, 1280 and 2560 microseconds. 272327156c5SLaxman Dewangan * The FPS register has 3 bits field to set the FPS period as 273327156c5SLaxman Dewangan * bits max77620 max20024 274327156c5SLaxman Dewangan * 000 40 20 275327156c5SLaxman Dewangan * 001 80 40 276327156c5SLaxman Dewangan * ::: 277327156c5SLaxman Dewangan */ 278327156c5SLaxman Dewangan static int max77620_get_fps_period_reg_value(struct max77620_chip *chip, 279327156c5SLaxman Dewangan int tperiod) 280327156c5SLaxman Dewangan { 281327156c5SLaxman Dewangan int fps_min_period; 282327156c5SLaxman Dewangan int i; 283327156c5SLaxman Dewangan 284327156c5SLaxman Dewangan switch (chip->chip_id) { 285327156c5SLaxman Dewangan case MAX20024: 286327156c5SLaxman Dewangan fps_min_period = MAX20024_FPS_PERIOD_MIN_US; 287327156c5SLaxman Dewangan break; 288327156c5SLaxman Dewangan case MAX77620: 289327156c5SLaxman Dewangan fps_min_period = MAX77620_FPS_PERIOD_MIN_US; 29082d8eb40SRhyland Klein break; 2914c58f701SDmitry Osipenko case MAX77663: 2924c58f701SDmitry Osipenko fps_min_period = MAX20024_FPS_PERIOD_MIN_US; 2934c58f701SDmitry Osipenko break; 294327156c5SLaxman Dewangan default: 295327156c5SLaxman Dewangan return -EINVAL; 296327156c5SLaxman Dewangan } 297327156c5SLaxman Dewangan 298327156c5SLaxman Dewangan for (i = 0; i < 7; i++) { 299327156c5SLaxman Dewangan if (fps_min_period >= tperiod) 300327156c5SLaxman Dewangan return i; 301327156c5SLaxman Dewangan fps_min_period *= 2; 302327156c5SLaxman Dewangan } 303327156c5SLaxman Dewangan 304327156c5SLaxman Dewangan return i; 305327156c5SLaxman Dewangan } 306327156c5SLaxman Dewangan 307327156c5SLaxman Dewangan /* max77620_config_fps: Configure FPS configuration registers 308327156c5SLaxman Dewangan * based on platform specific information. 309327156c5SLaxman Dewangan */ 310327156c5SLaxman Dewangan static int max77620_config_fps(struct max77620_chip *chip, 311327156c5SLaxman Dewangan struct device_node *fps_np) 312327156c5SLaxman Dewangan { 313327156c5SLaxman Dewangan struct device *dev = chip->dev; 314327156c5SLaxman Dewangan unsigned int mask = 0, config = 0; 315327156c5SLaxman Dewangan u32 fps_max_period; 316327156c5SLaxman Dewangan u32 param_val; 317327156c5SLaxman Dewangan int tperiod, fps_id; 318327156c5SLaxman Dewangan int ret; 319327156c5SLaxman Dewangan char fps_name[10]; 320327156c5SLaxman Dewangan 321327156c5SLaxman Dewangan switch (chip->chip_id) { 322327156c5SLaxman Dewangan case MAX20024: 323327156c5SLaxman Dewangan fps_max_period = MAX20024_FPS_PERIOD_MAX_US; 324327156c5SLaxman Dewangan break; 325327156c5SLaxman Dewangan case MAX77620: 326327156c5SLaxman Dewangan fps_max_period = MAX77620_FPS_PERIOD_MAX_US; 32782d8eb40SRhyland Klein break; 3284c58f701SDmitry Osipenko case MAX77663: 3294c58f701SDmitry Osipenko fps_max_period = MAX20024_FPS_PERIOD_MAX_US; 3304c58f701SDmitry Osipenko break; 331327156c5SLaxman Dewangan default: 332327156c5SLaxman Dewangan return -EINVAL; 333327156c5SLaxman Dewangan } 334327156c5SLaxman Dewangan 335327156c5SLaxman Dewangan for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 336327156c5SLaxman Dewangan sprintf(fps_name, "fps%d", fps_id); 33738df91ccSRob Herring if (of_node_name_eq(fps_np, fps_name)) 338327156c5SLaxman Dewangan break; 339327156c5SLaxman Dewangan } 340327156c5SLaxman Dewangan 341327156c5SLaxman Dewangan if (fps_id == MAX77620_FPS_COUNT) { 34275a11072SRob Herring dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np); 343327156c5SLaxman Dewangan return -EINVAL; 344327156c5SLaxman Dewangan } 345327156c5SLaxman Dewangan 346327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us", 347327156c5SLaxman Dewangan ¶m_val); 348327156c5SLaxman Dewangan if (!ret) { 349327156c5SLaxman Dewangan mask |= MAX77620_FPS_TIME_PERIOD_MASK; 350327156c5SLaxman Dewangan chip->shutdown_fps_period[fps_id] = min(param_val, 351327156c5SLaxman Dewangan fps_max_period); 352327156c5SLaxman Dewangan tperiod = max77620_get_fps_period_reg_value(chip, 353327156c5SLaxman Dewangan chip->shutdown_fps_period[fps_id]); 354327156c5SLaxman Dewangan config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT; 355327156c5SLaxman Dewangan } 356327156c5SLaxman Dewangan 357327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us", 358327156c5SLaxman Dewangan ¶m_val); 359327156c5SLaxman Dewangan if (!ret) 360327156c5SLaxman Dewangan chip->suspend_fps_period[fps_id] = min(param_val, 361327156c5SLaxman Dewangan fps_max_period); 362327156c5SLaxman Dewangan 363327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, "maxim,fps-event-source", 364327156c5SLaxman Dewangan ¶m_val); 365327156c5SLaxman Dewangan if (!ret) { 366327156c5SLaxman Dewangan if (param_val > 2) { 367327156c5SLaxman Dewangan dev_err(dev, "FPS%d event-source invalid\n", fps_id); 368327156c5SLaxman Dewangan return -EINVAL; 369327156c5SLaxman Dewangan } 370327156c5SLaxman Dewangan mask |= MAX77620_FPS_EN_SRC_MASK; 371327156c5SLaxman Dewangan config |= param_val << MAX77620_FPS_EN_SRC_SHIFT; 372327156c5SLaxman Dewangan if (param_val == 2) { 373327156c5SLaxman Dewangan mask |= MAX77620_FPS_ENFPS_SW_MASK; 374327156c5SLaxman Dewangan config |= MAX77620_FPS_ENFPS_SW; 375327156c5SLaxman Dewangan } 376327156c5SLaxman Dewangan } 377327156c5SLaxman Dewangan 378327156c5SLaxman Dewangan if (!chip->sleep_enable && !chip->enable_global_lpm) { 379327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, 380327156c5SLaxman Dewangan "maxim,device-state-on-disabled-event", 381327156c5SLaxman Dewangan ¶m_val); 382327156c5SLaxman Dewangan if (!ret) { 383327156c5SLaxman Dewangan if (param_val == 0) 384327156c5SLaxman Dewangan chip->sleep_enable = true; 385327156c5SLaxman Dewangan else if (param_val == 1) 386327156c5SLaxman Dewangan chip->enable_global_lpm = true; 387327156c5SLaxman Dewangan } 388327156c5SLaxman Dewangan } 389327156c5SLaxman Dewangan 390327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 391327156c5SLaxman Dewangan mask, config); 392327156c5SLaxman Dewangan if (ret < 0) { 393327156c5SLaxman Dewangan dev_err(dev, "Failed to update FPS CFG: %d\n", ret); 394327156c5SLaxman Dewangan return ret; 395327156c5SLaxman Dewangan } 396327156c5SLaxman Dewangan 397327156c5SLaxman Dewangan return 0; 398327156c5SLaxman Dewangan } 399327156c5SLaxman Dewangan 400327156c5SLaxman Dewangan static int max77620_initialise_fps(struct max77620_chip *chip) 401327156c5SLaxman Dewangan { 402327156c5SLaxman Dewangan struct device *dev = chip->dev; 403327156c5SLaxman Dewangan struct device_node *fps_np, *fps_child; 404327156c5SLaxman Dewangan u8 config; 405327156c5SLaxman Dewangan int fps_id; 406327156c5SLaxman Dewangan int ret; 407327156c5SLaxman Dewangan 408327156c5SLaxman Dewangan for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 409327156c5SLaxman Dewangan chip->shutdown_fps_period[fps_id] = -1; 410327156c5SLaxman Dewangan chip->suspend_fps_period[fps_id] = -1; 411327156c5SLaxman Dewangan } 412327156c5SLaxman Dewangan 413327156c5SLaxman Dewangan fps_np = of_get_child_by_name(dev->of_node, "fps"); 414327156c5SLaxman Dewangan if (!fps_np) 415327156c5SLaxman Dewangan goto skip_fps; 416327156c5SLaxman Dewangan 417327156c5SLaxman Dewangan for_each_child_of_node(fps_np, fps_child) { 418327156c5SLaxman Dewangan ret = max77620_config_fps(chip, fps_child); 419197df18fSNishka Dasgupta if (ret < 0) { 420197df18fSNishka Dasgupta of_node_put(fps_child); 421327156c5SLaxman Dewangan return ret; 422327156c5SLaxman Dewangan } 423197df18fSNishka Dasgupta } 424327156c5SLaxman Dewangan 425327156c5SLaxman Dewangan config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0; 426327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 427327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config); 428327156c5SLaxman Dewangan if (ret < 0) { 429327156c5SLaxman Dewangan dev_err(dev, "Failed to update SLP_LPM: %d\n", ret); 430327156c5SLaxman Dewangan return ret; 431327156c5SLaxman Dewangan } 432327156c5SLaxman Dewangan 433327156c5SLaxman Dewangan skip_fps: 4344c58f701SDmitry Osipenko if (chip->chip_id == MAX77663) 4354c58f701SDmitry Osipenko return 0; 4364c58f701SDmitry Osipenko 437327156c5SLaxman Dewangan /* Enable wake on EN0 pin */ 438327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 439327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0, 440327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0); 441327156c5SLaxman Dewangan if (ret < 0) { 442327156c5SLaxman Dewangan dev_err(dev, "Failed to update WK_EN0: %d\n", ret); 443327156c5SLaxman Dewangan return ret; 444327156c5SLaxman Dewangan } 445327156c5SLaxman Dewangan 446327156c5SLaxman Dewangan /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */ 447327156c5SLaxman Dewangan if ((chip->chip_id == MAX20024) && chip->sleep_enable) { 448327156c5SLaxman Dewangan config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE; 449327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 450327156c5SLaxman Dewangan config, config); 451327156c5SLaxman Dewangan if (ret < 0) { 452327156c5SLaxman Dewangan dev_err(dev, "Failed to update SLPEN: %d\n", ret); 453327156c5SLaxman Dewangan return ret; 454327156c5SLaxman Dewangan } 455327156c5SLaxman Dewangan } 456327156c5SLaxman Dewangan 457327156c5SLaxman Dewangan return 0; 458327156c5SLaxman Dewangan } 459327156c5SLaxman Dewangan 460327156c5SLaxman Dewangan static int max77620_read_es_version(struct max77620_chip *chip) 461327156c5SLaxman Dewangan { 462327156c5SLaxman Dewangan unsigned int val; 463327156c5SLaxman Dewangan u8 cid_val[6]; 464327156c5SLaxman Dewangan int i; 465327156c5SLaxman Dewangan int ret; 466327156c5SLaxman Dewangan 467327156c5SLaxman Dewangan for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) { 468327156c5SLaxman Dewangan ret = regmap_read(chip->rmap, i, &val); 469327156c5SLaxman Dewangan if (ret < 0) { 470327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to read CID: %d\n", ret); 471327156c5SLaxman Dewangan return ret; 472327156c5SLaxman Dewangan } 473327156c5SLaxman Dewangan dev_dbg(chip->dev, "CID%d: 0x%02x\n", 474327156c5SLaxman Dewangan i - MAX77620_REG_CID0, val); 475327156c5SLaxman Dewangan cid_val[i - MAX77620_REG_CID0] = val; 476327156c5SLaxman Dewangan } 477327156c5SLaxman Dewangan 478327156c5SLaxman Dewangan /* CID4 is OTP Version and CID5 is ES version */ 479327156c5SLaxman Dewangan dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n", 480327156c5SLaxman Dewangan cid_val[4], MAX77620_CID5_DIDM(cid_val[5])); 481327156c5SLaxman Dewangan 482327156c5SLaxman Dewangan return ret; 483327156c5SLaxman Dewangan } 484327156c5SLaxman Dewangan 485744b1310SDmitry Osipenko static void max77620_pm_power_off(void) 486744b1310SDmitry Osipenko { 487744b1310SDmitry Osipenko struct max77620_chip *chip = max77620_scratch; 488744b1310SDmitry Osipenko 489744b1310SDmitry Osipenko regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 490744b1310SDmitry Osipenko MAX77620_ONOFFCNFG1_SFT_RST, 491744b1310SDmitry Osipenko MAX77620_ONOFFCNFG1_SFT_RST); 492744b1310SDmitry Osipenko } 493744b1310SDmitry Osipenko 494327156c5SLaxman Dewangan static int max77620_probe(struct i2c_client *client, 495327156c5SLaxman Dewangan const struct i2c_device_id *id) 496327156c5SLaxman Dewangan { 497327156c5SLaxman Dewangan const struct regmap_config *rmap_config; 498327156c5SLaxman Dewangan struct max77620_chip *chip; 499327156c5SLaxman Dewangan const struct mfd_cell *mfd_cells; 500327156c5SLaxman Dewangan int n_mfd_cells; 501744b1310SDmitry Osipenko bool pm_off; 502327156c5SLaxman Dewangan int ret; 503327156c5SLaxman Dewangan 504327156c5SLaxman Dewangan chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 505327156c5SLaxman Dewangan if (!chip) 506327156c5SLaxman Dewangan return -ENOMEM; 507327156c5SLaxman Dewangan 508327156c5SLaxman Dewangan i2c_set_clientdata(client, chip); 509327156c5SLaxman Dewangan chip->dev = &client->dev; 510327156c5SLaxman Dewangan chip->chip_irq = client->irq; 511327156c5SLaxman Dewangan chip->chip_id = (enum max77620_chip_id)id->driver_data; 512327156c5SLaxman Dewangan 513327156c5SLaxman Dewangan switch (chip->chip_id) { 514327156c5SLaxman Dewangan case MAX77620: 515327156c5SLaxman Dewangan mfd_cells = max77620_children; 516327156c5SLaxman Dewangan n_mfd_cells = ARRAY_SIZE(max77620_children); 517327156c5SLaxman Dewangan rmap_config = &max77620_regmap_config; 518327156c5SLaxman Dewangan break; 519327156c5SLaxman Dewangan case MAX20024: 520327156c5SLaxman Dewangan mfd_cells = max20024_children; 521327156c5SLaxman Dewangan n_mfd_cells = ARRAY_SIZE(max20024_children); 522327156c5SLaxman Dewangan rmap_config = &max20024_regmap_config; 523327156c5SLaxman Dewangan break; 5244c58f701SDmitry Osipenko case MAX77663: 5254c58f701SDmitry Osipenko mfd_cells = max77663_children; 5264c58f701SDmitry Osipenko n_mfd_cells = ARRAY_SIZE(max77663_children); 5274c58f701SDmitry Osipenko rmap_config = &max77663_regmap_config; 5284c58f701SDmitry Osipenko break; 529327156c5SLaxman Dewangan default: 530327156c5SLaxman Dewangan dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id); 531327156c5SLaxman Dewangan return -EINVAL; 532327156c5SLaxman Dewangan } 533327156c5SLaxman Dewangan 534327156c5SLaxman Dewangan chip->rmap = devm_regmap_init_i2c(client, rmap_config); 535327156c5SLaxman Dewangan if (IS_ERR(chip->rmap)) { 536327156c5SLaxman Dewangan ret = PTR_ERR(chip->rmap); 5379165dabbSMasanari Iida dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret); 538327156c5SLaxman Dewangan return ret; 539327156c5SLaxman Dewangan } 540327156c5SLaxman Dewangan 541327156c5SLaxman Dewangan ret = max77620_read_es_version(chip); 542327156c5SLaxman Dewangan if (ret < 0) 543327156c5SLaxman Dewangan return ret; 544327156c5SLaxman Dewangan 5453df140d1SLaxman Dewangan max77620_top_irq_chip.irq_drv_data = chip; 546327156c5SLaxman Dewangan ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq, 5477f0e60c7SThierry Reding IRQF_ONESHOT | IRQF_SHARED, 0, 5487f0e60c7SThierry Reding &max77620_top_irq_chip, 549327156c5SLaxman Dewangan &chip->top_irq_data); 550327156c5SLaxman Dewangan if (ret < 0) { 551327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret); 552327156c5SLaxman Dewangan return ret; 553327156c5SLaxman Dewangan } 554327156c5SLaxman Dewangan 555327156c5SLaxman Dewangan ret = max77620_initialise_fps(chip); 556327156c5SLaxman Dewangan if (ret < 0) 557327156c5SLaxman Dewangan return ret; 558327156c5SLaxman Dewangan 559327156c5SLaxman Dewangan ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, 560327156c5SLaxman Dewangan mfd_cells, n_mfd_cells, NULL, 0, 561327156c5SLaxman Dewangan regmap_irq_get_domain(chip->top_irq_data)); 562327156c5SLaxman Dewangan if (ret < 0) { 563327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to add MFD children: %d\n", ret); 564327156c5SLaxman Dewangan return ret; 565327156c5SLaxman Dewangan } 566327156c5SLaxman Dewangan 567744b1310SDmitry Osipenko pm_off = of_device_is_system_power_controller(client->dev.of_node); 568744b1310SDmitry Osipenko if (pm_off && !pm_power_off) { 569744b1310SDmitry Osipenko max77620_scratch = chip; 570744b1310SDmitry Osipenko pm_power_off = max77620_pm_power_off; 571744b1310SDmitry Osipenko } 572744b1310SDmitry Osipenko 573327156c5SLaxman Dewangan return 0; 574327156c5SLaxman Dewangan } 575327156c5SLaxman Dewangan 576327156c5SLaxman Dewangan #ifdef CONFIG_PM_SLEEP 577327156c5SLaxman Dewangan static int max77620_set_fps_period(struct max77620_chip *chip, 578327156c5SLaxman Dewangan int fps_id, int time_period) 579327156c5SLaxman Dewangan { 580327156c5SLaxman Dewangan int period = max77620_get_fps_period_reg_value(chip, time_period); 581327156c5SLaxman Dewangan int ret; 582327156c5SLaxman Dewangan 583327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 584327156c5SLaxman Dewangan MAX77620_FPS_TIME_PERIOD_MASK, 585327156c5SLaxman Dewangan period << MAX77620_FPS_TIME_PERIOD_SHIFT); 586327156c5SLaxman Dewangan if (ret < 0) { 587327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to update FPS period: %d\n", ret); 588327156c5SLaxman Dewangan return ret; 589327156c5SLaxman Dewangan } 590327156c5SLaxman Dewangan 591327156c5SLaxman Dewangan return 0; 592327156c5SLaxman Dewangan } 593327156c5SLaxman Dewangan 594327156c5SLaxman Dewangan static int max77620_i2c_suspend(struct device *dev) 595327156c5SLaxman Dewangan { 596327156c5SLaxman Dewangan struct max77620_chip *chip = dev_get_drvdata(dev); 597327156c5SLaxman Dewangan struct i2c_client *client = to_i2c_client(dev); 598327156c5SLaxman Dewangan unsigned int config; 599327156c5SLaxman Dewangan int fps; 600327156c5SLaxman Dewangan int ret; 601327156c5SLaxman Dewangan 602327156c5SLaxman Dewangan for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 603327156c5SLaxman Dewangan if (chip->suspend_fps_period[fps] < 0) 604327156c5SLaxman Dewangan continue; 605327156c5SLaxman Dewangan 606327156c5SLaxman Dewangan ret = max77620_set_fps_period(chip, fps, 607327156c5SLaxman Dewangan chip->suspend_fps_period[fps]); 608327156c5SLaxman Dewangan if (ret < 0) 609327156c5SLaxman Dewangan return ret; 610327156c5SLaxman Dewangan } 611327156c5SLaxman Dewangan 612327156c5SLaxman Dewangan /* 613327156c5SLaxman Dewangan * For MAX20024: No need to configure SLPEN on suspend as 614327156c5SLaxman Dewangan * it will be configured on Init. 615327156c5SLaxman Dewangan */ 616327156c5SLaxman Dewangan if (chip->chip_id == MAX20024) 617327156c5SLaxman Dewangan goto out; 618327156c5SLaxman Dewangan 619327156c5SLaxman Dewangan config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0; 620327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 621327156c5SLaxman Dewangan MAX77620_ONOFFCNFG1_SLPEN, 622327156c5SLaxman Dewangan config); 623327156c5SLaxman Dewangan if (ret < 0) { 624327156c5SLaxman Dewangan dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret); 625327156c5SLaxman Dewangan return ret; 626327156c5SLaxman Dewangan } 627327156c5SLaxman Dewangan 6284c58f701SDmitry Osipenko if (chip->chip_id == MAX77663) 6294c58f701SDmitry Osipenko goto out; 6304c58f701SDmitry Osipenko 631327156c5SLaxman Dewangan /* Disable WK_EN0 */ 632327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 633327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0, 0); 634327156c5SLaxman Dewangan if (ret < 0) { 635327156c5SLaxman Dewangan dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret); 636327156c5SLaxman Dewangan return ret; 637327156c5SLaxman Dewangan } 638327156c5SLaxman Dewangan 639327156c5SLaxman Dewangan out: 640327156c5SLaxman Dewangan disable_irq(client->irq); 641327156c5SLaxman Dewangan 642327156c5SLaxman Dewangan return 0; 643327156c5SLaxman Dewangan } 644327156c5SLaxman Dewangan 645327156c5SLaxman Dewangan static int max77620_i2c_resume(struct device *dev) 646327156c5SLaxman Dewangan { 647327156c5SLaxman Dewangan struct max77620_chip *chip = dev_get_drvdata(dev); 648327156c5SLaxman Dewangan struct i2c_client *client = to_i2c_client(dev); 649327156c5SLaxman Dewangan int ret; 650327156c5SLaxman Dewangan int fps; 651327156c5SLaxman Dewangan 652327156c5SLaxman Dewangan for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 653327156c5SLaxman Dewangan if (chip->shutdown_fps_period[fps] < 0) 654327156c5SLaxman Dewangan continue; 655327156c5SLaxman Dewangan 656327156c5SLaxman Dewangan ret = max77620_set_fps_period(chip, fps, 657327156c5SLaxman Dewangan chip->shutdown_fps_period[fps]); 658327156c5SLaxman Dewangan if (ret < 0) 659327156c5SLaxman Dewangan return ret; 660327156c5SLaxman Dewangan } 661327156c5SLaxman Dewangan 662327156c5SLaxman Dewangan /* 663327156c5SLaxman Dewangan * For MAX20024: No need to configure WKEN0 on resume as 664327156c5SLaxman Dewangan * it is configured on Init. 665327156c5SLaxman Dewangan */ 6664c58f701SDmitry Osipenko if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663) 667327156c5SLaxman Dewangan goto out; 668327156c5SLaxman Dewangan 669327156c5SLaxman Dewangan /* Enable WK_EN0 */ 670327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 671327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0, 672327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0); 673327156c5SLaxman Dewangan if (ret < 0) { 674327156c5SLaxman Dewangan dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret); 675327156c5SLaxman Dewangan return ret; 676327156c5SLaxman Dewangan } 677327156c5SLaxman Dewangan 678327156c5SLaxman Dewangan out: 679327156c5SLaxman Dewangan enable_irq(client->irq); 680327156c5SLaxman Dewangan 681327156c5SLaxman Dewangan return 0; 682327156c5SLaxman Dewangan } 683327156c5SLaxman Dewangan #endif 684327156c5SLaxman Dewangan 685327156c5SLaxman Dewangan static const struct i2c_device_id max77620_id[] = { 686327156c5SLaxman Dewangan {"max77620", MAX77620}, 687327156c5SLaxman Dewangan {"max20024", MAX20024}, 6884c58f701SDmitry Osipenko {"max77663", MAX77663}, 689327156c5SLaxman Dewangan {}, 690327156c5SLaxman Dewangan }; 691327156c5SLaxman Dewangan 692327156c5SLaxman Dewangan static const struct dev_pm_ops max77620_pm_ops = { 693327156c5SLaxman Dewangan SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume) 694327156c5SLaxman Dewangan }; 695327156c5SLaxman Dewangan 696327156c5SLaxman Dewangan static struct i2c_driver max77620_driver = { 697327156c5SLaxman Dewangan .driver = { 698327156c5SLaxman Dewangan .name = "max77620", 699327156c5SLaxman Dewangan .pm = &max77620_pm_ops, 700327156c5SLaxman Dewangan }, 701327156c5SLaxman Dewangan .probe = max77620_probe, 702327156c5SLaxman Dewangan .id_table = max77620_id, 703327156c5SLaxman Dewangan }; 704c1fe7c45SPaul Gortmaker builtin_i2c_driver(max77620_driver); 705