1327156c5SLaxman Dewangan /* 2327156c5SLaxman Dewangan * Maxim MAX77620 MFD Driver 3327156c5SLaxman Dewangan * 4327156c5SLaxman Dewangan * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. 5327156c5SLaxman Dewangan * 6327156c5SLaxman Dewangan * Author: 7327156c5SLaxman Dewangan * Laxman Dewangan <ldewangan@nvidia.com> 8327156c5SLaxman Dewangan * Chaitanya Bandi <bandik@nvidia.com> 9327156c5SLaxman Dewangan * Mallikarjun Kasoju <mkasoju@nvidia.com> 10327156c5SLaxman Dewangan * 11327156c5SLaxman Dewangan * This program is free software; you can redistribute it and/or modify 12327156c5SLaxman Dewangan * it under the terms of the GNU General Public License version 2 as 13327156c5SLaxman Dewangan * published by the Free Software Foundation. 14327156c5SLaxman Dewangan */ 15327156c5SLaxman Dewangan 16327156c5SLaxman Dewangan /****************** Teminology used in driver ******************** 17327156c5SLaxman Dewangan * Here are some terminology used from datasheet for quick reference: 18327156c5SLaxman Dewangan * Flexible Power Sequence (FPS): 19327156c5SLaxman Dewangan * The Flexible Power Sequencer (FPS) allows each regulator to power up under 20327156c5SLaxman Dewangan * hardware or software control. Additionally, each regulator can power on 21327156c5SLaxman Dewangan * independently or among a group of other regulators with an adjustable 22327156c5SLaxman Dewangan * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can 23327156c5SLaxman Dewangan * be programmed to be part of a sequence allowing external regulators to be 24327156c5SLaxman Dewangan * sequenced along with internal regulators. 32KHz clock can be programmed to 25327156c5SLaxman Dewangan * be part of a sequence. 26327156c5SLaxman Dewangan * There is 3 FPS confguration registers and all resources are configured to 27327156c5SLaxman Dewangan * any of these FPS or no FPS. 28327156c5SLaxman Dewangan */ 29327156c5SLaxman Dewangan 30327156c5SLaxman Dewangan #include <linux/i2c.h> 31327156c5SLaxman Dewangan #include <linux/interrupt.h> 32327156c5SLaxman Dewangan #include <linux/mfd/core.h> 33327156c5SLaxman Dewangan #include <linux/mfd/max77620.h> 34c1fe7c45SPaul Gortmaker #include <linux/init.h> 35327156c5SLaxman Dewangan #include <linux/of.h> 36327156c5SLaxman Dewangan #include <linux/of_device.h> 37327156c5SLaxman Dewangan #include <linux/regmap.h> 38327156c5SLaxman Dewangan #include <linux/slab.h> 39327156c5SLaxman Dewangan 402be59755SAxel Lin static const struct resource gpio_resources[] = { 41327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO), 42327156c5SLaxman Dewangan }; 43327156c5SLaxman Dewangan 442be59755SAxel Lin static const struct resource power_resources[] = { 45327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW), 46327156c5SLaxman Dewangan }; 47327156c5SLaxman Dewangan 482be59755SAxel Lin static const struct resource rtc_resources[] = { 49327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC), 50327156c5SLaxman Dewangan }; 51327156c5SLaxman Dewangan 522be59755SAxel Lin static const struct resource thermal_resources[] = { 53327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1), 54327156c5SLaxman Dewangan DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2), 55327156c5SLaxman Dewangan }; 56327156c5SLaxman Dewangan 57327156c5SLaxman Dewangan static const struct regmap_irq max77620_top_irqs[] = { 58327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK), 59327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK), 60327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK), 61327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK), 62327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK), 63327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK), 64327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK), 65327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK), 66327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK), 67327156c5SLaxman Dewangan REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK), 68327156c5SLaxman Dewangan }; 69327156c5SLaxman Dewangan 70327156c5SLaxman Dewangan static const struct mfd_cell max77620_children[] = { 71327156c5SLaxman Dewangan { .name = "max77620-pinctrl", }, 72327156c5SLaxman Dewangan { .name = "max77620-clock", }, 73327156c5SLaxman Dewangan { .name = "max77620-pmic", }, 74327156c5SLaxman Dewangan { .name = "max77620-watchdog", }, 75327156c5SLaxman Dewangan { 76327156c5SLaxman Dewangan .name = "max77620-gpio", 77327156c5SLaxman Dewangan .resources = gpio_resources, 78327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(gpio_resources), 79327156c5SLaxman Dewangan }, { 80327156c5SLaxman Dewangan .name = "max77620-rtc", 81327156c5SLaxman Dewangan .resources = rtc_resources, 82327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(rtc_resources), 83327156c5SLaxman Dewangan }, { 84327156c5SLaxman Dewangan .name = "max77620-power", 85327156c5SLaxman Dewangan .resources = power_resources, 86327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(power_resources), 87327156c5SLaxman Dewangan }, { 88327156c5SLaxman Dewangan .name = "max77620-thermal", 89327156c5SLaxman Dewangan .resources = thermal_resources, 90327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(thermal_resources), 91327156c5SLaxman Dewangan }, 92327156c5SLaxman Dewangan }; 93327156c5SLaxman Dewangan 94327156c5SLaxman Dewangan static const struct mfd_cell max20024_children[] = { 95327156c5SLaxman Dewangan { .name = "max20024-pinctrl", }, 96327156c5SLaxman Dewangan { .name = "max77620-clock", }, 97327156c5SLaxman Dewangan { .name = "max20024-pmic", }, 98327156c5SLaxman Dewangan { .name = "max77620-watchdog", }, 99327156c5SLaxman Dewangan { 100327156c5SLaxman Dewangan .name = "max77620-gpio", 101327156c5SLaxman Dewangan .resources = gpio_resources, 102327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(gpio_resources), 103327156c5SLaxman Dewangan }, { 104327156c5SLaxman Dewangan .name = "max77620-rtc", 105327156c5SLaxman Dewangan .resources = rtc_resources, 106327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(rtc_resources), 107327156c5SLaxman Dewangan }, { 108327156c5SLaxman Dewangan .name = "max20024-power", 109327156c5SLaxman Dewangan .resources = power_resources, 110327156c5SLaxman Dewangan .num_resources = ARRAY_SIZE(power_resources), 111327156c5SLaxman Dewangan }, 112327156c5SLaxman Dewangan }; 113327156c5SLaxman Dewangan 114327156c5SLaxman Dewangan static const struct regmap_range max77620_readable_ranges[] = { 115327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 116327156c5SLaxman Dewangan }; 117327156c5SLaxman Dewangan 118327156c5SLaxman Dewangan static const struct regmap_access_table max77620_readable_table = { 119327156c5SLaxman Dewangan .yes_ranges = max77620_readable_ranges, 120327156c5SLaxman Dewangan .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges), 121327156c5SLaxman Dewangan }; 122327156c5SLaxman Dewangan 123327156c5SLaxman Dewangan static const struct regmap_range max20024_readable_ranges[] = { 124327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 125327156c5SLaxman Dewangan regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD), 126327156c5SLaxman Dewangan }; 127327156c5SLaxman Dewangan 128327156c5SLaxman Dewangan static const struct regmap_access_table max20024_readable_table = { 129327156c5SLaxman Dewangan .yes_ranges = max20024_readable_ranges, 130327156c5SLaxman Dewangan .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges), 131327156c5SLaxman Dewangan }; 132327156c5SLaxman Dewangan 133327156c5SLaxman Dewangan static const struct regmap_range max77620_writable_ranges[] = { 134327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), 135327156c5SLaxman Dewangan }; 136327156c5SLaxman Dewangan 137327156c5SLaxman Dewangan static const struct regmap_access_table max77620_writable_table = { 138327156c5SLaxman Dewangan .yes_ranges = max77620_writable_ranges, 139327156c5SLaxman Dewangan .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges), 140327156c5SLaxman Dewangan }; 141327156c5SLaxman Dewangan 142327156c5SLaxman Dewangan static const struct regmap_range max77620_cacheable_ranges[] = { 143327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3), 144327156c5SLaxman Dewangan regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3), 145327156c5SLaxman Dewangan }; 146327156c5SLaxman Dewangan 147327156c5SLaxman Dewangan static const struct regmap_access_table max77620_volatile_table = { 148327156c5SLaxman Dewangan .no_ranges = max77620_cacheable_ranges, 149327156c5SLaxman Dewangan .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges), 150327156c5SLaxman Dewangan }; 151327156c5SLaxman Dewangan 152327156c5SLaxman Dewangan static const struct regmap_config max77620_regmap_config = { 153327156c5SLaxman Dewangan .name = "power-slave", 154327156c5SLaxman Dewangan .reg_bits = 8, 155327156c5SLaxman Dewangan .val_bits = 8, 156327156c5SLaxman Dewangan .max_register = MAX77620_REG_DVSSD4 + 1, 157327156c5SLaxman Dewangan .cache_type = REGCACHE_RBTREE, 158327156c5SLaxman Dewangan .rd_table = &max77620_readable_table, 159327156c5SLaxman Dewangan .wr_table = &max77620_writable_table, 160327156c5SLaxman Dewangan .volatile_table = &max77620_volatile_table, 161327156c5SLaxman Dewangan }; 162327156c5SLaxman Dewangan 163327156c5SLaxman Dewangan static const struct regmap_config max20024_regmap_config = { 164327156c5SLaxman Dewangan .name = "power-slave", 165327156c5SLaxman Dewangan .reg_bits = 8, 166327156c5SLaxman Dewangan .val_bits = 8, 167327156c5SLaxman Dewangan .max_register = MAX20024_REG_MAX_ADD + 1, 168327156c5SLaxman Dewangan .cache_type = REGCACHE_RBTREE, 169327156c5SLaxman Dewangan .rd_table = &max20024_readable_table, 170327156c5SLaxman Dewangan .wr_table = &max77620_writable_table, 171327156c5SLaxman Dewangan .volatile_table = &max77620_volatile_table, 172327156c5SLaxman Dewangan }; 173327156c5SLaxman Dewangan 1743df140d1SLaxman Dewangan /* 1753df140d1SLaxman Dewangan * MAX77620 and MAX20024 has the following steps of the interrupt handling 1763df140d1SLaxman Dewangan * for TOP interrupts: 1773df140d1SLaxman Dewangan * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM. 1783df140d1SLaxman Dewangan * 2. Read IRQTOP and service the interrupt. 1793df140d1SLaxman Dewangan * 3. Once all interrupts has been checked and serviced, the interrupt service 1803df140d1SLaxman Dewangan * routine un-masks the hardware interrupt line by clearing GLBLM. 1813df140d1SLaxman Dewangan */ 1823df140d1SLaxman Dewangan static int max77620_irq_global_mask(void *irq_drv_data) 1833df140d1SLaxman Dewangan { 1843df140d1SLaxman Dewangan struct max77620_chip *chip = irq_drv_data; 1853df140d1SLaxman Dewangan int ret; 1863df140d1SLaxman Dewangan 1873df140d1SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 1883df140d1SLaxman Dewangan MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK); 1893df140d1SLaxman Dewangan if (ret < 0) 1903df140d1SLaxman Dewangan dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret); 1913df140d1SLaxman Dewangan 1923df140d1SLaxman Dewangan return ret; 1933df140d1SLaxman Dewangan } 1943df140d1SLaxman Dewangan 1953df140d1SLaxman Dewangan static int max77620_irq_global_unmask(void *irq_drv_data) 1963df140d1SLaxman Dewangan { 1973df140d1SLaxman Dewangan struct max77620_chip *chip = irq_drv_data; 1983df140d1SLaxman Dewangan int ret; 1993df140d1SLaxman Dewangan 2003df140d1SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT, 2013df140d1SLaxman Dewangan MAX77620_GLBLM_MASK, 0); 2023df140d1SLaxman Dewangan if (ret < 0) 2033df140d1SLaxman Dewangan dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret); 2043df140d1SLaxman Dewangan 2053df140d1SLaxman Dewangan return ret; 2063df140d1SLaxman Dewangan } 2073df140d1SLaxman Dewangan 2083df140d1SLaxman Dewangan static struct regmap_irq_chip max77620_top_irq_chip = { 2093df140d1SLaxman Dewangan .name = "max77620-top", 2103df140d1SLaxman Dewangan .irqs = max77620_top_irqs, 2113df140d1SLaxman Dewangan .num_irqs = ARRAY_SIZE(max77620_top_irqs), 2123df140d1SLaxman Dewangan .num_regs = 2, 2133df140d1SLaxman Dewangan .status_base = MAX77620_REG_IRQTOP, 2143df140d1SLaxman Dewangan .mask_base = MAX77620_REG_IRQTOPM, 2153df140d1SLaxman Dewangan .handle_pre_irq = max77620_irq_global_mask, 2163df140d1SLaxman Dewangan .handle_post_irq = max77620_irq_global_unmask, 2173df140d1SLaxman Dewangan }; 2183df140d1SLaxman Dewangan 219327156c5SLaxman Dewangan /* max77620_get_fps_period_reg_value: Get FPS bit field value from 220327156c5SLaxman Dewangan * requested periods. 221327156c5SLaxman Dewangan * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560 222327156c5SLaxman Dewangan * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80, 223327156c5SLaxman Dewangan * 160, 320, 540, 1280 and 2560 microseconds. 224327156c5SLaxman Dewangan * The FPS register has 3 bits field to set the FPS period as 225327156c5SLaxman Dewangan * bits max77620 max20024 226327156c5SLaxman Dewangan * 000 40 20 227327156c5SLaxman Dewangan * 001 80 40 228327156c5SLaxman Dewangan * ::: 229327156c5SLaxman Dewangan */ 230327156c5SLaxman Dewangan static int max77620_get_fps_period_reg_value(struct max77620_chip *chip, 231327156c5SLaxman Dewangan int tperiod) 232327156c5SLaxman Dewangan { 233327156c5SLaxman Dewangan int fps_min_period; 234327156c5SLaxman Dewangan int i; 235327156c5SLaxman Dewangan 236327156c5SLaxman Dewangan switch (chip->chip_id) { 237327156c5SLaxman Dewangan case MAX20024: 238327156c5SLaxman Dewangan fps_min_period = MAX20024_FPS_PERIOD_MIN_US; 239327156c5SLaxman Dewangan break; 240327156c5SLaxman Dewangan case MAX77620: 241327156c5SLaxman Dewangan fps_min_period = MAX77620_FPS_PERIOD_MIN_US; 24282d8eb40SRhyland Klein break; 243327156c5SLaxman Dewangan default: 244327156c5SLaxman Dewangan return -EINVAL; 245327156c5SLaxman Dewangan } 246327156c5SLaxman Dewangan 247327156c5SLaxman Dewangan for (i = 0; i < 7; i++) { 248327156c5SLaxman Dewangan if (fps_min_period >= tperiod) 249327156c5SLaxman Dewangan return i; 250327156c5SLaxman Dewangan fps_min_period *= 2; 251327156c5SLaxman Dewangan } 252327156c5SLaxman Dewangan 253327156c5SLaxman Dewangan return i; 254327156c5SLaxman Dewangan } 255327156c5SLaxman Dewangan 256327156c5SLaxman Dewangan /* max77620_config_fps: Configure FPS configuration registers 257327156c5SLaxman Dewangan * based on platform specific information. 258327156c5SLaxman Dewangan */ 259327156c5SLaxman Dewangan static int max77620_config_fps(struct max77620_chip *chip, 260327156c5SLaxman Dewangan struct device_node *fps_np) 261327156c5SLaxman Dewangan { 262327156c5SLaxman Dewangan struct device *dev = chip->dev; 263327156c5SLaxman Dewangan unsigned int mask = 0, config = 0; 264327156c5SLaxman Dewangan u32 fps_max_period; 265327156c5SLaxman Dewangan u32 param_val; 266327156c5SLaxman Dewangan int tperiod, fps_id; 267327156c5SLaxman Dewangan int ret; 268327156c5SLaxman Dewangan char fps_name[10]; 269327156c5SLaxman Dewangan 270327156c5SLaxman Dewangan switch (chip->chip_id) { 271327156c5SLaxman Dewangan case MAX20024: 272327156c5SLaxman Dewangan fps_max_period = MAX20024_FPS_PERIOD_MAX_US; 273327156c5SLaxman Dewangan break; 274327156c5SLaxman Dewangan case MAX77620: 275327156c5SLaxman Dewangan fps_max_period = MAX77620_FPS_PERIOD_MAX_US; 27682d8eb40SRhyland Klein break; 277327156c5SLaxman Dewangan default: 278327156c5SLaxman Dewangan return -EINVAL; 279327156c5SLaxman Dewangan } 280327156c5SLaxman Dewangan 281327156c5SLaxman Dewangan for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 282327156c5SLaxman Dewangan sprintf(fps_name, "fps%d", fps_id); 283327156c5SLaxman Dewangan if (!strcmp(fps_np->name, fps_name)) 284327156c5SLaxman Dewangan break; 285327156c5SLaxman Dewangan } 286327156c5SLaxman Dewangan 287327156c5SLaxman Dewangan if (fps_id == MAX77620_FPS_COUNT) { 28875a11072SRob Herring dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np); 289327156c5SLaxman Dewangan return -EINVAL; 290327156c5SLaxman Dewangan } 291327156c5SLaxman Dewangan 292327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us", 293327156c5SLaxman Dewangan ¶m_val); 294327156c5SLaxman Dewangan if (!ret) { 295327156c5SLaxman Dewangan mask |= MAX77620_FPS_TIME_PERIOD_MASK; 296327156c5SLaxman Dewangan chip->shutdown_fps_period[fps_id] = min(param_val, 297327156c5SLaxman Dewangan fps_max_period); 298327156c5SLaxman Dewangan tperiod = max77620_get_fps_period_reg_value(chip, 299327156c5SLaxman Dewangan chip->shutdown_fps_period[fps_id]); 300327156c5SLaxman Dewangan config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT; 301327156c5SLaxman Dewangan } 302327156c5SLaxman Dewangan 303327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us", 304327156c5SLaxman Dewangan ¶m_val); 305327156c5SLaxman Dewangan if (!ret) 306327156c5SLaxman Dewangan chip->suspend_fps_period[fps_id] = min(param_val, 307327156c5SLaxman Dewangan fps_max_period); 308327156c5SLaxman Dewangan 309327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, "maxim,fps-event-source", 310327156c5SLaxman Dewangan ¶m_val); 311327156c5SLaxman Dewangan if (!ret) { 312327156c5SLaxman Dewangan if (param_val > 2) { 313327156c5SLaxman Dewangan dev_err(dev, "FPS%d event-source invalid\n", fps_id); 314327156c5SLaxman Dewangan return -EINVAL; 315327156c5SLaxman Dewangan } 316327156c5SLaxman Dewangan mask |= MAX77620_FPS_EN_SRC_MASK; 317327156c5SLaxman Dewangan config |= param_val << MAX77620_FPS_EN_SRC_SHIFT; 318327156c5SLaxman Dewangan if (param_val == 2) { 319327156c5SLaxman Dewangan mask |= MAX77620_FPS_ENFPS_SW_MASK; 320327156c5SLaxman Dewangan config |= MAX77620_FPS_ENFPS_SW; 321327156c5SLaxman Dewangan } 322327156c5SLaxman Dewangan } 323327156c5SLaxman Dewangan 324327156c5SLaxman Dewangan if (!chip->sleep_enable && !chip->enable_global_lpm) { 325327156c5SLaxman Dewangan ret = of_property_read_u32(fps_np, 326327156c5SLaxman Dewangan "maxim,device-state-on-disabled-event", 327327156c5SLaxman Dewangan ¶m_val); 328327156c5SLaxman Dewangan if (!ret) { 329327156c5SLaxman Dewangan if (param_val == 0) 330327156c5SLaxman Dewangan chip->sleep_enable = true; 331327156c5SLaxman Dewangan else if (param_val == 1) 332327156c5SLaxman Dewangan chip->enable_global_lpm = true; 333327156c5SLaxman Dewangan } 334327156c5SLaxman Dewangan } 335327156c5SLaxman Dewangan 336327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 337327156c5SLaxman Dewangan mask, config); 338327156c5SLaxman Dewangan if (ret < 0) { 339327156c5SLaxman Dewangan dev_err(dev, "Failed to update FPS CFG: %d\n", ret); 340327156c5SLaxman Dewangan return ret; 341327156c5SLaxman Dewangan } 342327156c5SLaxman Dewangan 343327156c5SLaxman Dewangan return 0; 344327156c5SLaxman Dewangan } 345327156c5SLaxman Dewangan 346327156c5SLaxman Dewangan static int max77620_initialise_fps(struct max77620_chip *chip) 347327156c5SLaxman Dewangan { 348327156c5SLaxman Dewangan struct device *dev = chip->dev; 349327156c5SLaxman Dewangan struct device_node *fps_np, *fps_child; 350327156c5SLaxman Dewangan u8 config; 351327156c5SLaxman Dewangan int fps_id; 352327156c5SLaxman Dewangan int ret; 353327156c5SLaxman Dewangan 354327156c5SLaxman Dewangan for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { 355327156c5SLaxman Dewangan chip->shutdown_fps_period[fps_id] = -1; 356327156c5SLaxman Dewangan chip->suspend_fps_period[fps_id] = -1; 357327156c5SLaxman Dewangan } 358327156c5SLaxman Dewangan 359327156c5SLaxman Dewangan fps_np = of_get_child_by_name(dev->of_node, "fps"); 360327156c5SLaxman Dewangan if (!fps_np) 361327156c5SLaxman Dewangan goto skip_fps; 362327156c5SLaxman Dewangan 363327156c5SLaxman Dewangan for_each_child_of_node(fps_np, fps_child) { 364327156c5SLaxman Dewangan ret = max77620_config_fps(chip, fps_child); 365327156c5SLaxman Dewangan if (ret < 0) 366327156c5SLaxman Dewangan return ret; 367327156c5SLaxman Dewangan } 368327156c5SLaxman Dewangan 369327156c5SLaxman Dewangan config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0; 370327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 371327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config); 372327156c5SLaxman Dewangan if (ret < 0) { 373327156c5SLaxman Dewangan dev_err(dev, "Failed to update SLP_LPM: %d\n", ret); 374327156c5SLaxman Dewangan return ret; 375327156c5SLaxman Dewangan } 376327156c5SLaxman Dewangan 377327156c5SLaxman Dewangan skip_fps: 378327156c5SLaxman Dewangan /* Enable wake on EN0 pin */ 379327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 380327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0, 381327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0); 382327156c5SLaxman Dewangan if (ret < 0) { 383327156c5SLaxman Dewangan dev_err(dev, "Failed to update WK_EN0: %d\n", ret); 384327156c5SLaxman Dewangan return ret; 385327156c5SLaxman Dewangan } 386327156c5SLaxman Dewangan 387327156c5SLaxman Dewangan /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */ 388327156c5SLaxman Dewangan if ((chip->chip_id == MAX20024) && chip->sleep_enable) { 389327156c5SLaxman Dewangan config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE; 390327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 391327156c5SLaxman Dewangan config, config); 392327156c5SLaxman Dewangan if (ret < 0) { 393327156c5SLaxman Dewangan dev_err(dev, "Failed to update SLPEN: %d\n", ret); 394327156c5SLaxman Dewangan return ret; 395327156c5SLaxman Dewangan } 396327156c5SLaxman Dewangan } 397327156c5SLaxman Dewangan 398327156c5SLaxman Dewangan return 0; 399327156c5SLaxman Dewangan } 400327156c5SLaxman Dewangan 401327156c5SLaxman Dewangan static int max77620_read_es_version(struct max77620_chip *chip) 402327156c5SLaxman Dewangan { 403327156c5SLaxman Dewangan unsigned int val; 404327156c5SLaxman Dewangan u8 cid_val[6]; 405327156c5SLaxman Dewangan int i; 406327156c5SLaxman Dewangan int ret; 407327156c5SLaxman Dewangan 408327156c5SLaxman Dewangan for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) { 409327156c5SLaxman Dewangan ret = regmap_read(chip->rmap, i, &val); 410327156c5SLaxman Dewangan if (ret < 0) { 411327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to read CID: %d\n", ret); 412327156c5SLaxman Dewangan return ret; 413327156c5SLaxman Dewangan } 414327156c5SLaxman Dewangan dev_dbg(chip->dev, "CID%d: 0x%02x\n", 415327156c5SLaxman Dewangan i - MAX77620_REG_CID0, val); 416327156c5SLaxman Dewangan cid_val[i - MAX77620_REG_CID0] = val; 417327156c5SLaxman Dewangan } 418327156c5SLaxman Dewangan 419327156c5SLaxman Dewangan /* CID4 is OTP Version and CID5 is ES version */ 420327156c5SLaxman Dewangan dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n", 421327156c5SLaxman Dewangan cid_val[4], MAX77620_CID5_DIDM(cid_val[5])); 422327156c5SLaxman Dewangan 423327156c5SLaxman Dewangan return ret; 424327156c5SLaxman Dewangan } 425327156c5SLaxman Dewangan 426327156c5SLaxman Dewangan static int max77620_probe(struct i2c_client *client, 427327156c5SLaxman Dewangan const struct i2c_device_id *id) 428327156c5SLaxman Dewangan { 429327156c5SLaxman Dewangan const struct regmap_config *rmap_config; 430327156c5SLaxman Dewangan struct max77620_chip *chip; 431327156c5SLaxman Dewangan const struct mfd_cell *mfd_cells; 432327156c5SLaxman Dewangan int n_mfd_cells; 433327156c5SLaxman Dewangan int ret; 434327156c5SLaxman Dewangan 435327156c5SLaxman Dewangan chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 436327156c5SLaxman Dewangan if (!chip) 437327156c5SLaxman Dewangan return -ENOMEM; 438327156c5SLaxman Dewangan 439327156c5SLaxman Dewangan i2c_set_clientdata(client, chip); 440327156c5SLaxman Dewangan chip->dev = &client->dev; 441327156c5SLaxman Dewangan chip->irq_base = -1; 442327156c5SLaxman Dewangan chip->chip_irq = client->irq; 443327156c5SLaxman Dewangan chip->chip_id = (enum max77620_chip_id)id->driver_data; 444327156c5SLaxman Dewangan 445327156c5SLaxman Dewangan switch (chip->chip_id) { 446327156c5SLaxman Dewangan case MAX77620: 447327156c5SLaxman Dewangan mfd_cells = max77620_children; 448327156c5SLaxman Dewangan n_mfd_cells = ARRAY_SIZE(max77620_children); 449327156c5SLaxman Dewangan rmap_config = &max77620_regmap_config; 450327156c5SLaxman Dewangan break; 451327156c5SLaxman Dewangan case MAX20024: 452327156c5SLaxman Dewangan mfd_cells = max20024_children; 453327156c5SLaxman Dewangan n_mfd_cells = ARRAY_SIZE(max20024_children); 454327156c5SLaxman Dewangan rmap_config = &max20024_regmap_config; 455327156c5SLaxman Dewangan break; 456327156c5SLaxman Dewangan default: 457327156c5SLaxman Dewangan dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id); 458327156c5SLaxman Dewangan return -EINVAL; 459327156c5SLaxman Dewangan } 460327156c5SLaxman Dewangan 461327156c5SLaxman Dewangan chip->rmap = devm_regmap_init_i2c(client, rmap_config); 462327156c5SLaxman Dewangan if (IS_ERR(chip->rmap)) { 463327156c5SLaxman Dewangan ret = PTR_ERR(chip->rmap); 4649165dabbSMasanari Iida dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret); 465327156c5SLaxman Dewangan return ret; 466327156c5SLaxman Dewangan } 467327156c5SLaxman Dewangan 468327156c5SLaxman Dewangan ret = max77620_read_es_version(chip); 469327156c5SLaxman Dewangan if (ret < 0) 470327156c5SLaxman Dewangan return ret; 471327156c5SLaxman Dewangan 4723df140d1SLaxman Dewangan max77620_top_irq_chip.irq_drv_data = chip; 473327156c5SLaxman Dewangan ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq, 474327156c5SLaxman Dewangan IRQF_ONESHOT | IRQF_SHARED, 475327156c5SLaxman Dewangan chip->irq_base, &max77620_top_irq_chip, 476327156c5SLaxman Dewangan &chip->top_irq_data); 477327156c5SLaxman Dewangan if (ret < 0) { 478327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret); 479327156c5SLaxman Dewangan return ret; 480327156c5SLaxman Dewangan } 481327156c5SLaxman Dewangan 482327156c5SLaxman Dewangan ret = max77620_initialise_fps(chip); 483327156c5SLaxman Dewangan if (ret < 0) 484327156c5SLaxman Dewangan return ret; 485327156c5SLaxman Dewangan 486327156c5SLaxman Dewangan ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, 487327156c5SLaxman Dewangan mfd_cells, n_mfd_cells, NULL, 0, 488327156c5SLaxman Dewangan regmap_irq_get_domain(chip->top_irq_data)); 489327156c5SLaxman Dewangan if (ret < 0) { 490327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to add MFD children: %d\n", ret); 491327156c5SLaxman Dewangan return ret; 492327156c5SLaxman Dewangan } 493327156c5SLaxman Dewangan 494327156c5SLaxman Dewangan return 0; 495327156c5SLaxman Dewangan } 496327156c5SLaxman Dewangan 497327156c5SLaxman Dewangan #ifdef CONFIG_PM_SLEEP 498327156c5SLaxman Dewangan static int max77620_set_fps_period(struct max77620_chip *chip, 499327156c5SLaxman Dewangan int fps_id, int time_period) 500327156c5SLaxman Dewangan { 501327156c5SLaxman Dewangan int period = max77620_get_fps_period_reg_value(chip, time_period); 502327156c5SLaxman Dewangan int ret; 503327156c5SLaxman Dewangan 504327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, 505327156c5SLaxman Dewangan MAX77620_FPS_TIME_PERIOD_MASK, 506327156c5SLaxman Dewangan period << MAX77620_FPS_TIME_PERIOD_SHIFT); 507327156c5SLaxman Dewangan if (ret < 0) { 508327156c5SLaxman Dewangan dev_err(chip->dev, "Failed to update FPS period: %d\n", ret); 509327156c5SLaxman Dewangan return ret; 510327156c5SLaxman Dewangan } 511327156c5SLaxman Dewangan 512327156c5SLaxman Dewangan return 0; 513327156c5SLaxman Dewangan } 514327156c5SLaxman Dewangan 515327156c5SLaxman Dewangan static int max77620_i2c_suspend(struct device *dev) 516327156c5SLaxman Dewangan { 517327156c5SLaxman Dewangan struct max77620_chip *chip = dev_get_drvdata(dev); 518327156c5SLaxman Dewangan struct i2c_client *client = to_i2c_client(dev); 519327156c5SLaxman Dewangan unsigned int config; 520327156c5SLaxman Dewangan int fps; 521327156c5SLaxman Dewangan int ret; 522327156c5SLaxman Dewangan 523327156c5SLaxman Dewangan for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 524327156c5SLaxman Dewangan if (chip->suspend_fps_period[fps] < 0) 525327156c5SLaxman Dewangan continue; 526327156c5SLaxman Dewangan 527327156c5SLaxman Dewangan ret = max77620_set_fps_period(chip, fps, 528327156c5SLaxman Dewangan chip->suspend_fps_period[fps]); 529327156c5SLaxman Dewangan if (ret < 0) 530327156c5SLaxman Dewangan return ret; 531327156c5SLaxman Dewangan } 532327156c5SLaxman Dewangan 533327156c5SLaxman Dewangan /* 534327156c5SLaxman Dewangan * For MAX20024: No need to configure SLPEN on suspend as 535327156c5SLaxman Dewangan * it will be configured on Init. 536327156c5SLaxman Dewangan */ 537327156c5SLaxman Dewangan if (chip->chip_id == MAX20024) 538327156c5SLaxman Dewangan goto out; 539327156c5SLaxman Dewangan 540327156c5SLaxman Dewangan config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0; 541327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, 542327156c5SLaxman Dewangan MAX77620_ONOFFCNFG1_SLPEN, 543327156c5SLaxman Dewangan config); 544327156c5SLaxman Dewangan if (ret < 0) { 545327156c5SLaxman Dewangan dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret); 546327156c5SLaxman Dewangan return ret; 547327156c5SLaxman Dewangan } 548327156c5SLaxman Dewangan 549327156c5SLaxman Dewangan /* Disable WK_EN0 */ 550327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 551327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0, 0); 552327156c5SLaxman Dewangan if (ret < 0) { 553327156c5SLaxman Dewangan dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret); 554327156c5SLaxman Dewangan return ret; 555327156c5SLaxman Dewangan } 556327156c5SLaxman Dewangan 557327156c5SLaxman Dewangan out: 558327156c5SLaxman Dewangan disable_irq(client->irq); 559327156c5SLaxman Dewangan 560327156c5SLaxman Dewangan return 0; 561327156c5SLaxman Dewangan } 562327156c5SLaxman Dewangan 563327156c5SLaxman Dewangan static int max77620_i2c_resume(struct device *dev) 564327156c5SLaxman Dewangan { 565327156c5SLaxman Dewangan struct max77620_chip *chip = dev_get_drvdata(dev); 566327156c5SLaxman Dewangan struct i2c_client *client = to_i2c_client(dev); 567327156c5SLaxman Dewangan int ret; 568327156c5SLaxman Dewangan int fps; 569327156c5SLaxman Dewangan 570327156c5SLaxman Dewangan for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { 571327156c5SLaxman Dewangan if (chip->shutdown_fps_period[fps] < 0) 572327156c5SLaxman Dewangan continue; 573327156c5SLaxman Dewangan 574327156c5SLaxman Dewangan ret = max77620_set_fps_period(chip, fps, 575327156c5SLaxman Dewangan chip->shutdown_fps_period[fps]); 576327156c5SLaxman Dewangan if (ret < 0) 577327156c5SLaxman Dewangan return ret; 578327156c5SLaxman Dewangan } 579327156c5SLaxman Dewangan 580327156c5SLaxman Dewangan /* 581327156c5SLaxman Dewangan * For MAX20024: No need to configure WKEN0 on resume as 582327156c5SLaxman Dewangan * it is configured on Init. 583327156c5SLaxman Dewangan */ 584327156c5SLaxman Dewangan if (chip->chip_id == MAX20024) 585327156c5SLaxman Dewangan goto out; 586327156c5SLaxman Dewangan 587327156c5SLaxman Dewangan /* Enable WK_EN0 */ 588327156c5SLaxman Dewangan ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, 589327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0, 590327156c5SLaxman Dewangan MAX77620_ONOFFCNFG2_WK_EN0); 591327156c5SLaxman Dewangan if (ret < 0) { 592327156c5SLaxman Dewangan dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret); 593327156c5SLaxman Dewangan return ret; 594327156c5SLaxman Dewangan } 595327156c5SLaxman Dewangan 596327156c5SLaxman Dewangan out: 597327156c5SLaxman Dewangan enable_irq(client->irq); 598327156c5SLaxman Dewangan 599327156c5SLaxman Dewangan return 0; 600327156c5SLaxman Dewangan } 601327156c5SLaxman Dewangan #endif 602327156c5SLaxman Dewangan 603327156c5SLaxman Dewangan static const struct i2c_device_id max77620_id[] = { 604327156c5SLaxman Dewangan {"max77620", MAX77620}, 605327156c5SLaxman Dewangan {"max20024", MAX20024}, 606327156c5SLaxman Dewangan {}, 607327156c5SLaxman Dewangan }; 608327156c5SLaxman Dewangan 609327156c5SLaxman Dewangan static const struct dev_pm_ops max77620_pm_ops = { 610327156c5SLaxman Dewangan SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume) 611327156c5SLaxman Dewangan }; 612327156c5SLaxman Dewangan 613327156c5SLaxman Dewangan static struct i2c_driver max77620_driver = { 614327156c5SLaxman Dewangan .driver = { 615327156c5SLaxman Dewangan .name = "max77620", 616327156c5SLaxman Dewangan .pm = &max77620_pm_ops, 617327156c5SLaxman Dewangan }, 618327156c5SLaxman Dewangan .probe = max77620_probe, 619327156c5SLaxman Dewangan .id_table = max77620_id, 620327156c5SLaxman Dewangan }; 621c1fe7c45SPaul Gortmaker builtin_i2c_driver(max77620_driver); 622