1 /* 2 * lpc_ich.c - LPC interface for Intel ICH 3 * 4 * LPC bridge function of the Intel ICH contains many other 5 * functional units, such as Interrupt controllers, Timers, 6 * Power Management, System Management, GPIO, RTC, and LPC 7 * Configuration Registers. 8 * 9 * This driver is derived from lpc_sch. 10 11 * Copyright (c) 2011 Extreme Engineering Solution, Inc. 12 * Author: Aaron Sierra <asierra@xes-inc.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License 2 as published 16 * by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; see the file COPYING. If not, write to 25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * This driver supports the following I/O Controller hubs: 28 * (See the intel documentation on http://developer.intel.com.) 29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) 30 * document number 290687-002, 298242-027: 82801BA (ICH2) 31 * document number 290733-003, 290739-013: 82801CA (ICH3-S) 32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M) 33 * document number 290744-001, 290745-025: 82801DB (ICH4) 34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M) 35 * document number 273599-001, 273645-002: 82801E (C-ICH) 36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) 37 * document number 300641-004, 300884-013: 6300ESB 38 * document number 301473-002, 301474-026: 82801F (ICH6) 39 * document number 313082-001, 313075-006: 631xESB, 632xESB 40 * document number 307013-003, 307014-024: 82801G (ICH7) 41 * document number 322896-001, 322897-001: NM10 42 * document number 313056-003, 313057-017: 82801H (ICH8) 43 * document number 316972-004, 316973-012: 82801I (ICH9) 44 * document number 319973-002, 319974-002: 82801J (ICH10) 45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) 46 * document number 320066-003, 320257-008: EP80597 (IICH) 47 * document number 324645-001, 324646-001: Cougar Point (CPT) 48 * document number TBD : Patsburg (PBG) 49 * document number TBD : DH89xxCC 50 * document number TBD : Panther Point 51 * document number TBD : Lynx Point 52 * document number TBD : Lynx Point-LP 53 * document number TBD : Wellsburg 54 */ 55 56 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 57 58 #include <linux/init.h> 59 #include <linux/kernel.h> 60 #include <linux/module.h> 61 #include <linux/errno.h> 62 #include <linux/acpi.h> 63 #include <linux/pci.h> 64 #include <linux/mfd/core.h> 65 #include <linux/mfd/lpc_ich.h> 66 67 #define ACPIBASE 0x40 68 #define ACPIBASE_GPE_OFF 0x28 69 #define ACPIBASE_GPE_END 0x2f 70 #define ACPIBASE_SMI_OFF 0x30 71 #define ACPIBASE_SMI_END 0x33 72 #define ACPIBASE_TCO_OFF 0x60 73 #define ACPIBASE_TCO_END 0x7f 74 #define ACPICTRL 0x44 75 76 #define ACPIBASE_GCS_OFF 0x3410 77 #define ACPIBASE_GCS_END 0x3414 78 79 #define GPIOBASE_ICH0 0x58 80 #define GPIOCTRL_ICH0 0x5C 81 #define GPIOBASE_ICH6 0x48 82 #define GPIOCTRL_ICH6 0x4C 83 84 #define RCBABASE 0xf0 85 86 #define wdt_io_res(i) wdt_res(0, i) 87 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) 88 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) 89 90 struct lpc_ich_cfg { 91 int base; 92 int ctrl; 93 int save; 94 }; 95 96 struct lpc_ich_priv { 97 int chipset; 98 struct lpc_ich_cfg acpi; 99 struct lpc_ich_cfg gpio; 100 }; 101 102 static struct resource wdt_ich_res[] = { 103 /* ACPI - TCO */ 104 { 105 .flags = IORESOURCE_IO, 106 }, 107 /* ACPI - SMI */ 108 { 109 .flags = IORESOURCE_IO, 110 }, 111 /* GCS */ 112 { 113 .flags = IORESOURCE_MEM, 114 }, 115 }; 116 117 static struct resource gpio_ich_res[] = { 118 /* GPIO */ 119 { 120 .flags = IORESOURCE_IO, 121 }, 122 /* ACPI - GPE0 */ 123 { 124 .flags = IORESOURCE_IO, 125 }, 126 }; 127 128 enum lpc_cells { 129 LPC_WDT = 0, 130 LPC_GPIO, 131 }; 132 133 static struct mfd_cell lpc_ich_cells[] = { 134 [LPC_WDT] = { 135 .name = "iTCO_wdt", 136 .num_resources = ARRAY_SIZE(wdt_ich_res), 137 .resources = wdt_ich_res, 138 .ignore_resource_conflicts = true, 139 }, 140 [LPC_GPIO] = { 141 .name = "gpio_ich", 142 .num_resources = ARRAY_SIZE(gpio_ich_res), 143 .resources = gpio_ich_res, 144 .ignore_resource_conflicts = true, 145 }, 146 }; 147 148 /* chipset related info */ 149 enum lpc_chipsets { 150 LPC_ICH = 0, /* ICH */ 151 LPC_ICH0, /* ICH0 */ 152 LPC_ICH2, /* ICH2 */ 153 LPC_ICH2M, /* ICH2-M */ 154 LPC_ICH3, /* ICH3-S */ 155 LPC_ICH3M, /* ICH3-M */ 156 LPC_ICH4, /* ICH4 */ 157 LPC_ICH4M, /* ICH4-M */ 158 LPC_CICH, /* C-ICH */ 159 LPC_ICH5, /* ICH5 & ICH5R */ 160 LPC_6300ESB, /* 6300ESB */ 161 LPC_ICH6, /* ICH6 & ICH6R */ 162 LPC_ICH6M, /* ICH6-M */ 163 LPC_ICH6W, /* ICH6W & ICH6RW */ 164 LPC_631XESB, /* 631xESB/632xESB */ 165 LPC_ICH7, /* ICH7 & ICH7R */ 166 LPC_ICH7DH, /* ICH7DH */ 167 LPC_ICH7M, /* ICH7-M & ICH7-U */ 168 LPC_ICH7MDH, /* ICH7-M DH */ 169 LPC_NM10, /* NM10 */ 170 LPC_ICH8, /* ICH8 & ICH8R */ 171 LPC_ICH8DH, /* ICH8DH */ 172 LPC_ICH8DO, /* ICH8DO */ 173 LPC_ICH8M, /* ICH8M */ 174 LPC_ICH8ME, /* ICH8M-E */ 175 LPC_ICH9, /* ICH9 */ 176 LPC_ICH9R, /* ICH9R */ 177 LPC_ICH9DH, /* ICH9DH */ 178 LPC_ICH9DO, /* ICH9DO */ 179 LPC_ICH9M, /* ICH9M */ 180 LPC_ICH9ME, /* ICH9M-E */ 181 LPC_ICH10, /* ICH10 */ 182 LPC_ICH10R, /* ICH10R */ 183 LPC_ICH10D, /* ICH10D */ 184 LPC_ICH10DO, /* ICH10DO */ 185 LPC_PCH, /* PCH Desktop Full Featured */ 186 LPC_PCHM, /* PCH Mobile Full Featured */ 187 LPC_P55, /* P55 */ 188 LPC_PM55, /* PM55 */ 189 LPC_H55, /* H55 */ 190 LPC_QM57, /* QM57 */ 191 LPC_H57, /* H57 */ 192 LPC_HM55, /* HM55 */ 193 LPC_Q57, /* Q57 */ 194 LPC_HM57, /* HM57 */ 195 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ 196 LPC_QS57, /* QS57 */ 197 LPC_3400, /* 3400 */ 198 LPC_3420, /* 3420 */ 199 LPC_3450, /* 3450 */ 200 LPC_EP80579, /* EP80579 */ 201 LPC_CPT, /* Cougar Point */ 202 LPC_CPTD, /* Cougar Point Desktop */ 203 LPC_CPTM, /* Cougar Point Mobile */ 204 LPC_PBG, /* Patsburg */ 205 LPC_DH89XXCC, /* DH89xxCC */ 206 LPC_PPT, /* Panther Point */ 207 LPC_LPT, /* Lynx Point */ 208 LPC_LPT_LP, /* Lynx Point-LP */ 209 LPC_WBG, /* Wellsburg */ 210 }; 211 212 struct lpc_ich_info lpc_chipset_info[] = { 213 [LPC_ICH] = { 214 .name = "ICH", 215 .iTCO_version = 1, 216 }, 217 [LPC_ICH0] = { 218 .name = "ICH0", 219 .iTCO_version = 1, 220 }, 221 [LPC_ICH2] = { 222 .name = "ICH2", 223 .iTCO_version = 1, 224 }, 225 [LPC_ICH2M] = { 226 .name = "ICH2-M", 227 .iTCO_version = 1, 228 }, 229 [LPC_ICH3] = { 230 .name = "ICH3-S", 231 .iTCO_version = 1, 232 }, 233 [LPC_ICH3M] = { 234 .name = "ICH3-M", 235 .iTCO_version = 1, 236 }, 237 [LPC_ICH4] = { 238 .name = "ICH4", 239 .iTCO_version = 1, 240 }, 241 [LPC_ICH4M] = { 242 .name = "ICH4-M", 243 .iTCO_version = 1, 244 }, 245 [LPC_CICH] = { 246 .name = "C-ICH", 247 .iTCO_version = 1, 248 }, 249 [LPC_ICH5] = { 250 .name = "ICH5 or ICH5R", 251 .iTCO_version = 1, 252 }, 253 [LPC_6300ESB] = { 254 .name = "6300ESB", 255 .iTCO_version = 1, 256 }, 257 [LPC_ICH6] = { 258 .name = "ICH6 or ICH6R", 259 .iTCO_version = 2, 260 .gpio_version = ICH_V6_GPIO, 261 }, 262 [LPC_ICH6M] = { 263 .name = "ICH6-M", 264 .iTCO_version = 2, 265 .gpio_version = ICH_V6_GPIO, 266 }, 267 [LPC_ICH6W] = { 268 .name = "ICH6W or ICH6RW", 269 .iTCO_version = 2, 270 .gpio_version = ICH_V6_GPIO, 271 }, 272 [LPC_631XESB] = { 273 .name = "631xESB/632xESB", 274 .iTCO_version = 2, 275 .gpio_version = ICH_V6_GPIO, 276 }, 277 [LPC_ICH7] = { 278 .name = "ICH7 or ICH7R", 279 .iTCO_version = 2, 280 .gpio_version = ICH_V7_GPIO, 281 }, 282 [LPC_ICH7DH] = { 283 .name = "ICH7DH", 284 .iTCO_version = 2, 285 .gpio_version = ICH_V7_GPIO, 286 }, 287 [LPC_ICH7M] = { 288 .name = "ICH7-M or ICH7-U", 289 .iTCO_version = 2, 290 .gpio_version = ICH_V7_GPIO, 291 }, 292 [LPC_ICH7MDH] = { 293 .name = "ICH7-M DH", 294 .iTCO_version = 2, 295 .gpio_version = ICH_V7_GPIO, 296 }, 297 [LPC_NM10] = { 298 .name = "NM10", 299 .iTCO_version = 2, 300 }, 301 [LPC_ICH8] = { 302 .name = "ICH8 or ICH8R", 303 .iTCO_version = 2, 304 .gpio_version = ICH_V7_GPIO, 305 }, 306 [LPC_ICH8DH] = { 307 .name = "ICH8DH", 308 .iTCO_version = 2, 309 .gpio_version = ICH_V7_GPIO, 310 }, 311 [LPC_ICH8DO] = { 312 .name = "ICH8DO", 313 .iTCO_version = 2, 314 .gpio_version = ICH_V7_GPIO, 315 }, 316 [LPC_ICH8M] = { 317 .name = "ICH8M", 318 .iTCO_version = 2, 319 .gpio_version = ICH_V7_GPIO, 320 }, 321 [LPC_ICH8ME] = { 322 .name = "ICH8M-E", 323 .iTCO_version = 2, 324 .gpio_version = ICH_V7_GPIO, 325 }, 326 [LPC_ICH9] = { 327 .name = "ICH9", 328 .iTCO_version = 2, 329 .gpio_version = ICH_V9_GPIO, 330 }, 331 [LPC_ICH9R] = { 332 .name = "ICH9R", 333 .iTCO_version = 2, 334 .gpio_version = ICH_V9_GPIO, 335 }, 336 [LPC_ICH9DH] = { 337 .name = "ICH9DH", 338 .iTCO_version = 2, 339 .gpio_version = ICH_V9_GPIO, 340 }, 341 [LPC_ICH9DO] = { 342 .name = "ICH9DO", 343 .iTCO_version = 2, 344 .gpio_version = ICH_V9_GPIO, 345 }, 346 [LPC_ICH9M] = { 347 .name = "ICH9M", 348 .iTCO_version = 2, 349 .gpio_version = ICH_V9_GPIO, 350 }, 351 [LPC_ICH9ME] = { 352 .name = "ICH9M-E", 353 .iTCO_version = 2, 354 .gpio_version = ICH_V9_GPIO, 355 }, 356 [LPC_ICH10] = { 357 .name = "ICH10", 358 .iTCO_version = 2, 359 .gpio_version = ICH_V10CONS_GPIO, 360 }, 361 [LPC_ICH10R] = { 362 .name = "ICH10R", 363 .iTCO_version = 2, 364 .gpio_version = ICH_V10CONS_GPIO, 365 }, 366 [LPC_ICH10D] = { 367 .name = "ICH10D", 368 .iTCO_version = 2, 369 .gpio_version = ICH_V10CORP_GPIO, 370 }, 371 [LPC_ICH10DO] = { 372 .name = "ICH10DO", 373 .iTCO_version = 2, 374 .gpio_version = ICH_V10CORP_GPIO, 375 }, 376 [LPC_PCH] = { 377 .name = "PCH Desktop Full Featured", 378 .iTCO_version = 2, 379 .gpio_version = ICH_V5_GPIO, 380 }, 381 [LPC_PCHM] = { 382 .name = "PCH Mobile Full Featured", 383 .iTCO_version = 2, 384 .gpio_version = ICH_V5_GPIO, 385 }, 386 [LPC_P55] = { 387 .name = "P55", 388 .iTCO_version = 2, 389 .gpio_version = ICH_V5_GPIO, 390 }, 391 [LPC_PM55] = { 392 .name = "PM55", 393 .iTCO_version = 2, 394 .gpio_version = ICH_V5_GPIO, 395 }, 396 [LPC_H55] = { 397 .name = "H55", 398 .iTCO_version = 2, 399 .gpio_version = ICH_V5_GPIO, 400 }, 401 [LPC_QM57] = { 402 .name = "QM57", 403 .iTCO_version = 2, 404 .gpio_version = ICH_V5_GPIO, 405 }, 406 [LPC_H57] = { 407 .name = "H57", 408 .iTCO_version = 2, 409 .gpio_version = ICH_V5_GPIO, 410 }, 411 [LPC_HM55] = { 412 .name = "HM55", 413 .iTCO_version = 2, 414 .gpio_version = ICH_V5_GPIO, 415 }, 416 [LPC_Q57] = { 417 .name = "Q57", 418 .iTCO_version = 2, 419 .gpio_version = ICH_V5_GPIO, 420 }, 421 [LPC_HM57] = { 422 .name = "HM57", 423 .iTCO_version = 2, 424 .gpio_version = ICH_V5_GPIO, 425 }, 426 [LPC_PCHMSFF] = { 427 .name = "PCH Mobile SFF Full Featured", 428 .iTCO_version = 2, 429 .gpio_version = ICH_V5_GPIO, 430 }, 431 [LPC_QS57] = { 432 .name = "QS57", 433 .iTCO_version = 2, 434 .gpio_version = ICH_V5_GPIO, 435 }, 436 [LPC_3400] = { 437 .name = "3400", 438 .iTCO_version = 2, 439 .gpio_version = ICH_V5_GPIO, 440 }, 441 [LPC_3420] = { 442 .name = "3420", 443 .iTCO_version = 2, 444 .gpio_version = ICH_V5_GPIO, 445 }, 446 [LPC_3450] = { 447 .name = "3450", 448 .iTCO_version = 2, 449 .gpio_version = ICH_V5_GPIO, 450 }, 451 [LPC_EP80579] = { 452 .name = "EP80579", 453 .iTCO_version = 2, 454 }, 455 [LPC_CPT] = { 456 .name = "Cougar Point", 457 .iTCO_version = 2, 458 .gpio_version = ICH_V5_GPIO, 459 }, 460 [LPC_CPTD] = { 461 .name = "Cougar Point Desktop", 462 .iTCO_version = 2, 463 .gpio_version = ICH_V5_GPIO, 464 }, 465 [LPC_CPTM] = { 466 .name = "Cougar Point Mobile", 467 .iTCO_version = 2, 468 .gpio_version = ICH_V5_GPIO, 469 }, 470 [LPC_PBG] = { 471 .name = "Patsburg", 472 .iTCO_version = 2, 473 }, 474 [LPC_DH89XXCC] = { 475 .name = "DH89xxCC", 476 .iTCO_version = 2, 477 }, 478 [LPC_PPT] = { 479 .name = "Panther Point", 480 .iTCO_version = 2, 481 }, 482 [LPC_LPT] = { 483 .name = "Lynx Point", 484 .iTCO_version = 2, 485 }, 486 [LPC_LPT_LP] = { 487 .name = "Lynx Point_LP", 488 .iTCO_version = 2, 489 }, 490 [LPC_WBG] = { 491 .name = "Wellsburg", 492 .iTCO_version = 2, 493 }, 494 }; 495 496 /* 497 * This data only exists for exporting the supported PCI ids 498 * via MODULE_DEVICE_TABLE. We do not actually register a 499 * pci_driver, because the I/O Controller Hub has also other 500 * functions that probably will be registered by other drivers. 501 */ 502 static DEFINE_PCI_DEVICE_TABLE(lpc_ich_ids) = { 503 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, 504 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, 505 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, 506 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, 507 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, 508 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, 509 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, 510 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, 511 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, 512 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, 513 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, 514 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, 515 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, 516 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, 517 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, 518 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, 519 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, 520 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, 521 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, 522 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, 523 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, 524 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, 525 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, 526 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, 527 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, 528 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, 529 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, 530 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, 531 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, 532 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, 533 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, 534 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, 535 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, 536 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, 537 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, 538 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, 539 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, 540 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, 541 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, 542 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, 543 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, 544 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, 545 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, 546 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, 547 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, 548 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, 549 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, 550 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, 551 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, 552 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, 553 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, 554 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, 555 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, 556 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, 557 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, 558 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, 559 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, 560 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, 561 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, 562 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, 563 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, 564 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, 565 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, 566 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, 567 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, 568 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, 569 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, 570 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, 571 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, 572 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, 573 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, 574 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, 575 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, 576 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, 577 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, 578 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, 579 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, 580 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, 581 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, 582 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, 583 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, 584 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, 585 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, 586 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, 587 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, 588 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, 589 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, 590 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, 591 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, 592 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, 593 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, 594 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, 595 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, 596 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, 597 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, 598 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, 599 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, 600 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, 601 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, 602 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, 603 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, 604 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, 605 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, 606 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, 607 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, 608 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, 609 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, 610 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, 611 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, 612 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, 613 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, 614 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, 615 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, 616 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, 617 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, 618 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, 619 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, 620 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, 621 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, 622 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, 623 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, 624 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, 625 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, 626 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, 627 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, 628 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, 629 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, 630 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, 631 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, 632 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, 633 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, 634 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, 635 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, 636 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, 637 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, 638 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, 639 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, 640 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, 641 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, 642 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, 643 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, 644 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, 645 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, 646 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, 647 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, 648 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, 649 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, 650 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, 651 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, 652 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, 653 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, 654 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, 655 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, 656 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, 657 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, 658 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, 659 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, 660 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, 661 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, 662 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, 663 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, 664 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, 665 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, 666 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, 667 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, 668 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, 669 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, 670 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, 671 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, 672 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, 673 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, 674 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, 675 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, 676 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, 677 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, 678 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, 679 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, 680 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, 681 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, 682 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, 683 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, 684 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, 685 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, 686 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, 687 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, 688 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, 689 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, 690 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, 691 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, 692 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, 693 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, 694 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, 695 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, 696 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, 697 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, 698 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, 699 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, 700 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, 701 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, 702 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, 703 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, 704 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, 705 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, 706 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, 707 { 0, }, /* End of list */ 708 }; 709 MODULE_DEVICE_TABLE(pci, lpc_ich_ids); 710 711 static void lpc_ich_restore_config_space(struct pci_dev *dev) 712 { 713 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 714 715 if (priv->acpi.save >= 0) { 716 pci_write_config_byte(dev, priv->acpi.ctrl, priv->acpi.save); 717 priv->acpi.save = -1; 718 } 719 720 if (priv->gpio.save >= 0) { 721 pci_write_config_byte(dev, priv->gpio.ctrl, priv->gpio.save); 722 priv->gpio.save = -1; 723 } 724 } 725 726 static void lpc_ich_enable_acpi_space(struct pci_dev *dev) 727 { 728 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 729 u8 reg_save; 730 731 pci_read_config_byte(dev, priv->acpi.ctrl, ®_save); 732 pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x10); 733 priv->acpi.save = reg_save; 734 } 735 736 static void lpc_ich_enable_gpio_space(struct pci_dev *dev) 737 { 738 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 739 u8 reg_save; 740 741 pci_read_config_byte(dev, priv->gpio.ctrl, ®_save); 742 pci_write_config_byte(dev, priv->gpio.ctrl, reg_save | 0x10); 743 priv->gpio.save = reg_save; 744 } 745 746 static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell) 747 { 748 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 749 750 cell->platform_data = &lpc_chipset_info[priv->chipset]; 751 cell->pdata_size = sizeof(struct lpc_ich_info); 752 } 753 754 /* 755 * We don't check for resource conflict globally. There are 2 or 3 independent 756 * GPIO groups and it's enough to have access to one of these to instantiate 757 * the device. 758 */ 759 static int lpc_ich_check_conflict_gpio(struct resource *res) 760 { 761 int ret; 762 u8 use_gpio = 0; 763 764 if (resource_size(res) >= 0x50 && 765 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) 766 use_gpio |= 1 << 2; 767 768 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) 769 use_gpio |= 1 << 1; 770 771 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); 772 if (!ret) 773 use_gpio |= 1 << 0; 774 775 return use_gpio ? use_gpio : ret; 776 } 777 778 static int lpc_ich_init_gpio(struct pci_dev *dev) 779 { 780 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 781 u32 base_addr_cfg; 782 u32 base_addr; 783 int ret; 784 bool acpi_conflict = false; 785 struct resource *res; 786 787 /* Setup power management base register */ 788 pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg); 789 base_addr = base_addr_cfg & 0x0000ff80; 790 if (!base_addr) { 791 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 792 lpc_ich_cells[LPC_GPIO].num_resources--; 793 goto gpe0_done; 794 } 795 796 res = &gpio_ich_res[ICH_RES_GPE0]; 797 res->start = base_addr + ACPIBASE_GPE_OFF; 798 res->end = base_addr + ACPIBASE_GPE_END; 799 ret = acpi_check_resource_conflict(res); 800 if (ret) { 801 /* 802 * This isn't fatal for the GPIO, but we have to make sure that 803 * the platform_device subsystem doesn't see this resource 804 * or it will register an invalid region. 805 */ 806 lpc_ich_cells[LPC_GPIO].num_resources--; 807 acpi_conflict = true; 808 } else { 809 lpc_ich_enable_acpi_space(dev); 810 } 811 812 gpe0_done: 813 /* Setup GPIO base register */ 814 pci_read_config_dword(dev, priv->gpio.base, &base_addr_cfg); 815 base_addr = base_addr_cfg & 0x0000ff80; 816 if (!base_addr) { 817 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); 818 ret = -ENODEV; 819 goto gpio_done; 820 } 821 822 /* Older devices provide fewer GPIO and have a smaller resource size. */ 823 res = &gpio_ich_res[ICH_RES_GPIO]; 824 res->start = base_addr; 825 switch (lpc_chipset_info[priv->chipset].gpio_version) { 826 case ICH_V5_GPIO: 827 case ICH_V10CORP_GPIO: 828 res->end = res->start + 128 - 1; 829 break; 830 default: 831 res->end = res->start + 64 - 1; 832 break; 833 } 834 835 ret = lpc_ich_check_conflict_gpio(res); 836 if (ret < 0) { 837 /* this isn't necessarily fatal for the GPIO */ 838 acpi_conflict = true; 839 goto gpio_done; 840 } 841 lpc_chipset_info[priv->chipset].use_gpio = ret; 842 lpc_ich_enable_gpio_space(dev); 843 844 lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]); 845 ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO], 846 1, NULL, 0, NULL); 847 848 gpio_done: 849 if (acpi_conflict) 850 pr_warn("Resource conflict(s) found affecting %s\n", 851 lpc_ich_cells[LPC_GPIO].name); 852 return ret; 853 } 854 855 static int lpc_ich_init_wdt(struct pci_dev *dev) 856 { 857 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 858 u32 base_addr_cfg; 859 u32 base_addr; 860 int ret; 861 struct resource *res; 862 863 /* Setup power management base register */ 864 pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg); 865 base_addr = base_addr_cfg & 0x0000ff80; 866 if (!base_addr) { 867 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 868 ret = -ENODEV; 869 goto wdt_done; 870 } 871 872 res = wdt_io_res(ICH_RES_IO_TCO); 873 res->start = base_addr + ACPIBASE_TCO_OFF; 874 res->end = base_addr + ACPIBASE_TCO_END; 875 876 res = wdt_io_res(ICH_RES_IO_SMI); 877 res->start = base_addr + ACPIBASE_SMI_OFF; 878 res->end = base_addr + ACPIBASE_SMI_END; 879 880 lpc_ich_enable_acpi_space(dev); 881 882 /* 883 * Get the Memory-Mapped GCS register. To get access to it 884 * we have to read RCBA from PCI Config space 0xf0 and use 885 * it as base. GCS = RCBA + ICH6_GCS(0x3410). 886 */ 887 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { 888 /* Don't register iomem for TCO ver 1 */ 889 lpc_ich_cells[LPC_WDT].num_resources--; 890 } else { 891 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); 892 base_addr = base_addr_cfg & 0xffffc000; 893 if (!(base_addr_cfg & 1)) { 894 dev_notice(&dev->dev, "RCBA is disabled by " 895 "hardware/BIOS, device disabled\n"); 896 ret = -ENODEV; 897 goto wdt_done; 898 } 899 res = wdt_mem_res(ICH_RES_MEM_GCS); 900 res->start = base_addr + ACPIBASE_GCS_OFF; 901 res->end = base_addr + ACPIBASE_GCS_END; 902 } 903 904 lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]); 905 ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT], 906 1, NULL, 0, NULL); 907 908 wdt_done: 909 return ret; 910 } 911 912 static int lpc_ich_probe(struct pci_dev *dev, 913 const struct pci_device_id *id) 914 { 915 struct lpc_ich_priv *priv; 916 int ret; 917 bool cell_added = false; 918 919 priv = devm_kzalloc(&dev->dev, 920 sizeof(struct lpc_ich_priv), GFP_KERNEL); 921 if (!priv) 922 return -ENOMEM; 923 924 priv->chipset = id->driver_data; 925 priv->acpi.save = -1; 926 priv->acpi.base = ACPIBASE; 927 priv->acpi.ctrl = ACPICTRL; 928 929 priv->gpio.save = -1; 930 if (priv->chipset <= LPC_ICH5) { 931 priv->gpio.base = GPIOBASE_ICH0; 932 priv->gpio.ctrl = GPIOCTRL_ICH0; 933 } else { 934 priv->gpio.base = GPIOBASE_ICH6; 935 priv->gpio.ctrl = GPIOCTRL_ICH6; 936 } 937 938 pci_set_drvdata(dev, priv); 939 940 ret = lpc_ich_init_wdt(dev); 941 if (!ret) 942 cell_added = true; 943 944 ret = lpc_ich_init_gpio(dev); 945 if (!ret) 946 cell_added = true; 947 948 /* 949 * We only care if at least one or none of the cells registered 950 * successfully. 951 */ 952 if (!cell_added) { 953 dev_warn(&dev->dev, "No MFD cells added\n"); 954 lpc_ich_restore_config_space(dev); 955 pci_set_drvdata(dev, NULL); 956 return -ENODEV; 957 } 958 959 return 0; 960 } 961 962 static void lpc_ich_remove(struct pci_dev *dev) 963 { 964 mfd_remove_devices(&dev->dev); 965 lpc_ich_restore_config_space(dev); 966 pci_set_drvdata(dev, NULL); 967 } 968 969 static struct pci_driver lpc_ich_driver = { 970 .name = "lpc_ich", 971 .id_table = lpc_ich_ids, 972 .probe = lpc_ich_probe, 973 .remove = lpc_ich_remove, 974 }; 975 976 static int __init lpc_ich_init(void) 977 { 978 return pci_register_driver(&lpc_ich_driver); 979 } 980 981 static void __exit lpc_ich_exit(void) 982 { 983 pci_unregister_driver(&lpc_ich_driver); 984 } 985 986 module_init(lpc_ich_init); 987 module_exit(lpc_ich_exit); 988 989 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); 990 MODULE_DESCRIPTION("LPC interface for Intel ICH"); 991 MODULE_LICENSE("GPL"); 992