1 /* 2 * lpc_ich.c - LPC interface for Intel ICH 3 * 4 * LPC bridge function of the Intel ICH contains many other 5 * functional units, such as Interrupt controllers, Timers, 6 * Power Management, System Management, GPIO, RTC, and LPC 7 * Configuration Registers. 8 * 9 * This driver is derived from lpc_sch. 10 11 * Copyright (c) 2011 Extreme Engineering Solution, Inc. 12 * Author: Aaron Sierra <asierra@xes-inc.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License 2 as published 16 * by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; see the file COPYING. If not, write to 25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * This driver supports the following I/O Controller hubs: 28 * (See the intel documentation on http://developer.intel.com.) 29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) 30 * document number 290687-002, 298242-027: 82801BA (ICH2) 31 * document number 290733-003, 290739-013: 82801CA (ICH3-S) 32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M) 33 * document number 290744-001, 290745-025: 82801DB (ICH4) 34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M) 35 * document number 273599-001, 273645-002: 82801E (C-ICH) 36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) 37 * document number 300641-004, 300884-013: 6300ESB 38 * document number 301473-002, 301474-026: 82801F (ICH6) 39 * document number 313082-001, 313075-006: 631xESB, 632xESB 40 * document number 307013-003, 307014-024: 82801G (ICH7) 41 * document number 322896-001, 322897-001: NM10 42 * document number 313056-003, 313057-017: 82801H (ICH8) 43 * document number 316972-004, 316973-012: 82801I (ICH9) 44 * document number 319973-002, 319974-002: 82801J (ICH10) 45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) 46 * document number 320066-003, 320257-008: EP80597 (IICH) 47 * document number 324645-001, 324646-001: Cougar Point (CPT) 48 * document number TBD : Patsburg (PBG) 49 * document number TBD : DH89xxCC 50 * document number TBD : Panther Point 51 * document number TBD : Lynx Point 52 * document number TBD : Lynx Point-LP 53 * document number TBD : Wellsburg 54 * document number TBD : Avoton SoC 55 * document number TBD : Coleto Creek 56 * document number TBD : Wildcat Point-LP 57 * document number TBD : 9 Series 58 */ 59 60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 61 62 #include <linux/kernel.h> 63 #include <linux/module.h> 64 #include <linux/errno.h> 65 #include <linux/acpi.h> 66 #include <linux/pci.h> 67 #include <linux/mfd/core.h> 68 #include <linux/mfd/lpc_ich.h> 69 #include <linux/platform_data/itco_wdt.h> 70 71 #define ACPIBASE 0x40 72 #define ACPIBASE_GPE_OFF 0x28 73 #define ACPIBASE_GPE_END 0x2f 74 #define ACPIBASE_SMI_OFF 0x30 75 #define ACPIBASE_SMI_END 0x33 76 #define ACPIBASE_PMC_OFF 0x08 77 #define ACPIBASE_PMC_END 0x0c 78 #define ACPIBASE_TCO_OFF 0x60 79 #define ACPIBASE_TCO_END 0x7f 80 #define ACPICTRL_PMCBASE 0x44 81 82 #define ACPIBASE_GCS_OFF 0x3410 83 #define ACPIBASE_GCS_END 0x3414 84 85 #define GPIOBASE_ICH0 0x58 86 #define GPIOCTRL_ICH0 0x5C 87 #define GPIOBASE_ICH6 0x48 88 #define GPIOCTRL_ICH6 0x4C 89 90 #define RCBABASE 0xf0 91 92 #define wdt_io_res(i) wdt_res(0, i) 93 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) 94 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) 95 96 struct lpc_ich_priv { 97 int chipset; 98 99 int abase; /* ACPI base */ 100 int actrl_pbase; /* ACPI control or PMC base */ 101 int gbase; /* GPIO base */ 102 int gctrl; /* GPIO control */ 103 104 int abase_save; /* Cached ACPI base value */ 105 int actrl_pbase_save; /* Cached ACPI control or PMC base value */ 106 int gctrl_save; /* Cached GPIO control value */ 107 }; 108 109 static struct resource wdt_ich_res[] = { 110 /* ACPI - TCO */ 111 { 112 .flags = IORESOURCE_IO, 113 }, 114 /* ACPI - SMI */ 115 { 116 .flags = IORESOURCE_IO, 117 }, 118 /* GCS or PMC */ 119 { 120 .flags = IORESOURCE_MEM, 121 }, 122 }; 123 124 static struct resource gpio_ich_res[] = { 125 /* GPIO */ 126 { 127 .flags = IORESOURCE_IO, 128 }, 129 /* ACPI - GPE0 */ 130 { 131 .flags = IORESOURCE_IO, 132 }, 133 }; 134 135 enum lpc_cells { 136 LPC_WDT = 0, 137 LPC_GPIO, 138 }; 139 140 static struct mfd_cell lpc_ich_cells[] = { 141 [LPC_WDT] = { 142 .name = "iTCO_wdt", 143 .num_resources = ARRAY_SIZE(wdt_ich_res), 144 .resources = wdt_ich_res, 145 .ignore_resource_conflicts = true, 146 }, 147 [LPC_GPIO] = { 148 .name = "gpio_ich", 149 .num_resources = ARRAY_SIZE(gpio_ich_res), 150 .resources = gpio_ich_res, 151 .ignore_resource_conflicts = true, 152 }, 153 }; 154 155 /* chipset related info */ 156 enum lpc_chipsets { 157 LPC_ICH = 0, /* ICH */ 158 LPC_ICH0, /* ICH0 */ 159 LPC_ICH2, /* ICH2 */ 160 LPC_ICH2M, /* ICH2-M */ 161 LPC_ICH3, /* ICH3-S */ 162 LPC_ICH3M, /* ICH3-M */ 163 LPC_ICH4, /* ICH4 */ 164 LPC_ICH4M, /* ICH4-M */ 165 LPC_CICH, /* C-ICH */ 166 LPC_ICH5, /* ICH5 & ICH5R */ 167 LPC_6300ESB, /* 6300ESB */ 168 LPC_ICH6, /* ICH6 & ICH6R */ 169 LPC_ICH6M, /* ICH6-M */ 170 LPC_ICH6W, /* ICH6W & ICH6RW */ 171 LPC_631XESB, /* 631xESB/632xESB */ 172 LPC_ICH7, /* ICH7 & ICH7R */ 173 LPC_ICH7DH, /* ICH7DH */ 174 LPC_ICH7M, /* ICH7-M & ICH7-U */ 175 LPC_ICH7MDH, /* ICH7-M DH */ 176 LPC_NM10, /* NM10 */ 177 LPC_ICH8, /* ICH8 & ICH8R */ 178 LPC_ICH8DH, /* ICH8DH */ 179 LPC_ICH8DO, /* ICH8DO */ 180 LPC_ICH8M, /* ICH8M */ 181 LPC_ICH8ME, /* ICH8M-E */ 182 LPC_ICH9, /* ICH9 */ 183 LPC_ICH9R, /* ICH9R */ 184 LPC_ICH9DH, /* ICH9DH */ 185 LPC_ICH9DO, /* ICH9DO */ 186 LPC_ICH9M, /* ICH9M */ 187 LPC_ICH9ME, /* ICH9M-E */ 188 LPC_ICH10, /* ICH10 */ 189 LPC_ICH10R, /* ICH10R */ 190 LPC_ICH10D, /* ICH10D */ 191 LPC_ICH10DO, /* ICH10DO */ 192 LPC_PCH, /* PCH Desktop Full Featured */ 193 LPC_PCHM, /* PCH Mobile Full Featured */ 194 LPC_P55, /* P55 */ 195 LPC_PM55, /* PM55 */ 196 LPC_H55, /* H55 */ 197 LPC_QM57, /* QM57 */ 198 LPC_H57, /* H57 */ 199 LPC_HM55, /* HM55 */ 200 LPC_Q57, /* Q57 */ 201 LPC_HM57, /* HM57 */ 202 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ 203 LPC_QS57, /* QS57 */ 204 LPC_3400, /* 3400 */ 205 LPC_3420, /* 3420 */ 206 LPC_3450, /* 3450 */ 207 LPC_EP80579, /* EP80579 */ 208 LPC_CPT, /* Cougar Point */ 209 LPC_CPTD, /* Cougar Point Desktop */ 210 LPC_CPTM, /* Cougar Point Mobile */ 211 LPC_PBG, /* Patsburg */ 212 LPC_DH89XXCC, /* DH89xxCC */ 213 LPC_PPT, /* Panther Point */ 214 LPC_LPT, /* Lynx Point */ 215 LPC_LPT_LP, /* Lynx Point-LP */ 216 LPC_WBG, /* Wellsburg */ 217 LPC_AVN, /* Avoton SoC */ 218 LPC_BAYTRAIL, /* Bay Trail SoC */ 219 LPC_COLETO, /* Coleto Creek */ 220 LPC_WPT_LP, /* Wildcat Point-LP */ 221 LPC_BRASWELL, /* Braswell SoC */ 222 LPC_9S, /* 9 Series */ 223 }; 224 225 static struct lpc_ich_info lpc_chipset_info[] = { 226 [LPC_ICH] = { 227 .name = "ICH", 228 .iTCO_version = 1, 229 }, 230 [LPC_ICH0] = { 231 .name = "ICH0", 232 .iTCO_version = 1, 233 }, 234 [LPC_ICH2] = { 235 .name = "ICH2", 236 .iTCO_version = 1, 237 }, 238 [LPC_ICH2M] = { 239 .name = "ICH2-M", 240 .iTCO_version = 1, 241 }, 242 [LPC_ICH3] = { 243 .name = "ICH3-S", 244 .iTCO_version = 1, 245 }, 246 [LPC_ICH3M] = { 247 .name = "ICH3-M", 248 .iTCO_version = 1, 249 }, 250 [LPC_ICH4] = { 251 .name = "ICH4", 252 .iTCO_version = 1, 253 }, 254 [LPC_ICH4M] = { 255 .name = "ICH4-M", 256 .iTCO_version = 1, 257 }, 258 [LPC_CICH] = { 259 .name = "C-ICH", 260 .iTCO_version = 1, 261 }, 262 [LPC_ICH5] = { 263 .name = "ICH5 or ICH5R", 264 .iTCO_version = 1, 265 }, 266 [LPC_6300ESB] = { 267 .name = "6300ESB", 268 .iTCO_version = 1, 269 }, 270 [LPC_ICH6] = { 271 .name = "ICH6 or ICH6R", 272 .iTCO_version = 2, 273 .gpio_version = ICH_V6_GPIO, 274 }, 275 [LPC_ICH6M] = { 276 .name = "ICH6-M", 277 .iTCO_version = 2, 278 .gpio_version = ICH_V6_GPIO, 279 }, 280 [LPC_ICH6W] = { 281 .name = "ICH6W or ICH6RW", 282 .iTCO_version = 2, 283 .gpio_version = ICH_V6_GPIO, 284 }, 285 [LPC_631XESB] = { 286 .name = "631xESB/632xESB", 287 .iTCO_version = 2, 288 .gpio_version = ICH_V6_GPIO, 289 }, 290 [LPC_ICH7] = { 291 .name = "ICH7 or ICH7R", 292 .iTCO_version = 2, 293 .gpio_version = ICH_V7_GPIO, 294 }, 295 [LPC_ICH7DH] = { 296 .name = "ICH7DH", 297 .iTCO_version = 2, 298 .gpio_version = ICH_V7_GPIO, 299 }, 300 [LPC_ICH7M] = { 301 .name = "ICH7-M or ICH7-U", 302 .iTCO_version = 2, 303 .gpio_version = ICH_V7_GPIO, 304 }, 305 [LPC_ICH7MDH] = { 306 .name = "ICH7-M DH", 307 .iTCO_version = 2, 308 .gpio_version = ICH_V7_GPIO, 309 }, 310 [LPC_NM10] = { 311 .name = "NM10", 312 .iTCO_version = 2, 313 .gpio_version = ICH_V7_GPIO, 314 }, 315 [LPC_ICH8] = { 316 .name = "ICH8 or ICH8R", 317 .iTCO_version = 2, 318 .gpio_version = ICH_V7_GPIO, 319 }, 320 [LPC_ICH8DH] = { 321 .name = "ICH8DH", 322 .iTCO_version = 2, 323 .gpio_version = ICH_V7_GPIO, 324 }, 325 [LPC_ICH8DO] = { 326 .name = "ICH8DO", 327 .iTCO_version = 2, 328 .gpio_version = ICH_V7_GPIO, 329 }, 330 [LPC_ICH8M] = { 331 .name = "ICH8M", 332 .iTCO_version = 2, 333 .gpio_version = ICH_V7_GPIO, 334 }, 335 [LPC_ICH8ME] = { 336 .name = "ICH8M-E", 337 .iTCO_version = 2, 338 .gpio_version = ICH_V7_GPIO, 339 }, 340 [LPC_ICH9] = { 341 .name = "ICH9", 342 .iTCO_version = 2, 343 .gpio_version = ICH_V9_GPIO, 344 }, 345 [LPC_ICH9R] = { 346 .name = "ICH9R", 347 .iTCO_version = 2, 348 .gpio_version = ICH_V9_GPIO, 349 }, 350 [LPC_ICH9DH] = { 351 .name = "ICH9DH", 352 .iTCO_version = 2, 353 .gpio_version = ICH_V9_GPIO, 354 }, 355 [LPC_ICH9DO] = { 356 .name = "ICH9DO", 357 .iTCO_version = 2, 358 .gpio_version = ICH_V9_GPIO, 359 }, 360 [LPC_ICH9M] = { 361 .name = "ICH9M", 362 .iTCO_version = 2, 363 .gpio_version = ICH_V9_GPIO, 364 }, 365 [LPC_ICH9ME] = { 366 .name = "ICH9M-E", 367 .iTCO_version = 2, 368 .gpio_version = ICH_V9_GPIO, 369 }, 370 [LPC_ICH10] = { 371 .name = "ICH10", 372 .iTCO_version = 2, 373 .gpio_version = ICH_V10CONS_GPIO, 374 }, 375 [LPC_ICH10R] = { 376 .name = "ICH10R", 377 .iTCO_version = 2, 378 .gpio_version = ICH_V10CONS_GPIO, 379 }, 380 [LPC_ICH10D] = { 381 .name = "ICH10D", 382 .iTCO_version = 2, 383 .gpio_version = ICH_V10CORP_GPIO, 384 }, 385 [LPC_ICH10DO] = { 386 .name = "ICH10DO", 387 .iTCO_version = 2, 388 .gpio_version = ICH_V10CORP_GPIO, 389 }, 390 [LPC_PCH] = { 391 .name = "PCH Desktop Full Featured", 392 .iTCO_version = 2, 393 .gpio_version = ICH_V5_GPIO, 394 }, 395 [LPC_PCHM] = { 396 .name = "PCH Mobile Full Featured", 397 .iTCO_version = 2, 398 .gpio_version = ICH_V5_GPIO, 399 }, 400 [LPC_P55] = { 401 .name = "P55", 402 .iTCO_version = 2, 403 .gpio_version = ICH_V5_GPIO, 404 }, 405 [LPC_PM55] = { 406 .name = "PM55", 407 .iTCO_version = 2, 408 .gpio_version = ICH_V5_GPIO, 409 }, 410 [LPC_H55] = { 411 .name = "H55", 412 .iTCO_version = 2, 413 .gpio_version = ICH_V5_GPIO, 414 }, 415 [LPC_QM57] = { 416 .name = "QM57", 417 .iTCO_version = 2, 418 .gpio_version = ICH_V5_GPIO, 419 }, 420 [LPC_H57] = { 421 .name = "H57", 422 .iTCO_version = 2, 423 .gpio_version = ICH_V5_GPIO, 424 }, 425 [LPC_HM55] = { 426 .name = "HM55", 427 .iTCO_version = 2, 428 .gpio_version = ICH_V5_GPIO, 429 }, 430 [LPC_Q57] = { 431 .name = "Q57", 432 .iTCO_version = 2, 433 .gpio_version = ICH_V5_GPIO, 434 }, 435 [LPC_HM57] = { 436 .name = "HM57", 437 .iTCO_version = 2, 438 .gpio_version = ICH_V5_GPIO, 439 }, 440 [LPC_PCHMSFF] = { 441 .name = "PCH Mobile SFF Full Featured", 442 .iTCO_version = 2, 443 .gpio_version = ICH_V5_GPIO, 444 }, 445 [LPC_QS57] = { 446 .name = "QS57", 447 .iTCO_version = 2, 448 .gpio_version = ICH_V5_GPIO, 449 }, 450 [LPC_3400] = { 451 .name = "3400", 452 .iTCO_version = 2, 453 .gpio_version = ICH_V5_GPIO, 454 }, 455 [LPC_3420] = { 456 .name = "3420", 457 .iTCO_version = 2, 458 .gpio_version = ICH_V5_GPIO, 459 }, 460 [LPC_3450] = { 461 .name = "3450", 462 .iTCO_version = 2, 463 .gpio_version = ICH_V5_GPIO, 464 }, 465 [LPC_EP80579] = { 466 .name = "EP80579", 467 .iTCO_version = 2, 468 }, 469 [LPC_CPT] = { 470 .name = "Cougar Point", 471 .iTCO_version = 2, 472 .gpio_version = ICH_V5_GPIO, 473 }, 474 [LPC_CPTD] = { 475 .name = "Cougar Point Desktop", 476 .iTCO_version = 2, 477 .gpio_version = ICH_V5_GPIO, 478 }, 479 [LPC_CPTM] = { 480 .name = "Cougar Point Mobile", 481 .iTCO_version = 2, 482 .gpio_version = ICH_V5_GPIO, 483 }, 484 [LPC_PBG] = { 485 .name = "Patsburg", 486 .iTCO_version = 2, 487 }, 488 [LPC_DH89XXCC] = { 489 .name = "DH89xxCC", 490 .iTCO_version = 2, 491 }, 492 [LPC_PPT] = { 493 .name = "Panther Point", 494 .iTCO_version = 2, 495 .gpio_version = ICH_V5_GPIO, 496 }, 497 [LPC_LPT] = { 498 .name = "Lynx Point", 499 .iTCO_version = 2, 500 }, 501 [LPC_LPT_LP] = { 502 .name = "Lynx Point_LP", 503 .iTCO_version = 2, 504 }, 505 [LPC_WBG] = { 506 .name = "Wellsburg", 507 .iTCO_version = 2, 508 }, 509 [LPC_AVN] = { 510 .name = "Avoton SoC", 511 .iTCO_version = 3, 512 .gpio_version = AVOTON_GPIO, 513 }, 514 [LPC_BAYTRAIL] = { 515 .name = "Bay Trail SoC", 516 .iTCO_version = 3, 517 }, 518 [LPC_COLETO] = { 519 .name = "Coleto Creek", 520 .iTCO_version = 2, 521 }, 522 [LPC_WPT_LP] = { 523 .name = "Wildcat Point_LP", 524 .iTCO_version = 2, 525 }, 526 [LPC_BRASWELL] = { 527 .name = "Braswell SoC", 528 .iTCO_version = 3, 529 }, 530 [LPC_9S] = { 531 .name = "9 Series", 532 .iTCO_version = 2, 533 }, 534 }; 535 536 /* 537 * This data only exists for exporting the supported PCI ids 538 * via MODULE_DEVICE_TABLE. We do not actually register a 539 * pci_driver, because the I/O Controller Hub has also other 540 * functions that probably will be registered by other drivers. 541 */ 542 static const struct pci_device_id lpc_ich_ids[] = { 543 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, 544 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, 545 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, 546 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, 547 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, 548 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, 549 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, 550 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, 551 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, 552 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, 553 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, 554 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, 555 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, 556 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, 557 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, 558 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, 559 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, 560 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, 561 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, 562 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, 563 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, 564 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, 565 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, 566 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, 567 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, 568 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, 569 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, 570 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, 571 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, 572 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, 573 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, 574 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, 575 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, 576 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, 577 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, 578 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, 579 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, 580 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, 581 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, 582 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, 583 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, 584 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, 585 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, 586 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, 587 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, 588 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, 589 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, 590 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, 591 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, 592 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, 593 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, 594 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, 595 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, 596 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, 597 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, 598 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, 599 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, 600 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, 601 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, 602 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, 603 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, 604 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, 605 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, 606 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, 607 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, 608 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, 609 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, 610 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, 611 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, 612 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, 613 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL}, 614 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, 615 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, 616 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, 617 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, 618 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, 619 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, 620 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, 621 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, 622 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, 623 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, 624 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, 625 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, 626 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, 627 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, 628 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, 629 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, 630 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, 631 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, 632 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, 633 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, 634 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, 635 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, 636 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, 637 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, 638 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, 639 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, 640 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, 641 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, 642 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, 643 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, 644 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, 645 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, 646 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, 647 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, 648 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, 649 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, 650 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, 651 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, 652 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, 653 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, 654 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, 655 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, 656 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, 657 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, 658 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, 659 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, 660 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, 661 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, 662 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, 663 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, 664 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, 665 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, 666 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, 667 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, 668 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, 669 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, 670 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, 671 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, 672 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, 673 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, 674 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, 675 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, 676 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, 677 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, 678 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, 679 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, 680 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, 681 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, 682 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, 683 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, 684 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, 685 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, 686 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, 687 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, 688 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, 689 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, 690 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, 691 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, 692 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, 693 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, 694 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, 695 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, 696 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, 697 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, 698 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, 699 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, 700 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, 701 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, 702 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, 703 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, 704 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, 705 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, 706 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, 707 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, 708 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, 709 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, 710 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, 711 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, 712 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, 713 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, 714 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S}, 715 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S}, 716 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S}, 717 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S}, 718 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S}, 719 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, 720 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, 721 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, 722 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, 723 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, 724 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, 725 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, 726 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, 727 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, 728 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, 729 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, 730 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, 731 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, 732 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, 733 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, 734 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, 735 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, 736 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, 737 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, 738 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, 739 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, 740 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, 741 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, 742 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, 743 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, 744 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, 745 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, 746 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, 747 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, 748 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, 749 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, 750 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, 751 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, 752 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, 753 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, 754 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, 755 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, 756 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, 757 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, 758 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, 759 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, 760 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, 761 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, 762 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, 763 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, 764 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, 765 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, 766 { 0, }, /* End of list */ 767 }; 768 MODULE_DEVICE_TABLE(pci, lpc_ich_ids); 769 770 static void lpc_ich_restore_config_space(struct pci_dev *dev) 771 { 772 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 773 774 if (priv->abase_save >= 0) { 775 pci_write_config_byte(dev, priv->abase, priv->abase_save); 776 priv->abase_save = -1; 777 } 778 779 if (priv->actrl_pbase_save >= 0) { 780 pci_write_config_byte(dev, priv->actrl_pbase, 781 priv->actrl_pbase_save); 782 priv->actrl_pbase_save = -1; 783 } 784 785 if (priv->gctrl_save >= 0) { 786 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); 787 priv->gctrl_save = -1; 788 } 789 } 790 791 static void lpc_ich_enable_acpi_space(struct pci_dev *dev) 792 { 793 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 794 u8 reg_save; 795 796 switch (lpc_chipset_info[priv->chipset].iTCO_version) { 797 case 3: 798 /* 799 * Some chipsets (eg Avoton) enable the ACPI space in the 800 * ACPI BASE register. 801 */ 802 pci_read_config_byte(dev, priv->abase, ®_save); 803 pci_write_config_byte(dev, priv->abase, reg_save | 0x2); 804 priv->abase_save = reg_save; 805 break; 806 default: 807 /* 808 * Most chipsets enable the ACPI space in the ACPI control 809 * register. 810 */ 811 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); 812 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); 813 priv->actrl_pbase_save = reg_save; 814 break; 815 } 816 } 817 818 static void lpc_ich_enable_gpio_space(struct pci_dev *dev) 819 { 820 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 821 u8 reg_save; 822 823 pci_read_config_byte(dev, priv->gctrl, ®_save); 824 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); 825 priv->gctrl_save = reg_save; 826 } 827 828 static void lpc_ich_enable_pmc_space(struct pci_dev *dev) 829 { 830 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 831 u8 reg_save; 832 833 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); 834 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); 835 836 priv->actrl_pbase_save = reg_save; 837 } 838 839 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) 840 { 841 struct itco_wdt_platform_data *pdata; 842 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 843 struct lpc_ich_info *info; 844 struct mfd_cell *cell = &lpc_ich_cells[LPC_WDT]; 845 846 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); 847 if (!pdata) 848 return -ENOMEM; 849 850 info = &lpc_chipset_info[priv->chipset]; 851 852 pdata->version = info->iTCO_version; 853 strlcpy(pdata->name, info->name, sizeof(pdata->name)); 854 855 cell->platform_data = pdata; 856 cell->pdata_size = sizeof(*pdata); 857 return 0; 858 } 859 860 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) 861 { 862 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 863 struct mfd_cell *cell = &lpc_ich_cells[LPC_GPIO]; 864 865 cell->platform_data = &lpc_chipset_info[priv->chipset]; 866 cell->pdata_size = sizeof(struct lpc_ich_info); 867 } 868 869 /* 870 * We don't check for resource conflict globally. There are 2 or 3 independent 871 * GPIO groups and it's enough to have access to one of these to instantiate 872 * the device. 873 */ 874 static int lpc_ich_check_conflict_gpio(struct resource *res) 875 { 876 int ret; 877 u8 use_gpio = 0; 878 879 if (resource_size(res) >= 0x50 && 880 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) 881 use_gpio |= 1 << 2; 882 883 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) 884 use_gpio |= 1 << 1; 885 886 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); 887 if (!ret) 888 use_gpio |= 1 << 0; 889 890 return use_gpio ? use_gpio : ret; 891 } 892 893 static int lpc_ich_init_gpio(struct pci_dev *dev) 894 { 895 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 896 u32 base_addr_cfg; 897 u32 base_addr; 898 int ret; 899 bool acpi_conflict = false; 900 struct resource *res; 901 902 /* Setup power management base register */ 903 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); 904 base_addr = base_addr_cfg & 0x0000ff80; 905 if (!base_addr) { 906 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 907 lpc_ich_cells[LPC_GPIO].num_resources--; 908 goto gpe0_done; 909 } 910 911 res = &gpio_ich_res[ICH_RES_GPE0]; 912 res->start = base_addr + ACPIBASE_GPE_OFF; 913 res->end = base_addr + ACPIBASE_GPE_END; 914 ret = acpi_check_resource_conflict(res); 915 if (ret) { 916 /* 917 * This isn't fatal for the GPIO, but we have to make sure that 918 * the platform_device subsystem doesn't see this resource 919 * or it will register an invalid region. 920 */ 921 lpc_ich_cells[LPC_GPIO].num_resources--; 922 acpi_conflict = true; 923 } else { 924 lpc_ich_enable_acpi_space(dev); 925 } 926 927 gpe0_done: 928 /* Setup GPIO base register */ 929 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); 930 base_addr = base_addr_cfg & 0x0000ff80; 931 if (!base_addr) { 932 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); 933 ret = -ENODEV; 934 goto gpio_done; 935 } 936 937 /* Older devices provide fewer GPIO and have a smaller resource size. */ 938 res = &gpio_ich_res[ICH_RES_GPIO]; 939 res->start = base_addr; 940 switch (lpc_chipset_info[priv->chipset].gpio_version) { 941 case ICH_V5_GPIO: 942 case ICH_V10CORP_GPIO: 943 res->end = res->start + 128 - 1; 944 break; 945 default: 946 res->end = res->start + 64 - 1; 947 break; 948 } 949 950 ret = lpc_ich_check_conflict_gpio(res); 951 if (ret < 0) { 952 /* this isn't necessarily fatal for the GPIO */ 953 acpi_conflict = true; 954 goto gpio_done; 955 } 956 lpc_chipset_info[priv->chipset].use_gpio = ret; 957 lpc_ich_enable_gpio_space(dev); 958 959 lpc_ich_finalize_gpio_cell(dev); 960 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, 961 &lpc_ich_cells[LPC_GPIO], 1, NULL, 0, NULL); 962 963 gpio_done: 964 if (acpi_conflict) 965 pr_warn("Resource conflict(s) found affecting %s\n", 966 lpc_ich_cells[LPC_GPIO].name); 967 return ret; 968 } 969 970 static int lpc_ich_init_wdt(struct pci_dev *dev) 971 { 972 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 973 u32 base_addr_cfg; 974 u32 base_addr; 975 int ret; 976 struct resource *res; 977 978 /* Setup power management base register */ 979 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); 980 base_addr = base_addr_cfg & 0x0000ff80; 981 if (!base_addr) { 982 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 983 ret = -ENODEV; 984 goto wdt_done; 985 } 986 987 res = wdt_io_res(ICH_RES_IO_TCO); 988 res->start = base_addr + ACPIBASE_TCO_OFF; 989 res->end = base_addr + ACPIBASE_TCO_END; 990 991 res = wdt_io_res(ICH_RES_IO_SMI); 992 res->start = base_addr + ACPIBASE_SMI_OFF; 993 res->end = base_addr + ACPIBASE_SMI_END; 994 995 lpc_ich_enable_acpi_space(dev); 996 997 /* 998 * iTCO v2: 999 * Get the Memory-Mapped GCS register. To get access to it 1000 * we have to read RCBA from PCI Config space 0xf0 and use 1001 * it as base. GCS = RCBA + ICH6_GCS(0x3410). 1002 * 1003 * iTCO v3: 1004 * Get the Power Management Configuration register. To get access 1005 * to it we have to read the PMC BASE from config space and address 1006 * the register at offset 0x8. 1007 */ 1008 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { 1009 /* Don't register iomem for TCO ver 1 */ 1010 lpc_ich_cells[LPC_WDT].num_resources--; 1011 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { 1012 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); 1013 base_addr = base_addr_cfg & 0xffffc000; 1014 if (!(base_addr_cfg & 1)) { 1015 dev_notice(&dev->dev, "RCBA is disabled by " 1016 "hardware/BIOS, device disabled\n"); 1017 ret = -ENODEV; 1018 goto wdt_done; 1019 } 1020 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); 1021 res->start = base_addr + ACPIBASE_GCS_OFF; 1022 res->end = base_addr + ACPIBASE_GCS_END; 1023 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { 1024 lpc_ich_enable_pmc_space(dev); 1025 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); 1026 base_addr = base_addr_cfg & 0xfffffe00; 1027 1028 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); 1029 res->start = base_addr + ACPIBASE_PMC_OFF; 1030 res->end = base_addr + ACPIBASE_PMC_END; 1031 } 1032 1033 ret = lpc_ich_finalize_wdt_cell(dev); 1034 if (ret) 1035 goto wdt_done; 1036 1037 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, 1038 &lpc_ich_cells[LPC_WDT], 1, NULL, 0, NULL); 1039 1040 wdt_done: 1041 return ret; 1042 } 1043 1044 static int lpc_ich_probe(struct pci_dev *dev, 1045 const struct pci_device_id *id) 1046 { 1047 struct lpc_ich_priv *priv; 1048 int ret; 1049 bool cell_added = false; 1050 1051 priv = devm_kzalloc(&dev->dev, 1052 sizeof(struct lpc_ich_priv), GFP_KERNEL); 1053 if (!priv) 1054 return -ENOMEM; 1055 1056 priv->chipset = id->driver_data; 1057 1058 priv->actrl_pbase_save = -1; 1059 priv->abase_save = -1; 1060 1061 priv->abase = ACPIBASE; 1062 priv->actrl_pbase = ACPICTRL_PMCBASE; 1063 1064 priv->gctrl_save = -1; 1065 if (priv->chipset <= LPC_ICH5) { 1066 priv->gbase = GPIOBASE_ICH0; 1067 priv->gctrl = GPIOCTRL_ICH0; 1068 } else { 1069 priv->gbase = GPIOBASE_ICH6; 1070 priv->gctrl = GPIOCTRL_ICH6; 1071 } 1072 1073 pci_set_drvdata(dev, priv); 1074 1075 if (lpc_chipset_info[priv->chipset].iTCO_version) { 1076 ret = lpc_ich_init_wdt(dev); 1077 if (!ret) 1078 cell_added = true; 1079 } 1080 1081 if (lpc_chipset_info[priv->chipset].gpio_version) { 1082 ret = lpc_ich_init_gpio(dev); 1083 if (!ret) 1084 cell_added = true; 1085 } 1086 1087 /* 1088 * We only care if at least one or none of the cells registered 1089 * successfully. 1090 */ 1091 if (!cell_added) { 1092 dev_warn(&dev->dev, "No MFD cells added\n"); 1093 lpc_ich_restore_config_space(dev); 1094 return -ENODEV; 1095 } 1096 1097 return 0; 1098 } 1099 1100 static void lpc_ich_remove(struct pci_dev *dev) 1101 { 1102 mfd_remove_devices(&dev->dev); 1103 lpc_ich_restore_config_space(dev); 1104 } 1105 1106 static struct pci_driver lpc_ich_driver = { 1107 .name = "lpc_ich", 1108 .id_table = lpc_ich_ids, 1109 .probe = lpc_ich_probe, 1110 .remove = lpc_ich_remove, 1111 }; 1112 1113 module_pci_driver(lpc_ich_driver); 1114 1115 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); 1116 MODULE_DESCRIPTION("LPC interface for Intel ICH"); 1117 MODULE_LICENSE("GPL"); 1118