1 /* 2 * lpc_ich.c - LPC interface for Intel ICH 3 * 4 * LPC bridge function of the Intel ICH contains many other 5 * functional units, such as Interrupt controllers, Timers, 6 * Power Management, System Management, GPIO, RTC, and LPC 7 * Configuration Registers. 8 * 9 * This driver is derived from lpc_sch. 10 11 * Copyright (c) 2011 Extreme Engineering Solution, Inc. 12 * Author: Aaron Sierra <asierra@xes-inc.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License 2 as published 16 * by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; see the file COPYING. If not, write to 25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * This driver supports the following I/O Controller hubs: 28 * (See the intel documentation on http://developer.intel.com.) 29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) 30 * document number 290687-002, 298242-027: 82801BA (ICH2) 31 * document number 290733-003, 290739-013: 82801CA (ICH3-S) 32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M) 33 * document number 290744-001, 290745-025: 82801DB (ICH4) 34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M) 35 * document number 273599-001, 273645-002: 82801E (C-ICH) 36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) 37 * document number 300641-004, 300884-013: 6300ESB 38 * document number 301473-002, 301474-026: 82801F (ICH6) 39 * document number 313082-001, 313075-006: 631xESB, 632xESB 40 * document number 307013-003, 307014-024: 82801G (ICH7) 41 * document number 322896-001, 322897-001: NM10 42 * document number 313056-003, 313057-017: 82801H (ICH8) 43 * document number 316972-004, 316973-012: 82801I (ICH9) 44 * document number 319973-002, 319974-002: 82801J (ICH10) 45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) 46 * document number 320066-003, 320257-008: EP80597 (IICH) 47 * document number 324645-001, 324646-001: Cougar Point (CPT) 48 * document number TBD : Patsburg (PBG) 49 * document number TBD : DH89xxCC 50 * document number TBD : Panther Point 51 * document number TBD : Lynx Point 52 * document number TBD : Lynx Point-LP 53 * document number TBD : Wellsburg 54 * document number TBD : Avoton SoC 55 * document number TBD : Coleto Creek 56 * document number TBD : Wildcat Point-LP 57 * document number TBD : 9 Series 58 */ 59 60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 61 62 #include <linux/kernel.h> 63 #include <linux/module.h> 64 #include <linux/errno.h> 65 #include <linux/acpi.h> 66 #include <linux/pci.h> 67 #include <linux/mfd/core.h> 68 #include <linux/mfd/lpc_ich.h> 69 #include <linux/platform_data/itco_wdt.h> 70 71 #define ACPIBASE 0x40 72 #define ACPIBASE_GPE_OFF 0x28 73 #define ACPIBASE_GPE_END 0x2f 74 #define ACPIBASE_SMI_OFF 0x30 75 #define ACPIBASE_SMI_END 0x33 76 #define ACPIBASE_PMC_OFF 0x08 77 #define ACPIBASE_PMC_END 0x0c 78 #define ACPIBASE_TCO_OFF 0x60 79 #define ACPIBASE_TCO_END 0x7f 80 #define ACPICTRL_PMCBASE 0x44 81 82 #define ACPIBASE_GCS_OFF 0x3410 83 #define ACPIBASE_GCS_END 0x3414 84 85 #define GPIOBASE_ICH0 0x58 86 #define GPIOCTRL_ICH0 0x5C 87 #define GPIOBASE_ICH6 0x48 88 #define GPIOCTRL_ICH6 0x4C 89 90 #define RCBABASE 0xf0 91 92 #define wdt_io_res(i) wdt_res(0, i) 93 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) 94 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) 95 96 struct lpc_ich_priv { 97 int chipset; 98 99 int abase; /* ACPI base */ 100 int actrl_pbase; /* ACPI control or PMC base */ 101 int gbase; /* GPIO base */ 102 int gctrl; /* GPIO control */ 103 104 int abase_save; /* Cached ACPI base value */ 105 int actrl_pbase_save; /* Cached ACPI control or PMC base value */ 106 int gctrl_save; /* Cached GPIO control value */ 107 }; 108 109 static struct resource wdt_ich_res[] = { 110 /* ACPI - TCO */ 111 { 112 .flags = IORESOURCE_IO, 113 }, 114 /* ACPI - SMI */ 115 { 116 .flags = IORESOURCE_IO, 117 }, 118 /* GCS or PMC */ 119 { 120 .flags = IORESOURCE_MEM, 121 }, 122 }; 123 124 static struct resource gpio_ich_res[] = { 125 /* GPIO */ 126 { 127 .flags = IORESOURCE_IO, 128 }, 129 /* ACPI - GPE0 */ 130 { 131 .flags = IORESOURCE_IO, 132 }, 133 }; 134 135 static struct mfd_cell lpc_ich_wdt_cell = { 136 .name = "iTCO_wdt", 137 .num_resources = ARRAY_SIZE(wdt_ich_res), 138 .resources = wdt_ich_res, 139 .ignore_resource_conflicts = true, 140 }; 141 142 static struct mfd_cell lpc_ich_gpio_cell = { 143 .name = "gpio_ich", 144 .num_resources = ARRAY_SIZE(gpio_ich_res), 145 .resources = gpio_ich_res, 146 .ignore_resource_conflicts = true, 147 }; 148 149 /* chipset related info */ 150 enum lpc_chipsets { 151 LPC_ICH = 0, /* ICH */ 152 LPC_ICH0, /* ICH0 */ 153 LPC_ICH2, /* ICH2 */ 154 LPC_ICH2M, /* ICH2-M */ 155 LPC_ICH3, /* ICH3-S */ 156 LPC_ICH3M, /* ICH3-M */ 157 LPC_ICH4, /* ICH4 */ 158 LPC_ICH4M, /* ICH4-M */ 159 LPC_CICH, /* C-ICH */ 160 LPC_ICH5, /* ICH5 & ICH5R */ 161 LPC_6300ESB, /* 6300ESB */ 162 LPC_ICH6, /* ICH6 & ICH6R */ 163 LPC_ICH6M, /* ICH6-M */ 164 LPC_ICH6W, /* ICH6W & ICH6RW */ 165 LPC_631XESB, /* 631xESB/632xESB */ 166 LPC_ICH7, /* ICH7 & ICH7R */ 167 LPC_ICH7DH, /* ICH7DH */ 168 LPC_ICH7M, /* ICH7-M & ICH7-U */ 169 LPC_ICH7MDH, /* ICH7-M DH */ 170 LPC_NM10, /* NM10 */ 171 LPC_ICH8, /* ICH8 & ICH8R */ 172 LPC_ICH8DH, /* ICH8DH */ 173 LPC_ICH8DO, /* ICH8DO */ 174 LPC_ICH8M, /* ICH8M */ 175 LPC_ICH8ME, /* ICH8M-E */ 176 LPC_ICH9, /* ICH9 */ 177 LPC_ICH9R, /* ICH9R */ 178 LPC_ICH9DH, /* ICH9DH */ 179 LPC_ICH9DO, /* ICH9DO */ 180 LPC_ICH9M, /* ICH9M */ 181 LPC_ICH9ME, /* ICH9M-E */ 182 LPC_ICH10, /* ICH10 */ 183 LPC_ICH10R, /* ICH10R */ 184 LPC_ICH10D, /* ICH10D */ 185 LPC_ICH10DO, /* ICH10DO */ 186 LPC_PCH, /* PCH Desktop Full Featured */ 187 LPC_PCHM, /* PCH Mobile Full Featured */ 188 LPC_P55, /* P55 */ 189 LPC_PM55, /* PM55 */ 190 LPC_H55, /* H55 */ 191 LPC_QM57, /* QM57 */ 192 LPC_H57, /* H57 */ 193 LPC_HM55, /* HM55 */ 194 LPC_Q57, /* Q57 */ 195 LPC_HM57, /* HM57 */ 196 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ 197 LPC_QS57, /* QS57 */ 198 LPC_3400, /* 3400 */ 199 LPC_3420, /* 3420 */ 200 LPC_3450, /* 3450 */ 201 LPC_EP80579, /* EP80579 */ 202 LPC_CPT, /* Cougar Point */ 203 LPC_CPTD, /* Cougar Point Desktop */ 204 LPC_CPTM, /* Cougar Point Mobile */ 205 LPC_PBG, /* Patsburg */ 206 LPC_DH89XXCC, /* DH89xxCC */ 207 LPC_PPT, /* Panther Point */ 208 LPC_LPT, /* Lynx Point */ 209 LPC_LPT_LP, /* Lynx Point-LP */ 210 LPC_WBG, /* Wellsburg */ 211 LPC_AVN, /* Avoton SoC */ 212 LPC_BAYTRAIL, /* Bay Trail SoC */ 213 LPC_COLETO, /* Coleto Creek */ 214 LPC_WPT_LP, /* Wildcat Point-LP */ 215 LPC_BRASWELL, /* Braswell SoC */ 216 LPC_9S, /* 9 Series */ 217 }; 218 219 static struct lpc_ich_info lpc_chipset_info[] = { 220 [LPC_ICH] = { 221 .name = "ICH", 222 .iTCO_version = 1, 223 }, 224 [LPC_ICH0] = { 225 .name = "ICH0", 226 .iTCO_version = 1, 227 }, 228 [LPC_ICH2] = { 229 .name = "ICH2", 230 .iTCO_version = 1, 231 }, 232 [LPC_ICH2M] = { 233 .name = "ICH2-M", 234 .iTCO_version = 1, 235 }, 236 [LPC_ICH3] = { 237 .name = "ICH3-S", 238 .iTCO_version = 1, 239 }, 240 [LPC_ICH3M] = { 241 .name = "ICH3-M", 242 .iTCO_version = 1, 243 }, 244 [LPC_ICH4] = { 245 .name = "ICH4", 246 .iTCO_version = 1, 247 }, 248 [LPC_ICH4M] = { 249 .name = "ICH4-M", 250 .iTCO_version = 1, 251 }, 252 [LPC_CICH] = { 253 .name = "C-ICH", 254 .iTCO_version = 1, 255 }, 256 [LPC_ICH5] = { 257 .name = "ICH5 or ICH5R", 258 .iTCO_version = 1, 259 }, 260 [LPC_6300ESB] = { 261 .name = "6300ESB", 262 .iTCO_version = 1, 263 }, 264 [LPC_ICH6] = { 265 .name = "ICH6 or ICH6R", 266 .iTCO_version = 2, 267 .gpio_version = ICH_V6_GPIO, 268 }, 269 [LPC_ICH6M] = { 270 .name = "ICH6-M", 271 .iTCO_version = 2, 272 .gpio_version = ICH_V6_GPIO, 273 }, 274 [LPC_ICH6W] = { 275 .name = "ICH6W or ICH6RW", 276 .iTCO_version = 2, 277 .gpio_version = ICH_V6_GPIO, 278 }, 279 [LPC_631XESB] = { 280 .name = "631xESB/632xESB", 281 .iTCO_version = 2, 282 .gpio_version = ICH_V6_GPIO, 283 }, 284 [LPC_ICH7] = { 285 .name = "ICH7 or ICH7R", 286 .iTCO_version = 2, 287 .gpio_version = ICH_V7_GPIO, 288 }, 289 [LPC_ICH7DH] = { 290 .name = "ICH7DH", 291 .iTCO_version = 2, 292 .gpio_version = ICH_V7_GPIO, 293 }, 294 [LPC_ICH7M] = { 295 .name = "ICH7-M or ICH7-U", 296 .iTCO_version = 2, 297 .gpio_version = ICH_V7_GPIO, 298 }, 299 [LPC_ICH7MDH] = { 300 .name = "ICH7-M DH", 301 .iTCO_version = 2, 302 .gpio_version = ICH_V7_GPIO, 303 }, 304 [LPC_NM10] = { 305 .name = "NM10", 306 .iTCO_version = 2, 307 .gpio_version = ICH_V7_GPIO, 308 }, 309 [LPC_ICH8] = { 310 .name = "ICH8 or ICH8R", 311 .iTCO_version = 2, 312 .gpio_version = ICH_V7_GPIO, 313 }, 314 [LPC_ICH8DH] = { 315 .name = "ICH8DH", 316 .iTCO_version = 2, 317 .gpio_version = ICH_V7_GPIO, 318 }, 319 [LPC_ICH8DO] = { 320 .name = "ICH8DO", 321 .iTCO_version = 2, 322 .gpio_version = ICH_V7_GPIO, 323 }, 324 [LPC_ICH8M] = { 325 .name = "ICH8M", 326 .iTCO_version = 2, 327 .gpio_version = ICH_V7_GPIO, 328 }, 329 [LPC_ICH8ME] = { 330 .name = "ICH8M-E", 331 .iTCO_version = 2, 332 .gpio_version = ICH_V7_GPIO, 333 }, 334 [LPC_ICH9] = { 335 .name = "ICH9", 336 .iTCO_version = 2, 337 .gpio_version = ICH_V9_GPIO, 338 }, 339 [LPC_ICH9R] = { 340 .name = "ICH9R", 341 .iTCO_version = 2, 342 .gpio_version = ICH_V9_GPIO, 343 }, 344 [LPC_ICH9DH] = { 345 .name = "ICH9DH", 346 .iTCO_version = 2, 347 .gpio_version = ICH_V9_GPIO, 348 }, 349 [LPC_ICH9DO] = { 350 .name = "ICH9DO", 351 .iTCO_version = 2, 352 .gpio_version = ICH_V9_GPIO, 353 }, 354 [LPC_ICH9M] = { 355 .name = "ICH9M", 356 .iTCO_version = 2, 357 .gpio_version = ICH_V9_GPIO, 358 }, 359 [LPC_ICH9ME] = { 360 .name = "ICH9M-E", 361 .iTCO_version = 2, 362 .gpio_version = ICH_V9_GPIO, 363 }, 364 [LPC_ICH10] = { 365 .name = "ICH10", 366 .iTCO_version = 2, 367 .gpio_version = ICH_V10CONS_GPIO, 368 }, 369 [LPC_ICH10R] = { 370 .name = "ICH10R", 371 .iTCO_version = 2, 372 .gpio_version = ICH_V10CONS_GPIO, 373 }, 374 [LPC_ICH10D] = { 375 .name = "ICH10D", 376 .iTCO_version = 2, 377 .gpio_version = ICH_V10CORP_GPIO, 378 }, 379 [LPC_ICH10DO] = { 380 .name = "ICH10DO", 381 .iTCO_version = 2, 382 .gpio_version = ICH_V10CORP_GPIO, 383 }, 384 [LPC_PCH] = { 385 .name = "PCH Desktop Full Featured", 386 .iTCO_version = 2, 387 .gpio_version = ICH_V5_GPIO, 388 }, 389 [LPC_PCHM] = { 390 .name = "PCH Mobile Full Featured", 391 .iTCO_version = 2, 392 .gpio_version = ICH_V5_GPIO, 393 }, 394 [LPC_P55] = { 395 .name = "P55", 396 .iTCO_version = 2, 397 .gpio_version = ICH_V5_GPIO, 398 }, 399 [LPC_PM55] = { 400 .name = "PM55", 401 .iTCO_version = 2, 402 .gpio_version = ICH_V5_GPIO, 403 }, 404 [LPC_H55] = { 405 .name = "H55", 406 .iTCO_version = 2, 407 .gpio_version = ICH_V5_GPIO, 408 }, 409 [LPC_QM57] = { 410 .name = "QM57", 411 .iTCO_version = 2, 412 .gpio_version = ICH_V5_GPIO, 413 }, 414 [LPC_H57] = { 415 .name = "H57", 416 .iTCO_version = 2, 417 .gpio_version = ICH_V5_GPIO, 418 }, 419 [LPC_HM55] = { 420 .name = "HM55", 421 .iTCO_version = 2, 422 .gpio_version = ICH_V5_GPIO, 423 }, 424 [LPC_Q57] = { 425 .name = "Q57", 426 .iTCO_version = 2, 427 .gpio_version = ICH_V5_GPIO, 428 }, 429 [LPC_HM57] = { 430 .name = "HM57", 431 .iTCO_version = 2, 432 .gpio_version = ICH_V5_GPIO, 433 }, 434 [LPC_PCHMSFF] = { 435 .name = "PCH Mobile SFF Full Featured", 436 .iTCO_version = 2, 437 .gpio_version = ICH_V5_GPIO, 438 }, 439 [LPC_QS57] = { 440 .name = "QS57", 441 .iTCO_version = 2, 442 .gpio_version = ICH_V5_GPIO, 443 }, 444 [LPC_3400] = { 445 .name = "3400", 446 .iTCO_version = 2, 447 .gpio_version = ICH_V5_GPIO, 448 }, 449 [LPC_3420] = { 450 .name = "3420", 451 .iTCO_version = 2, 452 .gpio_version = ICH_V5_GPIO, 453 }, 454 [LPC_3450] = { 455 .name = "3450", 456 .iTCO_version = 2, 457 .gpio_version = ICH_V5_GPIO, 458 }, 459 [LPC_EP80579] = { 460 .name = "EP80579", 461 .iTCO_version = 2, 462 }, 463 [LPC_CPT] = { 464 .name = "Cougar Point", 465 .iTCO_version = 2, 466 .gpio_version = ICH_V5_GPIO, 467 }, 468 [LPC_CPTD] = { 469 .name = "Cougar Point Desktop", 470 .iTCO_version = 2, 471 .gpio_version = ICH_V5_GPIO, 472 }, 473 [LPC_CPTM] = { 474 .name = "Cougar Point Mobile", 475 .iTCO_version = 2, 476 .gpio_version = ICH_V5_GPIO, 477 }, 478 [LPC_PBG] = { 479 .name = "Patsburg", 480 .iTCO_version = 2, 481 }, 482 [LPC_DH89XXCC] = { 483 .name = "DH89xxCC", 484 .iTCO_version = 2, 485 }, 486 [LPC_PPT] = { 487 .name = "Panther Point", 488 .iTCO_version = 2, 489 .gpio_version = ICH_V5_GPIO, 490 }, 491 [LPC_LPT] = { 492 .name = "Lynx Point", 493 .iTCO_version = 2, 494 }, 495 [LPC_LPT_LP] = { 496 .name = "Lynx Point_LP", 497 .iTCO_version = 2, 498 }, 499 [LPC_WBG] = { 500 .name = "Wellsburg", 501 .iTCO_version = 2, 502 }, 503 [LPC_AVN] = { 504 .name = "Avoton SoC", 505 .iTCO_version = 3, 506 .gpio_version = AVOTON_GPIO, 507 }, 508 [LPC_BAYTRAIL] = { 509 .name = "Bay Trail SoC", 510 .iTCO_version = 3, 511 }, 512 [LPC_COLETO] = { 513 .name = "Coleto Creek", 514 .iTCO_version = 2, 515 }, 516 [LPC_WPT_LP] = { 517 .name = "Wildcat Point_LP", 518 .iTCO_version = 2, 519 }, 520 [LPC_BRASWELL] = { 521 .name = "Braswell SoC", 522 .iTCO_version = 3, 523 }, 524 [LPC_9S] = { 525 .name = "9 Series", 526 .iTCO_version = 2, 527 }, 528 }; 529 530 /* 531 * This data only exists for exporting the supported PCI ids 532 * via MODULE_DEVICE_TABLE. We do not actually register a 533 * pci_driver, because the I/O Controller Hub has also other 534 * functions that probably will be registered by other drivers. 535 */ 536 static const struct pci_device_id lpc_ich_ids[] = { 537 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, 538 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, 539 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, 540 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, 541 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, 542 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, 543 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, 544 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, 545 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, 546 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, 547 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, 548 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, 549 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, 550 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, 551 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, 552 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, 553 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, 554 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, 555 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, 556 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, 557 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, 558 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, 559 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, 560 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, 561 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, 562 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, 563 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, 564 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, 565 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, 566 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, 567 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, 568 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, 569 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, 570 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, 571 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, 572 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, 573 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, 574 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, 575 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, 576 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, 577 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, 578 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, 579 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, 580 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, 581 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, 582 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, 583 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, 584 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, 585 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, 586 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, 587 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, 588 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, 589 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, 590 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, 591 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, 592 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, 593 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, 594 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, 595 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, 596 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, 597 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, 598 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, 599 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, 600 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, 601 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, 602 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, 603 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, 604 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, 605 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, 606 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, 607 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL}, 608 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, 609 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, 610 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, 611 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, 612 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, 613 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, 614 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, 615 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, 616 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, 617 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, 618 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, 619 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, 620 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, 621 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, 622 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, 623 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, 624 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, 625 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, 626 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, 627 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, 628 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, 629 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, 630 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, 631 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, 632 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, 633 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, 634 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, 635 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, 636 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, 637 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, 638 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, 639 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, 640 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, 641 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, 642 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, 643 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, 644 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, 645 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, 646 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, 647 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, 648 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, 649 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, 650 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, 651 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, 652 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, 653 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, 654 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, 655 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, 656 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, 657 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, 658 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, 659 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, 660 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, 661 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, 662 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, 663 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, 664 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, 665 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, 666 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, 667 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, 668 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, 669 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, 670 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, 671 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, 672 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, 673 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, 674 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, 675 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, 676 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, 677 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, 678 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, 679 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, 680 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, 681 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, 682 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, 683 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, 684 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, 685 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, 686 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, 687 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, 688 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, 689 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, 690 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, 691 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, 692 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, 693 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, 694 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, 695 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, 696 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, 697 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, 698 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, 699 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, 700 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, 701 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, 702 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, 703 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, 704 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, 705 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, 706 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, 707 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, 708 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S}, 709 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S}, 710 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S}, 711 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S}, 712 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S}, 713 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, 714 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, 715 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, 716 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, 717 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, 718 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, 719 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, 720 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, 721 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, 722 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, 723 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, 724 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, 725 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, 726 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, 727 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, 728 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, 729 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, 730 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, 731 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, 732 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, 733 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, 734 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, 735 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, 736 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, 737 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, 738 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, 739 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, 740 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, 741 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, 742 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, 743 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, 744 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, 745 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, 746 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, 747 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, 748 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, 749 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, 750 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, 751 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, 752 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, 753 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, 754 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, 755 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, 756 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, 757 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, 758 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, 759 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, 760 { 0, }, /* End of list */ 761 }; 762 MODULE_DEVICE_TABLE(pci, lpc_ich_ids); 763 764 static void lpc_ich_restore_config_space(struct pci_dev *dev) 765 { 766 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 767 768 if (priv->abase_save >= 0) { 769 pci_write_config_byte(dev, priv->abase, priv->abase_save); 770 priv->abase_save = -1; 771 } 772 773 if (priv->actrl_pbase_save >= 0) { 774 pci_write_config_byte(dev, priv->actrl_pbase, 775 priv->actrl_pbase_save); 776 priv->actrl_pbase_save = -1; 777 } 778 779 if (priv->gctrl_save >= 0) { 780 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); 781 priv->gctrl_save = -1; 782 } 783 } 784 785 static void lpc_ich_enable_acpi_space(struct pci_dev *dev) 786 { 787 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 788 u8 reg_save; 789 790 switch (lpc_chipset_info[priv->chipset].iTCO_version) { 791 case 3: 792 /* 793 * Some chipsets (eg Avoton) enable the ACPI space in the 794 * ACPI BASE register. 795 */ 796 pci_read_config_byte(dev, priv->abase, ®_save); 797 pci_write_config_byte(dev, priv->abase, reg_save | 0x2); 798 priv->abase_save = reg_save; 799 break; 800 default: 801 /* 802 * Most chipsets enable the ACPI space in the ACPI control 803 * register. 804 */ 805 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); 806 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); 807 priv->actrl_pbase_save = reg_save; 808 break; 809 } 810 } 811 812 static void lpc_ich_enable_gpio_space(struct pci_dev *dev) 813 { 814 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 815 u8 reg_save; 816 817 pci_read_config_byte(dev, priv->gctrl, ®_save); 818 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); 819 priv->gctrl_save = reg_save; 820 } 821 822 static void lpc_ich_enable_pmc_space(struct pci_dev *dev) 823 { 824 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 825 u8 reg_save; 826 827 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); 828 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); 829 830 priv->actrl_pbase_save = reg_save; 831 } 832 833 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) 834 { 835 struct itco_wdt_platform_data *pdata; 836 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 837 struct lpc_ich_info *info; 838 struct mfd_cell *cell = &lpc_ich_wdt_cell; 839 840 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); 841 if (!pdata) 842 return -ENOMEM; 843 844 info = &lpc_chipset_info[priv->chipset]; 845 846 pdata->version = info->iTCO_version; 847 strlcpy(pdata->name, info->name, sizeof(pdata->name)); 848 849 cell->platform_data = pdata; 850 cell->pdata_size = sizeof(*pdata); 851 return 0; 852 } 853 854 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) 855 { 856 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 857 struct mfd_cell *cell = &lpc_ich_gpio_cell; 858 859 cell->platform_data = &lpc_chipset_info[priv->chipset]; 860 cell->pdata_size = sizeof(struct lpc_ich_info); 861 } 862 863 /* 864 * We don't check for resource conflict globally. There are 2 or 3 independent 865 * GPIO groups and it's enough to have access to one of these to instantiate 866 * the device. 867 */ 868 static int lpc_ich_check_conflict_gpio(struct resource *res) 869 { 870 int ret; 871 u8 use_gpio = 0; 872 873 if (resource_size(res) >= 0x50 && 874 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) 875 use_gpio |= 1 << 2; 876 877 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) 878 use_gpio |= 1 << 1; 879 880 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); 881 if (!ret) 882 use_gpio |= 1 << 0; 883 884 return use_gpio ? use_gpio : ret; 885 } 886 887 static int lpc_ich_init_gpio(struct pci_dev *dev) 888 { 889 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 890 u32 base_addr_cfg; 891 u32 base_addr; 892 int ret; 893 bool acpi_conflict = false; 894 struct resource *res; 895 896 /* Setup power management base register */ 897 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); 898 base_addr = base_addr_cfg & 0x0000ff80; 899 if (!base_addr) { 900 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 901 lpc_ich_gpio_cell.num_resources--; 902 goto gpe0_done; 903 } 904 905 res = &gpio_ich_res[ICH_RES_GPE0]; 906 res->start = base_addr + ACPIBASE_GPE_OFF; 907 res->end = base_addr + ACPIBASE_GPE_END; 908 ret = acpi_check_resource_conflict(res); 909 if (ret) { 910 /* 911 * This isn't fatal for the GPIO, but we have to make sure that 912 * the platform_device subsystem doesn't see this resource 913 * or it will register an invalid region. 914 */ 915 lpc_ich_gpio_cell.num_resources--; 916 acpi_conflict = true; 917 } else { 918 lpc_ich_enable_acpi_space(dev); 919 } 920 921 gpe0_done: 922 /* Setup GPIO base register */ 923 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); 924 base_addr = base_addr_cfg & 0x0000ff80; 925 if (!base_addr) { 926 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); 927 ret = -ENODEV; 928 goto gpio_done; 929 } 930 931 /* Older devices provide fewer GPIO and have a smaller resource size. */ 932 res = &gpio_ich_res[ICH_RES_GPIO]; 933 res->start = base_addr; 934 switch (lpc_chipset_info[priv->chipset].gpio_version) { 935 case ICH_V5_GPIO: 936 case ICH_V10CORP_GPIO: 937 res->end = res->start + 128 - 1; 938 break; 939 default: 940 res->end = res->start + 64 - 1; 941 break; 942 } 943 944 ret = lpc_ich_check_conflict_gpio(res); 945 if (ret < 0) { 946 /* this isn't necessarily fatal for the GPIO */ 947 acpi_conflict = true; 948 goto gpio_done; 949 } 950 lpc_chipset_info[priv->chipset].use_gpio = ret; 951 lpc_ich_enable_gpio_space(dev); 952 953 lpc_ich_finalize_gpio_cell(dev); 954 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, 955 &lpc_ich_gpio_cell, 1, NULL, 0, NULL); 956 957 gpio_done: 958 if (acpi_conflict) 959 pr_warn("Resource conflict(s) found affecting %s\n", 960 lpc_ich_gpio_cell.name); 961 return ret; 962 } 963 964 static int lpc_ich_init_wdt(struct pci_dev *dev) 965 { 966 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 967 u32 base_addr_cfg; 968 u32 base_addr; 969 int ret; 970 struct resource *res; 971 972 /* Setup power management base register */ 973 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); 974 base_addr = base_addr_cfg & 0x0000ff80; 975 if (!base_addr) { 976 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 977 ret = -ENODEV; 978 goto wdt_done; 979 } 980 981 res = wdt_io_res(ICH_RES_IO_TCO); 982 res->start = base_addr + ACPIBASE_TCO_OFF; 983 res->end = base_addr + ACPIBASE_TCO_END; 984 985 res = wdt_io_res(ICH_RES_IO_SMI); 986 res->start = base_addr + ACPIBASE_SMI_OFF; 987 res->end = base_addr + ACPIBASE_SMI_END; 988 989 lpc_ich_enable_acpi_space(dev); 990 991 /* 992 * iTCO v2: 993 * Get the Memory-Mapped GCS register. To get access to it 994 * we have to read RCBA from PCI Config space 0xf0 and use 995 * it as base. GCS = RCBA + ICH6_GCS(0x3410). 996 * 997 * iTCO v3: 998 * Get the Power Management Configuration register. To get access 999 * to it we have to read the PMC BASE from config space and address 1000 * the register at offset 0x8. 1001 */ 1002 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { 1003 /* Don't register iomem for TCO ver 1 */ 1004 lpc_ich_wdt_cell.num_resources--; 1005 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { 1006 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); 1007 base_addr = base_addr_cfg & 0xffffc000; 1008 if (!(base_addr_cfg & 1)) { 1009 dev_notice(&dev->dev, "RCBA is disabled by " 1010 "hardware/BIOS, device disabled\n"); 1011 ret = -ENODEV; 1012 goto wdt_done; 1013 } 1014 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); 1015 res->start = base_addr + ACPIBASE_GCS_OFF; 1016 res->end = base_addr + ACPIBASE_GCS_END; 1017 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { 1018 lpc_ich_enable_pmc_space(dev); 1019 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); 1020 base_addr = base_addr_cfg & 0xfffffe00; 1021 1022 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); 1023 res->start = base_addr + ACPIBASE_PMC_OFF; 1024 res->end = base_addr + ACPIBASE_PMC_END; 1025 } 1026 1027 ret = lpc_ich_finalize_wdt_cell(dev); 1028 if (ret) 1029 goto wdt_done; 1030 1031 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, 1032 &lpc_ich_wdt_cell, 1, NULL, 0, NULL); 1033 1034 wdt_done: 1035 return ret; 1036 } 1037 1038 static int lpc_ich_probe(struct pci_dev *dev, 1039 const struct pci_device_id *id) 1040 { 1041 struct lpc_ich_priv *priv; 1042 int ret; 1043 bool cell_added = false; 1044 1045 priv = devm_kzalloc(&dev->dev, 1046 sizeof(struct lpc_ich_priv), GFP_KERNEL); 1047 if (!priv) 1048 return -ENOMEM; 1049 1050 priv->chipset = id->driver_data; 1051 1052 priv->actrl_pbase_save = -1; 1053 priv->abase_save = -1; 1054 1055 priv->abase = ACPIBASE; 1056 priv->actrl_pbase = ACPICTRL_PMCBASE; 1057 1058 priv->gctrl_save = -1; 1059 if (priv->chipset <= LPC_ICH5) { 1060 priv->gbase = GPIOBASE_ICH0; 1061 priv->gctrl = GPIOCTRL_ICH0; 1062 } else { 1063 priv->gbase = GPIOBASE_ICH6; 1064 priv->gctrl = GPIOCTRL_ICH6; 1065 } 1066 1067 pci_set_drvdata(dev, priv); 1068 1069 if (lpc_chipset_info[priv->chipset].iTCO_version) { 1070 ret = lpc_ich_init_wdt(dev); 1071 if (!ret) 1072 cell_added = true; 1073 } 1074 1075 if (lpc_chipset_info[priv->chipset].gpio_version) { 1076 ret = lpc_ich_init_gpio(dev); 1077 if (!ret) 1078 cell_added = true; 1079 } 1080 1081 /* 1082 * We only care if at least one or none of the cells registered 1083 * successfully. 1084 */ 1085 if (!cell_added) { 1086 dev_warn(&dev->dev, "No MFD cells added\n"); 1087 lpc_ich_restore_config_space(dev); 1088 return -ENODEV; 1089 } 1090 1091 return 0; 1092 } 1093 1094 static void lpc_ich_remove(struct pci_dev *dev) 1095 { 1096 mfd_remove_devices(&dev->dev); 1097 lpc_ich_restore_config_space(dev); 1098 } 1099 1100 static struct pci_driver lpc_ich_driver = { 1101 .name = "lpc_ich", 1102 .id_table = lpc_ich_ids, 1103 .probe = lpc_ich_probe, 1104 .remove = lpc_ich_remove, 1105 }; 1106 1107 module_pci_driver(lpc_ich_driver); 1108 1109 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); 1110 MODULE_DESCRIPTION("LPC interface for Intel ICH"); 1111 MODULE_LICENSE("GPL"); 1112