1b9a801dfSAndy Shevchenko // SPDX-License-Identifier: GPL-2.0
2b9a801dfSAndy Shevchenko /*
3b9a801dfSAndy Shevchenko * Device access for Basin Cove PMIC
4b9a801dfSAndy Shevchenko *
5b9a801dfSAndy Shevchenko * Copyright (c) 2019, Intel Corporation.
6b9a801dfSAndy Shevchenko * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7b9a801dfSAndy Shevchenko */
8b9a801dfSAndy Shevchenko
9b9a801dfSAndy Shevchenko #include <linux/acpi.h>
10b9a801dfSAndy Shevchenko #include <linux/interrupt.h>
11b9a801dfSAndy Shevchenko #include <linux/mfd/core.h>
12b9a801dfSAndy Shevchenko #include <linux/mfd/intel_soc_pmic.h>
13b9a801dfSAndy Shevchenko #include <linux/mfd/intel_soc_pmic_mrfld.h>
14b9a801dfSAndy Shevchenko #include <linux/module.h>
15b9a801dfSAndy Shevchenko #include <linux/platform_device.h>
16b9a801dfSAndy Shevchenko #include <linux/regmap.h>
17b9a801dfSAndy Shevchenko
18b9a801dfSAndy Shevchenko #include <asm/intel_scu_ipc.h>
19b9a801dfSAndy Shevchenko
20b9a801dfSAndy Shevchenko /*
21b9a801dfSAndy Shevchenko * Level 2 IRQs
22b9a801dfSAndy Shevchenko *
23b9a801dfSAndy Shevchenko * Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
24b9a801dfSAndy Shevchenko * without an assistance. Thus, each of the Level 1 IRQ is represented
25b9a801dfSAndy Shevchenko * as a separate RTE in IOAPIC.
26b9a801dfSAndy Shevchenko */
27b9a801dfSAndy Shevchenko static struct resource irq_level2_resources[] = {
28b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* power button */
29b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* TMU */
30b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* thermal */
31b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* BCU */
32b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* ADC */
33b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* charger */
34b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* GPIO */
35b9a801dfSAndy Shevchenko };
36b9a801dfSAndy Shevchenko
37b9a801dfSAndy Shevchenko static const struct mfd_cell bcove_dev[] = {
38b9a801dfSAndy Shevchenko {
39b9a801dfSAndy Shevchenko .name = "mrfld_bcove_pwrbtn",
40b9a801dfSAndy Shevchenko .num_resources = 1,
41b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[0],
42b9a801dfSAndy Shevchenko }, {
43b9a801dfSAndy Shevchenko .name = "mrfld_bcove_tmu",
44b9a801dfSAndy Shevchenko .num_resources = 1,
45b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[1],
46b9a801dfSAndy Shevchenko }, {
47b9a801dfSAndy Shevchenko .name = "mrfld_bcove_thermal",
48b9a801dfSAndy Shevchenko .num_resources = 1,
49b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[2],
50b9a801dfSAndy Shevchenko }, {
51b9a801dfSAndy Shevchenko .name = "mrfld_bcove_bcu",
52b9a801dfSAndy Shevchenko .num_resources = 1,
53b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[3],
54b9a801dfSAndy Shevchenko }, {
55b9a801dfSAndy Shevchenko .name = "mrfld_bcove_adc",
56b9a801dfSAndy Shevchenko .num_resources = 1,
57b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[4],
58b9a801dfSAndy Shevchenko }, {
59b9a801dfSAndy Shevchenko .name = "mrfld_bcove_charger",
60b9a801dfSAndy Shevchenko .num_resources = 1,
61b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[5],
62b9a801dfSAndy Shevchenko }, {
63b9a801dfSAndy Shevchenko .name = "mrfld_bcove_pwrsrc",
64b9a801dfSAndy Shevchenko .num_resources = 1,
65b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[5],
66b9a801dfSAndy Shevchenko }, {
67b9a801dfSAndy Shevchenko .name = "mrfld_bcove_gpio",
68b9a801dfSAndy Shevchenko .num_resources = 1,
69b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[6],
70b9a801dfSAndy Shevchenko },
71b9a801dfSAndy Shevchenko { .name = "mrfld_bcove_region", },
72b9a801dfSAndy Shevchenko };
73b9a801dfSAndy Shevchenko
bcove_ipc_byte_reg_read(void * context,unsigned int reg,unsigned int * val)74b9a801dfSAndy Shevchenko static int bcove_ipc_byte_reg_read(void *context, unsigned int reg,
75b9a801dfSAndy Shevchenko unsigned int *val)
76b9a801dfSAndy Shevchenko {
7750362083SMika Westerberg struct intel_soc_pmic *pmic = context;
78b9a801dfSAndy Shevchenko u8 ipc_out;
79b9a801dfSAndy Shevchenko int ret;
80b9a801dfSAndy Shevchenko
8150362083SMika Westerberg ret = intel_scu_ipc_dev_ioread8(pmic->scu, reg, &ipc_out);
82b9a801dfSAndy Shevchenko if (ret)
83b9a801dfSAndy Shevchenko return ret;
84b9a801dfSAndy Shevchenko
85b9a801dfSAndy Shevchenko *val = ipc_out;
86b9a801dfSAndy Shevchenko return 0;
87b9a801dfSAndy Shevchenko }
88b9a801dfSAndy Shevchenko
bcove_ipc_byte_reg_write(void * context,unsigned int reg,unsigned int val)89b9a801dfSAndy Shevchenko static int bcove_ipc_byte_reg_write(void *context, unsigned int reg,
90b9a801dfSAndy Shevchenko unsigned int val)
91b9a801dfSAndy Shevchenko {
9250362083SMika Westerberg struct intel_soc_pmic *pmic = context;
93b9a801dfSAndy Shevchenko u8 ipc_in = val;
94b9a801dfSAndy Shevchenko
954ee1d9dcSXu Wang return intel_scu_ipc_dev_iowrite8(pmic->scu, reg, ipc_in);
96b9a801dfSAndy Shevchenko }
97b9a801dfSAndy Shevchenko
98b9a801dfSAndy Shevchenko static const struct regmap_config bcove_regmap_config = {
99b9a801dfSAndy Shevchenko .reg_bits = 16,
100b9a801dfSAndy Shevchenko .val_bits = 8,
101b9a801dfSAndy Shevchenko .max_register = 0xff,
102b9a801dfSAndy Shevchenko .reg_write = bcove_ipc_byte_reg_write,
103b9a801dfSAndy Shevchenko .reg_read = bcove_ipc_byte_reg_read,
104b9a801dfSAndy Shevchenko };
105b9a801dfSAndy Shevchenko
bcove_probe(struct platform_device * pdev)106b9a801dfSAndy Shevchenko static int bcove_probe(struct platform_device *pdev)
107b9a801dfSAndy Shevchenko {
108b9a801dfSAndy Shevchenko struct device *dev = &pdev->dev;
109b9a801dfSAndy Shevchenko struct intel_soc_pmic *pmic;
110b9a801dfSAndy Shevchenko unsigned int i;
111b9a801dfSAndy Shevchenko int ret;
112b9a801dfSAndy Shevchenko
113b9a801dfSAndy Shevchenko pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
114b9a801dfSAndy Shevchenko if (!pmic)
115b9a801dfSAndy Shevchenko return -ENOMEM;
116b9a801dfSAndy Shevchenko
11750362083SMika Westerberg pmic->scu = devm_intel_scu_ipc_dev_get(dev);
11850362083SMika Westerberg if (!pmic->scu)
11950362083SMika Westerberg return -ENOMEM;
12050362083SMika Westerberg
121b9a801dfSAndy Shevchenko platform_set_drvdata(pdev, pmic);
122b9a801dfSAndy Shevchenko pmic->dev = &pdev->dev;
123b9a801dfSAndy Shevchenko
124b9a801dfSAndy Shevchenko pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bcove_regmap_config);
125b9a801dfSAndy Shevchenko if (IS_ERR(pmic->regmap))
126b9a801dfSAndy Shevchenko return PTR_ERR(pmic->regmap);
127b9a801dfSAndy Shevchenko
128b9a801dfSAndy Shevchenko for (i = 0; i < ARRAY_SIZE(irq_level2_resources); i++) {
129b9a801dfSAndy Shevchenko ret = platform_get_irq(pdev, i);
130b9a801dfSAndy Shevchenko if (ret < 0)
131b9a801dfSAndy Shevchenko return ret;
132b9a801dfSAndy Shevchenko
133b9a801dfSAndy Shevchenko irq_level2_resources[i].start = ret;
134b9a801dfSAndy Shevchenko irq_level2_resources[i].end = ret;
135b9a801dfSAndy Shevchenko }
136b9a801dfSAndy Shevchenko
137b9a801dfSAndy Shevchenko return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
138b9a801dfSAndy Shevchenko bcove_dev, ARRAY_SIZE(bcove_dev),
139b9a801dfSAndy Shevchenko NULL, 0, NULL);
140b9a801dfSAndy Shevchenko }
141b9a801dfSAndy Shevchenko
142b9a801dfSAndy Shevchenko static const struct acpi_device_id bcove_acpi_ids[] = {
143b9a801dfSAndy Shevchenko { "INTC100E" },
144b9a801dfSAndy Shevchenko {}
145b9a801dfSAndy Shevchenko };
146b9a801dfSAndy Shevchenko MODULE_DEVICE_TABLE(acpi, bcove_acpi_ids);
147b9a801dfSAndy Shevchenko
148b9a801dfSAndy Shevchenko static struct platform_driver bcove_driver = {
149b9a801dfSAndy Shevchenko .driver = {
150b9a801dfSAndy Shevchenko .name = "intel_soc_pmic_mrfld",
151b9a801dfSAndy Shevchenko .acpi_match_table = bcove_acpi_ids,
152b9a801dfSAndy Shevchenko },
153b9a801dfSAndy Shevchenko .probe = bcove_probe,
154b9a801dfSAndy Shevchenko };
155b9a801dfSAndy Shevchenko module_platform_driver(bcove_driver);
156b9a801dfSAndy Shevchenko
157b9a801dfSAndy Shevchenko MODULE_DESCRIPTION("IPC driver for Intel SoC Basin Cove PMIC");
158b9a801dfSAndy Shevchenko MODULE_LICENSE("GPL v2");
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