1 /* 2 * MFD core driver for Intel Broxton Whiskey Cove PMIC 3 * 4 * Copyright (C) 2015 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/acpi.h> 18 #include <linux/err.h> 19 #include <linux/delay.h> 20 #include <linux/interrupt.h> 21 #include <linux/kernel.h> 22 #include <linux/mfd/core.h> 23 #include <linux/mfd/intel_bxtwc.h> 24 #include <asm/intel_pmc_ipc.h> 25 26 /* PMIC device registers */ 27 #define REG_ADDR_MASK 0xFF00 28 #define REG_ADDR_SHIFT 8 29 #define REG_OFFSET_MASK 0xFF 30 31 /* Interrupt Status Registers */ 32 #define BXTWC_IRQLVL1 0x4E02 33 #define BXTWC_PWRBTNIRQ 0x4E03 34 35 #define BXTWC_THRM0IRQ 0x4E04 36 #define BXTWC_THRM1IRQ 0x4E05 37 #define BXTWC_THRM2IRQ 0x4E06 38 #define BXTWC_BCUIRQ 0x4E07 39 #define BXTWC_ADCIRQ 0x4E08 40 #define BXTWC_CHGR0IRQ 0x4E09 41 #define BXTWC_CHGR1IRQ 0x4E0A 42 #define BXTWC_GPIOIRQ0 0x4E0B 43 #define BXTWC_GPIOIRQ1 0x4E0C 44 #define BXTWC_CRITIRQ 0x4E0D 45 46 /* Interrupt MASK Registers */ 47 #define BXTWC_MIRQLVL1 0x4E0E 48 #define BXTWC_MPWRTNIRQ 0x4E0F 49 50 #define BXTWC_MIRQLVL1_MCHGR BIT(5) 51 52 #define BXTWC_MTHRM0IRQ 0x4E12 53 #define BXTWC_MTHRM1IRQ 0x4E13 54 #define BXTWC_MTHRM2IRQ 0x4E14 55 #define BXTWC_MBCUIRQ 0x4E15 56 #define BXTWC_MADCIRQ 0x4E16 57 #define BXTWC_MCHGR0IRQ 0x4E17 58 #define BXTWC_MCHGR1IRQ 0x4E18 59 #define BXTWC_MGPIO0IRQ 0x4E19 60 #define BXTWC_MGPIO1IRQ 0x4E1A 61 #define BXTWC_MCRITIRQ 0x4E1B 62 63 /* Whiskey Cove PMIC share same ACPI ID between different platforms */ 64 #define BROXTON_PMIC_WC_HRV 4 65 66 /* Manage in two IRQ chips since mask registers are not consecutive */ 67 enum bxtwc_irqs { 68 /* Level 1 */ 69 BXTWC_PWRBTN_LVL1_IRQ = 0, 70 BXTWC_TMU_LVL1_IRQ, 71 BXTWC_THRM_LVL1_IRQ, 72 BXTWC_BCU_LVL1_IRQ, 73 BXTWC_ADC_LVL1_IRQ, 74 BXTWC_CHGR_LVL1_IRQ, 75 BXTWC_GPIO_LVL1_IRQ, 76 BXTWC_CRIT_LVL1_IRQ, 77 78 /* Level 2 */ 79 BXTWC_PWRBTN_IRQ, 80 }; 81 82 enum bxtwc_irqs_level2 { 83 /* Level 2 */ 84 BXTWC_THRM0_IRQ = 0, 85 BXTWC_THRM1_IRQ, 86 BXTWC_THRM2_IRQ, 87 BXTWC_BCU_IRQ, 88 BXTWC_ADC_IRQ, 89 BXTWC_USBC_IRQ, 90 BXTWC_CHGR0_IRQ, 91 BXTWC_CHGR1_IRQ, 92 BXTWC_GPIO0_IRQ, 93 BXTWC_GPIO1_IRQ, 94 BXTWC_CRIT_IRQ, 95 }; 96 97 static const struct regmap_irq bxtwc_regmap_irqs[] = { 98 REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)), 99 REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)), 100 REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)), 101 REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)), 102 REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)), 103 REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)), 104 REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)), 105 REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)), 106 REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03), 107 }; 108 109 static const struct regmap_irq bxtwc_regmap_irqs_level2[] = { 110 REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff), 111 REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf), 112 REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff), 113 REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f), 114 REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff), 115 REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)), 116 REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f), 117 REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f), 118 REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff), 119 REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f), 120 REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03), 121 }; 122 123 static struct regmap_irq_chip bxtwc_regmap_irq_chip = { 124 .name = "bxtwc_irq_chip", 125 .status_base = BXTWC_IRQLVL1, 126 .mask_base = BXTWC_MIRQLVL1, 127 .irqs = bxtwc_regmap_irqs, 128 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs), 129 .num_regs = 2, 130 }; 131 132 static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = { 133 .name = "bxtwc_irq_chip_level2", 134 .status_base = BXTWC_THRM0IRQ, 135 .mask_base = BXTWC_MTHRM0IRQ, 136 .irqs = bxtwc_regmap_irqs_level2, 137 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2), 138 .num_regs = 10, 139 }; 140 141 static struct resource gpio_resources[] = { 142 DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"), 143 DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"), 144 }; 145 146 static struct resource adc_resources[] = { 147 DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"), 148 }; 149 150 static struct resource usbc_resources[] = { 151 DEFINE_RES_IRQ(BXTWC_USBC_IRQ), 152 }; 153 154 static struct resource charger_resources[] = { 155 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"), 156 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"), 157 }; 158 159 static struct resource thermal_resources[] = { 160 DEFINE_RES_IRQ(BXTWC_THRM0_IRQ), 161 DEFINE_RES_IRQ(BXTWC_THRM1_IRQ), 162 DEFINE_RES_IRQ(BXTWC_THRM2_IRQ), 163 }; 164 165 static struct resource bcu_resources[] = { 166 DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"), 167 }; 168 169 static struct mfd_cell bxt_wc_dev[] = { 170 { 171 .name = "bxt_wcove_gpadc", 172 .num_resources = ARRAY_SIZE(adc_resources), 173 .resources = adc_resources, 174 }, 175 { 176 .name = "bxt_wcove_thermal", 177 .num_resources = ARRAY_SIZE(thermal_resources), 178 .resources = thermal_resources, 179 }, 180 { 181 .name = "bxt_wcove_usbc", 182 .num_resources = ARRAY_SIZE(usbc_resources), 183 .resources = usbc_resources, 184 }, 185 { 186 .name = "bxt_wcove_ext_charger", 187 .num_resources = ARRAY_SIZE(charger_resources), 188 .resources = charger_resources, 189 }, 190 { 191 .name = "bxt_wcove_bcu", 192 .num_resources = ARRAY_SIZE(bcu_resources), 193 .resources = bcu_resources, 194 }, 195 { 196 .name = "bxt_wcove_gpio", 197 .num_resources = ARRAY_SIZE(gpio_resources), 198 .resources = gpio_resources, 199 }, 200 { 201 .name = "bxt_wcove_region", 202 }, 203 }; 204 205 static int regmap_ipc_byte_reg_read(void *context, unsigned int reg, 206 unsigned int *val) 207 { 208 int ret; 209 int i2c_addr; 210 u8 ipc_in[2]; 211 u8 ipc_out[4]; 212 struct intel_soc_pmic *pmic = context; 213 214 if (reg & REG_ADDR_MASK) 215 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; 216 else { 217 i2c_addr = BXTWC_DEVICE1_ADDR; 218 if (!i2c_addr) { 219 dev_err(pmic->dev, "I2C address not set\n"); 220 return -EINVAL; 221 } 222 } 223 reg &= REG_OFFSET_MASK; 224 225 ipc_in[0] = reg; 226 ipc_in[1] = i2c_addr; 227 ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS, 228 PMC_IPC_PMIC_ACCESS_READ, 229 ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1); 230 if (ret) { 231 dev_err(pmic->dev, "Failed to read from PMIC\n"); 232 return ret; 233 } 234 *val = ipc_out[0]; 235 236 return 0; 237 } 238 239 static int regmap_ipc_byte_reg_write(void *context, unsigned int reg, 240 unsigned int val) 241 { 242 int ret; 243 int i2c_addr; 244 u8 ipc_in[3]; 245 struct intel_soc_pmic *pmic = context; 246 247 if (reg & REG_ADDR_MASK) 248 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; 249 else { 250 i2c_addr = BXTWC_DEVICE1_ADDR; 251 if (!i2c_addr) { 252 dev_err(pmic->dev, "I2C address not set\n"); 253 return -EINVAL; 254 } 255 } 256 reg &= REG_OFFSET_MASK; 257 258 ipc_in[0] = reg; 259 ipc_in[1] = i2c_addr; 260 ipc_in[2] = val; 261 ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS, 262 PMC_IPC_PMIC_ACCESS_WRITE, 263 ipc_in, sizeof(ipc_in), NULL, 0); 264 if (ret) { 265 dev_err(pmic->dev, "Failed to write to PMIC\n"); 266 return ret; 267 } 268 269 return 0; 270 } 271 272 /* sysfs interfaces to r/w PMIC registers, required by initial script */ 273 static unsigned long bxtwc_reg_addr; 274 static ssize_t bxtwc_reg_show(struct device *dev, 275 struct device_attribute *attr, char *buf) 276 { 277 return sprintf(buf, "0x%lx\n", bxtwc_reg_addr); 278 } 279 280 static ssize_t bxtwc_reg_store(struct device *dev, 281 struct device_attribute *attr, const char *buf, size_t count) 282 { 283 if (kstrtoul(buf, 0, &bxtwc_reg_addr)) { 284 dev_err(dev, "Invalid register address\n"); 285 return -EINVAL; 286 } 287 return (ssize_t)count; 288 } 289 290 static ssize_t bxtwc_val_show(struct device *dev, 291 struct device_attribute *attr, char *buf) 292 { 293 int ret; 294 unsigned int val; 295 struct intel_soc_pmic *pmic = dev_get_drvdata(dev); 296 297 ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val); 298 if (ret < 0) { 299 dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr); 300 return -EIO; 301 } 302 303 return sprintf(buf, "0x%02x\n", val); 304 } 305 306 static ssize_t bxtwc_val_store(struct device *dev, 307 struct device_attribute *attr, const char *buf, size_t count) 308 { 309 int ret; 310 unsigned int val; 311 struct intel_soc_pmic *pmic = dev_get_drvdata(dev); 312 313 ret = kstrtouint(buf, 0, &val); 314 if (ret) 315 return ret; 316 317 ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val); 318 if (ret) { 319 dev_err(dev, "Failed to write value 0x%02x to address 0x%lx", 320 val, bxtwc_reg_addr); 321 return -EIO; 322 } 323 return count; 324 } 325 326 static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store); 327 static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store); 328 static struct attribute *bxtwc_attrs[] = { 329 &dev_attr_addr.attr, 330 &dev_attr_val.attr, 331 NULL 332 }; 333 334 static const struct attribute_group bxtwc_group = { 335 .attrs = bxtwc_attrs, 336 }; 337 338 static const struct regmap_config bxtwc_regmap_config = { 339 .reg_bits = 16, 340 .val_bits = 8, 341 .reg_write = regmap_ipc_byte_reg_write, 342 .reg_read = regmap_ipc_byte_reg_read, 343 }; 344 345 static int bxtwc_probe(struct platform_device *pdev) 346 { 347 int ret; 348 acpi_handle handle; 349 acpi_status status; 350 unsigned long long hrv; 351 struct intel_soc_pmic *pmic; 352 353 handle = ACPI_HANDLE(&pdev->dev); 354 status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv); 355 if (ACPI_FAILURE(status)) { 356 dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n"); 357 return -ENODEV; 358 } 359 if (hrv != BROXTON_PMIC_WC_HRV) { 360 dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n", 361 hrv); 362 return -ENODEV; 363 } 364 365 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); 366 if (!pmic) 367 return -ENOMEM; 368 369 ret = platform_get_irq(pdev, 0); 370 if (ret < 0) { 371 dev_err(&pdev->dev, "Invalid IRQ\n"); 372 return ret; 373 } 374 pmic->irq = ret; 375 376 dev_set_drvdata(&pdev->dev, pmic); 377 pmic->dev = &pdev->dev; 378 379 pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic, 380 &bxtwc_regmap_config); 381 if (IS_ERR(pmic->regmap)) { 382 ret = PTR_ERR(pmic->regmap); 383 dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret); 384 return ret; 385 } 386 387 ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, 388 IRQF_ONESHOT | IRQF_SHARED, 389 0, &bxtwc_regmap_irq_chip, 390 &pmic->irq_chip_data); 391 if (ret) { 392 dev_err(&pdev->dev, "Failed to add IRQ chip\n"); 393 return ret; 394 } 395 396 ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, 397 IRQF_ONESHOT | IRQF_SHARED, 398 0, &bxtwc_regmap_irq_chip_level2, 399 &pmic->irq_chip_data_level2); 400 if (ret) { 401 dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n"); 402 goto err_irq_chip_level2; 403 } 404 405 ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev, 406 ARRAY_SIZE(bxt_wc_dev), NULL, 0, 407 NULL); 408 if (ret) { 409 dev_err(&pdev->dev, "Failed to add devices\n"); 410 goto err_mfd; 411 } 412 413 ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group); 414 if (ret) { 415 dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret); 416 goto err_sysfs; 417 } 418 419 /* 420 * There is known hw bug. Upon reset BIT 5 of register 421 * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However, 422 * later it's set to 1(masked) automatically by hardware. So we 423 * have the software workaround here to unmaksed it in order to let 424 * charger interrutp work. 425 */ 426 regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, 427 BXTWC_MIRQLVL1_MCHGR, 0); 428 429 return 0; 430 431 err_sysfs: 432 mfd_remove_devices(&pdev->dev); 433 err_mfd: 434 regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2); 435 err_irq_chip_level2: 436 regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data); 437 438 return ret; 439 } 440 441 static int bxtwc_remove(struct platform_device *pdev) 442 { 443 struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev); 444 445 sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group); 446 mfd_remove_devices(&pdev->dev); 447 regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data); 448 regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2); 449 450 return 0; 451 } 452 453 static void bxtwc_shutdown(struct platform_device *pdev) 454 { 455 struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev); 456 457 disable_irq(pmic->irq); 458 } 459 460 #ifdef CONFIG_PM_SLEEP 461 static int bxtwc_suspend(struct device *dev) 462 { 463 struct intel_soc_pmic *pmic = dev_get_drvdata(dev); 464 465 disable_irq(pmic->irq); 466 467 return 0; 468 } 469 470 static int bxtwc_resume(struct device *dev) 471 { 472 struct intel_soc_pmic *pmic = dev_get_drvdata(dev); 473 474 enable_irq(pmic->irq); 475 return 0; 476 } 477 #endif 478 static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume); 479 480 static const struct acpi_device_id bxtwc_acpi_ids[] = { 481 { "INT34D3", }, 482 { } 483 }; 484 MODULE_DEVICE_TABLE(acpi, pmic_acpi_ids); 485 486 static struct platform_driver bxtwc_driver = { 487 .probe = bxtwc_probe, 488 .remove = bxtwc_remove, 489 .shutdown = bxtwc_shutdown, 490 .driver = { 491 .name = "BXTWC PMIC", 492 .pm = &bxtwc_pm_ops, 493 .acpi_match_table = ACPI_PTR(bxtwc_acpi_ids), 494 }, 495 }; 496 497 module_platform_driver(bxtwc_driver); 498 499 MODULE_LICENSE("GPL v2"); 500 MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>"); 501