1 /* 2 * Intel Sunrisepoint LPSS core support. 3 * 4 * Copyright (C) 2015, Intel Corporation 5 * 6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 * Heikki Krogerus <heikki.krogerus@linux.intel.com> 9 * Jarkko Nikula <jarkko.nikula@linux.intel.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk-provider.h> 19 #include <linux/debugfs.h> 20 #include <linux/idr.h> 21 #include <linux/io.h> 22 #include <linux/ioport.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/mfd/core.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/property.h> 29 #include <linux/seq_file.h> 30 #include <linux/io-64-nonatomic-lo-hi.h> 31 32 #include <linux/dma/idma64.h> 33 34 #include "intel-lpss.h" 35 36 #define LPSS_DEV_OFFSET 0x000 37 #define LPSS_DEV_SIZE 0x200 38 #define LPSS_PRIV_OFFSET 0x200 39 #define LPSS_PRIV_SIZE 0x100 40 #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4) 41 #define LPSS_IDMA64_OFFSET 0x800 42 #define LPSS_IDMA64_SIZE 0x800 43 44 /* Offsets from lpss->priv */ 45 #define LPSS_PRIV_RESETS 0x04 46 #define LPSS_PRIV_RESETS_IDMA BIT(2) 47 #define LPSS_PRIV_RESETS_FUNC 0x3 48 49 #define LPSS_PRIV_ACTIVELTR 0x10 50 #define LPSS_PRIV_IDLELTR 0x14 51 52 #define LPSS_PRIV_LTR_REQ BIT(15) 53 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00 54 #define LPSS_PRIV_LTR_SCALE_1US 0x800 55 #define LPSS_PRIV_LTR_SCALE_32US 0xc00 56 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff 57 58 #define LPSS_PRIV_SSP_REG 0x20 59 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0) 60 61 #define LPSS_PRIV_REMAP_ADDR 0x40 62 63 #define LPSS_PRIV_CAPS 0xfc 64 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8) 65 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4 66 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT) 67 68 /* This matches the type field in CAPS register */ 69 enum intel_lpss_dev_type { 70 LPSS_DEV_I2C = 0, 71 LPSS_DEV_UART, 72 LPSS_DEV_SPI, 73 }; 74 75 struct intel_lpss { 76 const struct intel_lpss_platform_info *info; 77 enum intel_lpss_dev_type type; 78 struct clk *clk; 79 struct clk_lookup *clock; 80 struct mfd_cell *cell; 81 struct device *dev; 82 void __iomem *priv; 83 u32 priv_ctx[LPSS_PRIV_REG_COUNT]; 84 int devid; 85 u32 caps; 86 u32 active_ltr; 87 u32 idle_ltr; 88 struct dentry *debugfs; 89 }; 90 91 static const struct resource intel_lpss_dev_resources[] = { 92 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"), 93 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"), 94 DEFINE_RES_IRQ(0), 95 }; 96 97 static const struct resource intel_lpss_idma64_resources[] = { 98 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE), 99 DEFINE_RES_IRQ(0), 100 }; 101 102 /* 103 * Cells needs to be ordered so that the iDMA is created first. This is 104 * because we need to be sure the DMA is available when the host controller 105 * driver is probed. 106 */ 107 static const struct mfd_cell intel_lpss_idma64_cell = { 108 .name = LPSS_IDMA64_DRIVER_NAME, 109 .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources), 110 .resources = intel_lpss_idma64_resources, 111 }; 112 113 static const struct mfd_cell intel_lpss_i2c_cell = { 114 .name = "i2c_designware", 115 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), 116 .resources = intel_lpss_dev_resources, 117 }; 118 119 static const struct mfd_cell intel_lpss_uart_cell = { 120 .name = "dw-apb-uart", 121 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), 122 .resources = intel_lpss_dev_resources, 123 }; 124 125 static const struct mfd_cell intel_lpss_spi_cell = { 126 .name = "pxa2xx-spi", 127 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), 128 .resources = intel_lpss_dev_resources, 129 }; 130 131 static DEFINE_IDA(intel_lpss_devid_ida); 132 static struct dentry *intel_lpss_debugfs; 133 134 static int intel_lpss_request_dma_module(const char *name) 135 { 136 static bool intel_lpss_dma_requested; 137 138 if (intel_lpss_dma_requested) 139 return 0; 140 141 intel_lpss_dma_requested = true; 142 return request_module("%s", name); 143 } 144 145 static void intel_lpss_cache_ltr(struct intel_lpss *lpss) 146 { 147 lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR); 148 lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR); 149 } 150 151 static int intel_lpss_debugfs_add(struct intel_lpss *lpss) 152 { 153 struct dentry *dir; 154 155 dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs); 156 if (IS_ERR(dir)) 157 return PTR_ERR(dir); 158 159 /* Cache the values into lpss structure */ 160 intel_lpss_cache_ltr(lpss); 161 162 debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps); 163 debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr); 164 debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr); 165 166 lpss->debugfs = dir; 167 return 0; 168 } 169 170 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss) 171 { 172 debugfs_remove_recursive(lpss->debugfs); 173 } 174 175 static void intel_lpss_ltr_set(struct device *dev, s32 val) 176 { 177 struct intel_lpss *lpss = dev_get_drvdata(dev); 178 u32 ltr; 179 180 /* 181 * Program latency tolerance (LTR) accordingly what has been asked 182 * by the PM QoS layer or disable it in case we were passed 183 * negative value or PM_QOS_LATENCY_ANY. 184 */ 185 ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR); 186 187 if (val == PM_QOS_LATENCY_ANY || val < 0) { 188 ltr &= ~LPSS_PRIV_LTR_REQ; 189 } else { 190 ltr |= LPSS_PRIV_LTR_REQ; 191 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK; 192 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK; 193 194 if (val > LPSS_PRIV_LTR_VALUE_MASK) 195 ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5; 196 else 197 ltr |= LPSS_PRIV_LTR_SCALE_1US | val; 198 } 199 200 if (ltr == lpss->active_ltr) 201 return; 202 203 writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR); 204 writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR); 205 206 /* Cache the values into lpss structure */ 207 intel_lpss_cache_ltr(lpss); 208 } 209 210 static void intel_lpss_ltr_expose(struct intel_lpss *lpss) 211 { 212 lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set; 213 dev_pm_qos_expose_latency_tolerance(lpss->dev); 214 } 215 216 static void intel_lpss_ltr_hide(struct intel_lpss *lpss) 217 { 218 dev_pm_qos_hide_latency_tolerance(lpss->dev); 219 lpss->dev->power.set_latency_tolerance = NULL; 220 } 221 222 static int intel_lpss_assign_devs(struct intel_lpss *lpss) 223 { 224 const struct mfd_cell *cell; 225 unsigned int type; 226 227 type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK; 228 type >>= LPSS_PRIV_CAPS_TYPE_SHIFT; 229 230 switch (type) { 231 case LPSS_DEV_I2C: 232 cell = &intel_lpss_i2c_cell; 233 break; 234 case LPSS_DEV_UART: 235 cell = &intel_lpss_uart_cell; 236 break; 237 case LPSS_DEV_SPI: 238 cell = &intel_lpss_spi_cell; 239 break; 240 default: 241 return -ENODEV; 242 } 243 244 lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL); 245 if (!lpss->cell) 246 return -ENOMEM; 247 248 lpss->type = type; 249 250 return 0; 251 } 252 253 static bool intel_lpss_has_idma(const struct intel_lpss *lpss) 254 { 255 return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0; 256 } 257 258 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss) 259 { 260 resource_size_t addr = lpss->info->mem->start; 261 262 lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR); 263 } 264 265 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss) 266 { 267 u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA; 268 269 /* Bring out the device from reset */ 270 writel(value, lpss->priv + LPSS_PRIV_RESETS); 271 } 272 273 static void intel_lpss_init_dev(const struct intel_lpss *lpss) 274 { 275 u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN; 276 277 /* Set the device in reset state */ 278 writel(0, lpss->priv + LPSS_PRIV_RESETS); 279 280 intel_lpss_deassert_reset(lpss); 281 282 intel_lpss_set_remap_addr(lpss); 283 284 if (!intel_lpss_has_idma(lpss)) 285 return; 286 287 /* Make sure that SPI multiblock DMA transfers are re-enabled */ 288 if (lpss->type == LPSS_DEV_SPI) 289 writel(value, lpss->priv + LPSS_PRIV_SSP_REG); 290 } 291 292 static void intel_lpss_unregister_clock_tree(struct clk *clk) 293 { 294 struct clk *parent; 295 296 while (clk) { 297 parent = clk_get_parent(clk); 298 clk_unregister(clk); 299 clk = parent; 300 } 301 } 302 303 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss, 304 const char *devname, 305 struct clk **clk) 306 { 307 char name[32]; 308 struct clk *tmp = *clk; 309 310 snprintf(name, sizeof(name), "%s-enable", devname); 311 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0, 312 lpss->priv, 0, 0, NULL); 313 if (IS_ERR(tmp)) 314 return PTR_ERR(tmp); 315 316 snprintf(name, sizeof(name), "%s-div", devname); 317 tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp), 318 0, lpss->priv, 1, 15, 16, 15, 0, 319 NULL); 320 if (IS_ERR(tmp)) 321 return PTR_ERR(tmp); 322 *clk = tmp; 323 324 snprintf(name, sizeof(name), "%s-update", devname); 325 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 326 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL); 327 if (IS_ERR(tmp)) 328 return PTR_ERR(tmp); 329 *clk = tmp; 330 331 return 0; 332 } 333 334 static int intel_lpss_register_clock(struct intel_lpss *lpss) 335 { 336 const struct mfd_cell *cell = lpss->cell; 337 struct clk *clk; 338 char devname[24]; 339 int ret; 340 341 if (!lpss->info->clk_rate) 342 return 0; 343 344 /* Root clock */ 345 clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0, 346 lpss->info->clk_rate); 347 if (IS_ERR(clk)) 348 return PTR_ERR(clk); 349 350 snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid); 351 352 /* 353 * Support for clock divider only if it has some preset value. 354 * Otherwise we assume that the divider is not used. 355 */ 356 if (lpss->type != LPSS_DEV_I2C) { 357 ret = intel_lpss_register_clock_divider(lpss, devname, &clk); 358 if (ret) 359 goto err_clk_register; 360 } 361 362 ret = -ENOMEM; 363 364 /* Clock for the host controller */ 365 lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname); 366 if (!lpss->clock) 367 goto err_clk_register; 368 369 lpss->clk = clk; 370 371 return 0; 372 373 err_clk_register: 374 intel_lpss_unregister_clock_tree(clk); 375 376 return ret; 377 } 378 379 static void intel_lpss_unregister_clock(struct intel_lpss *lpss) 380 { 381 if (IS_ERR_OR_NULL(lpss->clk)) 382 return; 383 384 clkdev_drop(lpss->clock); 385 intel_lpss_unregister_clock_tree(lpss->clk); 386 } 387 388 int intel_lpss_probe(struct device *dev, 389 const struct intel_lpss_platform_info *info) 390 { 391 struct intel_lpss *lpss; 392 int ret; 393 394 if (!info || !info->mem || info->irq <= 0) 395 return -EINVAL; 396 397 lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL); 398 if (!lpss) 399 return -ENOMEM; 400 401 lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET, 402 LPSS_PRIV_SIZE); 403 if (!lpss->priv) 404 return -ENOMEM; 405 406 lpss->info = info; 407 lpss->dev = dev; 408 lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS); 409 410 dev_set_drvdata(dev, lpss); 411 412 ret = intel_lpss_assign_devs(lpss); 413 if (ret) 414 return ret; 415 416 lpss->cell->properties = info->properties; 417 418 intel_lpss_init_dev(lpss); 419 420 lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL); 421 if (lpss->devid < 0) 422 return lpss->devid; 423 424 ret = intel_lpss_register_clock(lpss); 425 if (ret) 426 goto err_clk_register; 427 428 intel_lpss_ltr_expose(lpss); 429 430 ret = intel_lpss_debugfs_add(lpss); 431 if (ret) 432 dev_warn(dev, "Failed to create debugfs entries\n"); 433 434 if (intel_lpss_has_idma(lpss)) { 435 /* 436 * Ensure the DMA driver is loaded before the host 437 * controller device appears, so that the host controller 438 * driver can request its DMA channels as early as 439 * possible. 440 * 441 * If the DMA module is not there that's OK as well. 442 */ 443 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME); 444 445 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell, 446 1, info->mem, info->irq, NULL); 447 if (ret) 448 dev_warn(dev, "Failed to add %s, fallback to PIO\n", 449 LPSS_IDMA64_DRIVER_NAME); 450 } 451 452 ret = mfd_add_devices(dev, lpss->devid, lpss->cell, 453 1, info->mem, info->irq, NULL); 454 if (ret) 455 goto err_remove_ltr; 456 457 dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND); 458 459 return 0; 460 461 err_remove_ltr: 462 intel_lpss_debugfs_remove(lpss); 463 intel_lpss_ltr_hide(lpss); 464 intel_lpss_unregister_clock(lpss); 465 466 err_clk_register: 467 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid); 468 469 return ret; 470 } 471 EXPORT_SYMBOL_GPL(intel_lpss_probe); 472 473 void intel_lpss_remove(struct device *dev) 474 { 475 struct intel_lpss *lpss = dev_get_drvdata(dev); 476 477 mfd_remove_devices(dev); 478 intel_lpss_debugfs_remove(lpss); 479 intel_lpss_ltr_hide(lpss); 480 intel_lpss_unregister_clock(lpss); 481 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid); 482 } 483 EXPORT_SYMBOL_GPL(intel_lpss_remove); 484 485 static int resume_lpss_device(struct device *dev, void *data) 486 { 487 if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND)) 488 pm_runtime_resume(dev); 489 490 return 0; 491 } 492 493 int intel_lpss_prepare(struct device *dev) 494 { 495 /* 496 * Resume both child devices before entering system sleep. This 497 * ensures that they are in proper state before they get suspended. 498 */ 499 device_for_each_child_reverse(dev, NULL, resume_lpss_device); 500 return 0; 501 } 502 EXPORT_SYMBOL_GPL(intel_lpss_prepare); 503 504 int intel_lpss_suspend(struct device *dev) 505 { 506 struct intel_lpss *lpss = dev_get_drvdata(dev); 507 unsigned int i; 508 509 /* Save device context */ 510 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++) 511 lpss->priv_ctx[i] = readl(lpss->priv + i * 4); 512 513 /* 514 * If the device type is not UART, then put the controller into 515 * reset. UART cannot be put into reset since S3/S0ix fail when 516 * no_console_suspend flag is enabled. 517 */ 518 if (lpss->type != LPSS_DEV_UART) 519 writel(0, lpss->priv + LPSS_PRIV_RESETS); 520 521 return 0; 522 } 523 EXPORT_SYMBOL_GPL(intel_lpss_suspend); 524 525 int intel_lpss_resume(struct device *dev) 526 { 527 struct intel_lpss *lpss = dev_get_drvdata(dev); 528 unsigned int i; 529 530 intel_lpss_deassert_reset(lpss); 531 532 /* Restore device context */ 533 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++) 534 writel(lpss->priv_ctx[i], lpss->priv + i * 4); 535 536 return 0; 537 } 538 EXPORT_SYMBOL_GPL(intel_lpss_resume); 539 540 static int __init intel_lpss_init(void) 541 { 542 intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL); 543 return 0; 544 } 545 module_init(intel_lpss_init); 546 547 static void __exit intel_lpss_exit(void) 548 { 549 debugfs_remove(intel_lpss_debugfs); 550 } 551 module_exit(intel_lpss_exit); 552 553 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 554 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 555 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>"); 556 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>"); 557 MODULE_DESCRIPTION("Intel LPSS core driver"); 558 MODULE_LICENSE("GPL v2"); 559