1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdesc.h> 10 #include <linux/irqdomain.h> 11 #include <linux/irq.h> 12 #include <linux/mfd/imx25-tsadc.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 static struct regmap_config mx25_tsadc_regmap_config = { 20 .fast_io = true, 21 .max_register = 8, 22 .reg_bits = 32, 23 .val_bits = 32, 24 .reg_stride = 4, 25 }; 26 27 static void mx25_tsadc_irq_handler(struct irq_desc *desc) 28 { 29 struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc); 30 struct irq_chip *chip = irq_desc_get_chip(desc); 31 u32 status; 32 33 chained_irq_enter(chip, desc); 34 35 regmap_read(tsadc->regs, MX25_TSC_TGSR, &status); 36 37 if (status & MX25_TGSR_GCQ_INT) 38 generic_handle_irq(irq_find_mapping(tsadc->domain, 1)); 39 40 if (status & MX25_TGSR_TCQ_INT) 41 generic_handle_irq(irq_find_mapping(tsadc->domain, 0)); 42 43 chained_irq_exit(chip, desc); 44 } 45 46 static int mx25_tsadc_domain_map(struct irq_domain *d, unsigned int irq, 47 irq_hw_number_t hwirq) 48 { 49 struct mx25_tsadc *tsadc = d->host_data; 50 51 irq_set_chip_data(irq, tsadc); 52 irq_set_chip_and_handler(irq, &dummy_irq_chip, 53 handle_level_irq); 54 irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE); 55 56 return 0; 57 } 58 59 static const struct irq_domain_ops mx25_tsadc_domain_ops = { 60 .map = mx25_tsadc_domain_map, 61 .xlate = irq_domain_xlate_onecell, 62 }; 63 64 static int mx25_tsadc_setup_irq(struct platform_device *pdev, 65 struct mx25_tsadc *tsadc) 66 { 67 struct device *dev = &pdev->dev; 68 struct device_node *np = dev->of_node; 69 int irq; 70 71 irq = platform_get_irq(pdev, 0); 72 if (irq <= 0) { 73 dev_err(dev, "Failed to get irq\n"); 74 return irq; 75 } 76 77 tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops, 78 tsadc); 79 if (!tsadc->domain) { 80 dev_err(dev, "Failed to add irq domain\n"); 81 return -ENOMEM; 82 } 83 84 irq_set_chained_handler_and_data(irq, mx25_tsadc_irq_handler, tsadc); 85 86 return 0; 87 } 88 89 static void mx25_tsadc_setup_clk(struct platform_device *pdev, 90 struct mx25_tsadc *tsadc) 91 { 92 unsigned clk_div; 93 94 /* 95 * According to the datasheet the ADC clock should never 96 * exceed 1,75 MHz. Base clock is the IPG and the ADC unit uses 97 * a funny clock divider. To keep the ADC conversion time constant 98 * adapt the ADC internal clock divider to the IPG clock rate. 99 */ 100 101 dev_dbg(&pdev->dev, "Found master clock at %lu Hz\n", 102 clk_get_rate(tsadc->clk)); 103 104 clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000); 105 dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div); 106 107 /* adc clock = IPG clock / (2 * div + 2) */ 108 clk_div -= 2; 109 clk_div /= 2; 110 111 /* 112 * the ADC clock divider changes its behaviour when values below 4 113 * are used: it is fixed to "/ 10" in this case 114 */ 115 clk_div = max_t(unsigned, 4, clk_div); 116 117 dev_dbg(&pdev->dev, "Resulting ADC conversion clock at %lu Hz\n", 118 clk_get_rate(tsadc->clk) / (2 * clk_div + 2)); 119 120 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, 121 MX25_TGCR_ADCCLKCFG(0x1f), 122 MX25_TGCR_ADCCLKCFG(clk_div)); 123 } 124 125 static int mx25_tsadc_probe(struct platform_device *pdev) 126 { 127 struct device *dev = &pdev->dev; 128 struct mx25_tsadc *tsadc; 129 struct resource *res; 130 int ret; 131 void __iomem *iomem; 132 133 tsadc = devm_kzalloc(dev, sizeof(*tsadc), GFP_KERNEL); 134 if (!tsadc) 135 return -ENOMEM; 136 137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 138 iomem = devm_ioremap_resource(dev, res); 139 if (IS_ERR(iomem)) 140 return PTR_ERR(iomem); 141 142 tsadc->regs = devm_regmap_init_mmio(dev, iomem, 143 &mx25_tsadc_regmap_config); 144 if (IS_ERR(tsadc->regs)) { 145 dev_err(dev, "Failed to initialize regmap\n"); 146 return PTR_ERR(tsadc->regs); 147 } 148 149 tsadc->clk = devm_clk_get(dev, "ipg"); 150 if (IS_ERR(tsadc->clk)) { 151 dev_err(dev, "Failed to get ipg clock\n"); 152 return PTR_ERR(tsadc->clk); 153 } 154 155 /* setup clock according to the datasheet */ 156 mx25_tsadc_setup_clk(pdev, tsadc); 157 158 /* Enable clock and reset the component */ 159 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_CLK_EN, 160 MX25_TGCR_CLK_EN); 161 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_TSC_RST, 162 MX25_TGCR_TSC_RST); 163 164 /* Setup powersaving mode, but enable internal reference voltage */ 165 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_POWERMODE_MASK, 166 MX25_TGCR_POWERMODE_SAVE); 167 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_INTREFEN, 168 MX25_TGCR_INTREFEN); 169 170 ret = mx25_tsadc_setup_irq(pdev, tsadc); 171 if (ret) 172 return ret; 173 174 platform_set_drvdata(pdev, tsadc); 175 176 return devm_of_platform_populate(dev); 177 } 178 179 static int mx25_tsadc_remove(struct platform_device *pdev) 180 { 181 struct mx25_tsadc *tsadc = platform_get_drvdata(pdev); 182 int irq = platform_get_irq(pdev, 0); 183 184 if (irq) { 185 irq_set_chained_handler_and_data(irq, NULL, NULL); 186 irq_domain_remove(tsadc->domain); 187 } 188 189 return 0; 190 } 191 192 static const struct of_device_id mx25_tsadc_ids[] = { 193 { .compatible = "fsl,imx25-tsadc" }, 194 { /* Sentinel */ } 195 }; 196 MODULE_DEVICE_TABLE(of, mx25_tsadc_ids); 197 198 static struct platform_driver mx25_tsadc_driver = { 199 .driver = { 200 .name = "mx25-tsadc", 201 .of_match_table = of_match_ptr(mx25_tsadc_ids), 202 }, 203 .probe = mx25_tsadc_probe, 204 .remove = mx25_tsadc_remove, 205 }; 206 module_platform_driver(mx25_tsadc_driver); 207 208 MODULE_DESCRIPTION("MFD for ADC/TSC for Freescale mx25"); 209 MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>"); 210 MODULE_LICENSE("GPL v2"); 211 MODULE_ALIAS("platform:mx25-tsadc"); 212