xref: /openbmc/linux/drivers/mfd/db8500-prcmu.c (revision ae40e94f)
1 /*
2  * DB8500 PRCM Unit driver
3  *
4  * Copyright (C) STMicroelectronics 2009
5  * Copyright (C) ST-Ericsson SA 2010
6  *
7  * License Terms: GNU General Public License v2
8  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
9  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
10  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
11  *
12  * U8500 PRCM Unit interface driver
13  *
14  */
15 #include <linux/init.h>
16 #include <linux/export.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/slab.h>
24 #include <linux/mutex.h>
25 #include <linux/completion.h>
26 #include <linux/irq.h>
27 #include <linux/jiffies.h>
28 #include <linux/bitops.h>
29 #include <linux/fs.h>
30 #include <linux/of.h>
31 #include <linux/of_irq.h>
32 #include <linux/platform_device.h>
33 #include <linux/uaccess.h>
34 #include <linux/mfd/core.h>
35 #include <linux/mfd/dbx500-prcmu.h>
36 #include <linux/mfd/abx500/ab8500.h>
37 #include <linux/regulator/db8500-prcmu.h>
38 #include <linux/regulator/machine.h>
39 #include <linux/platform_data/ux500_wdt.h>
40 #include <linux/platform_data/db8500_thermal.h>
41 #include "dbx500-prcmu-regs.h"
42 
43 /* Index of different voltages to be used when accessing AVSData */
44 #define PRCM_AVS_BASE		0x2FC
45 #define PRCM_AVS_VBB_RET	(PRCM_AVS_BASE + 0x0)
46 #define PRCM_AVS_VBB_MAX_OPP	(PRCM_AVS_BASE + 0x1)
47 #define PRCM_AVS_VBB_100_OPP	(PRCM_AVS_BASE + 0x2)
48 #define PRCM_AVS_VBB_50_OPP	(PRCM_AVS_BASE + 0x3)
49 #define PRCM_AVS_VARM_MAX_OPP	(PRCM_AVS_BASE + 0x4)
50 #define PRCM_AVS_VARM_100_OPP	(PRCM_AVS_BASE + 0x5)
51 #define PRCM_AVS_VARM_50_OPP	(PRCM_AVS_BASE + 0x6)
52 #define PRCM_AVS_VARM_RET	(PRCM_AVS_BASE + 0x7)
53 #define PRCM_AVS_VAPE_100_OPP	(PRCM_AVS_BASE + 0x8)
54 #define PRCM_AVS_VAPE_50_OPP	(PRCM_AVS_BASE + 0x9)
55 #define PRCM_AVS_VMOD_100_OPP	(PRCM_AVS_BASE + 0xA)
56 #define PRCM_AVS_VMOD_50_OPP	(PRCM_AVS_BASE + 0xB)
57 #define PRCM_AVS_VSAFE		(PRCM_AVS_BASE + 0xC)
58 
59 #define PRCM_AVS_VOLTAGE		0
60 #define PRCM_AVS_VOLTAGE_MASK		0x3f
61 #define PRCM_AVS_ISSLOWSTARTUP		6
62 #define PRCM_AVS_ISSLOWSTARTUP_MASK	(1 << PRCM_AVS_ISSLOWSTARTUP)
63 #define PRCM_AVS_ISMODEENABLE		7
64 #define PRCM_AVS_ISMODEENABLE_MASK	(1 << PRCM_AVS_ISMODEENABLE)
65 
66 #define PRCM_BOOT_STATUS	0xFFF
67 #define PRCM_ROMCODE_A2P	0xFFE
68 #define PRCM_ROMCODE_P2A	0xFFD
69 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
70 
71 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
72 
73 #define _PRCM_MBOX_HEADER		0xFE8 /* 16 bytes */
74 #define PRCM_MBOX_HEADER_REQ_MB0	(_PRCM_MBOX_HEADER + 0x0)
75 #define PRCM_MBOX_HEADER_REQ_MB1	(_PRCM_MBOX_HEADER + 0x1)
76 #define PRCM_MBOX_HEADER_REQ_MB2	(_PRCM_MBOX_HEADER + 0x2)
77 #define PRCM_MBOX_HEADER_REQ_MB3	(_PRCM_MBOX_HEADER + 0x3)
78 #define PRCM_MBOX_HEADER_REQ_MB4	(_PRCM_MBOX_HEADER + 0x4)
79 #define PRCM_MBOX_HEADER_REQ_MB5	(_PRCM_MBOX_HEADER + 0x5)
80 #define PRCM_MBOX_HEADER_ACK_MB0	(_PRCM_MBOX_HEADER + 0x8)
81 
82 /* Req Mailboxes */
83 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
84 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
85 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
86 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
87 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
88 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
89 
90 /* Ack Mailboxes */
91 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
92 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
93 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
94 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
95 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
96 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
97 
98 /* Mailbox 0 headers */
99 #define MB0H_POWER_STATE_TRANS		0
100 #define MB0H_CONFIG_WAKEUPS_EXE		1
101 #define MB0H_READ_WAKEUP_ACK		3
102 #define MB0H_CONFIG_WAKEUPS_SLEEP	4
103 
104 #define MB0H_WAKEUP_EXE 2
105 #define MB0H_WAKEUP_SLEEP 5
106 
107 /* Mailbox 0 REQs */
108 #define PRCM_REQ_MB0_AP_POWER_STATE	(PRCM_REQ_MB0 + 0x0)
109 #define PRCM_REQ_MB0_AP_PLL_STATE	(PRCM_REQ_MB0 + 0x1)
110 #define PRCM_REQ_MB0_ULP_CLOCK_STATE	(PRCM_REQ_MB0 + 0x2)
111 #define PRCM_REQ_MB0_DO_NOT_WFI		(PRCM_REQ_MB0 + 0x3)
112 #define PRCM_REQ_MB0_WAKEUP_8500	(PRCM_REQ_MB0 + 0x4)
113 #define PRCM_REQ_MB0_WAKEUP_4500	(PRCM_REQ_MB0 + 0x8)
114 
115 /* Mailbox 0 ACKs */
116 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS	(PRCM_ACK_MB0 + 0x0)
117 #define PRCM_ACK_MB0_READ_POINTER	(PRCM_ACK_MB0 + 0x1)
118 #define PRCM_ACK_MB0_WAKEUP_0_8500	(PRCM_ACK_MB0 + 0x4)
119 #define PRCM_ACK_MB0_WAKEUP_0_4500	(PRCM_ACK_MB0 + 0x8)
120 #define PRCM_ACK_MB0_WAKEUP_1_8500	(PRCM_ACK_MB0 + 0x1C)
121 #define PRCM_ACK_MB0_WAKEUP_1_4500	(PRCM_ACK_MB0 + 0x20)
122 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS	20
123 
124 /* Mailbox 1 headers */
125 #define MB1H_ARM_APE_OPP 0x0
126 #define MB1H_RESET_MODEM 0x2
127 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
128 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
129 #define MB1H_RELEASE_USB_WAKEUP 0x5
130 #define MB1H_PLL_ON_OFF 0x6
131 
132 /* Mailbox 1 Requests */
133 #define PRCM_REQ_MB1_ARM_OPP			(PRCM_REQ_MB1 + 0x0)
134 #define PRCM_REQ_MB1_APE_OPP			(PRCM_REQ_MB1 + 0x1)
135 #define PRCM_REQ_MB1_PLL_ON_OFF			(PRCM_REQ_MB1 + 0x4)
136 #define PLL_SOC0_OFF	0x1
137 #define PLL_SOC0_ON	0x2
138 #define PLL_SOC1_OFF	0x4
139 #define PLL_SOC1_ON	0x8
140 
141 /* Mailbox 1 ACKs */
142 #define PRCM_ACK_MB1_CURRENT_ARM_OPP	(PRCM_ACK_MB1 + 0x0)
143 #define PRCM_ACK_MB1_CURRENT_APE_OPP	(PRCM_ACK_MB1 + 0x1)
144 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS	(PRCM_ACK_MB1 + 0x2)
145 #define PRCM_ACK_MB1_DVFS_STATUS	(PRCM_ACK_MB1 + 0x3)
146 
147 /* Mailbox 2 headers */
148 #define MB2H_DPS	0x0
149 #define MB2H_AUTO_PWR	0x1
150 
151 /* Mailbox 2 REQs */
152 #define PRCM_REQ_MB2_SVA_MMDSP		(PRCM_REQ_MB2 + 0x0)
153 #define PRCM_REQ_MB2_SVA_PIPE		(PRCM_REQ_MB2 + 0x1)
154 #define PRCM_REQ_MB2_SIA_MMDSP		(PRCM_REQ_MB2 + 0x2)
155 #define PRCM_REQ_MB2_SIA_PIPE		(PRCM_REQ_MB2 + 0x3)
156 #define PRCM_REQ_MB2_SGA		(PRCM_REQ_MB2 + 0x4)
157 #define PRCM_REQ_MB2_B2R2_MCDE		(PRCM_REQ_MB2 + 0x5)
158 #define PRCM_REQ_MB2_ESRAM12		(PRCM_REQ_MB2 + 0x6)
159 #define PRCM_REQ_MB2_ESRAM34		(PRCM_REQ_MB2 + 0x7)
160 #define PRCM_REQ_MB2_AUTO_PM_SLEEP	(PRCM_REQ_MB2 + 0x8)
161 #define PRCM_REQ_MB2_AUTO_PM_IDLE	(PRCM_REQ_MB2 + 0xC)
162 
163 /* Mailbox 2 ACKs */
164 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
165 #define HWACC_PWR_ST_OK 0xFE
166 
167 /* Mailbox 3 headers */
168 #define MB3H_ANC	0x0
169 #define MB3H_SIDETONE	0x1
170 #define MB3H_SYSCLK	0xE
171 
172 /* Mailbox 3 Requests */
173 #define PRCM_REQ_MB3_ANC_FIR_COEFF	(PRCM_REQ_MB3 + 0x0)
174 #define PRCM_REQ_MB3_ANC_IIR_COEFF	(PRCM_REQ_MB3 + 0x20)
175 #define PRCM_REQ_MB3_ANC_SHIFTER	(PRCM_REQ_MB3 + 0x60)
176 #define PRCM_REQ_MB3_ANC_WARP		(PRCM_REQ_MB3 + 0x64)
177 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN	(PRCM_REQ_MB3 + 0x68)
178 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF	(PRCM_REQ_MB3 + 0x6C)
179 #define PRCM_REQ_MB3_SYSCLK_MGT		(PRCM_REQ_MB3 + 0x16C)
180 
181 /* Mailbox 4 headers */
182 #define MB4H_DDR_INIT	0x0
183 #define MB4H_MEM_ST	0x1
184 #define MB4H_HOTDOG	0x12
185 #define MB4H_HOTMON	0x13
186 #define MB4H_HOT_PERIOD	0x14
187 #define MB4H_A9WDOG_CONF 0x16
188 #define MB4H_A9WDOG_EN   0x17
189 #define MB4H_A9WDOG_DIS  0x18
190 #define MB4H_A9WDOG_LOAD 0x19
191 #define MB4H_A9WDOG_KICK 0x20
192 
193 /* Mailbox 4 Requests */
194 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE	(PRCM_REQ_MB4 + 0x0)
195 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE	(PRCM_REQ_MB4 + 0x1)
196 #define PRCM_REQ_MB4_ESRAM0_ST			(PRCM_REQ_MB4 + 0x3)
197 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD		(PRCM_REQ_MB4 + 0x0)
198 #define PRCM_REQ_MB4_HOTMON_LOW			(PRCM_REQ_MB4 + 0x0)
199 #define PRCM_REQ_MB4_HOTMON_HIGH		(PRCM_REQ_MB4 + 0x1)
200 #define PRCM_REQ_MB4_HOTMON_CONFIG		(PRCM_REQ_MB4 + 0x2)
201 #define PRCM_REQ_MB4_HOT_PERIOD			(PRCM_REQ_MB4 + 0x0)
202 #define HOTMON_CONFIG_LOW			BIT(0)
203 #define HOTMON_CONFIG_HIGH			BIT(1)
204 #define PRCM_REQ_MB4_A9WDOG_0			(PRCM_REQ_MB4 + 0x0)
205 #define PRCM_REQ_MB4_A9WDOG_1			(PRCM_REQ_MB4 + 0x1)
206 #define PRCM_REQ_MB4_A9WDOG_2			(PRCM_REQ_MB4 + 0x2)
207 #define PRCM_REQ_MB4_A9WDOG_3			(PRCM_REQ_MB4 + 0x3)
208 #define A9WDOG_AUTO_OFF_EN			BIT(7)
209 #define A9WDOG_AUTO_OFF_DIS			0
210 #define A9WDOG_ID_MASK				0xf
211 
212 /* Mailbox 5 Requests */
213 #define PRCM_REQ_MB5_I2C_SLAVE_OP	(PRCM_REQ_MB5 + 0x0)
214 #define PRCM_REQ_MB5_I2C_HW_BITS	(PRCM_REQ_MB5 + 0x1)
215 #define PRCM_REQ_MB5_I2C_REG		(PRCM_REQ_MB5 + 0x2)
216 #define PRCM_REQ_MB5_I2C_VAL		(PRCM_REQ_MB5 + 0x3)
217 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
218 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
219 #define PRCMU_I2C_STOP_EN		BIT(3)
220 
221 /* Mailbox 5 ACKs */
222 #define PRCM_ACK_MB5_I2C_STATUS	(PRCM_ACK_MB5 + 0x1)
223 #define PRCM_ACK_MB5_I2C_VAL	(PRCM_ACK_MB5 + 0x3)
224 #define I2C_WR_OK 0x1
225 #define I2C_RD_OK 0x2
226 
227 #define NUM_MB 8
228 #define MBOX_BIT BIT
229 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
230 
231 /*
232  * Wakeups/IRQs
233  */
234 
235 #define WAKEUP_BIT_RTC BIT(0)
236 #define WAKEUP_BIT_RTT0 BIT(1)
237 #define WAKEUP_BIT_RTT1 BIT(2)
238 #define WAKEUP_BIT_HSI0 BIT(3)
239 #define WAKEUP_BIT_HSI1 BIT(4)
240 #define WAKEUP_BIT_CA_WAKE BIT(5)
241 #define WAKEUP_BIT_USB BIT(6)
242 #define WAKEUP_BIT_ABB BIT(7)
243 #define WAKEUP_BIT_ABB_FIFO BIT(8)
244 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
245 #define WAKEUP_BIT_CA_SLEEP BIT(10)
246 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
247 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
248 #define WAKEUP_BIT_ANC_OK BIT(13)
249 #define WAKEUP_BIT_SW_ERROR BIT(14)
250 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
251 #define WAKEUP_BIT_ARM BIT(17)
252 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
253 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
254 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
255 #define WAKEUP_BIT_GPIO0 BIT(23)
256 #define WAKEUP_BIT_GPIO1 BIT(24)
257 #define WAKEUP_BIT_GPIO2 BIT(25)
258 #define WAKEUP_BIT_GPIO3 BIT(26)
259 #define WAKEUP_BIT_GPIO4 BIT(27)
260 #define WAKEUP_BIT_GPIO5 BIT(28)
261 #define WAKEUP_BIT_GPIO6 BIT(29)
262 #define WAKEUP_BIT_GPIO7 BIT(30)
263 #define WAKEUP_BIT_GPIO8 BIT(31)
264 
265 static struct {
266 	bool valid;
267 	struct prcmu_fw_version version;
268 } fw_info;
269 
270 static struct irq_domain *db8500_irq_domain;
271 
272 /*
273  * This vector maps irq numbers to the bits in the bit field used in
274  * communication with the PRCMU firmware.
275  *
276  * The reason for having this is to keep the irq numbers contiguous even though
277  * the bits in the bit field are not. (The bits also have a tendency to move
278  * around, to further complicate matters.)
279  */
280 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
281 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
282 
283 #define IRQ_PRCMU_RTC 0
284 #define IRQ_PRCMU_RTT0 1
285 #define IRQ_PRCMU_RTT1 2
286 #define IRQ_PRCMU_HSI0 3
287 #define IRQ_PRCMU_HSI1 4
288 #define IRQ_PRCMU_CA_WAKE 5
289 #define IRQ_PRCMU_USB 6
290 #define IRQ_PRCMU_ABB 7
291 #define IRQ_PRCMU_ABB_FIFO 8
292 #define IRQ_PRCMU_ARM 9
293 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
294 #define IRQ_PRCMU_GPIO0 11
295 #define IRQ_PRCMU_GPIO1 12
296 #define IRQ_PRCMU_GPIO2 13
297 #define IRQ_PRCMU_GPIO3 14
298 #define IRQ_PRCMU_GPIO4 15
299 #define IRQ_PRCMU_GPIO5 16
300 #define IRQ_PRCMU_GPIO6 17
301 #define IRQ_PRCMU_GPIO7 18
302 #define IRQ_PRCMU_GPIO8 19
303 #define IRQ_PRCMU_CA_SLEEP 20
304 #define IRQ_PRCMU_HOTMON_LOW 21
305 #define IRQ_PRCMU_HOTMON_HIGH 22
306 #define NUM_PRCMU_WAKEUPS 23
307 
308 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
309 	IRQ_ENTRY(RTC),
310 	IRQ_ENTRY(RTT0),
311 	IRQ_ENTRY(RTT1),
312 	IRQ_ENTRY(HSI0),
313 	IRQ_ENTRY(HSI1),
314 	IRQ_ENTRY(CA_WAKE),
315 	IRQ_ENTRY(USB),
316 	IRQ_ENTRY(ABB),
317 	IRQ_ENTRY(ABB_FIFO),
318 	IRQ_ENTRY(CA_SLEEP),
319 	IRQ_ENTRY(ARM),
320 	IRQ_ENTRY(HOTMON_LOW),
321 	IRQ_ENTRY(HOTMON_HIGH),
322 	IRQ_ENTRY(MODEM_SW_RESET_REQ),
323 	IRQ_ENTRY(GPIO0),
324 	IRQ_ENTRY(GPIO1),
325 	IRQ_ENTRY(GPIO2),
326 	IRQ_ENTRY(GPIO3),
327 	IRQ_ENTRY(GPIO4),
328 	IRQ_ENTRY(GPIO5),
329 	IRQ_ENTRY(GPIO6),
330 	IRQ_ENTRY(GPIO7),
331 	IRQ_ENTRY(GPIO8)
332 };
333 
334 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
335 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
336 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
337 	WAKEUP_ENTRY(RTC),
338 	WAKEUP_ENTRY(RTT0),
339 	WAKEUP_ENTRY(RTT1),
340 	WAKEUP_ENTRY(HSI0),
341 	WAKEUP_ENTRY(HSI1),
342 	WAKEUP_ENTRY(USB),
343 	WAKEUP_ENTRY(ABB),
344 	WAKEUP_ENTRY(ABB_FIFO),
345 	WAKEUP_ENTRY(ARM)
346 };
347 
348 /*
349  * mb0_transfer - state needed for mailbox 0 communication.
350  * @lock:		The transaction lock.
351  * @dbb_events_lock:	A lock used to handle concurrent access to (parts of)
352  *			the request data.
353  * @mask_work:		Work structure used for (un)masking wakeup interrupts.
354  * @req:		Request data that need to persist between requests.
355  */
356 static struct {
357 	spinlock_t lock;
358 	spinlock_t dbb_irqs_lock;
359 	struct work_struct mask_work;
360 	struct mutex ac_wake_lock;
361 	struct completion ac_wake_work;
362 	struct {
363 		u32 dbb_irqs;
364 		u32 dbb_wakeups;
365 		u32 abb_events;
366 	} req;
367 } mb0_transfer;
368 
369 /*
370  * mb1_transfer - state needed for mailbox 1 communication.
371  * @lock:	The transaction lock.
372  * @work:	The transaction completion structure.
373  * @ape_opp:	The current APE OPP.
374  * @ack:	Reply ("acknowledge") data.
375  */
376 static struct {
377 	struct mutex lock;
378 	struct completion work;
379 	u8 ape_opp;
380 	struct {
381 		u8 header;
382 		u8 arm_opp;
383 		u8 ape_opp;
384 		u8 ape_voltage_status;
385 	} ack;
386 } mb1_transfer;
387 
388 /*
389  * mb2_transfer - state needed for mailbox 2 communication.
390  * @lock:            The transaction lock.
391  * @work:            The transaction completion structure.
392  * @auto_pm_lock:    The autonomous power management configuration lock.
393  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
394  * @req:             Request data that need to persist between requests.
395  * @ack:             Reply ("acknowledge") data.
396  */
397 static struct {
398 	struct mutex lock;
399 	struct completion work;
400 	spinlock_t auto_pm_lock;
401 	bool auto_pm_enabled;
402 	struct {
403 		u8 status;
404 	} ack;
405 } mb2_transfer;
406 
407 /*
408  * mb3_transfer - state needed for mailbox 3 communication.
409  * @lock:		The request lock.
410  * @sysclk_lock:	A lock used to handle concurrent sysclk requests.
411  * @sysclk_work:	Work structure used for sysclk requests.
412  */
413 static struct {
414 	spinlock_t lock;
415 	struct mutex sysclk_lock;
416 	struct completion sysclk_work;
417 } mb3_transfer;
418 
419 /*
420  * mb4_transfer - state needed for mailbox 4 communication.
421  * @lock:	The transaction lock.
422  * @work:	The transaction completion structure.
423  */
424 static struct {
425 	struct mutex lock;
426 	struct completion work;
427 } mb4_transfer;
428 
429 /*
430  * mb5_transfer - state needed for mailbox 5 communication.
431  * @lock:	The transaction lock.
432  * @work:	The transaction completion structure.
433  * @ack:	Reply ("acknowledge") data.
434  */
435 static struct {
436 	struct mutex lock;
437 	struct completion work;
438 	struct {
439 		u8 status;
440 		u8 value;
441 	} ack;
442 } mb5_transfer;
443 
444 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
445 
446 /* Spinlocks */
447 static DEFINE_SPINLOCK(prcmu_lock);
448 static DEFINE_SPINLOCK(clkout_lock);
449 
450 /* Global var to runtime determine TCDM base for v2 or v1 */
451 static __iomem void *tcdm_base;
452 static __iomem void *prcmu_base;
453 
454 struct clk_mgt {
455 	u32 offset;
456 	u32 pllsw;
457 	int branch;
458 	bool clk38div;
459 };
460 
461 enum {
462 	PLL_RAW,
463 	PLL_FIX,
464 	PLL_DIV
465 };
466 
467 static DEFINE_SPINLOCK(clk_mgt_lock);
468 
469 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
470 	{ (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
471 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
472 	CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
473 	CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
474 	CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
475 	CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
476 	CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
477 	CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
478 	CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
479 	CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
480 	CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
481 	CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
482 	CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
483 	CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
484 	CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
485 	CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
486 	CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
487 	CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
488 	CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
489 	CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
490 	CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
491 	CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
492 	CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
493 	CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
494 	CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
495 	CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
496 	CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
497 	CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
498 	CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
499 	CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
500 	CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
501 };
502 
503 struct dsiclk {
504 	u32 divsel_mask;
505 	u32 divsel_shift;
506 	u32 divsel;
507 };
508 
509 static struct dsiclk dsiclk[2] = {
510 	{
511 		.divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
512 		.divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
513 		.divsel = PRCM_DSI_PLLOUT_SEL_PHI,
514 	},
515 	{
516 		.divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
517 		.divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
518 		.divsel = PRCM_DSI_PLLOUT_SEL_PHI,
519 	}
520 };
521 
522 struct dsiescclk {
523 	u32 en;
524 	u32 div_mask;
525 	u32 div_shift;
526 };
527 
528 static struct dsiescclk dsiescclk[3] = {
529 	{
530 		.en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
531 		.div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
532 		.div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
533 	},
534 	{
535 		.en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
536 		.div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
537 		.div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
538 	},
539 	{
540 		.en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
541 		.div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
542 		.div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
543 	}
544 };
545 
546 
547 /*
548 * Used by MCDE to setup all necessary PRCMU registers
549 */
550 #define PRCMU_RESET_DSIPLL		0x00004000
551 #define PRCMU_UNCLAMP_DSIPLL		0x00400800
552 
553 #define PRCMU_CLK_PLL_DIV_SHIFT		0
554 #define PRCMU_CLK_PLL_SW_SHIFT		5
555 #define PRCMU_CLK_38			(1 << 9)
556 #define PRCMU_CLK_38_SRC		(1 << 10)
557 #define PRCMU_CLK_38_DIV		(1 << 11)
558 
559 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
560 #define PRCMU_DSI_CLOCK_SETTING		0x0000008C
561 
562 /* DPI 50000000 Hz */
563 #define PRCMU_DPI_CLOCK_SETTING		((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
564 					  (16 << PRCMU_CLK_PLL_DIV_SHIFT))
565 #define PRCMU_DSI_LP_CLOCK_SETTING	0x00000E00
566 
567 /* D=101, N=1, R=4, SELDIV2=0 */
568 #define PRCMU_PLLDSI_FREQ_SETTING	0x00040165
569 
570 #define PRCMU_ENABLE_PLLDSI		0x00000001
571 #define PRCMU_DISABLE_PLLDSI		0x00000000
572 #define PRCMU_RELEASE_RESET_DSS		0x0000400C
573 #define PRCMU_DSI_PLLOUT_SEL_SETTING	0x00000202
574 /* ESC clk, div0=1, div1=1, div2=3 */
575 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV	0x07030101
576 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV	0x00030101
577 #define PRCMU_DSI_RESET_SW		0x00000007
578 
579 #define PRCMU_PLLDSI_LOCKP_LOCKED	0x3
580 
581 int db8500_prcmu_enable_dsipll(void)
582 {
583 	int i;
584 
585 	/* Clear DSIPLL_RESETN */
586 	writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
587 	/* Unclamp DSIPLL in/out */
588 	writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
589 
590 	/* Set DSI PLL FREQ */
591 	writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
592 	writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
593 	/* Enable Escape clocks */
594 	writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
595 
596 	/* Start DSI PLL */
597 	writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
598 	/* Reset DSI PLL */
599 	writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
600 	for (i = 0; i < 10; i++) {
601 		if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
602 					== PRCMU_PLLDSI_LOCKP_LOCKED)
603 			break;
604 		udelay(100);
605 	}
606 	/* Set DSIPLL_RESETN */
607 	writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
608 	return 0;
609 }
610 
611 int db8500_prcmu_disable_dsipll(void)
612 {
613 	/* Disable dsi pll */
614 	writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
615 	/* Disable  escapeclock */
616 	writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
617 	return 0;
618 }
619 
620 int db8500_prcmu_set_display_clocks(void)
621 {
622 	unsigned long flags;
623 
624 	spin_lock_irqsave(&clk_mgt_lock, flags);
625 
626 	/* Grab the HW semaphore. */
627 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
628 		cpu_relax();
629 
630 	writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
631 	writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
632 	writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
633 
634 	/* Release the HW semaphore. */
635 	writel(0, PRCM_SEM);
636 
637 	spin_unlock_irqrestore(&clk_mgt_lock, flags);
638 
639 	return 0;
640 }
641 
642 u32 db8500_prcmu_read(unsigned int reg)
643 {
644 	return readl(prcmu_base + reg);
645 }
646 
647 void db8500_prcmu_write(unsigned int reg, u32 value)
648 {
649 	unsigned long flags;
650 
651 	spin_lock_irqsave(&prcmu_lock, flags);
652 	writel(value, (prcmu_base + reg));
653 	spin_unlock_irqrestore(&prcmu_lock, flags);
654 }
655 
656 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
657 {
658 	u32 val;
659 	unsigned long flags;
660 
661 	spin_lock_irqsave(&prcmu_lock, flags);
662 	val = readl(prcmu_base + reg);
663 	val = ((val & ~mask) | (value & mask));
664 	writel(val, (prcmu_base + reg));
665 	spin_unlock_irqrestore(&prcmu_lock, flags);
666 }
667 
668 struct prcmu_fw_version *prcmu_get_fw_version(void)
669 {
670 	return fw_info.valid ? &fw_info.version : NULL;
671 }
672 
673 bool prcmu_has_arm_maxopp(void)
674 {
675 	return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
676 		PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
677 }
678 
679 /**
680  * prcmu_set_rc_a2p - This function is used to run few power state sequences
681  * @val: Value to be set, i.e. transition requested
682  * Returns: 0 on success, -EINVAL on invalid argument
683  *
684  * This function is used to run the following power state sequences -
685  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
686  */
687 int prcmu_set_rc_a2p(enum romcode_write val)
688 {
689 	if (val < RDY_2_DS || val > RDY_2_XP70_RST)
690 		return -EINVAL;
691 	writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
692 	return 0;
693 }
694 
695 /**
696  * prcmu_get_rc_p2a - This function is used to get power state sequences
697  * Returns: the power transition that has last happened
698  *
699  * This function can return the following transitions-
700  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
701  */
702 enum romcode_read prcmu_get_rc_p2a(void)
703 {
704 	return readb(tcdm_base + PRCM_ROMCODE_P2A);
705 }
706 
707 /**
708  * prcmu_get_current_mode - Return the current XP70 power mode
709  * Returns: Returns the current AP(ARM) power mode: init,
710  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
711  */
712 enum ap_pwrst prcmu_get_xp70_current_state(void)
713 {
714 	return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
715 }
716 
717 /**
718  * prcmu_config_clkout - Configure one of the programmable clock outputs.
719  * @clkout:	The CLKOUT number (0 or 1).
720  * @source:	The clock to be used (one of the PRCMU_CLKSRC_*).
721  * @div:	The divider to be applied.
722  *
723  * Configures one of the programmable clock outputs (CLKOUTs).
724  * @div should be in the range [1,63] to request a configuration, or 0 to
725  * inform that the configuration is no longer requested.
726  */
727 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
728 {
729 	static int requests[2];
730 	int r = 0;
731 	unsigned long flags;
732 	u32 val;
733 	u32 bits;
734 	u32 mask;
735 	u32 div_mask;
736 
737 	BUG_ON(clkout > 1);
738 	BUG_ON(div > 63);
739 	BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
740 
741 	if (!div && !requests[clkout])
742 		return -EINVAL;
743 
744 	if (clkout == 0) {
745 		div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
746 		mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
747 		bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
748 			(div << PRCM_CLKOCR_CLKODIV0_SHIFT));
749 	} else {
750 		div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
751 		mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
752 			PRCM_CLKOCR_CLK1TYPE);
753 		bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
754 			(div << PRCM_CLKOCR_CLKODIV1_SHIFT));
755 	}
756 	bits &= mask;
757 
758 	spin_lock_irqsave(&clkout_lock, flags);
759 
760 	val = readl(PRCM_CLKOCR);
761 	if (val & div_mask) {
762 		if (div) {
763 			if ((val & mask) != bits) {
764 				r = -EBUSY;
765 				goto unlock_and_return;
766 			}
767 		} else {
768 			if ((val & mask & ~div_mask) != bits) {
769 				r = -EINVAL;
770 				goto unlock_and_return;
771 			}
772 		}
773 	}
774 	writel((bits | (val & ~mask)), PRCM_CLKOCR);
775 	requests[clkout] += (div ? 1 : -1);
776 
777 unlock_and_return:
778 	spin_unlock_irqrestore(&clkout_lock, flags);
779 
780 	return r;
781 }
782 
783 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
784 {
785 	unsigned long flags;
786 
787 	BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
788 
789 	spin_lock_irqsave(&mb0_transfer.lock, flags);
790 
791 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
792 		cpu_relax();
793 
794 	writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
795 	writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
796 	writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
797 	writeb((keep_ulp_clk ? 1 : 0),
798 		(tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
799 	writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
800 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
801 
802 	spin_unlock_irqrestore(&mb0_transfer.lock, flags);
803 
804 	return 0;
805 }
806 
807 u8 db8500_prcmu_get_power_state_result(void)
808 {
809 	return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
810 }
811 
812 /* This function should only be called while mb0_transfer.lock is held. */
813 static void config_wakeups(void)
814 {
815 	const u8 header[2] = {
816 		MB0H_CONFIG_WAKEUPS_EXE,
817 		MB0H_CONFIG_WAKEUPS_SLEEP
818 	};
819 	static u32 last_dbb_events;
820 	static u32 last_abb_events;
821 	u32 dbb_events;
822 	u32 abb_events;
823 	unsigned int i;
824 
825 	dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
826 	dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
827 
828 	abb_events = mb0_transfer.req.abb_events;
829 
830 	if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
831 		return;
832 
833 	for (i = 0; i < 2; i++) {
834 		while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
835 			cpu_relax();
836 		writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
837 		writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
838 		writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
839 		writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
840 	}
841 	last_dbb_events = dbb_events;
842 	last_abb_events = abb_events;
843 }
844 
845 void db8500_prcmu_enable_wakeups(u32 wakeups)
846 {
847 	unsigned long flags;
848 	u32 bits;
849 	int i;
850 
851 	BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
852 
853 	for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
854 		if (wakeups & BIT(i))
855 			bits |= prcmu_wakeup_bit[i];
856 	}
857 
858 	spin_lock_irqsave(&mb0_transfer.lock, flags);
859 
860 	mb0_transfer.req.dbb_wakeups = bits;
861 	config_wakeups();
862 
863 	spin_unlock_irqrestore(&mb0_transfer.lock, flags);
864 }
865 
866 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
867 {
868 	unsigned long flags;
869 
870 	spin_lock_irqsave(&mb0_transfer.lock, flags);
871 
872 	mb0_transfer.req.abb_events = abb_events;
873 	config_wakeups();
874 
875 	spin_unlock_irqrestore(&mb0_transfer.lock, flags);
876 }
877 
878 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
879 {
880 	if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
881 		*buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
882 	else
883 		*buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
884 }
885 
886 /**
887  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
888  * @opp: The new ARM operating point to which transition is to be made
889  * Returns: 0 on success, non-zero on failure
890  *
891  * This function sets the the operating point of the ARM.
892  */
893 int db8500_prcmu_set_arm_opp(u8 opp)
894 {
895 	int r;
896 
897 	if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
898 		return -EINVAL;
899 
900 	r = 0;
901 
902 	mutex_lock(&mb1_transfer.lock);
903 
904 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
905 		cpu_relax();
906 
907 	writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
908 	writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
909 	writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
910 
911 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
912 	wait_for_completion(&mb1_transfer.work);
913 
914 	if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
915 		(mb1_transfer.ack.arm_opp != opp))
916 		r = -EIO;
917 
918 	mutex_unlock(&mb1_transfer.lock);
919 
920 	return r;
921 }
922 
923 /**
924  * db8500_prcmu_get_arm_opp - get the current ARM OPP
925  *
926  * Returns: the current ARM OPP
927  */
928 int db8500_prcmu_get_arm_opp(void)
929 {
930 	return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
931 }
932 
933 /**
934  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
935  *
936  * Returns: the current DDR OPP
937  */
938 int db8500_prcmu_get_ddr_opp(void)
939 {
940 	return readb(PRCM_DDR_SUBSYS_APE_MINBW);
941 }
942 
943 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
944 static void request_even_slower_clocks(bool enable)
945 {
946 	u32 clock_reg[] = {
947 		PRCM_ACLK_MGT,
948 		PRCM_DMACLK_MGT
949 	};
950 	unsigned long flags;
951 	unsigned int i;
952 
953 	spin_lock_irqsave(&clk_mgt_lock, flags);
954 
955 	/* Grab the HW semaphore. */
956 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
957 		cpu_relax();
958 
959 	for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
960 		u32 val;
961 		u32 div;
962 
963 		val = readl(prcmu_base + clock_reg[i]);
964 		div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
965 		if (enable) {
966 			if ((div <= 1) || (div > 15)) {
967 				pr_err("prcmu: Bad clock divider %d in %s\n",
968 					div, __func__);
969 				goto unlock_and_return;
970 			}
971 			div <<= 1;
972 		} else {
973 			if (div <= 2)
974 				goto unlock_and_return;
975 			div >>= 1;
976 		}
977 		val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
978 			(div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
979 		writel(val, prcmu_base + clock_reg[i]);
980 	}
981 
982 unlock_and_return:
983 	/* Release the HW semaphore. */
984 	writel(0, PRCM_SEM);
985 
986 	spin_unlock_irqrestore(&clk_mgt_lock, flags);
987 }
988 
989 /**
990  * db8500_set_ape_opp - set the appropriate APE OPP
991  * @opp: The new APE operating point to which transition is to be made
992  * Returns: 0 on success, non-zero on failure
993  *
994  * This function sets the operating point of the APE.
995  */
996 int db8500_prcmu_set_ape_opp(u8 opp)
997 {
998 	int r = 0;
999 
1000 	if (opp == mb1_transfer.ape_opp)
1001 		return 0;
1002 
1003 	mutex_lock(&mb1_transfer.lock);
1004 
1005 	if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1006 		request_even_slower_clocks(false);
1007 
1008 	if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1009 		goto skip_message;
1010 
1011 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1012 		cpu_relax();
1013 
1014 	writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1015 	writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1016 	writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1017 		(tcdm_base + PRCM_REQ_MB1_APE_OPP));
1018 
1019 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1020 	wait_for_completion(&mb1_transfer.work);
1021 
1022 	if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1023 		(mb1_transfer.ack.ape_opp != opp))
1024 		r = -EIO;
1025 
1026 skip_message:
1027 	if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1028 		(r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1029 		request_even_slower_clocks(true);
1030 	if (!r)
1031 		mb1_transfer.ape_opp = opp;
1032 
1033 	mutex_unlock(&mb1_transfer.lock);
1034 
1035 	return r;
1036 }
1037 
1038 /**
1039  * db8500_prcmu_get_ape_opp - get the current APE OPP
1040  *
1041  * Returns: the current APE OPP
1042  */
1043 int db8500_prcmu_get_ape_opp(void)
1044 {
1045 	return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1046 }
1047 
1048 /**
1049  * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1050  * @enable: true to request the higher voltage, false to drop a request.
1051  *
1052  * Calls to this function to enable and disable requests must be balanced.
1053  */
1054 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1055 {
1056 	int r = 0;
1057 	u8 header;
1058 	static unsigned int requests;
1059 
1060 	mutex_lock(&mb1_transfer.lock);
1061 
1062 	if (enable) {
1063 		if (0 != requests++)
1064 			goto unlock_and_return;
1065 		header = MB1H_REQUEST_APE_OPP_100_VOLT;
1066 	} else {
1067 		if (requests == 0) {
1068 			r = -EIO;
1069 			goto unlock_and_return;
1070 		} else if (1 != requests--) {
1071 			goto unlock_and_return;
1072 		}
1073 		header = MB1H_RELEASE_APE_OPP_100_VOLT;
1074 	}
1075 
1076 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1077 		cpu_relax();
1078 
1079 	writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1080 
1081 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1082 	wait_for_completion(&mb1_transfer.work);
1083 
1084 	if ((mb1_transfer.ack.header != header) ||
1085 		((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1086 		r = -EIO;
1087 
1088 unlock_and_return:
1089 	mutex_unlock(&mb1_transfer.lock);
1090 
1091 	return r;
1092 }
1093 
1094 /**
1095  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1096  *
1097  * This function releases the power state requirements of a USB wakeup.
1098  */
1099 int prcmu_release_usb_wakeup_state(void)
1100 {
1101 	int r = 0;
1102 
1103 	mutex_lock(&mb1_transfer.lock);
1104 
1105 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1106 		cpu_relax();
1107 
1108 	writeb(MB1H_RELEASE_USB_WAKEUP,
1109 		(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1110 
1111 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1112 	wait_for_completion(&mb1_transfer.work);
1113 
1114 	if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1115 		((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1116 		r = -EIO;
1117 
1118 	mutex_unlock(&mb1_transfer.lock);
1119 
1120 	return r;
1121 }
1122 
1123 static int request_pll(u8 clock, bool enable)
1124 {
1125 	int r = 0;
1126 
1127 	if (clock == PRCMU_PLLSOC0)
1128 		clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1129 	else if (clock == PRCMU_PLLSOC1)
1130 		clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1131 	else
1132 		return -EINVAL;
1133 
1134 	mutex_lock(&mb1_transfer.lock);
1135 
1136 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1137 		cpu_relax();
1138 
1139 	writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1140 	writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1141 
1142 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1143 	wait_for_completion(&mb1_transfer.work);
1144 
1145 	if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1146 		r = -EIO;
1147 
1148 	mutex_unlock(&mb1_transfer.lock);
1149 
1150 	return r;
1151 }
1152 
1153 /**
1154  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1155  * @epod_id: The EPOD to set
1156  * @epod_state: The new EPOD state
1157  *
1158  * This function sets the state of a EPOD (power domain). It may not be called
1159  * from interrupt context.
1160  */
1161 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1162 {
1163 	int r = 0;
1164 	bool ram_retention = false;
1165 	int i;
1166 
1167 	/* check argument */
1168 	BUG_ON(epod_id >= NUM_EPOD_ID);
1169 
1170 	/* set flag if retention is possible */
1171 	switch (epod_id) {
1172 	case EPOD_ID_SVAMMDSP:
1173 	case EPOD_ID_SIAMMDSP:
1174 	case EPOD_ID_ESRAM12:
1175 	case EPOD_ID_ESRAM34:
1176 		ram_retention = true;
1177 		break;
1178 	}
1179 
1180 	/* check argument */
1181 	BUG_ON(epod_state > EPOD_STATE_ON);
1182 	BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1183 
1184 	/* get lock */
1185 	mutex_lock(&mb2_transfer.lock);
1186 
1187 	/* wait for mailbox */
1188 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1189 		cpu_relax();
1190 
1191 	/* fill in mailbox */
1192 	for (i = 0; i < NUM_EPOD_ID; i++)
1193 		writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1194 	writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1195 
1196 	writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1197 
1198 	writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1199 
1200 	/*
1201 	 * The current firmware version does not handle errors correctly,
1202 	 * and we cannot recover if there is an error.
1203 	 * This is expected to change when the firmware is updated.
1204 	 */
1205 	if (!wait_for_completion_timeout(&mb2_transfer.work,
1206 			msecs_to_jiffies(20000))) {
1207 		pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1208 			__func__);
1209 		r = -EIO;
1210 		goto unlock_and_return;
1211 	}
1212 
1213 	if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1214 		r = -EIO;
1215 
1216 unlock_and_return:
1217 	mutex_unlock(&mb2_transfer.lock);
1218 	return r;
1219 }
1220 
1221 /**
1222  * prcmu_configure_auto_pm - Configure autonomous power management.
1223  * @sleep: Configuration for ApSleep.
1224  * @idle:  Configuration for ApIdle.
1225  */
1226 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1227 	struct prcmu_auto_pm_config *idle)
1228 {
1229 	u32 sleep_cfg;
1230 	u32 idle_cfg;
1231 	unsigned long flags;
1232 
1233 	BUG_ON((sleep == NULL) || (idle == NULL));
1234 
1235 	sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1236 	sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1237 	sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1238 	sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1239 	sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1240 	sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1241 
1242 	idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1243 	idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1244 	idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1245 	idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1246 	idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1247 	idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1248 
1249 	spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1250 
1251 	/*
1252 	 * The autonomous power management configuration is done through
1253 	 * fields in mailbox 2, but these fields are only used as shared
1254 	 * variables - i.e. there is no need to send a message.
1255 	 */
1256 	writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1257 	writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1258 
1259 	mb2_transfer.auto_pm_enabled =
1260 		((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1261 		 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1262 		 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1263 		 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1264 
1265 	spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1266 }
1267 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1268 
1269 bool prcmu_is_auto_pm_enabled(void)
1270 {
1271 	return mb2_transfer.auto_pm_enabled;
1272 }
1273 
1274 static int request_sysclk(bool enable)
1275 {
1276 	int r;
1277 	unsigned long flags;
1278 
1279 	r = 0;
1280 
1281 	mutex_lock(&mb3_transfer.sysclk_lock);
1282 
1283 	spin_lock_irqsave(&mb3_transfer.lock, flags);
1284 
1285 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1286 		cpu_relax();
1287 
1288 	writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1289 
1290 	writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1291 	writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1292 
1293 	spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1294 
1295 	/*
1296 	 * The firmware only sends an ACK if we want to enable the
1297 	 * SysClk, and it succeeds.
1298 	 */
1299 	if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1300 			msecs_to_jiffies(20000))) {
1301 		pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1302 			__func__);
1303 		r = -EIO;
1304 	}
1305 
1306 	mutex_unlock(&mb3_transfer.sysclk_lock);
1307 
1308 	return r;
1309 }
1310 
1311 static int request_timclk(bool enable)
1312 {
1313 	u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1314 
1315 	if (!enable)
1316 		val |= PRCM_TCR_STOP_TIMERS;
1317 	writel(val, PRCM_TCR);
1318 
1319 	return 0;
1320 }
1321 
1322 static int request_clock(u8 clock, bool enable)
1323 {
1324 	u32 val;
1325 	unsigned long flags;
1326 
1327 	spin_lock_irqsave(&clk_mgt_lock, flags);
1328 
1329 	/* Grab the HW semaphore. */
1330 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1331 		cpu_relax();
1332 
1333 	val = readl(prcmu_base + clk_mgt[clock].offset);
1334 	if (enable) {
1335 		val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1336 	} else {
1337 		clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1338 		val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1339 	}
1340 	writel(val, prcmu_base + clk_mgt[clock].offset);
1341 
1342 	/* Release the HW semaphore. */
1343 	writel(0, PRCM_SEM);
1344 
1345 	spin_unlock_irqrestore(&clk_mgt_lock, flags);
1346 
1347 	return 0;
1348 }
1349 
1350 static int request_sga_clock(u8 clock, bool enable)
1351 {
1352 	u32 val;
1353 	int ret;
1354 
1355 	if (enable) {
1356 		val = readl(PRCM_CGATING_BYPASS);
1357 		writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1358 	}
1359 
1360 	ret = request_clock(clock, enable);
1361 
1362 	if (!ret && !enable) {
1363 		val = readl(PRCM_CGATING_BYPASS);
1364 		writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1365 	}
1366 
1367 	return ret;
1368 }
1369 
1370 static inline bool plldsi_locked(void)
1371 {
1372 	return (readl(PRCM_PLLDSI_LOCKP) &
1373 		(PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1374 		 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1375 		(PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1376 		 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1377 }
1378 
1379 static int request_plldsi(bool enable)
1380 {
1381 	int r = 0;
1382 	u32 val;
1383 
1384 	writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1385 		PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1386 		PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1387 
1388 	val = readl(PRCM_PLLDSI_ENABLE);
1389 	if (enable)
1390 		val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1391 	else
1392 		val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1393 	writel(val, PRCM_PLLDSI_ENABLE);
1394 
1395 	if (enable) {
1396 		unsigned int i;
1397 		bool locked = plldsi_locked();
1398 
1399 		for (i = 10; !locked && (i > 0); --i) {
1400 			udelay(100);
1401 			locked = plldsi_locked();
1402 		}
1403 		if (locked) {
1404 			writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1405 				PRCM_APE_RESETN_SET);
1406 		} else {
1407 			writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1408 				PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1409 				PRCM_MMIP_LS_CLAMP_SET);
1410 			val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1411 			writel(val, PRCM_PLLDSI_ENABLE);
1412 			r = -EAGAIN;
1413 		}
1414 	} else {
1415 		writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1416 	}
1417 	return r;
1418 }
1419 
1420 static int request_dsiclk(u8 n, bool enable)
1421 {
1422 	u32 val;
1423 
1424 	val = readl(PRCM_DSI_PLLOUT_SEL);
1425 	val &= ~dsiclk[n].divsel_mask;
1426 	val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1427 		dsiclk[n].divsel_shift);
1428 	writel(val, PRCM_DSI_PLLOUT_SEL);
1429 	return 0;
1430 }
1431 
1432 static int request_dsiescclk(u8 n, bool enable)
1433 {
1434 	u32 val;
1435 
1436 	val = readl(PRCM_DSITVCLK_DIV);
1437 	enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1438 	writel(val, PRCM_DSITVCLK_DIV);
1439 	return 0;
1440 }
1441 
1442 /**
1443  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1444  * @clock:      The clock for which the request is made.
1445  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1446  *
1447  * This function should only be used by the clock implementation.
1448  * Do not use it from any other place!
1449  */
1450 int db8500_prcmu_request_clock(u8 clock, bool enable)
1451 {
1452 	if (clock == PRCMU_SGACLK)
1453 		return request_sga_clock(clock, enable);
1454 	else if (clock < PRCMU_NUM_REG_CLOCKS)
1455 		return request_clock(clock, enable);
1456 	else if (clock == PRCMU_TIMCLK)
1457 		return request_timclk(enable);
1458 	else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1459 		return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1460 	else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1461 		return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1462 	else if (clock == PRCMU_PLLDSI)
1463 		return request_plldsi(enable);
1464 	else if (clock == PRCMU_SYSCLK)
1465 		return request_sysclk(enable);
1466 	else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1467 		return request_pll(clock, enable);
1468 	else
1469 		return -EINVAL;
1470 }
1471 
1472 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1473 	int branch)
1474 {
1475 	u64 rate;
1476 	u32 val;
1477 	u32 d;
1478 	u32 div = 1;
1479 
1480 	val = readl(reg);
1481 
1482 	rate = src_rate;
1483 	rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1484 
1485 	d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1486 	if (d > 1)
1487 		div *= d;
1488 
1489 	d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1490 	if (d > 1)
1491 		div *= d;
1492 
1493 	if (val & PRCM_PLL_FREQ_SELDIV2)
1494 		div *= 2;
1495 
1496 	if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1497 		(val & PRCM_PLL_FREQ_DIV2EN) &&
1498 		((reg == PRCM_PLLSOC0_FREQ) ||
1499 		 (reg == PRCM_PLLARM_FREQ) ||
1500 		 (reg == PRCM_PLLDDR_FREQ))))
1501 		div *= 2;
1502 
1503 	(void)do_div(rate, div);
1504 
1505 	return (unsigned long)rate;
1506 }
1507 
1508 #define ROOT_CLOCK_RATE 38400000
1509 
1510 static unsigned long clock_rate(u8 clock)
1511 {
1512 	u32 val;
1513 	u32 pllsw;
1514 	unsigned long rate = ROOT_CLOCK_RATE;
1515 
1516 	val = readl(prcmu_base + clk_mgt[clock].offset);
1517 
1518 	if (val & PRCM_CLK_MGT_CLK38) {
1519 		if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1520 			rate /= 2;
1521 		return rate;
1522 	}
1523 
1524 	val |= clk_mgt[clock].pllsw;
1525 	pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1526 
1527 	if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1528 		rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1529 	else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1530 		rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1531 	else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1532 		rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1533 	else
1534 		return 0;
1535 
1536 	if ((clock == PRCMU_SGACLK) &&
1537 		(val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1538 		u64 r = (rate * 10);
1539 
1540 		(void)do_div(r, 25);
1541 		return (unsigned long)r;
1542 	}
1543 	val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1544 	if (val)
1545 		return rate / val;
1546 	else
1547 		return 0;
1548 }
1549 
1550 static unsigned long armss_rate(void)
1551 {
1552 	u32 r;
1553 	unsigned long rate;
1554 
1555 	r = readl(PRCM_ARM_CHGCLKREQ);
1556 
1557 	if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1558 		/* External ARMCLKFIX clock */
1559 
1560 		rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1561 
1562 		/* Check PRCM_ARM_CHGCLKREQ divider */
1563 		if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1564 			rate /= 2;
1565 
1566 		/* Check PRCM_ARMCLKFIX_MGT divider */
1567 		r = readl(PRCM_ARMCLKFIX_MGT);
1568 		r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1569 		rate /= r;
1570 
1571 	} else {/* ARM PLL */
1572 		rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1573 	}
1574 
1575 	return rate;
1576 }
1577 
1578 static unsigned long dsiclk_rate(u8 n)
1579 {
1580 	u32 divsel;
1581 	u32 div = 1;
1582 
1583 	divsel = readl(PRCM_DSI_PLLOUT_SEL);
1584 	divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1585 
1586 	if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1587 		divsel = dsiclk[n].divsel;
1588 	else
1589 		dsiclk[n].divsel = divsel;
1590 
1591 	switch (divsel) {
1592 	case PRCM_DSI_PLLOUT_SEL_PHI_4:
1593 		div *= 2;
1594 	case PRCM_DSI_PLLOUT_SEL_PHI_2:
1595 		div *= 2;
1596 	case PRCM_DSI_PLLOUT_SEL_PHI:
1597 		return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1598 			PLL_RAW) / div;
1599 	default:
1600 		return 0;
1601 	}
1602 }
1603 
1604 static unsigned long dsiescclk_rate(u8 n)
1605 {
1606 	u32 div;
1607 
1608 	div = readl(PRCM_DSITVCLK_DIV);
1609 	div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1610 	return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1611 }
1612 
1613 unsigned long prcmu_clock_rate(u8 clock)
1614 {
1615 	if (clock < PRCMU_NUM_REG_CLOCKS)
1616 		return clock_rate(clock);
1617 	else if (clock == PRCMU_TIMCLK)
1618 		return ROOT_CLOCK_RATE / 16;
1619 	else if (clock == PRCMU_SYSCLK)
1620 		return ROOT_CLOCK_RATE;
1621 	else if (clock == PRCMU_PLLSOC0)
1622 		return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1623 	else if (clock == PRCMU_PLLSOC1)
1624 		return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1625 	else if (clock == PRCMU_ARMSS)
1626 		return armss_rate();
1627 	else if (clock == PRCMU_PLLDDR)
1628 		return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1629 	else if (clock == PRCMU_PLLDSI)
1630 		return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1631 			PLL_RAW);
1632 	else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1633 		return dsiclk_rate(clock - PRCMU_DSI0CLK);
1634 	else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1635 		return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1636 	else
1637 		return 0;
1638 }
1639 
1640 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1641 {
1642 	if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1643 		return ROOT_CLOCK_RATE;
1644 	clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1645 	if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1646 		return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1647 	else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1648 		return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1649 	else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1650 		return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1651 	else
1652 		return 0;
1653 }
1654 
1655 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1656 {
1657 	u32 div;
1658 
1659 	div = (src_rate / rate);
1660 	if (div == 0)
1661 		return 1;
1662 	if (rate < (src_rate / div))
1663 		div++;
1664 	return div;
1665 }
1666 
1667 static long round_clock_rate(u8 clock, unsigned long rate)
1668 {
1669 	u32 val;
1670 	u32 div;
1671 	unsigned long src_rate;
1672 	long rounded_rate;
1673 
1674 	val = readl(prcmu_base + clk_mgt[clock].offset);
1675 	src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1676 		clk_mgt[clock].branch);
1677 	div = clock_divider(src_rate, rate);
1678 	if (val & PRCM_CLK_MGT_CLK38) {
1679 		if (clk_mgt[clock].clk38div) {
1680 			if (div > 2)
1681 				div = 2;
1682 		} else {
1683 			div = 1;
1684 		}
1685 	} else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1686 		u64 r = (src_rate * 10);
1687 
1688 		(void)do_div(r, 25);
1689 		if (r <= rate)
1690 			return (unsigned long)r;
1691 	}
1692 	rounded_rate = (src_rate / min(div, (u32)31));
1693 
1694 	return rounded_rate;
1695 }
1696 
1697 static const unsigned long armss_freqs[] = {
1698 	200000000,
1699 	400000000,
1700 	800000000,
1701 	998400000
1702 };
1703 
1704 static long round_armss_rate(unsigned long rate)
1705 {
1706 	unsigned long freq = 0;
1707 	int i;
1708 
1709 	/* Find the corresponding arm opp from the cpufreq table. */
1710 	for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) {
1711 		freq = armss_freqs[i];
1712 		if (rate <= freq)
1713 			break;
1714 	}
1715 
1716 	/* Return the last valid value, even if a match was not found. */
1717 	return freq;
1718 }
1719 
1720 #define MIN_PLL_VCO_RATE 600000000ULL
1721 #define MAX_PLL_VCO_RATE 1680640000ULL
1722 
1723 static long round_plldsi_rate(unsigned long rate)
1724 {
1725 	long rounded_rate = 0;
1726 	unsigned long src_rate;
1727 	unsigned long rem;
1728 	u32 r;
1729 
1730 	src_rate = clock_rate(PRCMU_HDMICLK);
1731 	rem = rate;
1732 
1733 	for (r = 7; (rem > 0) && (r > 0); r--) {
1734 		u64 d;
1735 
1736 		d = (r * rate);
1737 		(void)do_div(d, src_rate);
1738 		if (d < 6)
1739 			d = 6;
1740 		else if (d > 255)
1741 			d = 255;
1742 		d *= src_rate;
1743 		if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1744 			((r * MAX_PLL_VCO_RATE) < (2 * d)))
1745 			continue;
1746 		(void)do_div(d, r);
1747 		if (rate < d) {
1748 			if (rounded_rate == 0)
1749 				rounded_rate = (long)d;
1750 			break;
1751 		}
1752 		if ((rate - d) < rem) {
1753 			rem = (rate - d);
1754 			rounded_rate = (long)d;
1755 		}
1756 	}
1757 	return rounded_rate;
1758 }
1759 
1760 static long round_dsiclk_rate(unsigned long rate)
1761 {
1762 	u32 div;
1763 	unsigned long src_rate;
1764 	long rounded_rate;
1765 
1766 	src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1767 		PLL_RAW);
1768 	div = clock_divider(src_rate, rate);
1769 	rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1770 
1771 	return rounded_rate;
1772 }
1773 
1774 static long round_dsiescclk_rate(unsigned long rate)
1775 {
1776 	u32 div;
1777 	unsigned long src_rate;
1778 	long rounded_rate;
1779 
1780 	src_rate = clock_rate(PRCMU_TVCLK);
1781 	div = clock_divider(src_rate, rate);
1782 	rounded_rate = (src_rate / min(div, (u32)255));
1783 
1784 	return rounded_rate;
1785 }
1786 
1787 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1788 {
1789 	if (clock < PRCMU_NUM_REG_CLOCKS)
1790 		return round_clock_rate(clock, rate);
1791 	else if (clock == PRCMU_ARMSS)
1792 		return round_armss_rate(rate);
1793 	else if (clock == PRCMU_PLLDSI)
1794 		return round_plldsi_rate(rate);
1795 	else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1796 		return round_dsiclk_rate(rate);
1797 	else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1798 		return round_dsiescclk_rate(rate);
1799 	else
1800 		return (long)prcmu_clock_rate(clock);
1801 }
1802 
1803 static void set_clock_rate(u8 clock, unsigned long rate)
1804 {
1805 	u32 val;
1806 	u32 div;
1807 	unsigned long src_rate;
1808 	unsigned long flags;
1809 
1810 	spin_lock_irqsave(&clk_mgt_lock, flags);
1811 
1812 	/* Grab the HW semaphore. */
1813 	while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1814 		cpu_relax();
1815 
1816 	val = readl(prcmu_base + clk_mgt[clock].offset);
1817 	src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1818 		clk_mgt[clock].branch);
1819 	div = clock_divider(src_rate, rate);
1820 	if (val & PRCM_CLK_MGT_CLK38) {
1821 		if (clk_mgt[clock].clk38div) {
1822 			if (div > 1)
1823 				val |= PRCM_CLK_MGT_CLK38DIV;
1824 			else
1825 				val &= ~PRCM_CLK_MGT_CLK38DIV;
1826 		}
1827 	} else if (clock == PRCMU_SGACLK) {
1828 		val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1829 			PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1830 		if (div == 3) {
1831 			u64 r = (src_rate * 10);
1832 
1833 			(void)do_div(r, 25);
1834 			if (r <= rate) {
1835 				val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1836 				div = 0;
1837 			}
1838 		}
1839 		val |= min(div, (u32)31);
1840 	} else {
1841 		val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1842 		val |= min(div, (u32)31);
1843 	}
1844 	writel(val, prcmu_base + clk_mgt[clock].offset);
1845 
1846 	/* Release the HW semaphore. */
1847 	writel(0, PRCM_SEM);
1848 
1849 	spin_unlock_irqrestore(&clk_mgt_lock, flags);
1850 }
1851 
1852 static int set_armss_rate(unsigned long rate)
1853 {
1854 	unsigned long freq;
1855 	u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1856 	int i;
1857 
1858 	/* Find the corresponding arm opp from the cpufreq table. */
1859 	for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) {
1860 		freq = armss_freqs[i];
1861 		if (rate == freq)
1862 			break;
1863 	}
1864 
1865 	if (rate != freq)
1866 		return -EINVAL;
1867 
1868 	/* Set the new arm opp. */
1869 	pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1870 	return db8500_prcmu_set_arm_opp(opps[i]);
1871 }
1872 
1873 static int set_plldsi_rate(unsigned long rate)
1874 {
1875 	unsigned long src_rate;
1876 	unsigned long rem;
1877 	u32 pll_freq = 0;
1878 	u32 r;
1879 
1880 	src_rate = clock_rate(PRCMU_HDMICLK);
1881 	rem = rate;
1882 
1883 	for (r = 7; (rem > 0) && (r > 0); r--) {
1884 		u64 d;
1885 		u64 hwrate;
1886 
1887 		d = (r * rate);
1888 		(void)do_div(d, src_rate);
1889 		if (d < 6)
1890 			d = 6;
1891 		else if (d > 255)
1892 			d = 255;
1893 		hwrate = (d * src_rate);
1894 		if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1895 			((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1896 			continue;
1897 		(void)do_div(hwrate, r);
1898 		if (rate < hwrate) {
1899 			if (pll_freq == 0)
1900 				pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1901 					(r << PRCM_PLL_FREQ_R_SHIFT));
1902 			break;
1903 		}
1904 		if ((rate - hwrate) < rem) {
1905 			rem = (rate - hwrate);
1906 			pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1907 				(r << PRCM_PLL_FREQ_R_SHIFT));
1908 		}
1909 	}
1910 	if (pll_freq == 0)
1911 		return -EINVAL;
1912 
1913 	pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1914 	writel(pll_freq, PRCM_PLLDSI_FREQ);
1915 
1916 	return 0;
1917 }
1918 
1919 static void set_dsiclk_rate(u8 n, unsigned long rate)
1920 {
1921 	u32 val;
1922 	u32 div;
1923 
1924 	div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1925 			clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1926 
1927 	dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1928 			   (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1929 			   /* else */	PRCM_DSI_PLLOUT_SEL_PHI_4;
1930 
1931 	val = readl(PRCM_DSI_PLLOUT_SEL);
1932 	val &= ~dsiclk[n].divsel_mask;
1933 	val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1934 	writel(val, PRCM_DSI_PLLOUT_SEL);
1935 }
1936 
1937 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1938 {
1939 	u32 val;
1940 	u32 div;
1941 
1942 	div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1943 	val = readl(PRCM_DSITVCLK_DIV);
1944 	val &= ~dsiescclk[n].div_mask;
1945 	val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1946 	writel(val, PRCM_DSITVCLK_DIV);
1947 }
1948 
1949 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1950 {
1951 	if (clock < PRCMU_NUM_REG_CLOCKS)
1952 		set_clock_rate(clock, rate);
1953 	else if (clock == PRCMU_ARMSS)
1954 		return set_armss_rate(rate);
1955 	else if (clock == PRCMU_PLLDSI)
1956 		return set_plldsi_rate(rate);
1957 	else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1958 		set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1959 	else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1960 		set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1961 	return 0;
1962 }
1963 
1964 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1965 {
1966 	if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1967 	    (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1968 		return -EINVAL;
1969 
1970 	mutex_lock(&mb4_transfer.lock);
1971 
1972 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1973 		cpu_relax();
1974 
1975 	writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1976 	writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
1977 	       (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
1978 	writeb(DDR_PWR_STATE_ON,
1979 	       (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
1980 	writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
1981 
1982 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1983 	wait_for_completion(&mb4_transfer.work);
1984 
1985 	mutex_unlock(&mb4_transfer.lock);
1986 
1987 	return 0;
1988 }
1989 
1990 int db8500_prcmu_config_hotdog(u8 threshold)
1991 {
1992 	mutex_lock(&mb4_transfer.lock);
1993 
1994 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1995 		cpu_relax();
1996 
1997 	writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
1998 	writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1999 
2000 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2001 	wait_for_completion(&mb4_transfer.work);
2002 
2003 	mutex_unlock(&mb4_transfer.lock);
2004 
2005 	return 0;
2006 }
2007 
2008 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2009 {
2010 	mutex_lock(&mb4_transfer.lock);
2011 
2012 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2013 		cpu_relax();
2014 
2015 	writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2016 	writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2017 	writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2018 		(tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2019 	writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2020 
2021 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2022 	wait_for_completion(&mb4_transfer.work);
2023 
2024 	mutex_unlock(&mb4_transfer.lock);
2025 
2026 	return 0;
2027 }
2028 EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
2029 
2030 static int config_hot_period(u16 val)
2031 {
2032 	mutex_lock(&mb4_transfer.lock);
2033 
2034 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2035 		cpu_relax();
2036 
2037 	writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2038 	writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2039 
2040 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2041 	wait_for_completion(&mb4_transfer.work);
2042 
2043 	mutex_unlock(&mb4_transfer.lock);
2044 
2045 	return 0;
2046 }
2047 
2048 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2049 {
2050 	if (cycles32k == 0xFFFF)
2051 		return -EINVAL;
2052 
2053 	return config_hot_period(cycles32k);
2054 }
2055 EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
2056 
2057 int db8500_prcmu_stop_temp_sense(void)
2058 {
2059 	return config_hot_period(0xFFFF);
2060 }
2061 EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
2062 
2063 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2064 {
2065 
2066 	mutex_lock(&mb4_transfer.lock);
2067 
2068 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2069 		cpu_relax();
2070 
2071 	writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2072 	writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2073 	writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2074 	writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2075 
2076 	writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2077 
2078 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2079 	wait_for_completion(&mb4_transfer.work);
2080 
2081 	mutex_unlock(&mb4_transfer.lock);
2082 
2083 	return 0;
2084 
2085 }
2086 
2087 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2088 {
2089 	BUG_ON(num == 0 || num > 0xf);
2090 	return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2091 			    sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2092 			    A9WDOG_AUTO_OFF_DIS);
2093 }
2094 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2095 
2096 int db8500_prcmu_enable_a9wdog(u8 id)
2097 {
2098 	return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2099 }
2100 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2101 
2102 int db8500_prcmu_disable_a9wdog(u8 id)
2103 {
2104 	return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2105 }
2106 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2107 
2108 int db8500_prcmu_kick_a9wdog(u8 id)
2109 {
2110 	return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2111 }
2112 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2113 
2114 /*
2115  * timeout is 28 bit, in ms.
2116  */
2117 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2118 {
2119 	return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2120 			    (id & A9WDOG_ID_MASK) |
2121 			    /*
2122 			     * Put the lowest 28 bits of timeout at
2123 			     * offset 4. Four first bits are used for id.
2124 			     */
2125 			    (u8)((timeout << 4) & 0xf0),
2126 			    (u8)((timeout >> 4) & 0xff),
2127 			    (u8)((timeout >> 12) & 0xff),
2128 			    (u8)((timeout >> 20) & 0xff));
2129 }
2130 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2131 
2132 /**
2133  * prcmu_abb_read() - Read register value(s) from the ABB.
2134  * @slave:	The I2C slave address.
2135  * @reg:	The (start) register address.
2136  * @value:	The read out value(s).
2137  * @size:	The number of registers to read.
2138  *
2139  * Reads register value(s) from the ABB.
2140  * @size has to be 1 for the current firmware version.
2141  */
2142 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2143 {
2144 	int r;
2145 
2146 	if (size != 1)
2147 		return -EINVAL;
2148 
2149 	mutex_lock(&mb5_transfer.lock);
2150 
2151 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2152 		cpu_relax();
2153 
2154 	writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2155 	writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2156 	writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2157 	writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2158 	writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2159 
2160 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2161 
2162 	if (!wait_for_completion_timeout(&mb5_transfer.work,
2163 				msecs_to_jiffies(20000))) {
2164 		pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2165 			__func__);
2166 		r = -EIO;
2167 	} else {
2168 		r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2169 	}
2170 
2171 	if (!r)
2172 		*value = mb5_transfer.ack.value;
2173 
2174 	mutex_unlock(&mb5_transfer.lock);
2175 
2176 	return r;
2177 }
2178 
2179 /**
2180  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2181  * @slave:	The I2C slave address.
2182  * @reg:	The (start) register address.
2183  * @value:	The value(s) to write.
2184  * @mask:	The mask(s) to use.
2185  * @size:	The number of registers to write.
2186  *
2187  * Writes masked register value(s) to the ABB.
2188  * For each @value, only the bits set to 1 in the corresponding @mask
2189  * will be written. The other bits are not changed.
2190  * @size has to be 1 for the current firmware version.
2191  */
2192 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2193 {
2194 	int r;
2195 
2196 	if (size != 1)
2197 		return -EINVAL;
2198 
2199 	mutex_lock(&mb5_transfer.lock);
2200 
2201 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2202 		cpu_relax();
2203 
2204 	writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2205 	writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2206 	writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2207 	writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2208 	writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2209 
2210 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2211 
2212 	if (!wait_for_completion_timeout(&mb5_transfer.work,
2213 				msecs_to_jiffies(20000))) {
2214 		pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2215 			__func__);
2216 		r = -EIO;
2217 	} else {
2218 		r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2219 	}
2220 
2221 	mutex_unlock(&mb5_transfer.lock);
2222 
2223 	return r;
2224 }
2225 
2226 /**
2227  * prcmu_abb_write() - Write register value(s) to the ABB.
2228  * @slave:	The I2C slave address.
2229  * @reg:	The (start) register address.
2230  * @value:	The value(s) to write.
2231  * @size:	The number of registers to write.
2232  *
2233  * Writes register value(s) to the ABB.
2234  * @size has to be 1 for the current firmware version.
2235  */
2236 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2237 {
2238 	u8 mask = ~0;
2239 
2240 	return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2241 }
2242 
2243 /**
2244  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2245  */
2246 int prcmu_ac_wake_req(void)
2247 {
2248 	u32 val;
2249 	int ret = 0;
2250 
2251 	mutex_lock(&mb0_transfer.ac_wake_lock);
2252 
2253 	val = readl(PRCM_HOSTACCESS_REQ);
2254 	if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2255 		goto unlock_and_return;
2256 
2257 	atomic_set(&ac_wake_req_state, 1);
2258 
2259 	/*
2260 	 * Force Modem Wake-up before hostaccess_req ping-pong.
2261 	 * It prevents Modem to enter in Sleep while acking the hostaccess
2262 	 * request. The 31us delay has been calculated by HWI.
2263 	 */
2264 	val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2265 	writel(val, PRCM_HOSTACCESS_REQ);
2266 
2267 	udelay(31);
2268 
2269 	val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2270 	writel(val, PRCM_HOSTACCESS_REQ);
2271 
2272 	if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2273 			msecs_to_jiffies(5000))) {
2274 		pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2275 			__func__);
2276 		ret = -EFAULT;
2277 	}
2278 
2279 unlock_and_return:
2280 	mutex_unlock(&mb0_transfer.ac_wake_lock);
2281 	return ret;
2282 }
2283 
2284 /**
2285  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2286  */
2287 void prcmu_ac_sleep_req(void)
2288 {
2289 	u32 val;
2290 
2291 	mutex_lock(&mb0_transfer.ac_wake_lock);
2292 
2293 	val = readl(PRCM_HOSTACCESS_REQ);
2294 	if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2295 		goto unlock_and_return;
2296 
2297 	writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2298 		PRCM_HOSTACCESS_REQ);
2299 
2300 	if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2301 			msecs_to_jiffies(5000))) {
2302 		pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2303 			__func__);
2304 	}
2305 
2306 	atomic_set(&ac_wake_req_state, 0);
2307 
2308 unlock_and_return:
2309 	mutex_unlock(&mb0_transfer.ac_wake_lock);
2310 }
2311 
2312 bool db8500_prcmu_is_ac_wake_requested(void)
2313 {
2314 	return (atomic_read(&ac_wake_req_state) != 0);
2315 }
2316 
2317 /**
2318  * db8500_prcmu_system_reset - System reset
2319  *
2320  * Saves the reset reason code and then sets the APE_SOFTRST register which
2321  * fires interrupt to fw
2322  */
2323 void db8500_prcmu_system_reset(u16 reset_code)
2324 {
2325 	writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2326 	writel(1, PRCM_APE_SOFTRST);
2327 }
2328 
2329 /**
2330  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2331  *
2332  * Retrieves the reset reason code stored by prcmu_system_reset() before
2333  * last restart.
2334  */
2335 u16 db8500_prcmu_get_reset_code(void)
2336 {
2337 	return readw(tcdm_base + PRCM_SW_RST_REASON);
2338 }
2339 
2340 /**
2341  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2342  */
2343 void db8500_prcmu_modem_reset(void)
2344 {
2345 	mutex_lock(&mb1_transfer.lock);
2346 
2347 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2348 		cpu_relax();
2349 
2350 	writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2351 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2352 	wait_for_completion(&mb1_transfer.work);
2353 
2354 	/*
2355 	 * No need to check return from PRCMU as modem should go in reset state
2356 	 * This state is already managed by upper layer
2357 	 */
2358 
2359 	mutex_unlock(&mb1_transfer.lock);
2360 }
2361 
2362 static void ack_dbb_wakeup(void)
2363 {
2364 	unsigned long flags;
2365 
2366 	spin_lock_irqsave(&mb0_transfer.lock, flags);
2367 
2368 	while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2369 		cpu_relax();
2370 
2371 	writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2372 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2373 
2374 	spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2375 }
2376 
2377 static inline void print_unknown_header_warning(u8 n, u8 header)
2378 {
2379 	pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
2380 		header, n);
2381 }
2382 
2383 static bool read_mailbox_0(void)
2384 {
2385 	bool r;
2386 	u32 ev;
2387 	unsigned int n;
2388 	u8 header;
2389 
2390 	header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2391 	switch (header) {
2392 	case MB0H_WAKEUP_EXE:
2393 	case MB0H_WAKEUP_SLEEP:
2394 		if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2395 			ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2396 		else
2397 			ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2398 
2399 		if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2400 			complete(&mb0_transfer.ac_wake_work);
2401 		if (ev & WAKEUP_BIT_SYSCLK_OK)
2402 			complete(&mb3_transfer.sysclk_work);
2403 
2404 		ev &= mb0_transfer.req.dbb_irqs;
2405 
2406 		for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2407 			if (ev & prcmu_irq_bit[n])
2408 				generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2409 		}
2410 		r = true;
2411 		break;
2412 	default:
2413 		print_unknown_header_warning(0, header);
2414 		r = false;
2415 		break;
2416 	}
2417 	writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2418 	return r;
2419 }
2420 
2421 static bool read_mailbox_1(void)
2422 {
2423 	mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2424 	mb1_transfer.ack.arm_opp = readb(tcdm_base +
2425 		PRCM_ACK_MB1_CURRENT_ARM_OPP);
2426 	mb1_transfer.ack.ape_opp = readb(tcdm_base +
2427 		PRCM_ACK_MB1_CURRENT_APE_OPP);
2428 	mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2429 		PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2430 	writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2431 	complete(&mb1_transfer.work);
2432 	return false;
2433 }
2434 
2435 static bool read_mailbox_2(void)
2436 {
2437 	mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2438 	writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2439 	complete(&mb2_transfer.work);
2440 	return false;
2441 }
2442 
2443 static bool read_mailbox_3(void)
2444 {
2445 	writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2446 	return false;
2447 }
2448 
2449 static bool read_mailbox_4(void)
2450 {
2451 	u8 header;
2452 	bool do_complete = true;
2453 
2454 	header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2455 	switch (header) {
2456 	case MB4H_MEM_ST:
2457 	case MB4H_HOTDOG:
2458 	case MB4H_HOTMON:
2459 	case MB4H_HOT_PERIOD:
2460 	case MB4H_A9WDOG_CONF:
2461 	case MB4H_A9WDOG_EN:
2462 	case MB4H_A9WDOG_DIS:
2463 	case MB4H_A9WDOG_LOAD:
2464 	case MB4H_A9WDOG_KICK:
2465 		break;
2466 	default:
2467 		print_unknown_header_warning(4, header);
2468 		do_complete = false;
2469 		break;
2470 	}
2471 
2472 	writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2473 
2474 	if (do_complete)
2475 		complete(&mb4_transfer.work);
2476 
2477 	return false;
2478 }
2479 
2480 static bool read_mailbox_5(void)
2481 {
2482 	mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2483 	mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2484 	writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2485 	complete(&mb5_transfer.work);
2486 	return false;
2487 }
2488 
2489 static bool read_mailbox_6(void)
2490 {
2491 	writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2492 	return false;
2493 }
2494 
2495 static bool read_mailbox_7(void)
2496 {
2497 	writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2498 	return false;
2499 }
2500 
2501 static bool (* const read_mailbox[NUM_MB])(void) = {
2502 	read_mailbox_0,
2503 	read_mailbox_1,
2504 	read_mailbox_2,
2505 	read_mailbox_3,
2506 	read_mailbox_4,
2507 	read_mailbox_5,
2508 	read_mailbox_6,
2509 	read_mailbox_7
2510 };
2511 
2512 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2513 {
2514 	u32 bits;
2515 	u8 n;
2516 	irqreturn_t r;
2517 
2518 	bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2519 	if (unlikely(!bits))
2520 		return IRQ_NONE;
2521 
2522 	r = IRQ_HANDLED;
2523 	for (n = 0; bits; n++) {
2524 		if (bits & MBOX_BIT(n)) {
2525 			bits -= MBOX_BIT(n);
2526 			if (read_mailbox[n]())
2527 				r = IRQ_WAKE_THREAD;
2528 		}
2529 	}
2530 	return r;
2531 }
2532 
2533 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2534 {
2535 	ack_dbb_wakeup();
2536 	return IRQ_HANDLED;
2537 }
2538 
2539 static void prcmu_mask_work(struct work_struct *work)
2540 {
2541 	unsigned long flags;
2542 
2543 	spin_lock_irqsave(&mb0_transfer.lock, flags);
2544 
2545 	config_wakeups();
2546 
2547 	spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2548 }
2549 
2550 static void prcmu_irq_mask(struct irq_data *d)
2551 {
2552 	unsigned long flags;
2553 
2554 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2555 
2556 	mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2557 
2558 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2559 
2560 	if (d->irq != IRQ_PRCMU_CA_SLEEP)
2561 		schedule_work(&mb0_transfer.mask_work);
2562 }
2563 
2564 static void prcmu_irq_unmask(struct irq_data *d)
2565 {
2566 	unsigned long flags;
2567 
2568 	spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2569 
2570 	mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2571 
2572 	spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2573 
2574 	if (d->irq != IRQ_PRCMU_CA_SLEEP)
2575 		schedule_work(&mb0_transfer.mask_work);
2576 }
2577 
2578 static void noop(struct irq_data *d)
2579 {
2580 }
2581 
2582 static struct irq_chip prcmu_irq_chip = {
2583 	.name		= "prcmu",
2584 	.irq_disable	= prcmu_irq_mask,
2585 	.irq_ack	= noop,
2586 	.irq_mask	= prcmu_irq_mask,
2587 	.irq_unmask	= prcmu_irq_unmask,
2588 };
2589 
2590 static char *fw_project_name(u32 project)
2591 {
2592 	switch (project) {
2593 	case PRCMU_FW_PROJECT_U8500:
2594 		return "U8500";
2595 	case PRCMU_FW_PROJECT_U8400:
2596 		return "U8400";
2597 	case PRCMU_FW_PROJECT_U9500:
2598 		return "U9500";
2599 	case PRCMU_FW_PROJECT_U8500_MBB:
2600 		return "U8500 MBB";
2601 	case PRCMU_FW_PROJECT_U8500_C1:
2602 		return "U8500 C1";
2603 	case PRCMU_FW_PROJECT_U8500_C2:
2604 		return "U8500 C2";
2605 	case PRCMU_FW_PROJECT_U8500_C3:
2606 		return "U8500 C3";
2607 	case PRCMU_FW_PROJECT_U8500_C4:
2608 		return "U8500 C4";
2609 	case PRCMU_FW_PROJECT_U9500_MBL:
2610 		return "U9500 MBL";
2611 	case PRCMU_FW_PROJECT_U8500_MBL:
2612 		return "U8500 MBL";
2613 	case PRCMU_FW_PROJECT_U8500_MBL2:
2614 		return "U8500 MBL2";
2615 	case PRCMU_FW_PROJECT_U8520:
2616 		return "U8520 MBL";
2617 	case PRCMU_FW_PROJECT_U8420:
2618 		return "U8420";
2619 	case PRCMU_FW_PROJECT_U9540:
2620 		return "U9540";
2621 	case PRCMU_FW_PROJECT_A9420:
2622 		return "A9420";
2623 	case PRCMU_FW_PROJECT_L8540:
2624 		return "L8540";
2625 	case PRCMU_FW_PROJECT_L8580:
2626 		return "L8580";
2627 	default:
2628 		return "Unknown";
2629 	}
2630 }
2631 
2632 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2633 				irq_hw_number_t hwirq)
2634 {
2635 	irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2636 				handle_simple_irq);
2637 
2638 	return 0;
2639 }
2640 
2641 static const struct irq_domain_ops db8500_irq_ops = {
2642 	.map    = db8500_irq_map,
2643 	.xlate  = irq_domain_xlate_twocell,
2644 };
2645 
2646 static int db8500_irq_init(struct device_node *np)
2647 {
2648 	int i;
2649 
2650 	db8500_irq_domain = irq_domain_add_simple(
2651 		np, NUM_PRCMU_WAKEUPS, 0,
2652 		&db8500_irq_ops, NULL);
2653 
2654 	if (!db8500_irq_domain) {
2655 		pr_err("Failed to create irqdomain\n");
2656 		return -ENOSYS;
2657 	}
2658 
2659 	/* All wakeups will be used, so create mappings for all */
2660 	for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2661 		irq_create_mapping(db8500_irq_domain, i);
2662 
2663 	return 0;
2664 }
2665 
2666 static void dbx500_fw_version_init(struct platform_device *pdev,
2667 			    u32 version_offset)
2668 {
2669 	struct resource *res;
2670 	void __iomem *tcpm_base;
2671 	u32 version;
2672 
2673 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2674 					   "prcmu-tcpm");
2675 	if (!res) {
2676 		dev_err(&pdev->dev,
2677 			"Error: no prcmu tcpm memory region provided\n");
2678 		return;
2679 	}
2680 	tcpm_base = ioremap(res->start, resource_size(res));
2681 	if (!tcpm_base) {
2682 		dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2683 		return;
2684 	}
2685 
2686 	version = readl(tcpm_base + version_offset);
2687 	fw_info.version.project = (version & 0xFF);
2688 	fw_info.version.api_version = (version >> 8) & 0xFF;
2689 	fw_info.version.func_version = (version >> 16) & 0xFF;
2690 	fw_info.version.errata = (version >> 24) & 0xFF;
2691 	strncpy(fw_info.version.project_name,
2692 		fw_project_name(fw_info.version.project),
2693 		PRCMU_FW_PROJECT_NAME_LEN);
2694 	fw_info.valid = true;
2695 	pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2696 		fw_info.version.project_name,
2697 		fw_info.version.project,
2698 		fw_info.version.api_version,
2699 		fw_info.version.func_version,
2700 		fw_info.version.errata);
2701 	iounmap(tcpm_base);
2702 }
2703 
2704 void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2705 {
2706 	/*
2707 	 * This is a temporary remap to bring up the clocks. It is
2708 	 * subsequently replaces with a real remap. After the merge of
2709 	 * the mailbox subsystem all of this early code goes away, and the
2710 	 * clock driver can probe independently. An early initcall will
2711 	 * still be needed, but it can be diverted into drivers/clk/ux500.
2712 	 */
2713 	prcmu_base = ioremap(phy_base, size);
2714 	if (!prcmu_base)
2715 		pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2716 
2717 	spin_lock_init(&mb0_transfer.lock);
2718 	spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2719 	mutex_init(&mb0_transfer.ac_wake_lock);
2720 	init_completion(&mb0_transfer.ac_wake_work);
2721 	mutex_init(&mb1_transfer.lock);
2722 	init_completion(&mb1_transfer.work);
2723 	mb1_transfer.ape_opp = APE_NO_CHANGE;
2724 	mutex_init(&mb2_transfer.lock);
2725 	init_completion(&mb2_transfer.work);
2726 	spin_lock_init(&mb2_transfer.auto_pm_lock);
2727 	spin_lock_init(&mb3_transfer.lock);
2728 	mutex_init(&mb3_transfer.sysclk_lock);
2729 	init_completion(&mb3_transfer.sysclk_work);
2730 	mutex_init(&mb4_transfer.lock);
2731 	init_completion(&mb4_transfer.work);
2732 	mutex_init(&mb5_transfer.lock);
2733 	init_completion(&mb5_transfer.work);
2734 
2735 	INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2736 }
2737 
2738 static void init_prcm_registers(void)
2739 {
2740 	u32 val;
2741 
2742 	val = readl(PRCM_A9PL_FORCE_CLKEN);
2743 	val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2744 		PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2745 	writel(val, (PRCM_A9PL_FORCE_CLKEN));
2746 }
2747 
2748 /*
2749  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2750  */
2751 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2752 	REGULATOR_SUPPLY("v-ape", NULL),
2753 	REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2754 	REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2755 	REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2756 	REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2757 	REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2758 	/* "v-mmc" changed to "vcore" in the mainline kernel */
2759 	REGULATOR_SUPPLY("vcore", "sdi0"),
2760 	REGULATOR_SUPPLY("vcore", "sdi1"),
2761 	REGULATOR_SUPPLY("vcore", "sdi2"),
2762 	REGULATOR_SUPPLY("vcore", "sdi3"),
2763 	REGULATOR_SUPPLY("vcore", "sdi4"),
2764 	REGULATOR_SUPPLY("v-dma", "dma40.0"),
2765 	REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2766 	/* "v-uart" changed to "vcore" in the mainline kernel */
2767 	REGULATOR_SUPPLY("vcore", "uart0"),
2768 	REGULATOR_SUPPLY("vcore", "uart1"),
2769 	REGULATOR_SUPPLY("vcore", "uart2"),
2770 	REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2771 	REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2772 	REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2773 };
2774 
2775 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2776 	REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2777 	/* AV8100 regulator */
2778 	REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2779 };
2780 
2781 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2782 	REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2783 	REGULATOR_SUPPLY("vsupply", "mcde"),
2784 };
2785 
2786 /* SVA MMDSP regulator switch */
2787 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2788 	REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2789 };
2790 
2791 /* SVA pipe regulator switch */
2792 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2793 	REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2794 };
2795 
2796 /* SIA MMDSP regulator switch */
2797 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2798 	REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2799 };
2800 
2801 /* SIA pipe regulator switch */
2802 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2803 	REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2804 };
2805 
2806 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2807 	REGULATOR_SUPPLY("v-mali", NULL),
2808 };
2809 
2810 /* ESRAM1 and 2 regulator switch */
2811 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2812 	REGULATOR_SUPPLY("esram12", "cm_control"),
2813 };
2814 
2815 /* ESRAM3 and 4 regulator switch */
2816 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2817 	REGULATOR_SUPPLY("v-esram34", "mcde"),
2818 	REGULATOR_SUPPLY("esram34", "cm_control"),
2819 	REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2820 };
2821 
2822 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2823 	[DB8500_REGULATOR_VAPE] = {
2824 		.constraints = {
2825 			.name = "db8500-vape",
2826 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2827 			.always_on = true,
2828 		},
2829 		.consumer_supplies = db8500_vape_consumers,
2830 		.num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2831 	},
2832 	[DB8500_REGULATOR_VARM] = {
2833 		.constraints = {
2834 			.name = "db8500-varm",
2835 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2836 		},
2837 	},
2838 	[DB8500_REGULATOR_VMODEM] = {
2839 		.constraints = {
2840 			.name = "db8500-vmodem",
2841 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2842 		},
2843 	},
2844 	[DB8500_REGULATOR_VPLL] = {
2845 		.constraints = {
2846 			.name = "db8500-vpll",
2847 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2848 		},
2849 	},
2850 	[DB8500_REGULATOR_VSMPS1] = {
2851 		.constraints = {
2852 			.name = "db8500-vsmps1",
2853 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2854 		},
2855 	},
2856 	[DB8500_REGULATOR_VSMPS2] = {
2857 		.constraints = {
2858 			.name = "db8500-vsmps2",
2859 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2860 		},
2861 		.consumer_supplies = db8500_vsmps2_consumers,
2862 		.num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2863 	},
2864 	[DB8500_REGULATOR_VSMPS3] = {
2865 		.constraints = {
2866 			.name = "db8500-vsmps3",
2867 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2868 		},
2869 	},
2870 	[DB8500_REGULATOR_VRF1] = {
2871 		.constraints = {
2872 			.name = "db8500-vrf1",
2873 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2874 		},
2875 	},
2876 	[DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2877 		/* dependency to u8500-vape is handled outside regulator framework */
2878 		.constraints = {
2879 			.name = "db8500-sva-mmdsp",
2880 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2881 		},
2882 		.consumer_supplies = db8500_svammdsp_consumers,
2883 		.num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2884 	},
2885 	[DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2886 		.constraints = {
2887 			/* "ret" means "retention" */
2888 			.name = "db8500-sva-mmdsp-ret",
2889 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2890 		},
2891 	},
2892 	[DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2893 		/* dependency to u8500-vape is handled outside regulator framework */
2894 		.constraints = {
2895 			.name = "db8500-sva-pipe",
2896 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2897 		},
2898 		.consumer_supplies = db8500_svapipe_consumers,
2899 		.num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2900 	},
2901 	[DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2902 		/* dependency to u8500-vape is handled outside regulator framework */
2903 		.constraints = {
2904 			.name = "db8500-sia-mmdsp",
2905 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2906 		},
2907 		.consumer_supplies = db8500_siammdsp_consumers,
2908 		.num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2909 	},
2910 	[DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2911 		.constraints = {
2912 			.name = "db8500-sia-mmdsp-ret",
2913 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2914 		},
2915 	},
2916 	[DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2917 		/* dependency to u8500-vape is handled outside regulator framework */
2918 		.constraints = {
2919 			.name = "db8500-sia-pipe",
2920 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2921 		},
2922 		.consumer_supplies = db8500_siapipe_consumers,
2923 		.num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2924 	},
2925 	[DB8500_REGULATOR_SWITCH_SGA] = {
2926 		.supply_regulator = "db8500-vape",
2927 		.constraints = {
2928 			.name = "db8500-sga",
2929 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2930 		},
2931 		.consumer_supplies = db8500_sga_consumers,
2932 		.num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2933 
2934 	},
2935 	[DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2936 		.supply_regulator = "db8500-vape",
2937 		.constraints = {
2938 			.name = "db8500-b2r2-mcde",
2939 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2940 		},
2941 		.consumer_supplies = db8500_b2r2_mcde_consumers,
2942 		.num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2943 	},
2944 	[DB8500_REGULATOR_SWITCH_ESRAM12] = {
2945 		/*
2946 		 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2947 		 * no need to hold Vape
2948 		 */
2949 		.constraints = {
2950 			.name = "db8500-esram12",
2951 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2952 		},
2953 		.consumer_supplies = db8500_esram12_consumers,
2954 		.num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2955 	},
2956 	[DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2957 		.constraints = {
2958 			.name = "db8500-esram12-ret",
2959 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2960 		},
2961 	},
2962 	[DB8500_REGULATOR_SWITCH_ESRAM34] = {
2963 		/*
2964 		 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2965 		 * no need to hold Vape
2966 		 */
2967 		.constraints = {
2968 			.name = "db8500-esram34",
2969 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2970 		},
2971 		.consumer_supplies = db8500_esram34_consumers,
2972 		.num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
2973 	},
2974 	[DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2975 		.constraints = {
2976 			.name = "db8500-esram34-ret",
2977 			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
2978 		},
2979 	},
2980 };
2981 
2982 static struct ux500_wdt_data db8500_wdt_pdata = {
2983 	.timeout = 600, /* 10 minutes */
2984 	.has_28_bits_resolution = true,
2985 };
2986 /*
2987  * Thermal Sensor
2988  */
2989 
2990 static struct resource db8500_thsens_resources[] = {
2991 	{
2992 		.name = "IRQ_HOTMON_LOW",
2993 		.start  = IRQ_PRCMU_HOTMON_LOW,
2994 		.end    = IRQ_PRCMU_HOTMON_LOW,
2995 		.flags  = IORESOURCE_IRQ,
2996 	},
2997 	{
2998 		.name = "IRQ_HOTMON_HIGH",
2999 		.start  = IRQ_PRCMU_HOTMON_HIGH,
3000 		.end    = IRQ_PRCMU_HOTMON_HIGH,
3001 		.flags  = IORESOURCE_IRQ,
3002 	},
3003 };
3004 
3005 static struct db8500_thsens_platform_data db8500_thsens_data = {
3006 	.trip_points[0] = {
3007 		.temp = 70000,
3008 		.type = THERMAL_TRIP_ACTIVE,
3009 		.cdev_name = {
3010 			[0] = "thermal-cpufreq-0",
3011 		},
3012 	},
3013 	.trip_points[1] = {
3014 		.temp = 75000,
3015 		.type = THERMAL_TRIP_ACTIVE,
3016 		.cdev_name = {
3017 			[0] = "thermal-cpufreq-0",
3018 		},
3019 	},
3020 	.trip_points[2] = {
3021 		.temp = 80000,
3022 		.type = THERMAL_TRIP_ACTIVE,
3023 		.cdev_name = {
3024 			[0] = "thermal-cpufreq-0",
3025 		},
3026 	},
3027 	.trip_points[3] = {
3028 		.temp = 85000,
3029 		.type = THERMAL_TRIP_CRITICAL,
3030 	},
3031 	.num_trips = 4,
3032 };
3033 
3034 static const struct mfd_cell common_prcmu_devs[] = {
3035 	{
3036 		.name = "ux500_wdt",
3037 		.platform_data = &db8500_wdt_pdata,
3038 		.pdata_size = sizeof(db8500_wdt_pdata),
3039 		.id = -1,
3040 	},
3041 };
3042 
3043 static const struct mfd_cell db8500_prcmu_devs[] = {
3044 	{
3045 		.name = "db8500-prcmu-regulators",
3046 		.of_compatible = "stericsson,db8500-prcmu-regulator",
3047 		.platform_data = &db8500_regulators,
3048 		.pdata_size = sizeof(db8500_regulators),
3049 	},
3050 	{
3051 		.name = "cpuidle-dbx500",
3052 		.of_compatible = "stericsson,cpuidle-dbx500",
3053 	},
3054 	{
3055 		.name = "db8500-thermal",
3056 		.num_resources = ARRAY_SIZE(db8500_thsens_resources),
3057 		.resources = db8500_thsens_resources,
3058 		.platform_data = &db8500_thsens_data,
3059 		.pdata_size = sizeof(db8500_thsens_data),
3060 	},
3061 };
3062 
3063 static int db8500_prcmu_register_ab8500(struct device *parent)
3064 {
3065 	struct device_node *np;
3066 	struct resource ab8500_resource;
3067 	const struct mfd_cell ab8500_cell = {
3068 		.name = "ab8500-core",
3069 		.of_compatible = "stericsson,ab8500",
3070 		.id = AB8500_VERSION_AB8500,
3071 		.resources = &ab8500_resource,
3072 		.num_resources = 1,
3073 	};
3074 
3075 	if (!parent->of_node)
3076 		return -ENODEV;
3077 
3078 	/* Look up the device node, sneak the IRQ out of it */
3079 	for_each_child_of_node(parent->of_node, np) {
3080 		if (of_device_is_compatible(np, ab8500_cell.of_compatible))
3081 			break;
3082 	}
3083 	if (!np) {
3084 		dev_info(parent, "could not find AB8500 node in the device tree\n");
3085 		return -ENODEV;
3086 	}
3087 	of_irq_to_resource_table(np, &ab8500_resource, 1);
3088 
3089 	return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3090 }
3091 
3092 /**
3093  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3094  *
3095  */
3096 static int db8500_prcmu_probe(struct platform_device *pdev)
3097 {
3098 	struct device_node *np = pdev->dev.of_node;
3099 	int irq = 0, err = 0;
3100 	struct resource *res;
3101 
3102 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3103 	if (!res) {
3104 		dev_err(&pdev->dev, "no prcmu memory region provided\n");
3105 		return -EINVAL;
3106 	}
3107 	prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3108 	if (!prcmu_base) {
3109 		dev_err(&pdev->dev,
3110 			"failed to ioremap prcmu register memory\n");
3111 		return -ENOMEM;
3112 	}
3113 	init_prcm_registers();
3114 	dbx500_fw_version_init(pdev, DB8500_PRCMU_FW_VERSION_OFFSET);
3115 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3116 	if (!res) {
3117 		dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3118 		return -EINVAL;
3119 	}
3120 	tcdm_base = devm_ioremap(&pdev->dev, res->start,
3121 			resource_size(res));
3122 	if (!tcdm_base) {
3123 		dev_err(&pdev->dev,
3124 			"failed to ioremap prcmu-tcdm register memory\n");
3125 		return -ENOMEM;
3126 	}
3127 
3128 	/* Clean up the mailbox interrupts after pre-kernel code. */
3129 	writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3130 
3131 	irq = platform_get_irq(pdev, 0);
3132 	if (irq <= 0) {
3133 		dev_err(&pdev->dev, "no prcmu irq provided\n");
3134 		return irq;
3135 	}
3136 
3137 	err = request_threaded_irq(irq, prcmu_irq_handler,
3138 	        prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3139 	if (err < 0) {
3140 		pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3141 		return err;
3142 	}
3143 
3144 	db8500_irq_init(np);
3145 
3146 	prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3147 
3148 	err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3149 			      ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3150 	if (err) {
3151 		pr_err("prcmu: Failed to add subdevices\n");
3152 		return err;
3153 	}
3154 
3155 	/* TODO: Remove restriction when clk definitions are available. */
3156 	if (!of_machine_is_compatible("st-ericsson,u8540")) {
3157 		err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3158 				      ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3159 				      db8500_irq_domain);
3160 		if (err) {
3161 			mfd_remove_devices(&pdev->dev);
3162 			pr_err("prcmu: Failed to add subdevices\n");
3163 			return err;
3164 		}
3165 	}
3166 
3167 	err = db8500_prcmu_register_ab8500(&pdev->dev);
3168 	if (err) {
3169 		mfd_remove_devices(&pdev->dev);
3170 		pr_err("prcmu: Failed to add ab8500 subdevice\n");
3171 		return err;
3172 	}
3173 
3174 	pr_info("DB8500 PRCMU initialized\n");
3175 	return err;
3176 }
3177 static const struct of_device_id db8500_prcmu_match[] = {
3178 	{ .compatible = "stericsson,db8500-prcmu"},
3179 	{ },
3180 };
3181 
3182 static struct platform_driver db8500_prcmu_driver = {
3183 	.driver = {
3184 		.name = "db8500-prcmu",
3185 		.of_match_table = db8500_prcmu_match,
3186 	},
3187 	.probe = db8500_prcmu_probe,
3188 };
3189 
3190 static int __init db8500_prcmu_init(void)
3191 {
3192 	return platform_driver_register(&db8500_prcmu_driver);
3193 }
3194 core_initcall(db8500_prcmu_init);
3195