1 /* 2 * Copyright (C) STMicroelectronics 2009 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * License Terms: GNU General Public License v2 6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7 * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9 * 10 * U8500 PRCM Unit interface driver 11 * 12 */ 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/delay.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/spinlock.h> 19 #include <linux/io.h> 20 #include <linux/slab.h> 21 #include <linux/mutex.h> 22 #include <linux/completion.h> 23 #include <linux/irq.h> 24 #include <linux/jiffies.h> 25 #include <linux/bitops.h> 26 #include <linux/fs.h> 27 #include <linux/platform_device.h> 28 #include <linux/uaccess.h> 29 #include <linux/mfd/core.h> 30 #include <linux/mfd/dbx500-prcmu.h> 31 #include <linux/regulator/db8500-prcmu.h> 32 #include <linux/regulator/machine.h> 33 #include <mach/hardware.h> 34 #include <mach/irqs.h> 35 #include <mach/db8500-regs.h> 36 #include <mach/id.h> 37 #include "dbx500-prcmu-regs.h" 38 39 /* Offset for the firmware version within the TCPM */ 40 #define PRCMU_FW_VERSION_OFFSET 0xA4 41 42 /* Index of different voltages to be used when accessing AVSData */ 43 #define PRCM_AVS_BASE 0x2FC 44 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 45 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 46 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 47 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 48 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 49 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 50 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 51 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 52 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 53 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 54 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 55 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 56 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 57 58 #define PRCM_AVS_VOLTAGE 0 59 #define PRCM_AVS_VOLTAGE_MASK 0x3f 60 #define PRCM_AVS_ISSLOWSTARTUP 6 61 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 62 #define PRCM_AVS_ISMODEENABLE 7 63 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 64 65 #define PRCM_BOOT_STATUS 0xFFF 66 #define PRCM_ROMCODE_A2P 0xFFE 67 #define PRCM_ROMCODE_P2A 0xFFD 68 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 69 70 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 71 72 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 73 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 74 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 75 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 76 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 77 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 78 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 79 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 80 81 /* Req Mailboxes */ 82 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 83 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 84 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 85 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 86 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 87 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 88 89 /* Ack Mailboxes */ 90 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 91 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 92 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 93 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 94 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 95 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 96 97 /* Mailbox 0 headers */ 98 #define MB0H_POWER_STATE_TRANS 0 99 #define MB0H_CONFIG_WAKEUPS_EXE 1 100 #define MB0H_READ_WAKEUP_ACK 3 101 #define MB0H_CONFIG_WAKEUPS_SLEEP 4 102 103 #define MB0H_WAKEUP_EXE 2 104 #define MB0H_WAKEUP_SLEEP 5 105 106 /* Mailbox 0 REQs */ 107 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 108 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 109 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 110 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 111 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 112 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 113 114 /* Mailbox 0 ACKs */ 115 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 116 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 117 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 118 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 119 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 120 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 121 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 122 123 /* Mailbox 1 headers */ 124 #define MB1H_ARM_APE_OPP 0x0 125 #define MB1H_RESET_MODEM 0x2 126 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 127 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 128 #define MB1H_RELEASE_USB_WAKEUP 0x5 129 #define MB1H_PLL_ON_OFF 0x6 130 131 /* Mailbox 1 Requests */ 132 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 133 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 134 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 135 #define PLL_SOC0_OFF 0x1 136 #define PLL_SOC0_ON 0x2 137 #define PLL_SOC1_OFF 0x4 138 #define PLL_SOC1_ON 0x8 139 140 /* Mailbox 1 ACKs */ 141 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 142 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 143 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 144 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 145 146 /* Mailbox 2 headers */ 147 #define MB2H_DPS 0x0 148 #define MB2H_AUTO_PWR 0x1 149 150 /* Mailbox 2 REQs */ 151 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 152 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 153 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 154 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 155 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 156 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 157 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 158 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 159 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 160 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 161 162 /* Mailbox 2 ACKs */ 163 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 164 #define HWACC_PWR_ST_OK 0xFE 165 166 /* Mailbox 3 headers */ 167 #define MB3H_ANC 0x0 168 #define MB3H_SIDETONE 0x1 169 #define MB3H_SYSCLK 0xE 170 171 /* Mailbox 3 Requests */ 172 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 173 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 174 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 175 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 176 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 177 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 178 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 179 180 /* Mailbox 4 headers */ 181 #define MB4H_DDR_INIT 0x0 182 #define MB4H_MEM_ST 0x1 183 #define MB4H_HOTDOG 0x12 184 #define MB4H_HOTMON 0x13 185 #define MB4H_HOT_PERIOD 0x14 186 #define MB4H_A9WDOG_CONF 0x16 187 #define MB4H_A9WDOG_EN 0x17 188 #define MB4H_A9WDOG_DIS 0x18 189 #define MB4H_A9WDOG_LOAD 0x19 190 #define MB4H_A9WDOG_KICK 0x20 191 192 /* Mailbox 4 Requests */ 193 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 194 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 195 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 196 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 197 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 198 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 199 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 200 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 201 #define HOTMON_CONFIG_LOW BIT(0) 202 #define HOTMON_CONFIG_HIGH BIT(1) 203 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 204 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 205 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 206 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 207 #define A9WDOG_AUTO_OFF_EN BIT(7) 208 #define A9WDOG_AUTO_OFF_DIS 0 209 #define A9WDOG_ID_MASK 0xf 210 211 /* Mailbox 5 Requests */ 212 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 213 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 214 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 215 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 216 #define PRCMU_I2C_WRITE(slave) \ 217 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) 218 #define PRCMU_I2C_READ(slave) \ 219 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) 220 #define PRCMU_I2C_STOP_EN BIT(3) 221 222 /* Mailbox 5 ACKs */ 223 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 224 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 225 #define I2C_WR_OK 0x1 226 #define I2C_RD_OK 0x2 227 228 #define NUM_MB 8 229 #define MBOX_BIT BIT 230 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 231 232 /* 233 * Wakeups/IRQs 234 */ 235 236 #define WAKEUP_BIT_RTC BIT(0) 237 #define WAKEUP_BIT_RTT0 BIT(1) 238 #define WAKEUP_BIT_RTT1 BIT(2) 239 #define WAKEUP_BIT_HSI0 BIT(3) 240 #define WAKEUP_BIT_HSI1 BIT(4) 241 #define WAKEUP_BIT_CA_WAKE BIT(5) 242 #define WAKEUP_BIT_USB BIT(6) 243 #define WAKEUP_BIT_ABB BIT(7) 244 #define WAKEUP_BIT_ABB_FIFO BIT(8) 245 #define WAKEUP_BIT_SYSCLK_OK BIT(9) 246 #define WAKEUP_BIT_CA_SLEEP BIT(10) 247 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 248 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 249 #define WAKEUP_BIT_ANC_OK BIT(13) 250 #define WAKEUP_BIT_SW_ERROR BIT(14) 251 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 252 #define WAKEUP_BIT_ARM BIT(17) 253 #define WAKEUP_BIT_HOTMON_LOW BIT(18) 254 #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 255 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 256 #define WAKEUP_BIT_GPIO0 BIT(23) 257 #define WAKEUP_BIT_GPIO1 BIT(24) 258 #define WAKEUP_BIT_GPIO2 BIT(25) 259 #define WAKEUP_BIT_GPIO3 BIT(26) 260 #define WAKEUP_BIT_GPIO4 BIT(27) 261 #define WAKEUP_BIT_GPIO5 BIT(28) 262 #define WAKEUP_BIT_GPIO6 BIT(29) 263 #define WAKEUP_BIT_GPIO7 BIT(30) 264 #define WAKEUP_BIT_GPIO8 BIT(31) 265 266 static struct { 267 bool valid; 268 struct prcmu_fw_version version; 269 } fw_info; 270 271 /* 272 * This vector maps irq numbers to the bits in the bit field used in 273 * communication with the PRCMU firmware. 274 * 275 * The reason for having this is to keep the irq numbers contiguous even though 276 * the bits in the bit field are not. (The bits also have a tendency to move 277 * around, to further complicate matters.) 278 */ 279 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) 280 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 281 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 282 IRQ_ENTRY(RTC), 283 IRQ_ENTRY(RTT0), 284 IRQ_ENTRY(RTT1), 285 IRQ_ENTRY(HSI0), 286 IRQ_ENTRY(HSI1), 287 IRQ_ENTRY(CA_WAKE), 288 IRQ_ENTRY(USB), 289 IRQ_ENTRY(ABB), 290 IRQ_ENTRY(ABB_FIFO), 291 IRQ_ENTRY(CA_SLEEP), 292 IRQ_ENTRY(ARM), 293 IRQ_ENTRY(HOTMON_LOW), 294 IRQ_ENTRY(HOTMON_HIGH), 295 IRQ_ENTRY(MODEM_SW_RESET_REQ), 296 IRQ_ENTRY(GPIO0), 297 IRQ_ENTRY(GPIO1), 298 IRQ_ENTRY(GPIO2), 299 IRQ_ENTRY(GPIO3), 300 IRQ_ENTRY(GPIO4), 301 IRQ_ENTRY(GPIO5), 302 IRQ_ENTRY(GPIO6), 303 IRQ_ENTRY(GPIO7), 304 IRQ_ENTRY(GPIO8) 305 }; 306 307 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 308 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 309 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 310 WAKEUP_ENTRY(RTC), 311 WAKEUP_ENTRY(RTT0), 312 WAKEUP_ENTRY(RTT1), 313 WAKEUP_ENTRY(HSI0), 314 WAKEUP_ENTRY(HSI1), 315 WAKEUP_ENTRY(USB), 316 WAKEUP_ENTRY(ABB), 317 WAKEUP_ENTRY(ABB_FIFO), 318 WAKEUP_ENTRY(ARM) 319 }; 320 321 /* 322 * mb0_transfer - state needed for mailbox 0 communication. 323 * @lock: The transaction lock. 324 * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 325 * the request data. 326 * @mask_work: Work structure used for (un)masking wakeup interrupts. 327 * @req: Request data that need to persist between requests. 328 */ 329 static struct { 330 spinlock_t lock; 331 spinlock_t dbb_irqs_lock; 332 struct work_struct mask_work; 333 struct mutex ac_wake_lock; 334 struct completion ac_wake_work; 335 struct { 336 u32 dbb_irqs; 337 u32 dbb_wakeups; 338 u32 abb_events; 339 } req; 340 } mb0_transfer; 341 342 /* 343 * mb1_transfer - state needed for mailbox 1 communication. 344 * @lock: The transaction lock. 345 * @work: The transaction completion structure. 346 * @ack: Reply ("acknowledge") data. 347 */ 348 static struct { 349 struct mutex lock; 350 struct completion work; 351 struct { 352 u8 header; 353 u8 arm_opp; 354 u8 ape_opp; 355 u8 ape_voltage_status; 356 } ack; 357 } mb1_transfer; 358 359 /* 360 * mb2_transfer - state needed for mailbox 2 communication. 361 * @lock: The transaction lock. 362 * @work: The transaction completion structure. 363 * @auto_pm_lock: The autonomous power management configuration lock. 364 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 365 * @req: Request data that need to persist between requests. 366 * @ack: Reply ("acknowledge") data. 367 */ 368 static struct { 369 struct mutex lock; 370 struct completion work; 371 spinlock_t auto_pm_lock; 372 bool auto_pm_enabled; 373 struct { 374 u8 status; 375 } ack; 376 } mb2_transfer; 377 378 /* 379 * mb3_transfer - state needed for mailbox 3 communication. 380 * @lock: The request lock. 381 * @sysclk_lock: A lock used to handle concurrent sysclk requests. 382 * @sysclk_work: Work structure used for sysclk requests. 383 */ 384 static struct { 385 spinlock_t lock; 386 struct mutex sysclk_lock; 387 struct completion sysclk_work; 388 } mb3_transfer; 389 390 /* 391 * mb4_transfer - state needed for mailbox 4 communication. 392 * @lock: The transaction lock. 393 * @work: The transaction completion structure. 394 */ 395 static struct { 396 struct mutex lock; 397 struct completion work; 398 } mb4_transfer; 399 400 /* 401 * mb5_transfer - state needed for mailbox 5 communication. 402 * @lock: The transaction lock. 403 * @work: The transaction completion structure. 404 * @ack: Reply ("acknowledge") data. 405 */ 406 static struct { 407 struct mutex lock; 408 struct completion work; 409 struct { 410 u8 status; 411 u8 value; 412 } ack; 413 } mb5_transfer; 414 415 static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 416 417 /* Spinlocks */ 418 static DEFINE_SPINLOCK(clkout_lock); 419 static DEFINE_SPINLOCK(gpiocr_lock); 420 421 /* Global var to runtime determine TCDM base for v2 or v1 */ 422 static __iomem void *tcdm_base; 423 424 struct clk_mgt { 425 void __iomem *reg; 426 u32 pllsw; 427 int branch; 428 bool clk38div; 429 }; 430 431 enum { 432 PLL_RAW, 433 PLL_FIX, 434 PLL_DIV 435 }; 436 437 static DEFINE_SPINLOCK(clk_mgt_lock); 438 439 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 440 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 441 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 442 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 443 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 444 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 445 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 446 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 447 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 448 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 449 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 450 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 451 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 452 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 453 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 454 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 455 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 456 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 457 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 458 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 459 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 460 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 461 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 462 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 463 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 464 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 465 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 466 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 467 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 468 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 469 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 470 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 471 }; 472 473 struct dsiclk { 474 u32 divsel_mask; 475 u32 divsel_shift; 476 u32 divsel; 477 }; 478 479 static struct dsiclk dsiclk[2] = { 480 { 481 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 482 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 483 .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 484 }, 485 { 486 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 487 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 488 .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 489 } 490 }; 491 492 struct dsiescclk { 493 u32 en; 494 u32 div_mask; 495 u32 div_shift; 496 }; 497 498 static struct dsiescclk dsiescclk[3] = { 499 { 500 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 501 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 502 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 503 }, 504 { 505 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 506 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 507 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 508 }, 509 { 510 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 511 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 512 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 513 } 514 }; 515 516 static struct regulator *hwacc_regulator[NUM_HW_ACC]; 517 static struct regulator *hwacc_ret_regulator[NUM_HW_ACC]; 518 519 static bool hwacc_enabled[NUM_HW_ACC]; 520 static bool hwacc_ret_enabled[NUM_HW_ACC]; 521 522 static const char *hwacc_regulator_name[NUM_HW_ACC] = { 523 [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp", 524 [HW_ACC_SVAPIPE] = "hwacc-sva-pipe", 525 [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp", 526 [HW_ACC_SIAPIPE] = "hwacc-sia-pipe", 527 [HW_ACC_SGA] = "hwacc-sga", 528 [HW_ACC_B2R2] = "hwacc-b2r2", 529 [HW_ACC_MCDE] = "hwacc-mcde", 530 [HW_ACC_ESRAM1] = "hwacc-esram1", 531 [HW_ACC_ESRAM2] = "hwacc-esram2", 532 [HW_ACC_ESRAM3] = "hwacc-esram3", 533 [HW_ACC_ESRAM4] = "hwacc-esram4", 534 }; 535 536 static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { 537 [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp-ret", 538 [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp-ret", 539 [HW_ACC_ESRAM1] = "hwacc-esram1-ret", 540 [HW_ACC_ESRAM2] = "hwacc-esram2-ret", 541 [HW_ACC_ESRAM3] = "hwacc-esram3-ret", 542 [HW_ACC_ESRAM4] = "hwacc-esram4-ret", 543 }; 544 545 /* 546 * Used by MCDE to setup all necessary PRCMU registers 547 */ 548 #define PRCMU_RESET_DSIPLL 0x00004000 549 #define PRCMU_UNCLAMP_DSIPLL 0x00400800 550 551 #define PRCMU_CLK_PLL_DIV_SHIFT 0 552 #define PRCMU_CLK_PLL_SW_SHIFT 5 553 #define PRCMU_CLK_38 (1 << 9) 554 #define PRCMU_CLK_38_SRC (1 << 10) 555 #define PRCMU_CLK_38_DIV (1 << 11) 556 557 /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 558 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 559 560 /* DPI 50000000 Hz */ 561 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 562 (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 563 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 564 565 /* D=101, N=1, R=4, SELDIV2=0 */ 566 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 567 568 #define PRCMU_ENABLE_PLLDSI 0x00000001 569 #define PRCMU_DISABLE_PLLDSI 0x00000000 570 #define PRCMU_RELEASE_RESET_DSS 0x0000400C 571 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 572 /* ESC clk, div0=1, div1=1, div2=3 */ 573 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 574 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 575 #define PRCMU_DSI_RESET_SW 0x00000007 576 577 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 578 579 int db8500_prcmu_enable_dsipll(void) 580 { 581 int i; 582 583 /* Clear DSIPLL_RESETN */ 584 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 585 /* Unclamp DSIPLL in/out */ 586 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 587 588 /* Set DSI PLL FREQ */ 589 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 590 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 591 /* Enable Escape clocks */ 592 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 593 594 /* Start DSI PLL */ 595 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 596 /* Reset DSI PLL */ 597 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 598 for (i = 0; i < 10; i++) { 599 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 600 == PRCMU_PLLDSI_LOCKP_LOCKED) 601 break; 602 udelay(100); 603 } 604 /* Set DSIPLL_RESETN */ 605 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 606 return 0; 607 } 608 609 int db8500_prcmu_disable_dsipll(void) 610 { 611 /* Disable dsi pll */ 612 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 613 /* Disable escapeclock */ 614 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 615 return 0; 616 } 617 618 int db8500_prcmu_set_display_clocks(void) 619 { 620 unsigned long flags; 621 622 spin_lock_irqsave(&clk_mgt_lock, flags); 623 624 /* Grab the HW semaphore. */ 625 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 626 cpu_relax(); 627 628 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); 629 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); 630 writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); 631 632 /* Release the HW semaphore. */ 633 writel(0, PRCM_SEM); 634 635 spin_unlock_irqrestore(&clk_mgt_lock, flags); 636 637 return 0; 638 } 639 640 /** 641 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. 642 */ 643 void prcmu_enable_spi2(void) 644 { 645 u32 reg; 646 unsigned long flags; 647 648 spin_lock_irqsave(&gpiocr_lock, flags); 649 reg = readl(PRCM_GPIOCR); 650 writel(reg | PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); 651 spin_unlock_irqrestore(&gpiocr_lock, flags); 652 } 653 654 /** 655 * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. 656 */ 657 void prcmu_disable_spi2(void) 658 { 659 u32 reg; 660 unsigned long flags; 661 662 spin_lock_irqsave(&gpiocr_lock, flags); 663 reg = readl(PRCM_GPIOCR); 664 writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); 665 spin_unlock_irqrestore(&gpiocr_lock, flags); 666 } 667 668 struct prcmu_fw_version *prcmu_get_fw_version(void) 669 { 670 return fw_info.valid ? &fw_info.version : NULL; 671 } 672 673 bool prcmu_has_arm_maxopp(void) 674 { 675 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 676 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 677 } 678 679 /** 680 * prcmu_get_boot_status - PRCMU boot status checking 681 * Returns: the current PRCMU boot status 682 */ 683 int prcmu_get_boot_status(void) 684 { 685 return readb(tcdm_base + PRCM_BOOT_STATUS); 686 } 687 688 /** 689 * prcmu_set_rc_a2p - This function is used to run few power state sequences 690 * @val: Value to be set, i.e. transition requested 691 * Returns: 0 on success, -EINVAL on invalid argument 692 * 693 * This function is used to run the following power state sequences - 694 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 695 */ 696 int prcmu_set_rc_a2p(enum romcode_write val) 697 { 698 if (val < RDY_2_DS || val > RDY_2_XP70_RST) 699 return -EINVAL; 700 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 701 return 0; 702 } 703 704 /** 705 * prcmu_get_rc_p2a - This function is used to get power state sequences 706 * Returns: the power transition that has last happened 707 * 708 * This function can return the following transitions- 709 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 710 */ 711 enum romcode_read prcmu_get_rc_p2a(void) 712 { 713 return readb(tcdm_base + PRCM_ROMCODE_P2A); 714 } 715 716 /** 717 * prcmu_get_current_mode - Return the current XP70 power mode 718 * Returns: Returns the current AP(ARM) power mode: init, 719 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 720 */ 721 enum ap_pwrst prcmu_get_xp70_current_state(void) 722 { 723 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 724 } 725 726 /** 727 * prcmu_config_clkout - Configure one of the programmable clock outputs. 728 * @clkout: The CLKOUT number (0 or 1). 729 * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 730 * @div: The divider to be applied. 731 * 732 * Configures one of the programmable clock outputs (CLKOUTs). 733 * @div should be in the range [1,63] to request a configuration, or 0 to 734 * inform that the configuration is no longer requested. 735 */ 736 int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 737 { 738 static int requests[2]; 739 int r = 0; 740 unsigned long flags; 741 u32 val; 742 u32 bits; 743 u32 mask; 744 u32 div_mask; 745 746 BUG_ON(clkout > 1); 747 BUG_ON(div > 63); 748 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 749 750 if (!div && !requests[clkout]) 751 return -EINVAL; 752 753 switch (clkout) { 754 case 0: 755 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 756 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 757 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 758 (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 759 break; 760 case 1: 761 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 762 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 763 PRCM_CLKOCR_CLK1TYPE); 764 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 765 (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 766 break; 767 } 768 bits &= mask; 769 770 spin_lock_irqsave(&clkout_lock, flags); 771 772 val = readl(PRCM_CLKOCR); 773 if (val & div_mask) { 774 if (div) { 775 if ((val & mask) != bits) { 776 r = -EBUSY; 777 goto unlock_and_return; 778 } 779 } else { 780 if ((val & mask & ~div_mask) != bits) { 781 r = -EINVAL; 782 goto unlock_and_return; 783 } 784 } 785 } 786 writel((bits | (val & ~mask)), PRCM_CLKOCR); 787 requests[clkout] += (div ? 1 : -1); 788 789 unlock_and_return: 790 spin_unlock_irqrestore(&clkout_lock, flags); 791 792 return r; 793 } 794 795 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 796 { 797 unsigned long flags; 798 799 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 800 801 spin_lock_irqsave(&mb0_transfer.lock, flags); 802 803 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 804 cpu_relax(); 805 806 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 807 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 808 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 809 writeb((keep_ulp_clk ? 1 : 0), 810 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 811 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 812 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 813 814 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 815 816 return 0; 817 } 818 819 /* This function should only be called while mb0_transfer.lock is held. */ 820 static void config_wakeups(void) 821 { 822 const u8 header[2] = { 823 MB0H_CONFIG_WAKEUPS_EXE, 824 MB0H_CONFIG_WAKEUPS_SLEEP 825 }; 826 static u32 last_dbb_events; 827 static u32 last_abb_events; 828 u32 dbb_events; 829 u32 abb_events; 830 unsigned int i; 831 832 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 833 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 834 835 abb_events = mb0_transfer.req.abb_events; 836 837 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 838 return; 839 840 for (i = 0; i < 2; i++) { 841 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 842 cpu_relax(); 843 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 844 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 845 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 846 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 847 } 848 last_dbb_events = dbb_events; 849 last_abb_events = abb_events; 850 } 851 852 void db8500_prcmu_enable_wakeups(u32 wakeups) 853 { 854 unsigned long flags; 855 u32 bits; 856 int i; 857 858 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 859 860 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 861 if (wakeups & BIT(i)) 862 bits |= prcmu_wakeup_bit[i]; 863 } 864 865 spin_lock_irqsave(&mb0_transfer.lock, flags); 866 867 mb0_transfer.req.dbb_wakeups = bits; 868 config_wakeups(); 869 870 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 871 } 872 873 void db8500_prcmu_config_abb_event_readout(u32 abb_events) 874 { 875 unsigned long flags; 876 877 spin_lock_irqsave(&mb0_transfer.lock, flags); 878 879 mb0_transfer.req.abb_events = abb_events; 880 config_wakeups(); 881 882 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 883 } 884 885 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 886 { 887 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 888 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 889 else 890 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 891 } 892 893 /** 894 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 895 * @opp: The new ARM operating point to which transition is to be made 896 * Returns: 0 on success, non-zero on failure 897 * 898 * This function sets the the operating point of the ARM. 899 */ 900 int db8500_prcmu_set_arm_opp(u8 opp) 901 { 902 int r; 903 904 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 905 return -EINVAL; 906 907 r = 0; 908 909 mutex_lock(&mb1_transfer.lock); 910 911 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 912 cpu_relax(); 913 914 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 915 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 916 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 917 918 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 919 wait_for_completion(&mb1_transfer.work); 920 921 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 922 (mb1_transfer.ack.arm_opp != opp)) 923 r = -EIO; 924 925 mutex_unlock(&mb1_transfer.lock); 926 927 return r; 928 } 929 930 /** 931 * db8500_prcmu_get_arm_opp - get the current ARM OPP 932 * 933 * Returns: the current ARM OPP 934 */ 935 int db8500_prcmu_get_arm_opp(void) 936 { 937 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 938 } 939 940 /** 941 * db8500_prcmu_get_ddr_opp - get the current DDR OPP 942 * 943 * Returns: the current DDR OPP 944 */ 945 int db8500_prcmu_get_ddr_opp(void) 946 { 947 return readb(PRCM_DDR_SUBSYS_APE_MINBW); 948 } 949 950 /** 951 * db8500_set_ddr_opp - set the appropriate DDR OPP 952 * @opp: The new DDR operating point to which transition is to be made 953 * Returns: 0 on success, non-zero on failure 954 * 955 * This function sets the operating point of the DDR. 956 */ 957 int db8500_prcmu_set_ddr_opp(u8 opp) 958 { 959 if (opp < DDR_100_OPP || opp > DDR_25_OPP) 960 return -EINVAL; 961 /* Changing the DDR OPP can hang the hardware pre-v21 */ 962 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) 963 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 964 965 return 0; 966 } 967 968 /** 969 * db8500_set_ape_opp - set the appropriate APE OPP 970 * @opp: The new APE operating point to which transition is to be made 971 * Returns: 0 on success, non-zero on failure 972 * 973 * This function sets the operating point of the APE. 974 */ 975 int db8500_prcmu_set_ape_opp(u8 opp) 976 { 977 int r = 0; 978 979 mutex_lock(&mb1_transfer.lock); 980 981 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 982 cpu_relax(); 983 984 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 985 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 986 writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 987 988 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 989 wait_for_completion(&mb1_transfer.work); 990 991 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 992 (mb1_transfer.ack.ape_opp != opp)) 993 r = -EIO; 994 995 mutex_unlock(&mb1_transfer.lock); 996 997 return r; 998 } 999 1000 /** 1001 * db8500_prcmu_get_ape_opp - get the current APE OPP 1002 * 1003 * Returns: the current APE OPP 1004 */ 1005 int db8500_prcmu_get_ape_opp(void) 1006 { 1007 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 1008 } 1009 1010 /** 1011 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 1012 * @enable: true to request the higher voltage, false to drop a request. 1013 * 1014 * Calls to this function to enable and disable requests must be balanced. 1015 */ 1016 int prcmu_request_ape_opp_100_voltage(bool enable) 1017 { 1018 int r = 0; 1019 u8 header; 1020 static unsigned int requests; 1021 1022 mutex_lock(&mb1_transfer.lock); 1023 1024 if (enable) { 1025 if (0 != requests++) 1026 goto unlock_and_return; 1027 header = MB1H_REQUEST_APE_OPP_100_VOLT; 1028 } else { 1029 if (requests == 0) { 1030 r = -EIO; 1031 goto unlock_and_return; 1032 } else if (1 != requests--) { 1033 goto unlock_and_return; 1034 } 1035 header = MB1H_RELEASE_APE_OPP_100_VOLT; 1036 } 1037 1038 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1039 cpu_relax(); 1040 1041 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1042 1043 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1044 wait_for_completion(&mb1_transfer.work); 1045 1046 if ((mb1_transfer.ack.header != header) || 1047 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 1048 r = -EIO; 1049 1050 unlock_and_return: 1051 mutex_unlock(&mb1_transfer.lock); 1052 1053 return r; 1054 } 1055 1056 /** 1057 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 1058 * 1059 * This function releases the power state requirements of a USB wakeup. 1060 */ 1061 int prcmu_release_usb_wakeup_state(void) 1062 { 1063 int r = 0; 1064 1065 mutex_lock(&mb1_transfer.lock); 1066 1067 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1068 cpu_relax(); 1069 1070 writeb(MB1H_RELEASE_USB_WAKEUP, 1071 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1072 1073 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1074 wait_for_completion(&mb1_transfer.work); 1075 1076 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 1077 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 1078 r = -EIO; 1079 1080 mutex_unlock(&mb1_transfer.lock); 1081 1082 return r; 1083 } 1084 1085 static int request_pll(u8 clock, bool enable) 1086 { 1087 int r = 0; 1088 1089 if (clock == PRCMU_PLLSOC0) 1090 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 1091 else if (clock == PRCMU_PLLSOC1) 1092 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 1093 else 1094 return -EINVAL; 1095 1096 mutex_lock(&mb1_transfer.lock); 1097 1098 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1099 cpu_relax(); 1100 1101 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1102 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 1103 1104 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1105 wait_for_completion(&mb1_transfer.work); 1106 1107 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 1108 r = -EIO; 1109 1110 mutex_unlock(&mb1_transfer.lock); 1111 1112 return r; 1113 } 1114 1115 /** 1116 * prcmu_set_hwacc - set the power state of a h/w accelerator 1117 * @hwacc_dev: The hardware accelerator (enum hw_acc_dev). 1118 * @state: The new power state (enum hw_acc_state). 1119 * 1120 * This function sets the power state of a hardware accelerator. 1121 * This function should not be called from interrupt context. 1122 * 1123 * NOTE! Deprecated, to be removed when all users switched over to use the 1124 * regulator framework API. 1125 */ 1126 int prcmu_set_hwacc(u16 hwacc_dev, u8 state) 1127 { 1128 int r = 0; 1129 bool ram_retention = false; 1130 bool enable, enable_ret; 1131 1132 /* check argument */ 1133 BUG_ON(hwacc_dev >= NUM_HW_ACC); 1134 1135 /* get state of switches */ 1136 enable = hwacc_enabled[hwacc_dev]; 1137 enable_ret = hwacc_ret_enabled[hwacc_dev]; 1138 1139 /* set flag if retention is possible */ 1140 switch (hwacc_dev) { 1141 case HW_ACC_SVAMMDSP: 1142 case HW_ACC_SIAMMDSP: 1143 case HW_ACC_ESRAM1: 1144 case HW_ACC_ESRAM2: 1145 case HW_ACC_ESRAM3: 1146 case HW_ACC_ESRAM4: 1147 ram_retention = true; 1148 break; 1149 } 1150 1151 /* check argument */ 1152 BUG_ON(state > HW_ON); 1153 BUG_ON(state == HW_OFF_RAMRET && !ram_retention); 1154 1155 /* modify enable flags */ 1156 switch (state) { 1157 case HW_OFF: 1158 enable_ret = false; 1159 enable = false; 1160 break; 1161 case HW_ON: 1162 enable = true; 1163 break; 1164 case HW_OFF_RAMRET: 1165 enable_ret = true; 1166 enable = false; 1167 break; 1168 } 1169 1170 /* get regulator (lazy) */ 1171 if (hwacc_regulator[hwacc_dev] == NULL) { 1172 hwacc_regulator[hwacc_dev] = regulator_get(NULL, 1173 hwacc_regulator_name[hwacc_dev]); 1174 if (IS_ERR(hwacc_regulator[hwacc_dev])) { 1175 pr_err("prcmu: failed to get supply %s\n", 1176 hwacc_regulator_name[hwacc_dev]); 1177 r = PTR_ERR(hwacc_regulator[hwacc_dev]); 1178 goto out; 1179 } 1180 } 1181 1182 if (ram_retention) { 1183 if (hwacc_ret_regulator[hwacc_dev] == NULL) { 1184 hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL, 1185 hwacc_ret_regulator_name[hwacc_dev]); 1186 if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) { 1187 pr_err("prcmu: failed to get supply %s\n", 1188 hwacc_ret_regulator_name[hwacc_dev]); 1189 r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]); 1190 goto out; 1191 } 1192 } 1193 } 1194 1195 /* set regulators */ 1196 if (ram_retention) { 1197 if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) { 1198 r = regulator_enable(hwacc_ret_regulator[hwacc_dev]); 1199 if (r < 0) { 1200 pr_err("prcmu_set_hwacc: ret enable failed\n"); 1201 goto out; 1202 } 1203 hwacc_ret_enabled[hwacc_dev] = true; 1204 } 1205 } 1206 1207 if (enable && !hwacc_enabled[hwacc_dev]) { 1208 r = regulator_enable(hwacc_regulator[hwacc_dev]); 1209 if (r < 0) { 1210 pr_err("prcmu_set_hwacc: enable failed\n"); 1211 goto out; 1212 } 1213 hwacc_enabled[hwacc_dev] = true; 1214 } 1215 1216 if (!enable && hwacc_enabled[hwacc_dev]) { 1217 r = regulator_disable(hwacc_regulator[hwacc_dev]); 1218 if (r < 0) { 1219 pr_err("prcmu_set_hwacc: disable failed\n"); 1220 goto out; 1221 } 1222 hwacc_enabled[hwacc_dev] = false; 1223 } 1224 1225 if (ram_retention) { 1226 if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) { 1227 r = regulator_disable(hwacc_ret_regulator[hwacc_dev]); 1228 if (r < 0) { 1229 pr_err("prcmu_set_hwacc: ret disable failed\n"); 1230 goto out; 1231 } 1232 hwacc_ret_enabled[hwacc_dev] = false; 1233 } 1234 } 1235 1236 out: 1237 return r; 1238 } 1239 EXPORT_SYMBOL(prcmu_set_hwacc); 1240 1241 /** 1242 * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 1243 * @epod_id: The EPOD to set 1244 * @epod_state: The new EPOD state 1245 * 1246 * This function sets the state of a EPOD (power domain). It may not be called 1247 * from interrupt context. 1248 */ 1249 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 1250 { 1251 int r = 0; 1252 bool ram_retention = false; 1253 int i; 1254 1255 /* check argument */ 1256 BUG_ON(epod_id >= NUM_EPOD_ID); 1257 1258 /* set flag if retention is possible */ 1259 switch (epod_id) { 1260 case EPOD_ID_SVAMMDSP: 1261 case EPOD_ID_SIAMMDSP: 1262 case EPOD_ID_ESRAM12: 1263 case EPOD_ID_ESRAM34: 1264 ram_retention = true; 1265 break; 1266 } 1267 1268 /* check argument */ 1269 BUG_ON(epod_state > EPOD_STATE_ON); 1270 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 1271 1272 /* get lock */ 1273 mutex_lock(&mb2_transfer.lock); 1274 1275 /* wait for mailbox */ 1276 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 1277 cpu_relax(); 1278 1279 /* fill in mailbox */ 1280 for (i = 0; i < NUM_EPOD_ID; i++) 1281 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 1282 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 1283 1284 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 1285 1286 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 1287 1288 /* 1289 * The current firmware version does not handle errors correctly, 1290 * and we cannot recover if there is an error. 1291 * This is expected to change when the firmware is updated. 1292 */ 1293 if (!wait_for_completion_timeout(&mb2_transfer.work, 1294 msecs_to_jiffies(20000))) { 1295 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 1296 __func__); 1297 r = -EIO; 1298 goto unlock_and_return; 1299 } 1300 1301 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 1302 r = -EIO; 1303 1304 unlock_and_return: 1305 mutex_unlock(&mb2_transfer.lock); 1306 return r; 1307 } 1308 1309 /** 1310 * prcmu_configure_auto_pm - Configure autonomous power management. 1311 * @sleep: Configuration for ApSleep. 1312 * @idle: Configuration for ApIdle. 1313 */ 1314 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 1315 struct prcmu_auto_pm_config *idle) 1316 { 1317 u32 sleep_cfg; 1318 u32 idle_cfg; 1319 unsigned long flags; 1320 1321 BUG_ON((sleep == NULL) || (idle == NULL)); 1322 1323 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 1324 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 1325 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 1326 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 1327 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 1328 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 1329 1330 idle_cfg = (idle->sva_auto_pm_enable & 0xF); 1331 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 1332 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 1333 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 1334 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 1335 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 1336 1337 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 1338 1339 /* 1340 * The autonomous power management configuration is done through 1341 * fields in mailbox 2, but these fields are only used as shared 1342 * variables - i.e. there is no need to send a message. 1343 */ 1344 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 1345 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 1346 1347 mb2_transfer.auto_pm_enabled = 1348 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 1349 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 1350 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 1351 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 1352 1353 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 1354 } 1355 EXPORT_SYMBOL(prcmu_configure_auto_pm); 1356 1357 bool prcmu_is_auto_pm_enabled(void) 1358 { 1359 return mb2_transfer.auto_pm_enabled; 1360 } 1361 1362 static int request_sysclk(bool enable) 1363 { 1364 int r; 1365 unsigned long flags; 1366 1367 r = 0; 1368 1369 mutex_lock(&mb3_transfer.sysclk_lock); 1370 1371 spin_lock_irqsave(&mb3_transfer.lock, flags); 1372 1373 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 1374 cpu_relax(); 1375 1376 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 1377 1378 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1379 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 1380 1381 spin_unlock_irqrestore(&mb3_transfer.lock, flags); 1382 1383 /* 1384 * The firmware only sends an ACK if we want to enable the 1385 * SysClk, and it succeeds. 1386 */ 1387 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 1388 msecs_to_jiffies(20000))) { 1389 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 1390 __func__); 1391 r = -EIO; 1392 } 1393 1394 mutex_unlock(&mb3_transfer.sysclk_lock); 1395 1396 return r; 1397 } 1398 1399 static int request_timclk(bool enable) 1400 { 1401 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 1402 1403 if (!enable) 1404 val |= PRCM_TCR_STOP_TIMERS; 1405 writel(val, PRCM_TCR); 1406 1407 return 0; 1408 } 1409 1410 static int request_clock(u8 clock, bool enable) 1411 { 1412 u32 val; 1413 unsigned long flags; 1414 1415 spin_lock_irqsave(&clk_mgt_lock, flags); 1416 1417 /* Grab the HW semaphore. */ 1418 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 1419 cpu_relax(); 1420 1421 val = readl(clk_mgt[clock].reg); 1422 if (enable) { 1423 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 1424 } else { 1425 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 1426 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 1427 } 1428 writel(val, clk_mgt[clock].reg); 1429 1430 /* Release the HW semaphore. */ 1431 writel(0, PRCM_SEM); 1432 1433 spin_unlock_irqrestore(&clk_mgt_lock, flags); 1434 1435 return 0; 1436 } 1437 1438 static int request_sga_clock(u8 clock, bool enable) 1439 { 1440 u32 val; 1441 int ret; 1442 1443 if (enable) { 1444 val = readl(PRCM_CGATING_BYPASS); 1445 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 1446 } 1447 1448 ret = request_clock(clock, enable); 1449 1450 if (!ret && !enable) { 1451 val = readl(PRCM_CGATING_BYPASS); 1452 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 1453 } 1454 1455 return ret; 1456 } 1457 1458 static inline bool plldsi_locked(void) 1459 { 1460 return (readl(PRCM_PLLDSI_LOCKP) & 1461 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 1462 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 1463 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 1464 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 1465 } 1466 1467 static int request_plldsi(bool enable) 1468 { 1469 int r = 0; 1470 u32 val; 1471 1472 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 1473 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 1474 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 1475 1476 val = readl(PRCM_PLLDSI_ENABLE); 1477 if (enable) 1478 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 1479 else 1480 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 1481 writel(val, PRCM_PLLDSI_ENABLE); 1482 1483 if (enable) { 1484 unsigned int i; 1485 bool locked = plldsi_locked(); 1486 1487 for (i = 10; !locked && (i > 0); --i) { 1488 udelay(100); 1489 locked = plldsi_locked(); 1490 } 1491 if (locked) { 1492 writel(PRCM_APE_RESETN_DSIPLL_RESETN, 1493 PRCM_APE_RESETN_SET); 1494 } else { 1495 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 1496 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 1497 PRCM_MMIP_LS_CLAMP_SET); 1498 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 1499 writel(val, PRCM_PLLDSI_ENABLE); 1500 r = -EAGAIN; 1501 } 1502 } else { 1503 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 1504 } 1505 return r; 1506 } 1507 1508 static int request_dsiclk(u8 n, bool enable) 1509 { 1510 u32 val; 1511 1512 val = readl(PRCM_DSI_PLLOUT_SEL); 1513 val &= ~dsiclk[n].divsel_mask; 1514 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 1515 dsiclk[n].divsel_shift); 1516 writel(val, PRCM_DSI_PLLOUT_SEL); 1517 return 0; 1518 } 1519 1520 static int request_dsiescclk(u8 n, bool enable) 1521 { 1522 u32 val; 1523 1524 val = readl(PRCM_DSITVCLK_DIV); 1525 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 1526 writel(val, PRCM_DSITVCLK_DIV); 1527 return 0; 1528 } 1529 1530 /** 1531 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 1532 * @clock: The clock for which the request is made. 1533 * @enable: Whether the clock should be enabled (true) or disabled (false). 1534 * 1535 * This function should only be used by the clock implementation. 1536 * Do not use it from any other place! 1537 */ 1538 int db8500_prcmu_request_clock(u8 clock, bool enable) 1539 { 1540 if (clock == PRCMU_SGACLK) 1541 return request_sga_clock(clock, enable); 1542 else if (clock < PRCMU_NUM_REG_CLOCKS) 1543 return request_clock(clock, enable); 1544 else if (clock == PRCMU_TIMCLK) 1545 return request_timclk(enable); 1546 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1547 return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 1548 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1549 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 1550 else if (clock == PRCMU_PLLDSI) 1551 return request_plldsi(enable); 1552 else if (clock == PRCMU_SYSCLK) 1553 return request_sysclk(enable); 1554 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 1555 return request_pll(clock, enable); 1556 else 1557 return -EINVAL; 1558 } 1559 1560 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 1561 int branch) 1562 { 1563 u64 rate; 1564 u32 val; 1565 u32 d; 1566 u32 div = 1; 1567 1568 val = readl(reg); 1569 1570 rate = src_rate; 1571 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 1572 1573 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 1574 if (d > 1) 1575 div *= d; 1576 1577 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 1578 if (d > 1) 1579 div *= d; 1580 1581 if (val & PRCM_PLL_FREQ_SELDIV2) 1582 div *= 2; 1583 1584 if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 1585 (val & PRCM_PLL_FREQ_DIV2EN) && 1586 ((reg == PRCM_PLLSOC0_FREQ) || 1587 (reg == PRCM_PLLDDR_FREQ)))) 1588 div *= 2; 1589 1590 (void)do_div(rate, div); 1591 1592 return (unsigned long)rate; 1593 } 1594 1595 #define ROOT_CLOCK_RATE 38400000 1596 1597 static unsigned long clock_rate(u8 clock) 1598 { 1599 u32 val; 1600 u32 pllsw; 1601 unsigned long rate = ROOT_CLOCK_RATE; 1602 1603 val = readl(clk_mgt[clock].reg); 1604 1605 if (val & PRCM_CLK_MGT_CLK38) { 1606 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 1607 rate /= 2; 1608 return rate; 1609 } 1610 1611 val |= clk_mgt[clock].pllsw; 1612 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 1613 1614 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 1615 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 1616 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 1617 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 1618 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 1619 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 1620 else 1621 return 0; 1622 1623 if ((clock == PRCMU_SGACLK) && 1624 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 1625 u64 r = (rate * 10); 1626 1627 (void)do_div(r, 25); 1628 return (unsigned long)r; 1629 } 1630 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 1631 if (val) 1632 return rate / val; 1633 else 1634 return 0; 1635 } 1636 1637 static unsigned long dsiclk_rate(u8 n) 1638 { 1639 u32 divsel; 1640 u32 div = 1; 1641 1642 divsel = readl(PRCM_DSI_PLLOUT_SEL); 1643 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 1644 1645 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 1646 divsel = dsiclk[n].divsel; 1647 1648 switch (divsel) { 1649 case PRCM_DSI_PLLOUT_SEL_PHI_4: 1650 div *= 2; 1651 case PRCM_DSI_PLLOUT_SEL_PHI_2: 1652 div *= 2; 1653 case PRCM_DSI_PLLOUT_SEL_PHI: 1654 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 1655 PLL_RAW) / div; 1656 default: 1657 return 0; 1658 } 1659 } 1660 1661 static unsigned long dsiescclk_rate(u8 n) 1662 { 1663 u32 div; 1664 1665 div = readl(PRCM_DSITVCLK_DIV); 1666 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 1667 return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 1668 } 1669 1670 unsigned long prcmu_clock_rate(u8 clock) 1671 { 1672 if (clock < PRCMU_NUM_REG_CLOCKS) 1673 return clock_rate(clock); 1674 else if (clock == PRCMU_TIMCLK) 1675 return ROOT_CLOCK_RATE / 16; 1676 else if (clock == PRCMU_SYSCLK) 1677 return ROOT_CLOCK_RATE; 1678 else if (clock == PRCMU_PLLSOC0) 1679 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1680 else if (clock == PRCMU_PLLSOC1) 1681 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1682 else if (clock == PRCMU_PLLDDR) 1683 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1684 else if (clock == PRCMU_PLLDSI) 1685 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 1686 PLL_RAW); 1687 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1688 return dsiclk_rate(clock - PRCMU_DSI0CLK); 1689 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1690 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 1691 else 1692 return 0; 1693 } 1694 1695 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 1696 { 1697 if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 1698 return ROOT_CLOCK_RATE; 1699 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 1700 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 1701 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 1702 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 1703 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 1704 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 1705 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 1706 else 1707 return 0; 1708 } 1709 1710 static u32 clock_divider(unsigned long src_rate, unsigned long rate) 1711 { 1712 u32 div; 1713 1714 div = (src_rate / rate); 1715 if (div == 0) 1716 return 1; 1717 if (rate < (src_rate / div)) 1718 div++; 1719 return div; 1720 } 1721 1722 static long round_clock_rate(u8 clock, unsigned long rate) 1723 { 1724 u32 val; 1725 u32 div; 1726 unsigned long src_rate; 1727 long rounded_rate; 1728 1729 val = readl(clk_mgt[clock].reg); 1730 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 1731 clk_mgt[clock].branch); 1732 div = clock_divider(src_rate, rate); 1733 if (val & PRCM_CLK_MGT_CLK38) { 1734 if (clk_mgt[clock].clk38div) { 1735 if (div > 2) 1736 div = 2; 1737 } else { 1738 div = 1; 1739 } 1740 } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 1741 u64 r = (src_rate * 10); 1742 1743 (void)do_div(r, 25); 1744 if (r <= rate) 1745 return (unsigned long)r; 1746 } 1747 rounded_rate = (src_rate / min(div, (u32)31)); 1748 1749 return rounded_rate; 1750 } 1751 1752 #define MIN_PLL_VCO_RATE 600000000ULL 1753 #define MAX_PLL_VCO_RATE 1680640000ULL 1754 1755 static long round_plldsi_rate(unsigned long rate) 1756 { 1757 long rounded_rate = 0; 1758 unsigned long src_rate; 1759 unsigned long rem; 1760 u32 r; 1761 1762 src_rate = clock_rate(PRCMU_HDMICLK); 1763 rem = rate; 1764 1765 for (r = 7; (rem > 0) && (r > 0); r--) { 1766 u64 d; 1767 1768 d = (r * rate); 1769 (void)do_div(d, src_rate); 1770 if (d < 6) 1771 d = 6; 1772 else if (d > 255) 1773 d = 255; 1774 d *= src_rate; 1775 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 1776 ((r * MAX_PLL_VCO_RATE) < (2 * d))) 1777 continue; 1778 (void)do_div(d, r); 1779 if (rate < d) { 1780 if (rounded_rate == 0) 1781 rounded_rate = (long)d; 1782 break; 1783 } 1784 if ((rate - d) < rem) { 1785 rem = (rate - d); 1786 rounded_rate = (long)d; 1787 } 1788 } 1789 return rounded_rate; 1790 } 1791 1792 static long round_dsiclk_rate(unsigned long rate) 1793 { 1794 u32 div; 1795 unsigned long src_rate; 1796 long rounded_rate; 1797 1798 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 1799 PLL_RAW); 1800 div = clock_divider(src_rate, rate); 1801 rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 1802 1803 return rounded_rate; 1804 } 1805 1806 static long round_dsiescclk_rate(unsigned long rate) 1807 { 1808 u32 div; 1809 unsigned long src_rate; 1810 long rounded_rate; 1811 1812 src_rate = clock_rate(PRCMU_TVCLK); 1813 div = clock_divider(src_rate, rate); 1814 rounded_rate = (src_rate / min(div, (u32)255)); 1815 1816 return rounded_rate; 1817 } 1818 1819 long prcmu_round_clock_rate(u8 clock, unsigned long rate) 1820 { 1821 if (clock < PRCMU_NUM_REG_CLOCKS) 1822 return round_clock_rate(clock, rate); 1823 else if (clock == PRCMU_PLLDSI) 1824 return round_plldsi_rate(rate); 1825 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1826 return round_dsiclk_rate(rate); 1827 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1828 return round_dsiescclk_rate(rate); 1829 else 1830 return (long)prcmu_clock_rate(clock); 1831 } 1832 1833 static void set_clock_rate(u8 clock, unsigned long rate) 1834 { 1835 u32 val; 1836 u32 div; 1837 unsigned long src_rate; 1838 unsigned long flags; 1839 1840 spin_lock_irqsave(&clk_mgt_lock, flags); 1841 1842 /* Grab the HW semaphore. */ 1843 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 1844 cpu_relax(); 1845 1846 val = readl(clk_mgt[clock].reg); 1847 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 1848 clk_mgt[clock].branch); 1849 div = clock_divider(src_rate, rate); 1850 if (val & PRCM_CLK_MGT_CLK38) { 1851 if (clk_mgt[clock].clk38div) { 1852 if (div > 1) 1853 val |= PRCM_CLK_MGT_CLK38DIV; 1854 else 1855 val &= ~PRCM_CLK_MGT_CLK38DIV; 1856 } 1857 } else if (clock == PRCMU_SGACLK) { 1858 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 1859 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 1860 if (div == 3) { 1861 u64 r = (src_rate * 10); 1862 1863 (void)do_div(r, 25); 1864 if (r <= rate) { 1865 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 1866 div = 0; 1867 } 1868 } 1869 val |= min(div, (u32)31); 1870 } else { 1871 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 1872 val |= min(div, (u32)31); 1873 } 1874 writel(val, clk_mgt[clock].reg); 1875 1876 /* Release the HW semaphore. */ 1877 writel(0, PRCM_SEM); 1878 1879 spin_unlock_irqrestore(&clk_mgt_lock, flags); 1880 } 1881 1882 static int set_plldsi_rate(unsigned long rate) 1883 { 1884 unsigned long src_rate; 1885 unsigned long rem; 1886 u32 pll_freq = 0; 1887 u32 r; 1888 1889 src_rate = clock_rate(PRCMU_HDMICLK); 1890 rem = rate; 1891 1892 for (r = 7; (rem > 0) && (r > 0); r--) { 1893 u64 d; 1894 u64 hwrate; 1895 1896 d = (r * rate); 1897 (void)do_div(d, src_rate); 1898 if (d < 6) 1899 d = 6; 1900 else if (d > 255) 1901 d = 255; 1902 hwrate = (d * src_rate); 1903 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 1904 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 1905 continue; 1906 (void)do_div(hwrate, r); 1907 if (rate < hwrate) { 1908 if (pll_freq == 0) 1909 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 1910 (r << PRCM_PLL_FREQ_R_SHIFT)); 1911 break; 1912 } 1913 if ((rate - hwrate) < rem) { 1914 rem = (rate - hwrate); 1915 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 1916 (r << PRCM_PLL_FREQ_R_SHIFT)); 1917 } 1918 } 1919 if (pll_freq == 0) 1920 return -EINVAL; 1921 1922 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 1923 writel(pll_freq, PRCM_PLLDSI_FREQ); 1924 1925 return 0; 1926 } 1927 1928 static void set_dsiclk_rate(u8 n, unsigned long rate) 1929 { 1930 u32 val; 1931 u32 div; 1932 1933 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 1934 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 1935 1936 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 1937 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 1938 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 1939 1940 val = readl(PRCM_DSI_PLLOUT_SEL); 1941 val &= ~dsiclk[n].divsel_mask; 1942 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 1943 writel(val, PRCM_DSI_PLLOUT_SEL); 1944 } 1945 1946 static void set_dsiescclk_rate(u8 n, unsigned long rate) 1947 { 1948 u32 val; 1949 u32 div; 1950 1951 div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 1952 val = readl(PRCM_DSITVCLK_DIV); 1953 val &= ~dsiescclk[n].div_mask; 1954 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 1955 writel(val, PRCM_DSITVCLK_DIV); 1956 } 1957 1958 int prcmu_set_clock_rate(u8 clock, unsigned long rate) 1959 { 1960 if (clock < PRCMU_NUM_REG_CLOCKS) 1961 set_clock_rate(clock, rate); 1962 else if (clock == PRCMU_PLLDSI) 1963 return set_plldsi_rate(rate); 1964 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1965 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 1966 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1967 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 1968 return 0; 1969 } 1970 1971 int db8500_prcmu_config_esram0_deep_sleep(u8 state) 1972 { 1973 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 1974 (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 1975 return -EINVAL; 1976 1977 mutex_lock(&mb4_transfer.lock); 1978 1979 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 1980 cpu_relax(); 1981 1982 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 1983 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 1984 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 1985 writeb(DDR_PWR_STATE_ON, 1986 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 1987 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 1988 1989 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 1990 wait_for_completion(&mb4_transfer.work); 1991 1992 mutex_unlock(&mb4_transfer.lock); 1993 1994 return 0; 1995 } 1996 1997 int db8500_prcmu_config_hotdog(u8 threshold) 1998 { 1999 mutex_lock(&mb4_transfer.lock); 2000 2001 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 2002 cpu_relax(); 2003 2004 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 2005 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 2006 2007 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 2008 wait_for_completion(&mb4_transfer.work); 2009 2010 mutex_unlock(&mb4_transfer.lock); 2011 2012 return 0; 2013 } 2014 2015 int db8500_prcmu_config_hotmon(u8 low, u8 high) 2016 { 2017 mutex_lock(&mb4_transfer.lock); 2018 2019 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 2020 cpu_relax(); 2021 2022 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 2023 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 2024 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 2025 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 2026 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 2027 2028 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 2029 wait_for_completion(&mb4_transfer.work); 2030 2031 mutex_unlock(&mb4_transfer.lock); 2032 2033 return 0; 2034 } 2035 2036 static int config_hot_period(u16 val) 2037 { 2038 mutex_lock(&mb4_transfer.lock); 2039 2040 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 2041 cpu_relax(); 2042 2043 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 2044 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 2045 2046 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 2047 wait_for_completion(&mb4_transfer.work); 2048 2049 mutex_unlock(&mb4_transfer.lock); 2050 2051 return 0; 2052 } 2053 2054 int db8500_prcmu_start_temp_sense(u16 cycles32k) 2055 { 2056 if (cycles32k == 0xFFFF) 2057 return -EINVAL; 2058 2059 return config_hot_period(cycles32k); 2060 } 2061 2062 int db8500_prcmu_stop_temp_sense(void) 2063 { 2064 return config_hot_period(0xFFFF); 2065 } 2066 2067 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 2068 { 2069 2070 mutex_lock(&mb4_transfer.lock); 2071 2072 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 2073 cpu_relax(); 2074 2075 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 2076 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 2077 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 2078 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 2079 2080 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 2081 2082 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 2083 wait_for_completion(&mb4_transfer.work); 2084 2085 mutex_unlock(&mb4_transfer.lock); 2086 2087 return 0; 2088 2089 } 2090 2091 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 2092 { 2093 BUG_ON(num == 0 || num > 0xf); 2094 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 2095 sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 2096 A9WDOG_AUTO_OFF_DIS); 2097 } 2098 2099 int db8500_prcmu_enable_a9wdog(u8 id) 2100 { 2101 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 2102 } 2103 2104 int db8500_prcmu_disable_a9wdog(u8 id) 2105 { 2106 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 2107 } 2108 2109 int db8500_prcmu_kick_a9wdog(u8 id) 2110 { 2111 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 2112 } 2113 2114 /* 2115 * timeout is 28 bit, in ms. 2116 */ 2117 #define MAX_WATCHDOG_TIMEOUT 131000 2118 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 2119 { 2120 if (timeout > MAX_WATCHDOG_TIMEOUT) 2121 /* 2122 * Due to calculation bug in prcmu fw, timeouts 2123 * can't be bigger than 131 seconds. 2124 */ 2125 return -EINVAL; 2126 2127 return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 2128 (id & A9WDOG_ID_MASK) | 2129 /* 2130 * Put the lowest 28 bits of timeout at 2131 * offset 4. Four first bits are used for id. 2132 */ 2133 (u8)((timeout << 4) & 0xf0), 2134 (u8)((timeout >> 4) & 0xff), 2135 (u8)((timeout >> 12) & 0xff), 2136 (u8)((timeout >> 20) & 0xff)); 2137 } 2138 2139 /** 2140 * prcmu_abb_read() - Read register value(s) from the ABB. 2141 * @slave: The I2C slave address. 2142 * @reg: The (start) register address. 2143 * @value: The read out value(s). 2144 * @size: The number of registers to read. 2145 * 2146 * Reads register value(s) from the ABB. 2147 * @size has to be 1 for the current firmware version. 2148 */ 2149 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2150 { 2151 int r; 2152 2153 if (size != 1) 2154 return -EINVAL; 2155 2156 mutex_lock(&mb5_transfer.lock); 2157 2158 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2159 cpu_relax(); 2160 2161 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 2162 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 2163 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 2164 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2165 2166 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 2167 2168 if (!wait_for_completion_timeout(&mb5_transfer.work, 2169 msecs_to_jiffies(20000))) { 2170 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 2171 __func__); 2172 r = -EIO; 2173 } else { 2174 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 2175 } 2176 2177 if (!r) 2178 *value = mb5_transfer.ack.value; 2179 2180 mutex_unlock(&mb5_transfer.lock); 2181 2182 return r; 2183 } 2184 2185 /** 2186 * prcmu_abb_write() - Write register value(s) to the ABB. 2187 * @slave: The I2C slave address. 2188 * @reg: The (start) register address. 2189 * @value: The value(s) to write. 2190 * @size: The number of registers to write. 2191 * 2192 * Reads register value(s) from the ABB. 2193 * @size has to be 1 for the current firmware version. 2194 */ 2195 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 2196 { 2197 int r; 2198 2199 if (size != 1) 2200 return -EINVAL; 2201 2202 mutex_lock(&mb5_transfer.lock); 2203 2204 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2205 cpu_relax(); 2206 2207 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 2208 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 2209 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 2210 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2211 2212 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 2213 2214 if (!wait_for_completion_timeout(&mb5_transfer.work, 2215 msecs_to_jiffies(20000))) { 2216 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 2217 __func__); 2218 r = -EIO; 2219 } else { 2220 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 2221 } 2222 2223 mutex_unlock(&mb5_transfer.lock); 2224 2225 return r; 2226 } 2227 2228 /** 2229 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 2230 */ 2231 void prcmu_ac_wake_req(void) 2232 { 2233 u32 val; 2234 u32 status; 2235 2236 mutex_lock(&mb0_transfer.ac_wake_lock); 2237 2238 val = readl(PRCM_HOSTACCESS_REQ); 2239 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 2240 goto unlock_and_return; 2241 2242 atomic_set(&ac_wake_req_state, 1); 2243 2244 retry: 2245 writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); 2246 2247 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2248 msecs_to_jiffies(5000))) { 2249 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2250 __func__); 2251 goto unlock_and_return; 2252 } 2253 2254 /* 2255 * The modem can generate an AC_WAKE_ACK, and then still go to sleep. 2256 * As a workaround, we wait, and then check that the modem is indeed 2257 * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS 2258 * register, which may not be the whole truth). 2259 */ 2260 udelay(400); 2261 status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2)); 2262 if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE | 2263 PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) { 2264 pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n", 2265 __func__, status); 2266 udelay(1200); 2267 writel(val, PRCM_HOSTACCESS_REQ); 2268 if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2269 msecs_to_jiffies(5000))) 2270 goto retry; 2271 pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n", 2272 __func__); 2273 } 2274 2275 unlock_and_return: 2276 mutex_unlock(&mb0_transfer.ac_wake_lock); 2277 } 2278 2279 /** 2280 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 2281 */ 2282 void prcmu_ac_sleep_req() 2283 { 2284 u32 val; 2285 2286 mutex_lock(&mb0_transfer.ac_wake_lock); 2287 2288 val = readl(PRCM_HOSTACCESS_REQ); 2289 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 2290 goto unlock_and_return; 2291 2292 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2293 PRCM_HOSTACCESS_REQ); 2294 2295 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2296 msecs_to_jiffies(5000))) { 2297 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2298 __func__); 2299 } 2300 2301 atomic_set(&ac_wake_req_state, 0); 2302 2303 unlock_and_return: 2304 mutex_unlock(&mb0_transfer.ac_wake_lock); 2305 } 2306 2307 bool db8500_prcmu_is_ac_wake_requested(void) 2308 { 2309 return (atomic_read(&ac_wake_req_state) != 0); 2310 } 2311 2312 /** 2313 * db8500_prcmu_system_reset - System reset 2314 * 2315 * Saves the reset reason code and then sets the APE_SOFTRST register which 2316 * fires interrupt to fw 2317 */ 2318 void db8500_prcmu_system_reset(u16 reset_code) 2319 { 2320 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2321 writel(1, PRCM_APE_SOFTRST); 2322 } 2323 2324 /** 2325 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2326 * 2327 * Retrieves the reset reason code stored by prcmu_system_reset() before 2328 * last restart. 2329 */ 2330 u16 db8500_prcmu_get_reset_code(void) 2331 { 2332 return readw(tcdm_base + PRCM_SW_RST_REASON); 2333 } 2334 2335 /** 2336 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 2337 */ 2338 void db8500_prcmu_modem_reset(void) 2339 { 2340 mutex_lock(&mb1_transfer.lock); 2341 2342 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2343 cpu_relax(); 2344 2345 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2346 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2347 wait_for_completion(&mb1_transfer.work); 2348 2349 /* 2350 * No need to check return from PRCMU as modem should go in reset state 2351 * This state is already managed by upper layer 2352 */ 2353 2354 mutex_unlock(&mb1_transfer.lock); 2355 } 2356 2357 static void ack_dbb_wakeup(void) 2358 { 2359 unsigned long flags; 2360 2361 spin_lock_irqsave(&mb0_transfer.lock, flags); 2362 2363 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 2364 cpu_relax(); 2365 2366 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2367 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2368 2369 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2370 } 2371 2372 static inline void print_unknown_header_warning(u8 n, u8 header) 2373 { 2374 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 2375 header, n); 2376 } 2377 2378 static bool read_mailbox_0(void) 2379 { 2380 bool r; 2381 u32 ev; 2382 unsigned int n; 2383 u8 header; 2384 2385 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 2386 switch (header) { 2387 case MB0H_WAKEUP_EXE: 2388 case MB0H_WAKEUP_SLEEP: 2389 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 2390 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 2391 else 2392 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 2393 2394 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 2395 complete(&mb0_transfer.ac_wake_work); 2396 if (ev & WAKEUP_BIT_SYSCLK_OK) 2397 complete(&mb3_transfer.sysclk_work); 2398 2399 ev &= mb0_transfer.req.dbb_irqs; 2400 2401 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 2402 if (ev & prcmu_irq_bit[n]) 2403 generic_handle_irq(IRQ_PRCMU_BASE + n); 2404 } 2405 r = true; 2406 break; 2407 default: 2408 print_unknown_header_warning(0, header); 2409 r = false; 2410 break; 2411 } 2412 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 2413 return r; 2414 } 2415 2416 static bool read_mailbox_1(void) 2417 { 2418 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 2419 mb1_transfer.ack.arm_opp = readb(tcdm_base + 2420 PRCM_ACK_MB1_CURRENT_ARM_OPP); 2421 mb1_transfer.ack.ape_opp = readb(tcdm_base + 2422 PRCM_ACK_MB1_CURRENT_APE_OPP); 2423 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 2424 PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2425 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2426 complete(&mb1_transfer.work); 2427 return false; 2428 } 2429 2430 static bool read_mailbox_2(void) 2431 { 2432 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2433 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 2434 complete(&mb2_transfer.work); 2435 return false; 2436 } 2437 2438 static bool read_mailbox_3(void) 2439 { 2440 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 2441 return false; 2442 } 2443 2444 static bool read_mailbox_4(void) 2445 { 2446 u8 header; 2447 bool do_complete = true; 2448 2449 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 2450 switch (header) { 2451 case MB4H_MEM_ST: 2452 case MB4H_HOTDOG: 2453 case MB4H_HOTMON: 2454 case MB4H_HOT_PERIOD: 2455 case MB4H_A9WDOG_CONF: 2456 case MB4H_A9WDOG_EN: 2457 case MB4H_A9WDOG_DIS: 2458 case MB4H_A9WDOG_LOAD: 2459 case MB4H_A9WDOG_KICK: 2460 break; 2461 default: 2462 print_unknown_header_warning(4, header); 2463 do_complete = false; 2464 break; 2465 } 2466 2467 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 2468 2469 if (do_complete) 2470 complete(&mb4_transfer.work); 2471 2472 return false; 2473 } 2474 2475 static bool read_mailbox_5(void) 2476 { 2477 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 2478 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2479 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2480 complete(&mb5_transfer.work); 2481 return false; 2482 } 2483 2484 static bool read_mailbox_6(void) 2485 { 2486 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 2487 return false; 2488 } 2489 2490 static bool read_mailbox_7(void) 2491 { 2492 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 2493 return false; 2494 } 2495 2496 static bool (* const read_mailbox[NUM_MB])(void) = { 2497 read_mailbox_0, 2498 read_mailbox_1, 2499 read_mailbox_2, 2500 read_mailbox_3, 2501 read_mailbox_4, 2502 read_mailbox_5, 2503 read_mailbox_6, 2504 read_mailbox_7 2505 }; 2506 2507 static irqreturn_t prcmu_irq_handler(int irq, void *data) 2508 { 2509 u32 bits; 2510 u8 n; 2511 irqreturn_t r; 2512 2513 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2514 if (unlikely(!bits)) 2515 return IRQ_NONE; 2516 2517 r = IRQ_HANDLED; 2518 for (n = 0; bits; n++) { 2519 if (bits & MBOX_BIT(n)) { 2520 bits -= MBOX_BIT(n); 2521 if (read_mailbox[n]()) 2522 r = IRQ_WAKE_THREAD; 2523 } 2524 } 2525 return r; 2526 } 2527 2528 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 2529 { 2530 ack_dbb_wakeup(); 2531 return IRQ_HANDLED; 2532 } 2533 2534 static void prcmu_mask_work(struct work_struct *work) 2535 { 2536 unsigned long flags; 2537 2538 spin_lock_irqsave(&mb0_transfer.lock, flags); 2539 2540 config_wakeups(); 2541 2542 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2543 } 2544 2545 static void prcmu_irq_mask(struct irq_data *d) 2546 { 2547 unsigned long flags; 2548 2549 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 2550 2551 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 2552 2553 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 2554 2555 if (d->irq != IRQ_PRCMU_CA_SLEEP) 2556 schedule_work(&mb0_transfer.mask_work); 2557 } 2558 2559 static void prcmu_irq_unmask(struct irq_data *d) 2560 { 2561 unsigned long flags; 2562 2563 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 2564 2565 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 2566 2567 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 2568 2569 if (d->irq != IRQ_PRCMU_CA_SLEEP) 2570 schedule_work(&mb0_transfer.mask_work); 2571 } 2572 2573 static void noop(struct irq_data *d) 2574 { 2575 } 2576 2577 static struct irq_chip prcmu_irq_chip = { 2578 .name = "prcmu", 2579 .irq_disable = prcmu_irq_mask, 2580 .irq_ack = noop, 2581 .irq_mask = prcmu_irq_mask, 2582 .irq_unmask = prcmu_irq_unmask, 2583 }; 2584 2585 static char *fw_project_name(u8 project) 2586 { 2587 switch (project) { 2588 case PRCMU_FW_PROJECT_U8500: 2589 return "U8500"; 2590 case PRCMU_FW_PROJECT_U8500_C2: 2591 return "U8500 C2"; 2592 case PRCMU_FW_PROJECT_U9500: 2593 return "U9500"; 2594 case PRCMU_FW_PROJECT_U9500_C2: 2595 return "U9500 C2"; 2596 default: 2597 return "Unknown"; 2598 } 2599 } 2600 2601 void __init db8500_prcmu_early_init(void) 2602 { 2603 unsigned int i; 2604 if (cpu_is_u8500v2()) { 2605 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); 2606 2607 if (tcpm_base != NULL) { 2608 u32 version; 2609 version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); 2610 fw_info.version.project = version & 0xFF; 2611 fw_info.version.api_version = (version >> 8) & 0xFF; 2612 fw_info.version.func_version = (version >> 16) & 0xFF; 2613 fw_info.version.errata = (version >> 24) & 0xFF; 2614 fw_info.valid = true; 2615 pr_info("PRCMU firmware: %s, version %d.%d.%d\n", 2616 fw_project_name(fw_info.version.project), 2617 (version >> 8) & 0xFF, (version >> 16) & 0xFF, 2618 (version >> 24) & 0xFF); 2619 iounmap(tcpm_base); 2620 } 2621 2622 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); 2623 } else { 2624 pr_err("prcmu: Unsupported chip version\n"); 2625 BUG(); 2626 } 2627 2628 spin_lock_init(&mb0_transfer.lock); 2629 spin_lock_init(&mb0_transfer.dbb_irqs_lock); 2630 mutex_init(&mb0_transfer.ac_wake_lock); 2631 init_completion(&mb0_transfer.ac_wake_work); 2632 mutex_init(&mb1_transfer.lock); 2633 init_completion(&mb1_transfer.work); 2634 mutex_init(&mb2_transfer.lock); 2635 init_completion(&mb2_transfer.work); 2636 spin_lock_init(&mb2_transfer.auto_pm_lock); 2637 spin_lock_init(&mb3_transfer.lock); 2638 mutex_init(&mb3_transfer.sysclk_lock); 2639 init_completion(&mb3_transfer.sysclk_work); 2640 mutex_init(&mb4_transfer.lock); 2641 init_completion(&mb4_transfer.work); 2642 mutex_init(&mb5_transfer.lock); 2643 init_completion(&mb5_transfer.work); 2644 2645 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2646 2647 /* Initalize irqs. */ 2648 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { 2649 unsigned int irq; 2650 2651 irq = IRQ_PRCMU_BASE + i; 2652 irq_set_chip_and_handler(irq, &prcmu_irq_chip, 2653 handle_simple_irq); 2654 set_irq_flags(irq, IRQF_VALID); 2655 } 2656 } 2657 2658 static void __init init_prcm_registers(void) 2659 { 2660 u32 val; 2661 2662 val = readl(PRCM_A9PL_FORCE_CLKEN); 2663 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2664 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2665 writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2666 } 2667 2668 /* 2669 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 2670 */ 2671 static struct regulator_consumer_supply db8500_vape_consumers[] = { 2672 REGULATOR_SUPPLY("v-ape", NULL), 2673 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 2674 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 2675 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 2676 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 2677 /* "v-mmc" changed to "vcore" in the mainline kernel */ 2678 REGULATOR_SUPPLY("vcore", "sdi0"), 2679 REGULATOR_SUPPLY("vcore", "sdi1"), 2680 REGULATOR_SUPPLY("vcore", "sdi2"), 2681 REGULATOR_SUPPLY("vcore", "sdi3"), 2682 REGULATOR_SUPPLY("vcore", "sdi4"), 2683 REGULATOR_SUPPLY("v-dma", "dma40.0"), 2684 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 2685 /* "v-uart" changed to "vcore" in the mainline kernel */ 2686 REGULATOR_SUPPLY("vcore", "uart0"), 2687 REGULATOR_SUPPLY("vcore", "uart1"), 2688 REGULATOR_SUPPLY("vcore", "uart2"), 2689 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2690 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 2691 }; 2692 2693 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 2694 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 2695 /* AV8100 regulator */ 2696 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 2697 }; 2698 2699 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2700 REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2701 REGULATOR_SUPPLY("vsupply", "mcde"), 2702 }; 2703 2704 /* SVA MMDSP regulator switch */ 2705 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2706 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2707 }; 2708 2709 /* SVA pipe regulator switch */ 2710 static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2711 REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2712 }; 2713 2714 /* SIA MMDSP regulator switch */ 2715 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2716 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2717 }; 2718 2719 /* SIA pipe regulator switch */ 2720 static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2721 REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2722 }; 2723 2724 static struct regulator_consumer_supply db8500_sga_consumers[] = { 2725 REGULATOR_SUPPLY("v-mali", NULL), 2726 }; 2727 2728 /* ESRAM1 and 2 regulator switch */ 2729 static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2730 REGULATOR_SUPPLY("esram12", "cm_control"), 2731 }; 2732 2733 /* ESRAM3 and 4 regulator switch */ 2734 static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2735 REGULATOR_SUPPLY("v-esram34", "mcde"), 2736 REGULATOR_SUPPLY("esram34", "cm_control"), 2737 REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 2738 }; 2739 2740 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 2741 [DB8500_REGULATOR_VAPE] = { 2742 .constraints = { 2743 .name = "db8500-vape", 2744 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2745 }, 2746 .consumer_supplies = db8500_vape_consumers, 2747 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 2748 }, 2749 [DB8500_REGULATOR_VARM] = { 2750 .constraints = { 2751 .name = "db8500-varm", 2752 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2753 }, 2754 }, 2755 [DB8500_REGULATOR_VMODEM] = { 2756 .constraints = { 2757 .name = "db8500-vmodem", 2758 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2759 }, 2760 }, 2761 [DB8500_REGULATOR_VPLL] = { 2762 .constraints = { 2763 .name = "db8500-vpll", 2764 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2765 }, 2766 }, 2767 [DB8500_REGULATOR_VSMPS1] = { 2768 .constraints = { 2769 .name = "db8500-vsmps1", 2770 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2771 }, 2772 }, 2773 [DB8500_REGULATOR_VSMPS2] = { 2774 .constraints = { 2775 .name = "db8500-vsmps2", 2776 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2777 }, 2778 .consumer_supplies = db8500_vsmps2_consumers, 2779 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 2780 }, 2781 [DB8500_REGULATOR_VSMPS3] = { 2782 .constraints = { 2783 .name = "db8500-vsmps3", 2784 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2785 }, 2786 }, 2787 [DB8500_REGULATOR_VRF1] = { 2788 .constraints = { 2789 .name = "db8500-vrf1", 2790 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2791 }, 2792 }, 2793 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2794 /* dependency to u8500-vape is handled outside regulator framework */ 2795 .constraints = { 2796 .name = "db8500-sva-mmdsp", 2797 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2798 }, 2799 .consumer_supplies = db8500_svammdsp_consumers, 2800 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 2801 }, 2802 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 2803 .constraints = { 2804 /* "ret" means "retention" */ 2805 .name = "db8500-sva-mmdsp-ret", 2806 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2807 }, 2808 }, 2809 [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2810 /* dependency to u8500-vape is handled outside regulator framework */ 2811 .constraints = { 2812 .name = "db8500-sva-pipe", 2813 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2814 }, 2815 .consumer_supplies = db8500_svapipe_consumers, 2816 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 2817 }, 2818 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2819 /* dependency to u8500-vape is handled outside regulator framework */ 2820 .constraints = { 2821 .name = "db8500-sia-mmdsp", 2822 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2823 }, 2824 .consumer_supplies = db8500_siammdsp_consumers, 2825 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 2826 }, 2827 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 2828 .constraints = { 2829 .name = "db8500-sia-mmdsp-ret", 2830 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2831 }, 2832 }, 2833 [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2834 /* dependency to u8500-vape is handled outside regulator framework */ 2835 .constraints = { 2836 .name = "db8500-sia-pipe", 2837 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2838 }, 2839 .consumer_supplies = db8500_siapipe_consumers, 2840 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 2841 }, 2842 [DB8500_REGULATOR_SWITCH_SGA] = { 2843 .supply_regulator = "db8500-vape", 2844 .constraints = { 2845 .name = "db8500-sga", 2846 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2847 }, 2848 .consumer_supplies = db8500_sga_consumers, 2849 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2850 2851 }, 2852 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 2853 .supply_regulator = "db8500-vape", 2854 .constraints = { 2855 .name = "db8500-b2r2-mcde", 2856 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2857 }, 2858 .consumer_supplies = db8500_b2r2_mcde_consumers, 2859 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 2860 }, 2861 [DB8500_REGULATOR_SWITCH_ESRAM12] = { 2862 /* 2863 * esram12 is set in retention and supplied by Vsafe when Vape is off, 2864 * no need to hold Vape 2865 */ 2866 .constraints = { 2867 .name = "db8500-esram12", 2868 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2869 }, 2870 .consumer_supplies = db8500_esram12_consumers, 2871 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 2872 }, 2873 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 2874 .constraints = { 2875 .name = "db8500-esram12-ret", 2876 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2877 }, 2878 }, 2879 [DB8500_REGULATOR_SWITCH_ESRAM34] = { 2880 /* 2881 * esram34 is set in retention and supplied by Vsafe when Vape is off, 2882 * no need to hold Vape 2883 */ 2884 .constraints = { 2885 .name = "db8500-esram34", 2886 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2887 }, 2888 .consumer_supplies = db8500_esram34_consumers, 2889 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 2890 }, 2891 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 2892 .constraints = { 2893 .name = "db8500-esram34-ret", 2894 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2895 }, 2896 }, 2897 }; 2898 2899 static struct mfd_cell db8500_prcmu_devs[] = { 2900 { 2901 .name = "db8500-prcmu-regulators", 2902 .platform_data = &db8500_regulators, 2903 .pdata_size = sizeof(db8500_regulators), 2904 }, 2905 { 2906 .name = "cpufreq-u8500", 2907 }, 2908 }; 2909 2910 /** 2911 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 2912 * 2913 */ 2914 static int __init db8500_prcmu_probe(struct platform_device *pdev) 2915 { 2916 int err = 0; 2917 2918 if (ux500_is_svp()) 2919 return -ENODEV; 2920 2921 init_prcm_registers(); 2922 2923 /* Clean up the mailbox interrupts after pre-kernel code. */ 2924 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 2925 2926 err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 2927 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 2928 if (err < 0) { 2929 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 2930 err = -EBUSY; 2931 goto no_irq_return; 2932 } 2933 2934 if (cpu_is_u8500v20_or_later()) 2935 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 2936 2937 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 2938 ARRAY_SIZE(db8500_prcmu_devs), NULL, 2939 0); 2940 2941 if (err) 2942 pr_err("prcmu: Failed to add subdevices\n"); 2943 else 2944 pr_info("DB8500 PRCMU initialized\n"); 2945 2946 no_irq_return: 2947 return err; 2948 } 2949 2950 static struct platform_driver db8500_prcmu_driver = { 2951 .driver = { 2952 .name = "db8500-prcmu", 2953 .owner = THIS_MODULE, 2954 }, 2955 }; 2956 2957 static int __init db8500_prcmu_init(void) 2958 { 2959 return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe); 2960 } 2961 2962 arch_initcall(db8500_prcmu_init); 2963 2964 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 2965 MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 2966 MODULE_LICENSE("GPL v2"); 2967