1 /* 2 * Copyright (C) STMicroelectronics 2009 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * License Terms: GNU General Public License v2 6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7 * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9 * 10 * U8500 PRCM Unit interface driver 11 * 12 */ 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/delay.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/spinlock.h> 19 #include <linux/io.h> 20 #include <linux/slab.h> 21 #include <linux/mutex.h> 22 #include <linux/completion.h> 23 #include <linux/irq.h> 24 #include <linux/jiffies.h> 25 #include <linux/bitops.h> 26 #include <linux/fs.h> 27 #include <linux/of.h> 28 #include <linux/of_irq.h> 29 #include <linux/platform_device.h> 30 #include <linux/uaccess.h> 31 #include <linux/mfd/core.h> 32 #include <linux/mfd/dbx500-prcmu.h> 33 #include <linux/mfd/abx500/ab8500.h> 34 #include <linux/regulator/db8500-prcmu.h> 35 #include <linux/regulator/machine.h> 36 #include <linux/platform_data/ux500_wdt.h> 37 #include <linux/platform_data/db8500_thermal.h> 38 #include "dbx500-prcmu-regs.h" 39 40 /* Index of different voltages to be used when accessing AVSData */ 41 #define PRCM_AVS_BASE 0x2FC 42 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 43 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 44 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 45 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 46 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 47 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 48 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 49 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 50 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 51 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 52 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 53 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 54 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 55 56 #define PRCM_AVS_VOLTAGE 0 57 #define PRCM_AVS_VOLTAGE_MASK 0x3f 58 #define PRCM_AVS_ISSLOWSTARTUP 6 59 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 60 #define PRCM_AVS_ISMODEENABLE 7 61 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 62 63 #define PRCM_BOOT_STATUS 0xFFF 64 #define PRCM_ROMCODE_A2P 0xFFE 65 #define PRCM_ROMCODE_P2A 0xFFD 66 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 67 68 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 69 70 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 71 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 72 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 73 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 74 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 75 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 76 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 77 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 78 79 /* Req Mailboxes */ 80 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 81 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 82 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 83 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 84 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 85 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 86 87 /* Ack Mailboxes */ 88 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 89 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 90 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 91 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 92 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 93 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 94 95 /* Mailbox 0 headers */ 96 #define MB0H_POWER_STATE_TRANS 0 97 #define MB0H_CONFIG_WAKEUPS_EXE 1 98 #define MB0H_READ_WAKEUP_ACK 3 99 #define MB0H_CONFIG_WAKEUPS_SLEEP 4 100 101 #define MB0H_WAKEUP_EXE 2 102 #define MB0H_WAKEUP_SLEEP 5 103 104 /* Mailbox 0 REQs */ 105 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 106 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 107 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 108 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 109 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 110 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 111 112 /* Mailbox 0 ACKs */ 113 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 114 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 115 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 116 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 117 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 118 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 119 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 120 121 /* Mailbox 1 headers */ 122 #define MB1H_ARM_APE_OPP 0x0 123 #define MB1H_RESET_MODEM 0x2 124 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 125 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 126 #define MB1H_RELEASE_USB_WAKEUP 0x5 127 #define MB1H_PLL_ON_OFF 0x6 128 129 /* Mailbox 1 Requests */ 130 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 131 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 132 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 133 #define PLL_SOC0_OFF 0x1 134 #define PLL_SOC0_ON 0x2 135 #define PLL_SOC1_OFF 0x4 136 #define PLL_SOC1_ON 0x8 137 138 /* Mailbox 1 ACKs */ 139 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 140 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 141 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 142 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 143 144 /* Mailbox 2 headers */ 145 #define MB2H_DPS 0x0 146 #define MB2H_AUTO_PWR 0x1 147 148 /* Mailbox 2 REQs */ 149 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 150 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 151 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 152 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 153 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 154 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 155 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 156 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 157 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 158 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 159 160 /* Mailbox 2 ACKs */ 161 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 162 #define HWACC_PWR_ST_OK 0xFE 163 164 /* Mailbox 3 headers */ 165 #define MB3H_ANC 0x0 166 #define MB3H_SIDETONE 0x1 167 #define MB3H_SYSCLK 0xE 168 169 /* Mailbox 3 Requests */ 170 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 171 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 172 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 173 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 174 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 175 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 176 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 177 178 /* Mailbox 4 headers */ 179 #define MB4H_DDR_INIT 0x0 180 #define MB4H_MEM_ST 0x1 181 #define MB4H_HOTDOG 0x12 182 #define MB4H_HOTMON 0x13 183 #define MB4H_HOT_PERIOD 0x14 184 #define MB4H_A9WDOG_CONF 0x16 185 #define MB4H_A9WDOG_EN 0x17 186 #define MB4H_A9WDOG_DIS 0x18 187 #define MB4H_A9WDOG_LOAD 0x19 188 #define MB4H_A9WDOG_KICK 0x20 189 190 /* Mailbox 4 Requests */ 191 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 192 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 193 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 194 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 195 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 196 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 197 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 198 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 199 #define HOTMON_CONFIG_LOW BIT(0) 200 #define HOTMON_CONFIG_HIGH BIT(1) 201 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 202 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 203 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 204 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 205 #define A9WDOG_AUTO_OFF_EN BIT(7) 206 #define A9WDOG_AUTO_OFF_DIS 0 207 #define A9WDOG_ID_MASK 0xf 208 209 /* Mailbox 5 Requests */ 210 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 211 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 212 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 213 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 214 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) 215 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) 216 #define PRCMU_I2C_STOP_EN BIT(3) 217 218 /* Mailbox 5 ACKs */ 219 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 220 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 221 #define I2C_WR_OK 0x1 222 #define I2C_RD_OK 0x2 223 224 #define NUM_MB 8 225 #define MBOX_BIT BIT 226 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 227 228 /* 229 * Wakeups/IRQs 230 */ 231 232 #define WAKEUP_BIT_RTC BIT(0) 233 #define WAKEUP_BIT_RTT0 BIT(1) 234 #define WAKEUP_BIT_RTT1 BIT(2) 235 #define WAKEUP_BIT_HSI0 BIT(3) 236 #define WAKEUP_BIT_HSI1 BIT(4) 237 #define WAKEUP_BIT_CA_WAKE BIT(5) 238 #define WAKEUP_BIT_USB BIT(6) 239 #define WAKEUP_BIT_ABB BIT(7) 240 #define WAKEUP_BIT_ABB_FIFO BIT(8) 241 #define WAKEUP_BIT_SYSCLK_OK BIT(9) 242 #define WAKEUP_BIT_CA_SLEEP BIT(10) 243 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 244 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 245 #define WAKEUP_BIT_ANC_OK BIT(13) 246 #define WAKEUP_BIT_SW_ERROR BIT(14) 247 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 248 #define WAKEUP_BIT_ARM BIT(17) 249 #define WAKEUP_BIT_HOTMON_LOW BIT(18) 250 #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 251 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 252 #define WAKEUP_BIT_GPIO0 BIT(23) 253 #define WAKEUP_BIT_GPIO1 BIT(24) 254 #define WAKEUP_BIT_GPIO2 BIT(25) 255 #define WAKEUP_BIT_GPIO3 BIT(26) 256 #define WAKEUP_BIT_GPIO4 BIT(27) 257 #define WAKEUP_BIT_GPIO5 BIT(28) 258 #define WAKEUP_BIT_GPIO6 BIT(29) 259 #define WAKEUP_BIT_GPIO7 BIT(30) 260 #define WAKEUP_BIT_GPIO8 BIT(31) 261 262 static struct { 263 bool valid; 264 struct prcmu_fw_version version; 265 } fw_info; 266 267 static struct irq_domain *db8500_irq_domain; 268 269 /* 270 * This vector maps irq numbers to the bits in the bit field used in 271 * communication with the PRCMU firmware. 272 * 273 * The reason for having this is to keep the irq numbers contiguous even though 274 * the bits in the bit field are not. (The bits also have a tendency to move 275 * around, to further complicate matters.) 276 */ 277 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name)) 278 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 279 280 #define IRQ_PRCMU_RTC 0 281 #define IRQ_PRCMU_RTT0 1 282 #define IRQ_PRCMU_RTT1 2 283 #define IRQ_PRCMU_HSI0 3 284 #define IRQ_PRCMU_HSI1 4 285 #define IRQ_PRCMU_CA_WAKE 5 286 #define IRQ_PRCMU_USB 6 287 #define IRQ_PRCMU_ABB 7 288 #define IRQ_PRCMU_ABB_FIFO 8 289 #define IRQ_PRCMU_ARM 9 290 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10 291 #define IRQ_PRCMU_GPIO0 11 292 #define IRQ_PRCMU_GPIO1 12 293 #define IRQ_PRCMU_GPIO2 13 294 #define IRQ_PRCMU_GPIO3 14 295 #define IRQ_PRCMU_GPIO4 15 296 #define IRQ_PRCMU_GPIO5 16 297 #define IRQ_PRCMU_GPIO6 17 298 #define IRQ_PRCMU_GPIO7 18 299 #define IRQ_PRCMU_GPIO8 19 300 #define IRQ_PRCMU_CA_SLEEP 20 301 #define IRQ_PRCMU_HOTMON_LOW 21 302 #define IRQ_PRCMU_HOTMON_HIGH 22 303 #define NUM_PRCMU_WAKEUPS 23 304 305 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 306 IRQ_ENTRY(RTC), 307 IRQ_ENTRY(RTT0), 308 IRQ_ENTRY(RTT1), 309 IRQ_ENTRY(HSI0), 310 IRQ_ENTRY(HSI1), 311 IRQ_ENTRY(CA_WAKE), 312 IRQ_ENTRY(USB), 313 IRQ_ENTRY(ABB), 314 IRQ_ENTRY(ABB_FIFO), 315 IRQ_ENTRY(CA_SLEEP), 316 IRQ_ENTRY(ARM), 317 IRQ_ENTRY(HOTMON_LOW), 318 IRQ_ENTRY(HOTMON_HIGH), 319 IRQ_ENTRY(MODEM_SW_RESET_REQ), 320 IRQ_ENTRY(GPIO0), 321 IRQ_ENTRY(GPIO1), 322 IRQ_ENTRY(GPIO2), 323 IRQ_ENTRY(GPIO3), 324 IRQ_ENTRY(GPIO4), 325 IRQ_ENTRY(GPIO5), 326 IRQ_ENTRY(GPIO6), 327 IRQ_ENTRY(GPIO7), 328 IRQ_ENTRY(GPIO8) 329 }; 330 331 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 332 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 333 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 334 WAKEUP_ENTRY(RTC), 335 WAKEUP_ENTRY(RTT0), 336 WAKEUP_ENTRY(RTT1), 337 WAKEUP_ENTRY(HSI0), 338 WAKEUP_ENTRY(HSI1), 339 WAKEUP_ENTRY(USB), 340 WAKEUP_ENTRY(ABB), 341 WAKEUP_ENTRY(ABB_FIFO), 342 WAKEUP_ENTRY(ARM) 343 }; 344 345 /* 346 * mb0_transfer - state needed for mailbox 0 communication. 347 * @lock: The transaction lock. 348 * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 349 * the request data. 350 * @mask_work: Work structure used for (un)masking wakeup interrupts. 351 * @req: Request data that need to persist between requests. 352 */ 353 static struct { 354 spinlock_t lock; 355 spinlock_t dbb_irqs_lock; 356 struct work_struct mask_work; 357 struct mutex ac_wake_lock; 358 struct completion ac_wake_work; 359 struct { 360 u32 dbb_irqs; 361 u32 dbb_wakeups; 362 u32 abb_events; 363 } req; 364 } mb0_transfer; 365 366 /* 367 * mb1_transfer - state needed for mailbox 1 communication. 368 * @lock: The transaction lock. 369 * @work: The transaction completion structure. 370 * @ape_opp: The current APE OPP. 371 * @ack: Reply ("acknowledge") data. 372 */ 373 static struct { 374 struct mutex lock; 375 struct completion work; 376 u8 ape_opp; 377 struct { 378 u8 header; 379 u8 arm_opp; 380 u8 ape_opp; 381 u8 ape_voltage_status; 382 } ack; 383 } mb1_transfer; 384 385 /* 386 * mb2_transfer - state needed for mailbox 2 communication. 387 * @lock: The transaction lock. 388 * @work: The transaction completion structure. 389 * @auto_pm_lock: The autonomous power management configuration lock. 390 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 391 * @req: Request data that need to persist between requests. 392 * @ack: Reply ("acknowledge") data. 393 */ 394 static struct { 395 struct mutex lock; 396 struct completion work; 397 spinlock_t auto_pm_lock; 398 bool auto_pm_enabled; 399 struct { 400 u8 status; 401 } ack; 402 } mb2_transfer; 403 404 /* 405 * mb3_transfer - state needed for mailbox 3 communication. 406 * @lock: The request lock. 407 * @sysclk_lock: A lock used to handle concurrent sysclk requests. 408 * @sysclk_work: Work structure used for sysclk requests. 409 */ 410 static struct { 411 spinlock_t lock; 412 struct mutex sysclk_lock; 413 struct completion sysclk_work; 414 } mb3_transfer; 415 416 /* 417 * mb4_transfer - state needed for mailbox 4 communication. 418 * @lock: The transaction lock. 419 * @work: The transaction completion structure. 420 */ 421 static struct { 422 struct mutex lock; 423 struct completion work; 424 } mb4_transfer; 425 426 /* 427 * mb5_transfer - state needed for mailbox 5 communication. 428 * @lock: The transaction lock. 429 * @work: The transaction completion structure. 430 * @ack: Reply ("acknowledge") data. 431 */ 432 static struct { 433 struct mutex lock; 434 struct completion work; 435 struct { 436 u8 status; 437 u8 value; 438 } ack; 439 } mb5_transfer; 440 441 static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 442 443 /* Spinlocks */ 444 static DEFINE_SPINLOCK(prcmu_lock); 445 static DEFINE_SPINLOCK(clkout_lock); 446 447 /* Global var to runtime determine TCDM base for v2 or v1 */ 448 static __iomem void *tcdm_base; 449 static __iomem void *prcmu_base; 450 451 struct clk_mgt { 452 u32 offset; 453 u32 pllsw; 454 int branch; 455 bool clk38div; 456 }; 457 458 enum { 459 PLL_RAW, 460 PLL_FIX, 461 PLL_DIV 462 }; 463 464 static DEFINE_SPINLOCK(clk_mgt_lock); 465 466 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 467 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 468 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 469 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 470 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 471 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 472 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 473 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 474 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 475 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 476 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 477 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 478 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 479 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 480 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 481 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 482 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 483 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 484 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 485 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 486 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 487 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 488 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 489 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 490 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 491 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 492 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 493 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 494 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 495 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 496 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 497 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 498 }; 499 500 struct dsiclk { 501 u32 divsel_mask; 502 u32 divsel_shift; 503 u32 divsel; 504 }; 505 506 static struct dsiclk dsiclk[2] = { 507 { 508 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 509 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 510 .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 511 }, 512 { 513 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 514 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 515 .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 516 } 517 }; 518 519 struct dsiescclk { 520 u32 en; 521 u32 div_mask; 522 u32 div_shift; 523 }; 524 525 static struct dsiescclk dsiescclk[3] = { 526 { 527 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 528 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 529 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 530 }, 531 { 532 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 533 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 534 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 535 }, 536 { 537 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 538 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 539 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 540 } 541 }; 542 543 544 /* 545 * Used by MCDE to setup all necessary PRCMU registers 546 */ 547 #define PRCMU_RESET_DSIPLL 0x00004000 548 #define PRCMU_UNCLAMP_DSIPLL 0x00400800 549 550 #define PRCMU_CLK_PLL_DIV_SHIFT 0 551 #define PRCMU_CLK_PLL_SW_SHIFT 5 552 #define PRCMU_CLK_38 (1 << 9) 553 #define PRCMU_CLK_38_SRC (1 << 10) 554 #define PRCMU_CLK_38_DIV (1 << 11) 555 556 /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 557 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 558 559 /* DPI 50000000 Hz */ 560 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 561 (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 562 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 563 564 /* D=101, N=1, R=4, SELDIV2=0 */ 565 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 566 567 #define PRCMU_ENABLE_PLLDSI 0x00000001 568 #define PRCMU_DISABLE_PLLDSI 0x00000000 569 #define PRCMU_RELEASE_RESET_DSS 0x0000400C 570 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 571 /* ESC clk, div0=1, div1=1, div2=3 */ 572 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 573 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 574 #define PRCMU_DSI_RESET_SW 0x00000007 575 576 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 577 578 int db8500_prcmu_enable_dsipll(void) 579 { 580 int i; 581 582 /* Clear DSIPLL_RESETN */ 583 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 584 /* Unclamp DSIPLL in/out */ 585 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 586 587 /* Set DSI PLL FREQ */ 588 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 589 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 590 /* Enable Escape clocks */ 591 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 592 593 /* Start DSI PLL */ 594 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 595 /* Reset DSI PLL */ 596 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 597 for (i = 0; i < 10; i++) { 598 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 599 == PRCMU_PLLDSI_LOCKP_LOCKED) 600 break; 601 udelay(100); 602 } 603 /* Set DSIPLL_RESETN */ 604 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 605 return 0; 606 } 607 608 int db8500_prcmu_disable_dsipll(void) 609 { 610 /* Disable dsi pll */ 611 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 612 /* Disable escapeclock */ 613 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 614 return 0; 615 } 616 617 int db8500_prcmu_set_display_clocks(void) 618 { 619 unsigned long flags; 620 621 spin_lock_irqsave(&clk_mgt_lock, flags); 622 623 /* Grab the HW semaphore. */ 624 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 625 cpu_relax(); 626 627 writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); 628 writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); 629 writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); 630 631 /* Release the HW semaphore. */ 632 writel(0, PRCM_SEM); 633 634 spin_unlock_irqrestore(&clk_mgt_lock, flags); 635 636 return 0; 637 } 638 639 u32 db8500_prcmu_read(unsigned int reg) 640 { 641 return readl(prcmu_base + reg); 642 } 643 644 void db8500_prcmu_write(unsigned int reg, u32 value) 645 { 646 unsigned long flags; 647 648 spin_lock_irqsave(&prcmu_lock, flags); 649 writel(value, (prcmu_base + reg)); 650 spin_unlock_irqrestore(&prcmu_lock, flags); 651 } 652 653 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 654 { 655 u32 val; 656 unsigned long flags; 657 658 spin_lock_irqsave(&prcmu_lock, flags); 659 val = readl(prcmu_base + reg); 660 val = ((val & ~mask) | (value & mask)); 661 writel(val, (prcmu_base + reg)); 662 spin_unlock_irqrestore(&prcmu_lock, flags); 663 } 664 665 struct prcmu_fw_version *prcmu_get_fw_version(void) 666 { 667 return fw_info.valid ? &fw_info.version : NULL; 668 } 669 670 bool prcmu_has_arm_maxopp(void) 671 { 672 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 673 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 674 } 675 676 /** 677 * prcmu_set_rc_a2p - This function is used to run few power state sequences 678 * @val: Value to be set, i.e. transition requested 679 * Returns: 0 on success, -EINVAL on invalid argument 680 * 681 * This function is used to run the following power state sequences - 682 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 683 */ 684 int prcmu_set_rc_a2p(enum romcode_write val) 685 { 686 if (val < RDY_2_DS || val > RDY_2_XP70_RST) 687 return -EINVAL; 688 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 689 return 0; 690 } 691 692 /** 693 * prcmu_get_rc_p2a - This function is used to get power state sequences 694 * Returns: the power transition that has last happened 695 * 696 * This function can return the following transitions- 697 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 698 */ 699 enum romcode_read prcmu_get_rc_p2a(void) 700 { 701 return readb(tcdm_base + PRCM_ROMCODE_P2A); 702 } 703 704 /** 705 * prcmu_get_current_mode - Return the current XP70 power mode 706 * Returns: Returns the current AP(ARM) power mode: init, 707 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 708 */ 709 enum ap_pwrst prcmu_get_xp70_current_state(void) 710 { 711 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 712 } 713 714 /** 715 * prcmu_config_clkout - Configure one of the programmable clock outputs. 716 * @clkout: The CLKOUT number (0 or 1). 717 * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 718 * @div: The divider to be applied. 719 * 720 * Configures one of the programmable clock outputs (CLKOUTs). 721 * @div should be in the range [1,63] to request a configuration, or 0 to 722 * inform that the configuration is no longer requested. 723 */ 724 int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 725 { 726 static int requests[2]; 727 int r = 0; 728 unsigned long flags; 729 u32 val; 730 u32 bits; 731 u32 mask; 732 u32 div_mask; 733 734 BUG_ON(clkout > 1); 735 BUG_ON(div > 63); 736 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 737 738 if (!div && !requests[clkout]) 739 return -EINVAL; 740 741 if (clkout == 0) { 742 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 743 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 744 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 745 (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 746 } else { 747 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 748 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 749 PRCM_CLKOCR_CLK1TYPE); 750 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 751 (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 752 } 753 bits &= mask; 754 755 spin_lock_irqsave(&clkout_lock, flags); 756 757 val = readl(PRCM_CLKOCR); 758 if (val & div_mask) { 759 if (div) { 760 if ((val & mask) != bits) { 761 r = -EBUSY; 762 goto unlock_and_return; 763 } 764 } else { 765 if ((val & mask & ~div_mask) != bits) { 766 r = -EINVAL; 767 goto unlock_and_return; 768 } 769 } 770 } 771 writel((bits | (val & ~mask)), PRCM_CLKOCR); 772 requests[clkout] += (div ? 1 : -1); 773 774 unlock_and_return: 775 spin_unlock_irqrestore(&clkout_lock, flags); 776 777 return r; 778 } 779 780 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 781 { 782 unsigned long flags; 783 784 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 785 786 spin_lock_irqsave(&mb0_transfer.lock, flags); 787 788 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 789 cpu_relax(); 790 791 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 792 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 793 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 794 writeb((keep_ulp_clk ? 1 : 0), 795 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 796 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 797 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 798 799 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 800 801 return 0; 802 } 803 804 u8 db8500_prcmu_get_power_state_result(void) 805 { 806 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 807 } 808 809 /* This function should only be called while mb0_transfer.lock is held. */ 810 static void config_wakeups(void) 811 { 812 const u8 header[2] = { 813 MB0H_CONFIG_WAKEUPS_EXE, 814 MB0H_CONFIG_WAKEUPS_SLEEP 815 }; 816 static u32 last_dbb_events; 817 static u32 last_abb_events; 818 u32 dbb_events; 819 u32 abb_events; 820 unsigned int i; 821 822 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 823 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 824 825 abb_events = mb0_transfer.req.abb_events; 826 827 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 828 return; 829 830 for (i = 0; i < 2; i++) { 831 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 832 cpu_relax(); 833 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 834 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 835 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 836 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 837 } 838 last_dbb_events = dbb_events; 839 last_abb_events = abb_events; 840 } 841 842 void db8500_prcmu_enable_wakeups(u32 wakeups) 843 { 844 unsigned long flags; 845 u32 bits; 846 int i; 847 848 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 849 850 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 851 if (wakeups & BIT(i)) 852 bits |= prcmu_wakeup_bit[i]; 853 } 854 855 spin_lock_irqsave(&mb0_transfer.lock, flags); 856 857 mb0_transfer.req.dbb_wakeups = bits; 858 config_wakeups(); 859 860 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 861 } 862 863 void db8500_prcmu_config_abb_event_readout(u32 abb_events) 864 { 865 unsigned long flags; 866 867 spin_lock_irqsave(&mb0_transfer.lock, flags); 868 869 mb0_transfer.req.abb_events = abb_events; 870 config_wakeups(); 871 872 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 873 } 874 875 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 876 { 877 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 878 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 879 else 880 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 881 } 882 883 /** 884 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 885 * @opp: The new ARM operating point to which transition is to be made 886 * Returns: 0 on success, non-zero on failure 887 * 888 * This function sets the the operating point of the ARM. 889 */ 890 int db8500_prcmu_set_arm_opp(u8 opp) 891 { 892 int r; 893 894 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 895 return -EINVAL; 896 897 r = 0; 898 899 mutex_lock(&mb1_transfer.lock); 900 901 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 902 cpu_relax(); 903 904 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 905 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 906 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 907 908 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 909 wait_for_completion(&mb1_transfer.work); 910 911 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 912 (mb1_transfer.ack.arm_opp != opp)) 913 r = -EIO; 914 915 mutex_unlock(&mb1_transfer.lock); 916 917 return r; 918 } 919 920 /** 921 * db8500_prcmu_get_arm_opp - get the current ARM OPP 922 * 923 * Returns: the current ARM OPP 924 */ 925 int db8500_prcmu_get_arm_opp(void) 926 { 927 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 928 } 929 930 /** 931 * db8500_prcmu_get_ddr_opp - get the current DDR OPP 932 * 933 * Returns: the current DDR OPP 934 */ 935 int db8500_prcmu_get_ddr_opp(void) 936 { 937 return readb(PRCM_DDR_SUBSYS_APE_MINBW); 938 } 939 940 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 941 static void request_even_slower_clocks(bool enable) 942 { 943 u32 clock_reg[] = { 944 PRCM_ACLK_MGT, 945 PRCM_DMACLK_MGT 946 }; 947 unsigned long flags; 948 unsigned int i; 949 950 spin_lock_irqsave(&clk_mgt_lock, flags); 951 952 /* Grab the HW semaphore. */ 953 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 954 cpu_relax(); 955 956 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 957 u32 val; 958 u32 div; 959 960 val = readl(prcmu_base + clock_reg[i]); 961 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 962 if (enable) { 963 if ((div <= 1) || (div > 15)) { 964 pr_err("prcmu: Bad clock divider %d in %s\n", 965 div, __func__); 966 goto unlock_and_return; 967 } 968 div <<= 1; 969 } else { 970 if (div <= 2) 971 goto unlock_and_return; 972 div >>= 1; 973 } 974 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 975 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 976 writel(val, prcmu_base + clock_reg[i]); 977 } 978 979 unlock_and_return: 980 /* Release the HW semaphore. */ 981 writel(0, PRCM_SEM); 982 983 spin_unlock_irqrestore(&clk_mgt_lock, flags); 984 } 985 986 /** 987 * db8500_set_ape_opp - set the appropriate APE OPP 988 * @opp: The new APE operating point to which transition is to be made 989 * Returns: 0 on success, non-zero on failure 990 * 991 * This function sets the operating point of the APE. 992 */ 993 int db8500_prcmu_set_ape_opp(u8 opp) 994 { 995 int r = 0; 996 997 if (opp == mb1_transfer.ape_opp) 998 return 0; 999 1000 mutex_lock(&mb1_transfer.lock); 1001 1002 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 1003 request_even_slower_clocks(false); 1004 1005 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 1006 goto skip_message; 1007 1008 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1009 cpu_relax(); 1010 1011 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1012 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 1013 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 1014 (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 1015 1016 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1017 wait_for_completion(&mb1_transfer.work); 1018 1019 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 1020 (mb1_transfer.ack.ape_opp != opp)) 1021 r = -EIO; 1022 1023 skip_message: 1024 if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 1025 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 1026 request_even_slower_clocks(true); 1027 if (!r) 1028 mb1_transfer.ape_opp = opp; 1029 1030 mutex_unlock(&mb1_transfer.lock); 1031 1032 return r; 1033 } 1034 1035 /** 1036 * db8500_prcmu_get_ape_opp - get the current APE OPP 1037 * 1038 * Returns: the current APE OPP 1039 */ 1040 int db8500_prcmu_get_ape_opp(void) 1041 { 1042 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 1043 } 1044 1045 /** 1046 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 1047 * @enable: true to request the higher voltage, false to drop a request. 1048 * 1049 * Calls to this function to enable and disable requests must be balanced. 1050 */ 1051 int db8500_prcmu_request_ape_opp_100_voltage(bool enable) 1052 { 1053 int r = 0; 1054 u8 header; 1055 static unsigned int requests; 1056 1057 mutex_lock(&mb1_transfer.lock); 1058 1059 if (enable) { 1060 if (0 != requests++) 1061 goto unlock_and_return; 1062 header = MB1H_REQUEST_APE_OPP_100_VOLT; 1063 } else { 1064 if (requests == 0) { 1065 r = -EIO; 1066 goto unlock_and_return; 1067 } else if (1 != requests--) { 1068 goto unlock_and_return; 1069 } 1070 header = MB1H_RELEASE_APE_OPP_100_VOLT; 1071 } 1072 1073 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1074 cpu_relax(); 1075 1076 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1077 1078 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1079 wait_for_completion(&mb1_transfer.work); 1080 1081 if ((mb1_transfer.ack.header != header) || 1082 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 1083 r = -EIO; 1084 1085 unlock_and_return: 1086 mutex_unlock(&mb1_transfer.lock); 1087 1088 return r; 1089 } 1090 1091 /** 1092 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 1093 * 1094 * This function releases the power state requirements of a USB wakeup. 1095 */ 1096 int prcmu_release_usb_wakeup_state(void) 1097 { 1098 int r = 0; 1099 1100 mutex_lock(&mb1_transfer.lock); 1101 1102 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1103 cpu_relax(); 1104 1105 writeb(MB1H_RELEASE_USB_WAKEUP, 1106 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1107 1108 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1109 wait_for_completion(&mb1_transfer.work); 1110 1111 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 1112 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 1113 r = -EIO; 1114 1115 mutex_unlock(&mb1_transfer.lock); 1116 1117 return r; 1118 } 1119 1120 static int request_pll(u8 clock, bool enable) 1121 { 1122 int r = 0; 1123 1124 if (clock == PRCMU_PLLSOC0) 1125 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 1126 else if (clock == PRCMU_PLLSOC1) 1127 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 1128 else 1129 return -EINVAL; 1130 1131 mutex_lock(&mb1_transfer.lock); 1132 1133 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1134 cpu_relax(); 1135 1136 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1137 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 1138 1139 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1140 wait_for_completion(&mb1_transfer.work); 1141 1142 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 1143 r = -EIO; 1144 1145 mutex_unlock(&mb1_transfer.lock); 1146 1147 return r; 1148 } 1149 1150 /** 1151 * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 1152 * @epod_id: The EPOD to set 1153 * @epod_state: The new EPOD state 1154 * 1155 * This function sets the state of a EPOD (power domain). It may not be called 1156 * from interrupt context. 1157 */ 1158 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 1159 { 1160 int r = 0; 1161 bool ram_retention = false; 1162 int i; 1163 1164 /* check argument */ 1165 BUG_ON(epod_id >= NUM_EPOD_ID); 1166 1167 /* set flag if retention is possible */ 1168 switch (epod_id) { 1169 case EPOD_ID_SVAMMDSP: 1170 case EPOD_ID_SIAMMDSP: 1171 case EPOD_ID_ESRAM12: 1172 case EPOD_ID_ESRAM34: 1173 ram_retention = true; 1174 break; 1175 } 1176 1177 /* check argument */ 1178 BUG_ON(epod_state > EPOD_STATE_ON); 1179 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 1180 1181 /* get lock */ 1182 mutex_lock(&mb2_transfer.lock); 1183 1184 /* wait for mailbox */ 1185 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 1186 cpu_relax(); 1187 1188 /* fill in mailbox */ 1189 for (i = 0; i < NUM_EPOD_ID; i++) 1190 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 1191 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 1192 1193 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 1194 1195 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 1196 1197 /* 1198 * The current firmware version does not handle errors correctly, 1199 * and we cannot recover if there is an error. 1200 * This is expected to change when the firmware is updated. 1201 */ 1202 if (!wait_for_completion_timeout(&mb2_transfer.work, 1203 msecs_to_jiffies(20000))) { 1204 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 1205 __func__); 1206 r = -EIO; 1207 goto unlock_and_return; 1208 } 1209 1210 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 1211 r = -EIO; 1212 1213 unlock_and_return: 1214 mutex_unlock(&mb2_transfer.lock); 1215 return r; 1216 } 1217 1218 /** 1219 * prcmu_configure_auto_pm - Configure autonomous power management. 1220 * @sleep: Configuration for ApSleep. 1221 * @idle: Configuration for ApIdle. 1222 */ 1223 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 1224 struct prcmu_auto_pm_config *idle) 1225 { 1226 u32 sleep_cfg; 1227 u32 idle_cfg; 1228 unsigned long flags; 1229 1230 BUG_ON((sleep == NULL) || (idle == NULL)); 1231 1232 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 1233 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 1234 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 1235 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 1236 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 1237 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 1238 1239 idle_cfg = (idle->sva_auto_pm_enable & 0xF); 1240 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 1241 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 1242 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 1243 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 1244 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 1245 1246 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 1247 1248 /* 1249 * The autonomous power management configuration is done through 1250 * fields in mailbox 2, but these fields are only used as shared 1251 * variables - i.e. there is no need to send a message. 1252 */ 1253 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 1254 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 1255 1256 mb2_transfer.auto_pm_enabled = 1257 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 1258 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 1259 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 1260 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 1261 1262 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 1263 } 1264 EXPORT_SYMBOL(prcmu_configure_auto_pm); 1265 1266 bool prcmu_is_auto_pm_enabled(void) 1267 { 1268 return mb2_transfer.auto_pm_enabled; 1269 } 1270 1271 static int request_sysclk(bool enable) 1272 { 1273 int r; 1274 unsigned long flags; 1275 1276 r = 0; 1277 1278 mutex_lock(&mb3_transfer.sysclk_lock); 1279 1280 spin_lock_irqsave(&mb3_transfer.lock, flags); 1281 1282 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 1283 cpu_relax(); 1284 1285 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 1286 1287 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1288 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 1289 1290 spin_unlock_irqrestore(&mb3_transfer.lock, flags); 1291 1292 /* 1293 * The firmware only sends an ACK if we want to enable the 1294 * SysClk, and it succeeds. 1295 */ 1296 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 1297 msecs_to_jiffies(20000))) { 1298 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 1299 __func__); 1300 r = -EIO; 1301 } 1302 1303 mutex_unlock(&mb3_transfer.sysclk_lock); 1304 1305 return r; 1306 } 1307 1308 static int request_timclk(bool enable) 1309 { 1310 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 1311 1312 if (!enable) 1313 val |= PRCM_TCR_STOP_TIMERS; 1314 writel(val, PRCM_TCR); 1315 1316 return 0; 1317 } 1318 1319 static int request_clock(u8 clock, bool enable) 1320 { 1321 u32 val; 1322 unsigned long flags; 1323 1324 spin_lock_irqsave(&clk_mgt_lock, flags); 1325 1326 /* Grab the HW semaphore. */ 1327 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 1328 cpu_relax(); 1329 1330 val = readl(prcmu_base + clk_mgt[clock].offset); 1331 if (enable) { 1332 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 1333 } else { 1334 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 1335 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 1336 } 1337 writel(val, prcmu_base + clk_mgt[clock].offset); 1338 1339 /* Release the HW semaphore. */ 1340 writel(0, PRCM_SEM); 1341 1342 spin_unlock_irqrestore(&clk_mgt_lock, flags); 1343 1344 return 0; 1345 } 1346 1347 static int request_sga_clock(u8 clock, bool enable) 1348 { 1349 u32 val; 1350 int ret; 1351 1352 if (enable) { 1353 val = readl(PRCM_CGATING_BYPASS); 1354 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 1355 } 1356 1357 ret = request_clock(clock, enable); 1358 1359 if (!ret && !enable) { 1360 val = readl(PRCM_CGATING_BYPASS); 1361 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 1362 } 1363 1364 return ret; 1365 } 1366 1367 static inline bool plldsi_locked(void) 1368 { 1369 return (readl(PRCM_PLLDSI_LOCKP) & 1370 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 1371 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 1372 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 1373 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 1374 } 1375 1376 static int request_plldsi(bool enable) 1377 { 1378 int r = 0; 1379 u32 val; 1380 1381 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 1382 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 1383 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 1384 1385 val = readl(PRCM_PLLDSI_ENABLE); 1386 if (enable) 1387 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 1388 else 1389 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 1390 writel(val, PRCM_PLLDSI_ENABLE); 1391 1392 if (enable) { 1393 unsigned int i; 1394 bool locked = plldsi_locked(); 1395 1396 for (i = 10; !locked && (i > 0); --i) { 1397 udelay(100); 1398 locked = plldsi_locked(); 1399 } 1400 if (locked) { 1401 writel(PRCM_APE_RESETN_DSIPLL_RESETN, 1402 PRCM_APE_RESETN_SET); 1403 } else { 1404 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 1405 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 1406 PRCM_MMIP_LS_CLAMP_SET); 1407 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 1408 writel(val, PRCM_PLLDSI_ENABLE); 1409 r = -EAGAIN; 1410 } 1411 } else { 1412 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 1413 } 1414 return r; 1415 } 1416 1417 static int request_dsiclk(u8 n, bool enable) 1418 { 1419 u32 val; 1420 1421 val = readl(PRCM_DSI_PLLOUT_SEL); 1422 val &= ~dsiclk[n].divsel_mask; 1423 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 1424 dsiclk[n].divsel_shift); 1425 writel(val, PRCM_DSI_PLLOUT_SEL); 1426 return 0; 1427 } 1428 1429 static int request_dsiescclk(u8 n, bool enable) 1430 { 1431 u32 val; 1432 1433 val = readl(PRCM_DSITVCLK_DIV); 1434 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 1435 writel(val, PRCM_DSITVCLK_DIV); 1436 return 0; 1437 } 1438 1439 /** 1440 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 1441 * @clock: The clock for which the request is made. 1442 * @enable: Whether the clock should be enabled (true) or disabled (false). 1443 * 1444 * This function should only be used by the clock implementation. 1445 * Do not use it from any other place! 1446 */ 1447 int db8500_prcmu_request_clock(u8 clock, bool enable) 1448 { 1449 if (clock == PRCMU_SGACLK) 1450 return request_sga_clock(clock, enable); 1451 else if (clock < PRCMU_NUM_REG_CLOCKS) 1452 return request_clock(clock, enable); 1453 else if (clock == PRCMU_TIMCLK) 1454 return request_timclk(enable); 1455 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1456 return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 1457 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1458 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 1459 else if (clock == PRCMU_PLLDSI) 1460 return request_plldsi(enable); 1461 else if (clock == PRCMU_SYSCLK) 1462 return request_sysclk(enable); 1463 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 1464 return request_pll(clock, enable); 1465 else 1466 return -EINVAL; 1467 } 1468 1469 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 1470 int branch) 1471 { 1472 u64 rate; 1473 u32 val; 1474 u32 d; 1475 u32 div = 1; 1476 1477 val = readl(reg); 1478 1479 rate = src_rate; 1480 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 1481 1482 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 1483 if (d > 1) 1484 div *= d; 1485 1486 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 1487 if (d > 1) 1488 div *= d; 1489 1490 if (val & PRCM_PLL_FREQ_SELDIV2) 1491 div *= 2; 1492 1493 if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 1494 (val & PRCM_PLL_FREQ_DIV2EN) && 1495 ((reg == PRCM_PLLSOC0_FREQ) || 1496 (reg == PRCM_PLLARM_FREQ) || 1497 (reg == PRCM_PLLDDR_FREQ)))) 1498 div *= 2; 1499 1500 (void)do_div(rate, div); 1501 1502 return (unsigned long)rate; 1503 } 1504 1505 #define ROOT_CLOCK_RATE 38400000 1506 1507 static unsigned long clock_rate(u8 clock) 1508 { 1509 u32 val; 1510 u32 pllsw; 1511 unsigned long rate = ROOT_CLOCK_RATE; 1512 1513 val = readl(prcmu_base + clk_mgt[clock].offset); 1514 1515 if (val & PRCM_CLK_MGT_CLK38) { 1516 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 1517 rate /= 2; 1518 return rate; 1519 } 1520 1521 val |= clk_mgt[clock].pllsw; 1522 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 1523 1524 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 1525 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 1526 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 1527 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 1528 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 1529 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 1530 else 1531 return 0; 1532 1533 if ((clock == PRCMU_SGACLK) && 1534 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 1535 u64 r = (rate * 10); 1536 1537 (void)do_div(r, 25); 1538 return (unsigned long)r; 1539 } 1540 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 1541 if (val) 1542 return rate / val; 1543 else 1544 return 0; 1545 } 1546 1547 static unsigned long armss_rate(void) 1548 { 1549 u32 r; 1550 unsigned long rate; 1551 1552 r = readl(PRCM_ARM_CHGCLKREQ); 1553 1554 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { 1555 /* External ARMCLKFIX clock */ 1556 1557 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); 1558 1559 /* Check PRCM_ARM_CHGCLKREQ divider */ 1560 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) 1561 rate /= 2; 1562 1563 /* Check PRCM_ARMCLKFIX_MGT divider */ 1564 r = readl(PRCM_ARMCLKFIX_MGT); 1565 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 1566 rate /= r; 1567 1568 } else {/* ARM PLL */ 1569 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); 1570 } 1571 1572 return rate; 1573 } 1574 1575 static unsigned long dsiclk_rate(u8 n) 1576 { 1577 u32 divsel; 1578 u32 div = 1; 1579 1580 divsel = readl(PRCM_DSI_PLLOUT_SEL); 1581 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 1582 1583 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 1584 divsel = dsiclk[n].divsel; 1585 else 1586 dsiclk[n].divsel = divsel; 1587 1588 switch (divsel) { 1589 case PRCM_DSI_PLLOUT_SEL_PHI_4: 1590 div *= 2; 1591 case PRCM_DSI_PLLOUT_SEL_PHI_2: 1592 div *= 2; 1593 case PRCM_DSI_PLLOUT_SEL_PHI: 1594 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 1595 PLL_RAW) / div; 1596 default: 1597 return 0; 1598 } 1599 } 1600 1601 static unsigned long dsiescclk_rate(u8 n) 1602 { 1603 u32 div; 1604 1605 div = readl(PRCM_DSITVCLK_DIV); 1606 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 1607 return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 1608 } 1609 1610 unsigned long prcmu_clock_rate(u8 clock) 1611 { 1612 if (clock < PRCMU_NUM_REG_CLOCKS) 1613 return clock_rate(clock); 1614 else if (clock == PRCMU_TIMCLK) 1615 return ROOT_CLOCK_RATE / 16; 1616 else if (clock == PRCMU_SYSCLK) 1617 return ROOT_CLOCK_RATE; 1618 else if (clock == PRCMU_PLLSOC0) 1619 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1620 else if (clock == PRCMU_PLLSOC1) 1621 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1622 else if (clock == PRCMU_ARMSS) 1623 return armss_rate(); 1624 else if (clock == PRCMU_PLLDDR) 1625 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1626 else if (clock == PRCMU_PLLDSI) 1627 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 1628 PLL_RAW); 1629 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1630 return dsiclk_rate(clock - PRCMU_DSI0CLK); 1631 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1632 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 1633 else 1634 return 0; 1635 } 1636 1637 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 1638 { 1639 if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 1640 return ROOT_CLOCK_RATE; 1641 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 1642 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 1643 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 1644 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 1645 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 1646 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 1647 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 1648 else 1649 return 0; 1650 } 1651 1652 static u32 clock_divider(unsigned long src_rate, unsigned long rate) 1653 { 1654 u32 div; 1655 1656 div = (src_rate / rate); 1657 if (div == 0) 1658 return 1; 1659 if (rate < (src_rate / div)) 1660 div++; 1661 return div; 1662 } 1663 1664 static long round_clock_rate(u8 clock, unsigned long rate) 1665 { 1666 u32 val; 1667 u32 div; 1668 unsigned long src_rate; 1669 long rounded_rate; 1670 1671 val = readl(prcmu_base + clk_mgt[clock].offset); 1672 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 1673 clk_mgt[clock].branch); 1674 div = clock_divider(src_rate, rate); 1675 if (val & PRCM_CLK_MGT_CLK38) { 1676 if (clk_mgt[clock].clk38div) { 1677 if (div > 2) 1678 div = 2; 1679 } else { 1680 div = 1; 1681 } 1682 } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 1683 u64 r = (src_rate * 10); 1684 1685 (void)do_div(r, 25); 1686 if (r <= rate) 1687 return (unsigned long)r; 1688 } 1689 rounded_rate = (src_rate / min(div, (u32)31)); 1690 1691 return rounded_rate; 1692 } 1693 1694 static const unsigned long armss_freqs[] = { 1695 200000000, 1696 400000000, 1697 800000000, 1698 998400000 1699 }; 1700 1701 static long round_armss_rate(unsigned long rate) 1702 { 1703 unsigned long freq = 0; 1704 int i; 1705 1706 /* Find the corresponding arm opp from the cpufreq table. */ 1707 for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) { 1708 freq = armss_freqs[i]; 1709 if (rate <= freq) 1710 break; 1711 } 1712 1713 /* Return the last valid value, even if a match was not found. */ 1714 return freq; 1715 } 1716 1717 #define MIN_PLL_VCO_RATE 600000000ULL 1718 #define MAX_PLL_VCO_RATE 1680640000ULL 1719 1720 static long round_plldsi_rate(unsigned long rate) 1721 { 1722 long rounded_rate = 0; 1723 unsigned long src_rate; 1724 unsigned long rem; 1725 u32 r; 1726 1727 src_rate = clock_rate(PRCMU_HDMICLK); 1728 rem = rate; 1729 1730 for (r = 7; (rem > 0) && (r > 0); r--) { 1731 u64 d; 1732 1733 d = (r * rate); 1734 (void)do_div(d, src_rate); 1735 if (d < 6) 1736 d = 6; 1737 else if (d > 255) 1738 d = 255; 1739 d *= src_rate; 1740 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 1741 ((r * MAX_PLL_VCO_RATE) < (2 * d))) 1742 continue; 1743 (void)do_div(d, r); 1744 if (rate < d) { 1745 if (rounded_rate == 0) 1746 rounded_rate = (long)d; 1747 break; 1748 } 1749 if ((rate - d) < rem) { 1750 rem = (rate - d); 1751 rounded_rate = (long)d; 1752 } 1753 } 1754 return rounded_rate; 1755 } 1756 1757 static long round_dsiclk_rate(unsigned long rate) 1758 { 1759 u32 div; 1760 unsigned long src_rate; 1761 long rounded_rate; 1762 1763 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 1764 PLL_RAW); 1765 div = clock_divider(src_rate, rate); 1766 rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 1767 1768 return rounded_rate; 1769 } 1770 1771 static long round_dsiescclk_rate(unsigned long rate) 1772 { 1773 u32 div; 1774 unsigned long src_rate; 1775 long rounded_rate; 1776 1777 src_rate = clock_rate(PRCMU_TVCLK); 1778 div = clock_divider(src_rate, rate); 1779 rounded_rate = (src_rate / min(div, (u32)255)); 1780 1781 return rounded_rate; 1782 } 1783 1784 long prcmu_round_clock_rate(u8 clock, unsigned long rate) 1785 { 1786 if (clock < PRCMU_NUM_REG_CLOCKS) 1787 return round_clock_rate(clock, rate); 1788 else if (clock == PRCMU_ARMSS) 1789 return round_armss_rate(rate); 1790 else if (clock == PRCMU_PLLDSI) 1791 return round_plldsi_rate(rate); 1792 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1793 return round_dsiclk_rate(rate); 1794 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1795 return round_dsiescclk_rate(rate); 1796 else 1797 return (long)prcmu_clock_rate(clock); 1798 } 1799 1800 static void set_clock_rate(u8 clock, unsigned long rate) 1801 { 1802 u32 val; 1803 u32 div; 1804 unsigned long src_rate; 1805 unsigned long flags; 1806 1807 spin_lock_irqsave(&clk_mgt_lock, flags); 1808 1809 /* Grab the HW semaphore. */ 1810 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 1811 cpu_relax(); 1812 1813 val = readl(prcmu_base + clk_mgt[clock].offset); 1814 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 1815 clk_mgt[clock].branch); 1816 div = clock_divider(src_rate, rate); 1817 if (val & PRCM_CLK_MGT_CLK38) { 1818 if (clk_mgt[clock].clk38div) { 1819 if (div > 1) 1820 val |= PRCM_CLK_MGT_CLK38DIV; 1821 else 1822 val &= ~PRCM_CLK_MGT_CLK38DIV; 1823 } 1824 } else if (clock == PRCMU_SGACLK) { 1825 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 1826 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 1827 if (div == 3) { 1828 u64 r = (src_rate * 10); 1829 1830 (void)do_div(r, 25); 1831 if (r <= rate) { 1832 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 1833 div = 0; 1834 } 1835 } 1836 val |= min(div, (u32)31); 1837 } else { 1838 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 1839 val |= min(div, (u32)31); 1840 } 1841 writel(val, prcmu_base + clk_mgt[clock].offset); 1842 1843 /* Release the HW semaphore. */ 1844 writel(0, PRCM_SEM); 1845 1846 spin_unlock_irqrestore(&clk_mgt_lock, flags); 1847 } 1848 1849 static int set_armss_rate(unsigned long rate) 1850 { 1851 unsigned long freq; 1852 u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP }; 1853 int i; 1854 1855 /* Find the corresponding arm opp from the cpufreq table. */ 1856 for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) { 1857 freq = armss_freqs[i]; 1858 if (rate == freq) 1859 break; 1860 } 1861 1862 if (rate != freq) 1863 return -EINVAL; 1864 1865 /* Set the new arm opp. */ 1866 pr_debug("SET ARM OPP 0x%02x\n", opps[i]); 1867 return db8500_prcmu_set_arm_opp(opps[i]); 1868 } 1869 1870 static int set_plldsi_rate(unsigned long rate) 1871 { 1872 unsigned long src_rate; 1873 unsigned long rem; 1874 u32 pll_freq = 0; 1875 u32 r; 1876 1877 src_rate = clock_rate(PRCMU_HDMICLK); 1878 rem = rate; 1879 1880 for (r = 7; (rem > 0) && (r > 0); r--) { 1881 u64 d; 1882 u64 hwrate; 1883 1884 d = (r * rate); 1885 (void)do_div(d, src_rate); 1886 if (d < 6) 1887 d = 6; 1888 else if (d > 255) 1889 d = 255; 1890 hwrate = (d * src_rate); 1891 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 1892 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 1893 continue; 1894 (void)do_div(hwrate, r); 1895 if (rate < hwrate) { 1896 if (pll_freq == 0) 1897 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 1898 (r << PRCM_PLL_FREQ_R_SHIFT)); 1899 break; 1900 } 1901 if ((rate - hwrate) < rem) { 1902 rem = (rate - hwrate); 1903 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 1904 (r << PRCM_PLL_FREQ_R_SHIFT)); 1905 } 1906 } 1907 if (pll_freq == 0) 1908 return -EINVAL; 1909 1910 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 1911 writel(pll_freq, PRCM_PLLDSI_FREQ); 1912 1913 return 0; 1914 } 1915 1916 static void set_dsiclk_rate(u8 n, unsigned long rate) 1917 { 1918 u32 val; 1919 u32 div; 1920 1921 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 1922 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 1923 1924 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 1925 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 1926 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 1927 1928 val = readl(PRCM_DSI_PLLOUT_SEL); 1929 val &= ~dsiclk[n].divsel_mask; 1930 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 1931 writel(val, PRCM_DSI_PLLOUT_SEL); 1932 } 1933 1934 static void set_dsiescclk_rate(u8 n, unsigned long rate) 1935 { 1936 u32 val; 1937 u32 div; 1938 1939 div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 1940 val = readl(PRCM_DSITVCLK_DIV); 1941 val &= ~dsiescclk[n].div_mask; 1942 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 1943 writel(val, PRCM_DSITVCLK_DIV); 1944 } 1945 1946 int prcmu_set_clock_rate(u8 clock, unsigned long rate) 1947 { 1948 if (clock < PRCMU_NUM_REG_CLOCKS) 1949 set_clock_rate(clock, rate); 1950 else if (clock == PRCMU_ARMSS) 1951 return set_armss_rate(rate); 1952 else if (clock == PRCMU_PLLDSI) 1953 return set_plldsi_rate(rate); 1954 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1955 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 1956 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 1957 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 1958 return 0; 1959 } 1960 1961 int db8500_prcmu_config_esram0_deep_sleep(u8 state) 1962 { 1963 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 1964 (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 1965 return -EINVAL; 1966 1967 mutex_lock(&mb4_transfer.lock); 1968 1969 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 1970 cpu_relax(); 1971 1972 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 1973 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 1974 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 1975 writeb(DDR_PWR_STATE_ON, 1976 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 1977 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 1978 1979 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 1980 wait_for_completion(&mb4_transfer.work); 1981 1982 mutex_unlock(&mb4_transfer.lock); 1983 1984 return 0; 1985 } 1986 1987 int db8500_prcmu_config_hotdog(u8 threshold) 1988 { 1989 mutex_lock(&mb4_transfer.lock); 1990 1991 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 1992 cpu_relax(); 1993 1994 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 1995 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 1996 1997 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 1998 wait_for_completion(&mb4_transfer.work); 1999 2000 mutex_unlock(&mb4_transfer.lock); 2001 2002 return 0; 2003 } 2004 2005 int db8500_prcmu_config_hotmon(u8 low, u8 high) 2006 { 2007 mutex_lock(&mb4_transfer.lock); 2008 2009 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 2010 cpu_relax(); 2011 2012 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 2013 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 2014 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 2015 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 2016 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 2017 2018 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 2019 wait_for_completion(&mb4_transfer.work); 2020 2021 mutex_unlock(&mb4_transfer.lock); 2022 2023 return 0; 2024 } 2025 EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon); 2026 2027 static int config_hot_period(u16 val) 2028 { 2029 mutex_lock(&mb4_transfer.lock); 2030 2031 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 2032 cpu_relax(); 2033 2034 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 2035 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 2036 2037 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 2038 wait_for_completion(&mb4_transfer.work); 2039 2040 mutex_unlock(&mb4_transfer.lock); 2041 2042 return 0; 2043 } 2044 2045 int db8500_prcmu_start_temp_sense(u16 cycles32k) 2046 { 2047 if (cycles32k == 0xFFFF) 2048 return -EINVAL; 2049 2050 return config_hot_period(cycles32k); 2051 } 2052 EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense); 2053 2054 int db8500_prcmu_stop_temp_sense(void) 2055 { 2056 return config_hot_period(0xFFFF); 2057 } 2058 EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense); 2059 2060 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 2061 { 2062 2063 mutex_lock(&mb4_transfer.lock); 2064 2065 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 2066 cpu_relax(); 2067 2068 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 2069 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 2070 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 2071 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 2072 2073 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 2074 2075 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 2076 wait_for_completion(&mb4_transfer.work); 2077 2078 mutex_unlock(&mb4_transfer.lock); 2079 2080 return 0; 2081 2082 } 2083 2084 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 2085 { 2086 BUG_ON(num == 0 || num > 0xf); 2087 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 2088 sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 2089 A9WDOG_AUTO_OFF_DIS); 2090 } 2091 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); 2092 2093 int db8500_prcmu_enable_a9wdog(u8 id) 2094 { 2095 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 2096 } 2097 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); 2098 2099 int db8500_prcmu_disable_a9wdog(u8 id) 2100 { 2101 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 2102 } 2103 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); 2104 2105 int db8500_prcmu_kick_a9wdog(u8 id) 2106 { 2107 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 2108 } 2109 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); 2110 2111 /* 2112 * timeout is 28 bit, in ms. 2113 */ 2114 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 2115 { 2116 return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 2117 (id & A9WDOG_ID_MASK) | 2118 /* 2119 * Put the lowest 28 bits of timeout at 2120 * offset 4. Four first bits are used for id. 2121 */ 2122 (u8)((timeout << 4) & 0xf0), 2123 (u8)((timeout >> 4) & 0xff), 2124 (u8)((timeout >> 12) & 0xff), 2125 (u8)((timeout >> 20) & 0xff)); 2126 } 2127 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); 2128 2129 /** 2130 * prcmu_abb_read() - Read register value(s) from the ABB. 2131 * @slave: The I2C slave address. 2132 * @reg: The (start) register address. 2133 * @value: The read out value(s). 2134 * @size: The number of registers to read. 2135 * 2136 * Reads register value(s) from the ABB. 2137 * @size has to be 1 for the current firmware version. 2138 */ 2139 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2140 { 2141 int r; 2142 2143 if (size != 1) 2144 return -EINVAL; 2145 2146 mutex_lock(&mb5_transfer.lock); 2147 2148 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2149 cpu_relax(); 2150 2151 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 2152 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 2153 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 2154 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 2155 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2156 2157 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 2158 2159 if (!wait_for_completion_timeout(&mb5_transfer.work, 2160 msecs_to_jiffies(20000))) { 2161 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 2162 __func__); 2163 r = -EIO; 2164 } else { 2165 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 2166 } 2167 2168 if (!r) 2169 *value = mb5_transfer.ack.value; 2170 2171 mutex_unlock(&mb5_transfer.lock); 2172 2173 return r; 2174 } 2175 2176 /** 2177 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. 2178 * @slave: The I2C slave address. 2179 * @reg: The (start) register address. 2180 * @value: The value(s) to write. 2181 * @mask: The mask(s) to use. 2182 * @size: The number of registers to write. 2183 * 2184 * Writes masked register value(s) to the ABB. 2185 * For each @value, only the bits set to 1 in the corresponding @mask 2186 * will be written. The other bits are not changed. 2187 * @size has to be 1 for the current firmware version. 2188 */ 2189 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) 2190 { 2191 int r; 2192 2193 if (size != 1) 2194 return -EINVAL; 2195 2196 mutex_lock(&mb5_transfer.lock); 2197 2198 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2199 cpu_relax(); 2200 2201 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 2202 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 2203 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 2204 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 2205 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2206 2207 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 2208 2209 if (!wait_for_completion_timeout(&mb5_transfer.work, 2210 msecs_to_jiffies(20000))) { 2211 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 2212 __func__); 2213 r = -EIO; 2214 } else { 2215 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 2216 } 2217 2218 mutex_unlock(&mb5_transfer.lock); 2219 2220 return r; 2221 } 2222 2223 /** 2224 * prcmu_abb_write() - Write register value(s) to the ABB. 2225 * @slave: The I2C slave address. 2226 * @reg: The (start) register address. 2227 * @value: The value(s) to write. 2228 * @size: The number of registers to write. 2229 * 2230 * Writes register value(s) to the ABB. 2231 * @size has to be 1 for the current firmware version. 2232 */ 2233 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 2234 { 2235 u8 mask = ~0; 2236 2237 return prcmu_abb_write_masked(slave, reg, value, &mask, size); 2238 } 2239 2240 /** 2241 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 2242 */ 2243 int prcmu_ac_wake_req(void) 2244 { 2245 u32 val; 2246 int ret = 0; 2247 2248 mutex_lock(&mb0_transfer.ac_wake_lock); 2249 2250 val = readl(PRCM_HOSTACCESS_REQ); 2251 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 2252 goto unlock_and_return; 2253 2254 atomic_set(&ac_wake_req_state, 1); 2255 2256 /* 2257 * Force Modem Wake-up before hostaccess_req ping-pong. 2258 * It prevents Modem to enter in Sleep while acking the hostaccess 2259 * request. The 31us delay has been calculated by HWI. 2260 */ 2261 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; 2262 writel(val, PRCM_HOSTACCESS_REQ); 2263 2264 udelay(31); 2265 2266 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; 2267 writel(val, PRCM_HOSTACCESS_REQ); 2268 2269 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2270 msecs_to_jiffies(5000))) { 2271 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2272 __func__); 2273 ret = -EFAULT; 2274 } 2275 2276 unlock_and_return: 2277 mutex_unlock(&mb0_transfer.ac_wake_lock); 2278 return ret; 2279 } 2280 2281 /** 2282 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 2283 */ 2284 void prcmu_ac_sleep_req(void) 2285 { 2286 u32 val; 2287 2288 mutex_lock(&mb0_transfer.ac_wake_lock); 2289 2290 val = readl(PRCM_HOSTACCESS_REQ); 2291 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 2292 goto unlock_and_return; 2293 2294 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2295 PRCM_HOSTACCESS_REQ); 2296 2297 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2298 msecs_to_jiffies(5000))) { 2299 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2300 __func__); 2301 } 2302 2303 atomic_set(&ac_wake_req_state, 0); 2304 2305 unlock_and_return: 2306 mutex_unlock(&mb0_transfer.ac_wake_lock); 2307 } 2308 2309 bool db8500_prcmu_is_ac_wake_requested(void) 2310 { 2311 return (atomic_read(&ac_wake_req_state) != 0); 2312 } 2313 2314 /** 2315 * db8500_prcmu_system_reset - System reset 2316 * 2317 * Saves the reset reason code and then sets the APE_SOFTRST register which 2318 * fires interrupt to fw 2319 */ 2320 void db8500_prcmu_system_reset(u16 reset_code) 2321 { 2322 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2323 writel(1, PRCM_APE_SOFTRST); 2324 } 2325 2326 /** 2327 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2328 * 2329 * Retrieves the reset reason code stored by prcmu_system_reset() before 2330 * last restart. 2331 */ 2332 u16 db8500_prcmu_get_reset_code(void) 2333 { 2334 return readw(tcdm_base + PRCM_SW_RST_REASON); 2335 } 2336 2337 /** 2338 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 2339 */ 2340 void db8500_prcmu_modem_reset(void) 2341 { 2342 mutex_lock(&mb1_transfer.lock); 2343 2344 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2345 cpu_relax(); 2346 2347 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2348 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2349 wait_for_completion(&mb1_transfer.work); 2350 2351 /* 2352 * No need to check return from PRCMU as modem should go in reset state 2353 * This state is already managed by upper layer 2354 */ 2355 2356 mutex_unlock(&mb1_transfer.lock); 2357 } 2358 2359 static void ack_dbb_wakeup(void) 2360 { 2361 unsigned long flags; 2362 2363 spin_lock_irqsave(&mb0_transfer.lock, flags); 2364 2365 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 2366 cpu_relax(); 2367 2368 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2369 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2370 2371 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2372 } 2373 2374 static inline void print_unknown_header_warning(u8 n, u8 header) 2375 { 2376 pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n", 2377 header, n); 2378 } 2379 2380 static bool read_mailbox_0(void) 2381 { 2382 bool r; 2383 u32 ev; 2384 unsigned int n; 2385 u8 header; 2386 2387 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 2388 switch (header) { 2389 case MB0H_WAKEUP_EXE: 2390 case MB0H_WAKEUP_SLEEP: 2391 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 2392 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 2393 else 2394 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 2395 2396 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 2397 complete(&mb0_transfer.ac_wake_work); 2398 if (ev & WAKEUP_BIT_SYSCLK_OK) 2399 complete(&mb3_transfer.sysclk_work); 2400 2401 ev &= mb0_transfer.req.dbb_irqs; 2402 2403 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 2404 if (ev & prcmu_irq_bit[n]) 2405 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); 2406 } 2407 r = true; 2408 break; 2409 default: 2410 print_unknown_header_warning(0, header); 2411 r = false; 2412 break; 2413 } 2414 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 2415 return r; 2416 } 2417 2418 static bool read_mailbox_1(void) 2419 { 2420 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 2421 mb1_transfer.ack.arm_opp = readb(tcdm_base + 2422 PRCM_ACK_MB1_CURRENT_ARM_OPP); 2423 mb1_transfer.ack.ape_opp = readb(tcdm_base + 2424 PRCM_ACK_MB1_CURRENT_APE_OPP); 2425 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 2426 PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2427 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2428 complete(&mb1_transfer.work); 2429 return false; 2430 } 2431 2432 static bool read_mailbox_2(void) 2433 { 2434 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2435 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 2436 complete(&mb2_transfer.work); 2437 return false; 2438 } 2439 2440 static bool read_mailbox_3(void) 2441 { 2442 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 2443 return false; 2444 } 2445 2446 static bool read_mailbox_4(void) 2447 { 2448 u8 header; 2449 bool do_complete = true; 2450 2451 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 2452 switch (header) { 2453 case MB4H_MEM_ST: 2454 case MB4H_HOTDOG: 2455 case MB4H_HOTMON: 2456 case MB4H_HOT_PERIOD: 2457 case MB4H_A9WDOG_CONF: 2458 case MB4H_A9WDOG_EN: 2459 case MB4H_A9WDOG_DIS: 2460 case MB4H_A9WDOG_LOAD: 2461 case MB4H_A9WDOG_KICK: 2462 break; 2463 default: 2464 print_unknown_header_warning(4, header); 2465 do_complete = false; 2466 break; 2467 } 2468 2469 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 2470 2471 if (do_complete) 2472 complete(&mb4_transfer.work); 2473 2474 return false; 2475 } 2476 2477 static bool read_mailbox_5(void) 2478 { 2479 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 2480 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2481 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2482 complete(&mb5_transfer.work); 2483 return false; 2484 } 2485 2486 static bool read_mailbox_6(void) 2487 { 2488 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 2489 return false; 2490 } 2491 2492 static bool read_mailbox_7(void) 2493 { 2494 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 2495 return false; 2496 } 2497 2498 static bool (* const read_mailbox[NUM_MB])(void) = { 2499 read_mailbox_0, 2500 read_mailbox_1, 2501 read_mailbox_2, 2502 read_mailbox_3, 2503 read_mailbox_4, 2504 read_mailbox_5, 2505 read_mailbox_6, 2506 read_mailbox_7 2507 }; 2508 2509 static irqreturn_t prcmu_irq_handler(int irq, void *data) 2510 { 2511 u32 bits; 2512 u8 n; 2513 irqreturn_t r; 2514 2515 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2516 if (unlikely(!bits)) 2517 return IRQ_NONE; 2518 2519 r = IRQ_HANDLED; 2520 for (n = 0; bits; n++) { 2521 if (bits & MBOX_BIT(n)) { 2522 bits -= MBOX_BIT(n); 2523 if (read_mailbox[n]()) 2524 r = IRQ_WAKE_THREAD; 2525 } 2526 } 2527 return r; 2528 } 2529 2530 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 2531 { 2532 ack_dbb_wakeup(); 2533 return IRQ_HANDLED; 2534 } 2535 2536 static void prcmu_mask_work(struct work_struct *work) 2537 { 2538 unsigned long flags; 2539 2540 spin_lock_irqsave(&mb0_transfer.lock, flags); 2541 2542 config_wakeups(); 2543 2544 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2545 } 2546 2547 static void prcmu_irq_mask(struct irq_data *d) 2548 { 2549 unsigned long flags; 2550 2551 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 2552 2553 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; 2554 2555 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 2556 2557 if (d->irq != IRQ_PRCMU_CA_SLEEP) 2558 schedule_work(&mb0_transfer.mask_work); 2559 } 2560 2561 static void prcmu_irq_unmask(struct irq_data *d) 2562 { 2563 unsigned long flags; 2564 2565 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 2566 2567 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; 2568 2569 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 2570 2571 if (d->irq != IRQ_PRCMU_CA_SLEEP) 2572 schedule_work(&mb0_transfer.mask_work); 2573 } 2574 2575 static void noop(struct irq_data *d) 2576 { 2577 } 2578 2579 static struct irq_chip prcmu_irq_chip = { 2580 .name = "prcmu", 2581 .irq_disable = prcmu_irq_mask, 2582 .irq_ack = noop, 2583 .irq_mask = prcmu_irq_mask, 2584 .irq_unmask = prcmu_irq_unmask, 2585 }; 2586 2587 static char *fw_project_name(u32 project) 2588 { 2589 switch (project) { 2590 case PRCMU_FW_PROJECT_U8500: 2591 return "U8500"; 2592 case PRCMU_FW_PROJECT_U8400: 2593 return "U8400"; 2594 case PRCMU_FW_PROJECT_U9500: 2595 return "U9500"; 2596 case PRCMU_FW_PROJECT_U8500_MBB: 2597 return "U8500 MBB"; 2598 case PRCMU_FW_PROJECT_U8500_C1: 2599 return "U8500 C1"; 2600 case PRCMU_FW_PROJECT_U8500_C2: 2601 return "U8500 C2"; 2602 case PRCMU_FW_PROJECT_U8500_C3: 2603 return "U8500 C3"; 2604 case PRCMU_FW_PROJECT_U8500_C4: 2605 return "U8500 C4"; 2606 case PRCMU_FW_PROJECT_U9500_MBL: 2607 return "U9500 MBL"; 2608 case PRCMU_FW_PROJECT_U8500_MBL: 2609 return "U8500 MBL"; 2610 case PRCMU_FW_PROJECT_U8500_MBL2: 2611 return "U8500 MBL2"; 2612 case PRCMU_FW_PROJECT_U8520: 2613 return "U8520 MBL"; 2614 case PRCMU_FW_PROJECT_U8420: 2615 return "U8420"; 2616 case PRCMU_FW_PROJECT_U9540: 2617 return "U9540"; 2618 case PRCMU_FW_PROJECT_A9420: 2619 return "A9420"; 2620 case PRCMU_FW_PROJECT_L8540: 2621 return "L8540"; 2622 case PRCMU_FW_PROJECT_L8580: 2623 return "L8580"; 2624 default: 2625 return "Unknown"; 2626 } 2627 } 2628 2629 static int db8500_irq_map(struct irq_domain *d, unsigned int virq, 2630 irq_hw_number_t hwirq) 2631 { 2632 irq_set_chip_and_handler(virq, &prcmu_irq_chip, 2633 handle_simple_irq); 2634 2635 return 0; 2636 } 2637 2638 static const struct irq_domain_ops db8500_irq_ops = { 2639 .map = db8500_irq_map, 2640 .xlate = irq_domain_xlate_twocell, 2641 }; 2642 2643 static int db8500_irq_init(struct device_node *np) 2644 { 2645 int i; 2646 2647 db8500_irq_domain = irq_domain_add_simple( 2648 np, NUM_PRCMU_WAKEUPS, 0, 2649 &db8500_irq_ops, NULL); 2650 2651 if (!db8500_irq_domain) { 2652 pr_err("Failed to create irqdomain\n"); 2653 return -ENOSYS; 2654 } 2655 2656 /* All wakeups will be used, so create mappings for all */ 2657 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) 2658 irq_create_mapping(db8500_irq_domain, i); 2659 2660 return 0; 2661 } 2662 2663 static void dbx500_fw_version_init(struct platform_device *pdev, 2664 u32 version_offset) 2665 { 2666 struct resource *res; 2667 void __iomem *tcpm_base; 2668 u32 version; 2669 2670 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2671 "prcmu-tcpm"); 2672 if (!res) { 2673 dev_err(&pdev->dev, 2674 "Error: no prcmu tcpm memory region provided\n"); 2675 return; 2676 } 2677 tcpm_base = ioremap(res->start, resource_size(res)); 2678 if (!tcpm_base) { 2679 dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n"); 2680 return; 2681 } 2682 2683 version = readl(tcpm_base + version_offset); 2684 fw_info.version.project = (version & 0xFF); 2685 fw_info.version.api_version = (version >> 8) & 0xFF; 2686 fw_info.version.func_version = (version >> 16) & 0xFF; 2687 fw_info.version.errata = (version >> 24) & 0xFF; 2688 strncpy(fw_info.version.project_name, 2689 fw_project_name(fw_info.version.project), 2690 PRCMU_FW_PROJECT_NAME_LEN); 2691 fw_info.valid = true; 2692 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", 2693 fw_info.version.project_name, 2694 fw_info.version.project, 2695 fw_info.version.api_version, 2696 fw_info.version.func_version, 2697 fw_info.version.errata); 2698 iounmap(tcpm_base); 2699 } 2700 2701 void __init db8500_prcmu_early_init(u32 phy_base, u32 size) 2702 { 2703 /* 2704 * This is a temporary remap to bring up the clocks. It is 2705 * subsequently replaces with a real remap. After the merge of 2706 * the mailbox subsystem all of this early code goes away, and the 2707 * clock driver can probe independently. An early initcall will 2708 * still be needed, but it can be diverted into drivers/clk/ux500. 2709 */ 2710 prcmu_base = ioremap(phy_base, size); 2711 if (!prcmu_base) 2712 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); 2713 2714 spin_lock_init(&mb0_transfer.lock); 2715 spin_lock_init(&mb0_transfer.dbb_irqs_lock); 2716 mutex_init(&mb0_transfer.ac_wake_lock); 2717 init_completion(&mb0_transfer.ac_wake_work); 2718 mutex_init(&mb1_transfer.lock); 2719 init_completion(&mb1_transfer.work); 2720 mb1_transfer.ape_opp = APE_NO_CHANGE; 2721 mutex_init(&mb2_transfer.lock); 2722 init_completion(&mb2_transfer.work); 2723 spin_lock_init(&mb2_transfer.auto_pm_lock); 2724 spin_lock_init(&mb3_transfer.lock); 2725 mutex_init(&mb3_transfer.sysclk_lock); 2726 init_completion(&mb3_transfer.sysclk_work); 2727 mutex_init(&mb4_transfer.lock); 2728 init_completion(&mb4_transfer.work); 2729 mutex_init(&mb5_transfer.lock); 2730 init_completion(&mb5_transfer.work); 2731 2732 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2733 } 2734 2735 static void init_prcm_registers(void) 2736 { 2737 u32 val; 2738 2739 val = readl(PRCM_A9PL_FORCE_CLKEN); 2740 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2741 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2742 writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2743 } 2744 2745 /* 2746 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 2747 */ 2748 static struct regulator_consumer_supply db8500_vape_consumers[] = { 2749 REGULATOR_SUPPLY("v-ape", NULL), 2750 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 2751 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 2752 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 2753 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 2754 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), 2755 /* "v-mmc" changed to "vcore" in the mainline kernel */ 2756 REGULATOR_SUPPLY("vcore", "sdi0"), 2757 REGULATOR_SUPPLY("vcore", "sdi1"), 2758 REGULATOR_SUPPLY("vcore", "sdi2"), 2759 REGULATOR_SUPPLY("vcore", "sdi3"), 2760 REGULATOR_SUPPLY("vcore", "sdi4"), 2761 REGULATOR_SUPPLY("v-dma", "dma40.0"), 2762 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 2763 /* "v-uart" changed to "vcore" in the mainline kernel */ 2764 REGULATOR_SUPPLY("vcore", "uart0"), 2765 REGULATOR_SUPPLY("vcore", "uart1"), 2766 REGULATOR_SUPPLY("vcore", "uart2"), 2767 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2768 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 2769 REGULATOR_SUPPLY("vddvario", "smsc911x.0"), 2770 }; 2771 2772 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 2773 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 2774 /* AV8100 regulator */ 2775 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 2776 }; 2777 2778 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2779 REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2780 REGULATOR_SUPPLY("vsupply", "mcde"), 2781 }; 2782 2783 /* SVA MMDSP regulator switch */ 2784 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2785 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2786 }; 2787 2788 /* SVA pipe regulator switch */ 2789 static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2790 REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2791 }; 2792 2793 /* SIA MMDSP regulator switch */ 2794 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2795 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2796 }; 2797 2798 /* SIA pipe regulator switch */ 2799 static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2800 REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2801 }; 2802 2803 static struct regulator_consumer_supply db8500_sga_consumers[] = { 2804 REGULATOR_SUPPLY("v-mali", NULL), 2805 }; 2806 2807 /* ESRAM1 and 2 regulator switch */ 2808 static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2809 REGULATOR_SUPPLY("esram12", "cm_control"), 2810 }; 2811 2812 /* ESRAM3 and 4 regulator switch */ 2813 static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2814 REGULATOR_SUPPLY("v-esram34", "mcde"), 2815 REGULATOR_SUPPLY("esram34", "cm_control"), 2816 REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 2817 }; 2818 2819 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 2820 [DB8500_REGULATOR_VAPE] = { 2821 .constraints = { 2822 .name = "db8500-vape", 2823 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2824 .always_on = true, 2825 }, 2826 .consumer_supplies = db8500_vape_consumers, 2827 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 2828 }, 2829 [DB8500_REGULATOR_VARM] = { 2830 .constraints = { 2831 .name = "db8500-varm", 2832 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2833 }, 2834 }, 2835 [DB8500_REGULATOR_VMODEM] = { 2836 .constraints = { 2837 .name = "db8500-vmodem", 2838 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2839 }, 2840 }, 2841 [DB8500_REGULATOR_VPLL] = { 2842 .constraints = { 2843 .name = "db8500-vpll", 2844 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2845 }, 2846 }, 2847 [DB8500_REGULATOR_VSMPS1] = { 2848 .constraints = { 2849 .name = "db8500-vsmps1", 2850 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2851 }, 2852 }, 2853 [DB8500_REGULATOR_VSMPS2] = { 2854 .constraints = { 2855 .name = "db8500-vsmps2", 2856 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2857 }, 2858 .consumer_supplies = db8500_vsmps2_consumers, 2859 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 2860 }, 2861 [DB8500_REGULATOR_VSMPS3] = { 2862 .constraints = { 2863 .name = "db8500-vsmps3", 2864 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2865 }, 2866 }, 2867 [DB8500_REGULATOR_VRF1] = { 2868 .constraints = { 2869 .name = "db8500-vrf1", 2870 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2871 }, 2872 }, 2873 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2874 /* dependency to u8500-vape is handled outside regulator framework */ 2875 .constraints = { 2876 .name = "db8500-sva-mmdsp", 2877 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2878 }, 2879 .consumer_supplies = db8500_svammdsp_consumers, 2880 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 2881 }, 2882 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 2883 .constraints = { 2884 /* "ret" means "retention" */ 2885 .name = "db8500-sva-mmdsp-ret", 2886 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2887 }, 2888 }, 2889 [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2890 /* dependency to u8500-vape is handled outside regulator framework */ 2891 .constraints = { 2892 .name = "db8500-sva-pipe", 2893 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2894 }, 2895 .consumer_supplies = db8500_svapipe_consumers, 2896 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 2897 }, 2898 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2899 /* dependency to u8500-vape is handled outside regulator framework */ 2900 .constraints = { 2901 .name = "db8500-sia-mmdsp", 2902 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2903 }, 2904 .consumer_supplies = db8500_siammdsp_consumers, 2905 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 2906 }, 2907 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 2908 .constraints = { 2909 .name = "db8500-sia-mmdsp-ret", 2910 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2911 }, 2912 }, 2913 [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2914 /* dependency to u8500-vape is handled outside regulator framework */ 2915 .constraints = { 2916 .name = "db8500-sia-pipe", 2917 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2918 }, 2919 .consumer_supplies = db8500_siapipe_consumers, 2920 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 2921 }, 2922 [DB8500_REGULATOR_SWITCH_SGA] = { 2923 .supply_regulator = "db8500-vape", 2924 .constraints = { 2925 .name = "db8500-sga", 2926 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2927 }, 2928 .consumer_supplies = db8500_sga_consumers, 2929 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2930 2931 }, 2932 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 2933 .supply_regulator = "db8500-vape", 2934 .constraints = { 2935 .name = "db8500-b2r2-mcde", 2936 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2937 }, 2938 .consumer_supplies = db8500_b2r2_mcde_consumers, 2939 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 2940 }, 2941 [DB8500_REGULATOR_SWITCH_ESRAM12] = { 2942 /* 2943 * esram12 is set in retention and supplied by Vsafe when Vape is off, 2944 * no need to hold Vape 2945 */ 2946 .constraints = { 2947 .name = "db8500-esram12", 2948 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2949 }, 2950 .consumer_supplies = db8500_esram12_consumers, 2951 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 2952 }, 2953 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 2954 .constraints = { 2955 .name = "db8500-esram12-ret", 2956 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2957 }, 2958 }, 2959 [DB8500_REGULATOR_SWITCH_ESRAM34] = { 2960 /* 2961 * esram34 is set in retention and supplied by Vsafe when Vape is off, 2962 * no need to hold Vape 2963 */ 2964 .constraints = { 2965 .name = "db8500-esram34", 2966 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2967 }, 2968 .consumer_supplies = db8500_esram34_consumers, 2969 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 2970 }, 2971 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 2972 .constraints = { 2973 .name = "db8500-esram34-ret", 2974 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 2975 }, 2976 }, 2977 }; 2978 2979 static struct ux500_wdt_data db8500_wdt_pdata = { 2980 .timeout = 600, /* 10 minutes */ 2981 .has_28_bits_resolution = true, 2982 }; 2983 /* 2984 * Thermal Sensor 2985 */ 2986 2987 static struct resource db8500_thsens_resources[] = { 2988 { 2989 .name = "IRQ_HOTMON_LOW", 2990 .start = IRQ_PRCMU_HOTMON_LOW, 2991 .end = IRQ_PRCMU_HOTMON_LOW, 2992 .flags = IORESOURCE_IRQ, 2993 }, 2994 { 2995 .name = "IRQ_HOTMON_HIGH", 2996 .start = IRQ_PRCMU_HOTMON_HIGH, 2997 .end = IRQ_PRCMU_HOTMON_HIGH, 2998 .flags = IORESOURCE_IRQ, 2999 }, 3000 }; 3001 3002 static struct db8500_thsens_platform_data db8500_thsens_data = { 3003 .trip_points[0] = { 3004 .temp = 70000, 3005 .type = THERMAL_TRIP_ACTIVE, 3006 .cdev_name = { 3007 [0] = "thermal-cpufreq-0", 3008 }, 3009 }, 3010 .trip_points[1] = { 3011 .temp = 75000, 3012 .type = THERMAL_TRIP_ACTIVE, 3013 .cdev_name = { 3014 [0] = "thermal-cpufreq-0", 3015 }, 3016 }, 3017 .trip_points[2] = { 3018 .temp = 80000, 3019 .type = THERMAL_TRIP_ACTIVE, 3020 .cdev_name = { 3021 [0] = "thermal-cpufreq-0", 3022 }, 3023 }, 3024 .trip_points[3] = { 3025 .temp = 85000, 3026 .type = THERMAL_TRIP_CRITICAL, 3027 }, 3028 .num_trips = 4, 3029 }; 3030 3031 static const struct mfd_cell common_prcmu_devs[] = { 3032 { 3033 .name = "ux500_wdt", 3034 .platform_data = &db8500_wdt_pdata, 3035 .pdata_size = sizeof(db8500_wdt_pdata), 3036 .id = -1, 3037 }, 3038 }; 3039 3040 static const struct mfd_cell db8500_prcmu_devs[] = { 3041 { 3042 .name = "db8500-prcmu-regulators", 3043 .of_compatible = "stericsson,db8500-prcmu-regulator", 3044 .platform_data = &db8500_regulators, 3045 .pdata_size = sizeof(db8500_regulators), 3046 }, 3047 { 3048 .name = "cpuidle-dbx500", 3049 .of_compatible = "stericsson,cpuidle-dbx500", 3050 }, 3051 { 3052 .name = "db8500-thermal", 3053 .num_resources = ARRAY_SIZE(db8500_thsens_resources), 3054 .resources = db8500_thsens_resources, 3055 .platform_data = &db8500_thsens_data, 3056 .pdata_size = sizeof(db8500_thsens_data), 3057 }, 3058 }; 3059 3060 static int db8500_prcmu_register_ab8500(struct device *parent) 3061 { 3062 struct device_node *np; 3063 struct resource ab8500_resource; 3064 const struct mfd_cell ab8500_cell = { 3065 .name = "ab8500-core", 3066 .of_compatible = "stericsson,ab8500", 3067 .id = AB8500_VERSION_AB8500, 3068 .resources = &ab8500_resource, 3069 .num_resources = 1, 3070 }; 3071 3072 if (!parent->of_node) 3073 return -ENODEV; 3074 3075 /* Look up the device node, sneak the IRQ out of it */ 3076 for_each_child_of_node(parent->of_node, np) { 3077 if (of_device_is_compatible(np, ab8500_cell.of_compatible)) 3078 break; 3079 } 3080 if (!np) { 3081 dev_info(parent, "could not find AB8500 node in the device tree\n"); 3082 return -ENODEV; 3083 } 3084 of_irq_to_resource_table(np, &ab8500_resource, 1); 3085 3086 return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL); 3087 } 3088 3089 /** 3090 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 3091 * 3092 */ 3093 static int db8500_prcmu_probe(struct platform_device *pdev) 3094 { 3095 struct device_node *np = pdev->dev.of_node; 3096 int irq = 0, err = 0; 3097 struct resource *res; 3098 3099 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); 3100 if (!res) { 3101 dev_err(&pdev->dev, "no prcmu memory region provided\n"); 3102 return -EINVAL; 3103 } 3104 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 3105 if (!prcmu_base) { 3106 dev_err(&pdev->dev, 3107 "failed to ioremap prcmu register memory\n"); 3108 return -ENOMEM; 3109 } 3110 init_prcm_registers(); 3111 dbx500_fw_version_init(pdev, DB8500_PRCMU_FW_VERSION_OFFSET); 3112 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); 3113 if (!res) { 3114 dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); 3115 return -EINVAL; 3116 } 3117 tcdm_base = devm_ioremap(&pdev->dev, res->start, 3118 resource_size(res)); 3119 if (!tcdm_base) { 3120 dev_err(&pdev->dev, 3121 "failed to ioremap prcmu-tcdm register memory\n"); 3122 return -ENOMEM; 3123 } 3124 3125 /* Clean up the mailbox interrupts after pre-kernel code. */ 3126 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 3127 3128 irq = platform_get_irq(pdev, 0); 3129 if (irq <= 0) { 3130 dev_err(&pdev->dev, "no prcmu irq provided\n"); 3131 return irq; 3132 } 3133 3134 err = request_threaded_irq(irq, prcmu_irq_handler, 3135 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 3136 if (err < 0) { 3137 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 3138 return err; 3139 } 3140 3141 db8500_irq_init(np); 3142 3143 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 3144 3145 err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs, 3146 ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain); 3147 if (err) { 3148 pr_err("prcmu: Failed to add subdevices\n"); 3149 return err; 3150 } 3151 3152 /* TODO: Remove restriction when clk definitions are available. */ 3153 if (!of_machine_is_compatible("st-ericsson,u8540")) { 3154 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3155 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, 3156 db8500_irq_domain); 3157 if (err) { 3158 mfd_remove_devices(&pdev->dev); 3159 pr_err("prcmu: Failed to add subdevices\n"); 3160 return err; 3161 } 3162 } 3163 3164 err = db8500_prcmu_register_ab8500(&pdev->dev); 3165 if (err) { 3166 mfd_remove_devices(&pdev->dev); 3167 pr_err("prcmu: Failed to add ab8500 subdevice\n"); 3168 return err; 3169 } 3170 3171 pr_info("DB8500 PRCMU initialized\n"); 3172 return err; 3173 } 3174 static const struct of_device_id db8500_prcmu_match[] = { 3175 { .compatible = "stericsson,db8500-prcmu"}, 3176 { }, 3177 }; 3178 3179 static struct platform_driver db8500_prcmu_driver = { 3180 .driver = { 3181 .name = "db8500-prcmu", 3182 .of_match_table = db8500_prcmu_match, 3183 }, 3184 .probe = db8500_prcmu_probe, 3185 }; 3186 3187 static int __init db8500_prcmu_init(void) 3188 { 3189 return platform_driver_register(&db8500_prcmu_driver); 3190 } 3191 3192 core_initcall(db8500_prcmu_init); 3193 3194 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 3195 MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 3196 MODULE_LICENSE("GPL v2"); 3197