1650c2a21SLinus Walleij /* 2650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 3650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 4650c2a21SLinus Walleij * 5650c2a21SLinus Walleij * License Terms: GNU General Public License v2 6650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9650c2a21SLinus Walleij * 10650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij */ 13650c2a21SLinus Walleij #include <linux/module.h> 143df57bcfSMattias Nilsson #include <linux/kernel.h> 153df57bcfSMattias Nilsson #include <linux/delay.h> 16650c2a21SLinus Walleij #include <linux/errno.h> 17650c2a21SLinus Walleij #include <linux/err.h> 183df57bcfSMattias Nilsson #include <linux/spinlock.h> 19650c2a21SLinus Walleij #include <linux/io.h> 203df57bcfSMattias Nilsson #include <linux/slab.h> 21650c2a21SLinus Walleij #include <linux/mutex.h> 22650c2a21SLinus Walleij #include <linux/completion.h> 233df57bcfSMattias Nilsson #include <linux/irq.h> 24650c2a21SLinus Walleij #include <linux/jiffies.h> 25650c2a21SLinus Walleij #include <linux/bitops.h> 263df57bcfSMattias Nilsson #include <linux/fs.h> 273df57bcfSMattias Nilsson #include <linux/platform_device.h> 283df57bcfSMattias Nilsson #include <linux/uaccess.h> 293df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3073180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 311032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 321032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 33650c2a21SLinus Walleij #include <mach/hardware.h> 343df57bcfSMattias Nilsson #include <mach/irqs.h> 353df57bcfSMattias Nilsson #include <mach/db8500-regs.h> 363df57bcfSMattias Nilsson #include <mach/id.h> 3773180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 38650c2a21SLinus Walleij 393df57bcfSMattias Nilsson /* Offset for the firmware version within the TCPM */ 403df57bcfSMattias Nilsson #define PRCMU_FW_VERSION_OFFSET 0xA4 41650c2a21SLinus Walleij 423df57bcfSMattias Nilsson /* PRCMU project numbers, defined by PRCMU FW */ 433df57bcfSMattias Nilsson #define PRCMU_PROJECT_ID_8500V1_0 1 443df57bcfSMattias Nilsson #define PRCMU_PROJECT_ID_8500V2_0 2 453df57bcfSMattias Nilsson #define PRCMU_PROJECT_ID_8400V2_0 3 46650c2a21SLinus Walleij 473df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 483df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 493df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 503df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 513df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 523df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 533df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 543df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 553df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 563df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 573df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 583df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 593df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 603df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 613df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 62650c2a21SLinus Walleij 633df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 643df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 653df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 663df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 67650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 68650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 69650c2a21SLinus Walleij 703df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 713df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 723df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 733df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 74650c2a21SLinus Walleij 753df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 763df57bcfSMattias Nilsson 773df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 793df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 803df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 813df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 823df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 833df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 843df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 853df57bcfSMattias Nilsson 863df57bcfSMattias Nilsson /* Req Mailboxes */ 873df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 883df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 893df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 903df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 913df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 923df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 933df57bcfSMattias Nilsson 943df57bcfSMattias Nilsson /* Ack Mailboxes */ 953df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 963df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 973df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 983df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 993df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 1003df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 1013df57bcfSMattias Nilsson 1023df57bcfSMattias Nilsson /* Mailbox 0 headers */ 1033df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 1043df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 1053df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 1063df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1073df57bcfSMattias Nilsson 1083df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1093df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1103df57bcfSMattias Nilsson 1113df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1123df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1133df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1143df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1153df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1163df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1173df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1183df57bcfSMattias Nilsson 1193df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1213df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1223df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1233df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1243df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1253df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1263df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1273df57bcfSMattias Nilsson 1283df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1293df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1303df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1313df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1323df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1333df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 134a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1353df57bcfSMattias Nilsson 1363df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1373df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1383df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 139a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 140a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 141a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1423df57bcfSMattias Nilsson 1433df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1443df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1453df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1463df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1473df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1483df57bcfSMattias Nilsson 1493df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1503df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1513df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1523df57bcfSMattias Nilsson 1533df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1603df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1613df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1623df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1633df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1643df57bcfSMattias Nilsson 1653df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1663df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1673df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1683df57bcfSMattias Nilsson 1693df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1703df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1713df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1723df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1733df57bcfSMattias Nilsson 1743df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1783df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1793df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1803df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1813df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1823df57bcfSMattias Nilsson 1833df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1843df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1853df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1863df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1873df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1883df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 190a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 191a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 192a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 193a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1943df57bcfSMattias Nilsson 1953df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 2003df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 2013df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 2023df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 2033df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 2043df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2053df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 206a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 207a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 208a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 209a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 210a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 211a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 212a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2133df57bcfSMattias Nilsson 2143df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2153df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2163df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2173df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2183df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2193df57bcfSMattias Nilsson #define PRCMU_I2C_WRITE(slave) \ 2203df57bcfSMattias Nilsson (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2213df57bcfSMattias Nilsson #define PRCMU_I2C_READ(slave) \ 2223df57bcfSMattias Nilsson (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2233df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2243df57bcfSMattias Nilsson 2253df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2263df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2273df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2283df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2293df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2303df57bcfSMattias Nilsson 2313df57bcfSMattias Nilsson #define NUM_MB 8 2323df57bcfSMattias Nilsson #define MBOX_BIT BIT 2333df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2343df57bcfSMattias Nilsson 2353df57bcfSMattias Nilsson /* 2363df57bcfSMattias Nilsson * Wakeups/IRQs 2373df57bcfSMattias Nilsson */ 2383df57bcfSMattias Nilsson 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2623df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2633df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2643df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2653df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2663df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2673df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2683df57bcfSMattias Nilsson 2693df57bcfSMattias Nilsson /* 2703df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2713df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2723df57bcfSMattias Nilsson * 2733df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2743df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2753df57bcfSMattias Nilsson * around, to further complicate matters.) 2763df57bcfSMattias Nilsson */ 2773df57bcfSMattias Nilsson #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) 2783df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 2793df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 2803df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 2813df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 2823df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 2833df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 2843df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 2853df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 2863df57bcfSMattias Nilsson IRQ_ENTRY(USB), 2873df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 2883df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 2893df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 2903df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 2913df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 2923df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 2933df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 2943df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 2953df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 2963df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 2973df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 2983df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 2993df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3003df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3013df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3023df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 303650c2a21SLinus Walleij }; 304650c2a21SLinus Walleij 3053df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3063df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3073df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3083df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3093df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3103df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3113df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3123df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3133df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3143df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3153df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3163df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3173df57bcfSMattias Nilsson }; 3183df57bcfSMattias Nilsson 3193df57bcfSMattias Nilsson /* 3203df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3213df57bcfSMattias Nilsson * @lock: The transaction lock. 3223df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3233df57bcfSMattias Nilsson * the request data. 3243df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3253df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3263df57bcfSMattias Nilsson */ 3273df57bcfSMattias Nilsson static struct { 3283df57bcfSMattias Nilsson spinlock_t lock; 3293df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3303df57bcfSMattias Nilsson struct work_struct mask_work; 3313df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3323df57bcfSMattias Nilsson struct completion ac_wake_work; 3333df57bcfSMattias Nilsson struct { 3343df57bcfSMattias Nilsson u32 dbb_irqs; 3353df57bcfSMattias Nilsson u32 dbb_wakeups; 3363df57bcfSMattias Nilsson u32 abb_events; 3373df57bcfSMattias Nilsson } req; 3383df57bcfSMattias Nilsson } mb0_transfer; 3393df57bcfSMattias Nilsson 3403df57bcfSMattias Nilsson /* 3413df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3423df57bcfSMattias Nilsson * @lock: The transaction lock. 3433df57bcfSMattias Nilsson * @work: The transaction completion structure. 3443df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3453df57bcfSMattias Nilsson */ 346650c2a21SLinus Walleij static struct { 347650c2a21SLinus Walleij struct mutex lock; 348650c2a21SLinus Walleij struct completion work; 349650c2a21SLinus Walleij struct { 3503df57bcfSMattias Nilsson u8 header; 351650c2a21SLinus Walleij u8 arm_opp; 352650c2a21SLinus Walleij u8 ape_opp; 3533df57bcfSMattias Nilsson u8 ape_voltage_status; 354650c2a21SLinus Walleij } ack; 355650c2a21SLinus Walleij } mb1_transfer; 356650c2a21SLinus Walleij 3573df57bcfSMattias Nilsson /* 3583df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3593df57bcfSMattias Nilsson * @lock: The transaction lock. 3603df57bcfSMattias Nilsson * @work: The transaction completion structure. 3613df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3623df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3633df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3643df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3653df57bcfSMattias Nilsson */ 366650c2a21SLinus Walleij static struct { 367650c2a21SLinus Walleij struct mutex lock; 368650c2a21SLinus Walleij struct completion work; 3693df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 3703df57bcfSMattias Nilsson bool auto_pm_enabled; 3713df57bcfSMattias Nilsson struct { 3723df57bcfSMattias Nilsson u8 status; 3733df57bcfSMattias Nilsson } ack; 3743df57bcfSMattias Nilsson } mb2_transfer; 3753df57bcfSMattias Nilsson 3763df57bcfSMattias Nilsson /* 3773df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 3783df57bcfSMattias Nilsson * @lock: The request lock. 3793df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 3803df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 3813df57bcfSMattias Nilsson */ 3823df57bcfSMattias Nilsson static struct { 3833df57bcfSMattias Nilsson spinlock_t lock; 3843df57bcfSMattias Nilsson struct mutex sysclk_lock; 3853df57bcfSMattias Nilsson struct completion sysclk_work; 3863df57bcfSMattias Nilsson } mb3_transfer; 3873df57bcfSMattias Nilsson 3883df57bcfSMattias Nilsson /* 3893df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 3903df57bcfSMattias Nilsson * @lock: The transaction lock. 3913df57bcfSMattias Nilsson * @work: The transaction completion structure. 3923df57bcfSMattias Nilsson */ 3933df57bcfSMattias Nilsson static struct { 3943df57bcfSMattias Nilsson struct mutex lock; 3953df57bcfSMattias Nilsson struct completion work; 3963df57bcfSMattias Nilsson } mb4_transfer; 3973df57bcfSMattias Nilsson 3983df57bcfSMattias Nilsson /* 3993df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4003df57bcfSMattias Nilsson * @lock: The transaction lock. 4013df57bcfSMattias Nilsson * @work: The transaction completion structure. 4023df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4033df57bcfSMattias Nilsson */ 4043df57bcfSMattias Nilsson static struct { 4053df57bcfSMattias Nilsson struct mutex lock; 4063df57bcfSMattias Nilsson struct completion work; 407650c2a21SLinus Walleij struct { 408650c2a21SLinus Walleij u8 status; 409650c2a21SLinus Walleij u8 value; 410650c2a21SLinus Walleij } ack; 411650c2a21SLinus Walleij } mb5_transfer; 412650c2a21SLinus Walleij 4133df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4143df57bcfSMattias Nilsson 4153df57bcfSMattias Nilsson /* Spinlocks */ 4163df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4173df57bcfSMattias Nilsson static DEFINE_SPINLOCK(gpiocr_lock); 4183df57bcfSMattias Nilsson 4193df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4203df57bcfSMattias Nilsson static __iomem void *tcdm_base; 4213df57bcfSMattias Nilsson 4223df57bcfSMattias Nilsson struct clk_mgt { 4233df57bcfSMattias Nilsson unsigned int offset; 4243df57bcfSMattias Nilsson u32 pllsw; 4253df57bcfSMattias Nilsson }; 4263df57bcfSMattias Nilsson 4273df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4283df57bcfSMattias Nilsson 429c553b3caSMattias Nilsson #define CLK_MGT_ENTRY(_name)[PRCMU_##_name] = { (PRCM_##_name##_MGT_OFF), 0 } 4303df57bcfSMattias Nilsson struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4313df57bcfSMattias Nilsson CLK_MGT_ENTRY(SGACLK), 4323df57bcfSMattias Nilsson CLK_MGT_ENTRY(UARTCLK), 4333df57bcfSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK), 4343df57bcfSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK), 4353df57bcfSMattias Nilsson CLK_MGT_ENTRY(I2CCLK), 4363df57bcfSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK), 4373df57bcfSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK), 4383df57bcfSMattias Nilsson CLK_MGT_ENTRY(PER1CLK), 4393df57bcfSMattias Nilsson CLK_MGT_ENTRY(PER2CLK), 4403df57bcfSMattias Nilsson CLK_MGT_ENTRY(PER3CLK), 4413df57bcfSMattias Nilsson CLK_MGT_ENTRY(PER5CLK), 4423df57bcfSMattias Nilsson CLK_MGT_ENTRY(PER6CLK), 4433df57bcfSMattias Nilsson CLK_MGT_ENTRY(PER7CLK), 4443df57bcfSMattias Nilsson CLK_MGT_ENTRY(LCDCLK), 4453df57bcfSMattias Nilsson CLK_MGT_ENTRY(BMLCLK), 4463df57bcfSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK), 4473df57bcfSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK), 4483df57bcfSMattias Nilsson CLK_MGT_ENTRY(HDMICLK), 4493df57bcfSMattias Nilsson CLK_MGT_ENTRY(APEATCLK), 4503df57bcfSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK), 4513df57bcfSMattias Nilsson CLK_MGT_ENTRY(MCDECLK), 4523df57bcfSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK), 4533df57bcfSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK), 4543df57bcfSMattias Nilsson CLK_MGT_ENTRY(DMACLK), 4553df57bcfSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK), 4563df57bcfSMattias Nilsson CLK_MGT_ENTRY(TVCLK), 4573df57bcfSMattias Nilsson CLK_MGT_ENTRY(SSPCLK), 4583df57bcfSMattias Nilsson CLK_MGT_ENTRY(RNGCLK), 4593df57bcfSMattias Nilsson CLK_MGT_ENTRY(UICCCLK), 4603df57bcfSMattias Nilsson }; 4613df57bcfSMattias Nilsson 4620837bb72SMattias Nilsson static struct regulator *hwacc_regulator[NUM_HW_ACC]; 4630837bb72SMattias Nilsson static struct regulator *hwacc_ret_regulator[NUM_HW_ACC]; 4640837bb72SMattias Nilsson 4650837bb72SMattias Nilsson static bool hwacc_enabled[NUM_HW_ACC]; 4660837bb72SMattias Nilsson static bool hwacc_ret_enabled[NUM_HW_ACC]; 4670837bb72SMattias Nilsson 4680837bb72SMattias Nilsson static const char *hwacc_regulator_name[NUM_HW_ACC] = { 4690837bb72SMattias Nilsson [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp", 4700837bb72SMattias Nilsson [HW_ACC_SVAPIPE] = "hwacc-sva-pipe", 4710837bb72SMattias Nilsson [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp", 4720837bb72SMattias Nilsson [HW_ACC_SIAPIPE] = "hwacc-sia-pipe", 4730837bb72SMattias Nilsson [HW_ACC_SGA] = "hwacc-sga", 4740837bb72SMattias Nilsson [HW_ACC_B2R2] = "hwacc-b2r2", 4750837bb72SMattias Nilsson [HW_ACC_MCDE] = "hwacc-mcde", 4760837bb72SMattias Nilsson [HW_ACC_ESRAM1] = "hwacc-esram1", 4770837bb72SMattias Nilsson [HW_ACC_ESRAM2] = "hwacc-esram2", 4780837bb72SMattias Nilsson [HW_ACC_ESRAM3] = "hwacc-esram3", 4790837bb72SMattias Nilsson [HW_ACC_ESRAM4] = "hwacc-esram4", 4800837bb72SMattias Nilsson }; 4810837bb72SMattias Nilsson 4820837bb72SMattias Nilsson static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { 4830837bb72SMattias Nilsson [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp-ret", 4840837bb72SMattias Nilsson [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp-ret", 4850837bb72SMattias Nilsson [HW_ACC_ESRAM1] = "hwacc-esram1-ret", 4860837bb72SMattias Nilsson [HW_ACC_ESRAM2] = "hwacc-esram2-ret", 4870837bb72SMattias Nilsson [HW_ACC_ESRAM3] = "hwacc-esram3-ret", 4880837bb72SMattias Nilsson [HW_ACC_ESRAM4] = "hwacc-esram4-ret", 4890837bb72SMattias Nilsson }; 4900837bb72SMattias Nilsson 4913df57bcfSMattias Nilsson /* 4923df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 4933df57bcfSMattias Nilsson */ 4943df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 4953df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 4963df57bcfSMattias Nilsson 4973df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 4983df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 4993df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5003df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5013df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5023df57bcfSMattias Nilsson 5033df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5043df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5053df57bcfSMattias Nilsson 5063df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5073df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5083df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5093df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5103df57bcfSMattias Nilsson 5113df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5123df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5133df57bcfSMattias Nilsson 5143df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5153df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5163df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5173df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5183df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5193df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5203df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5213df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5223df57bcfSMattias Nilsson 5233df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5243df57bcfSMattias Nilsson 5253df57bcfSMattias Nilsson static struct { 5263df57bcfSMattias Nilsson u8 project_number; 5273df57bcfSMattias Nilsson u8 api_version; 5283df57bcfSMattias Nilsson u8 func_version; 5293df57bcfSMattias Nilsson u8 errata; 5303df57bcfSMattias Nilsson } prcmu_version; 5313df57bcfSMattias Nilsson 5323df57bcfSMattias Nilsson 53373180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5343df57bcfSMattias Nilsson { 5353df57bcfSMattias Nilsson int i; 5363df57bcfSMattias Nilsson 5373df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 538c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5393df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 540c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5413df57bcfSMattias Nilsson 5423df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 543c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 544c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5453df57bcfSMattias Nilsson /* Enable Escape clocks */ 546c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5473df57bcfSMattias Nilsson 5483df57bcfSMattias Nilsson /* Start DSI PLL */ 549c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5503df57bcfSMattias Nilsson /* Reset DSI PLL */ 551c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 5523df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 553c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 5543df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 5553df57bcfSMattias Nilsson break; 5563df57bcfSMattias Nilsson udelay(100); 5573df57bcfSMattias Nilsson } 5583df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 559c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 5603df57bcfSMattias Nilsson return 0; 5613df57bcfSMattias Nilsson } 5623df57bcfSMattias Nilsson 56373180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 5643df57bcfSMattias Nilsson { 5653df57bcfSMattias Nilsson /* Disable dsi pll */ 566c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5673df57bcfSMattias Nilsson /* Disable escapeclock */ 568c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5693df57bcfSMattias Nilsson return 0; 5703df57bcfSMattias Nilsson } 5713df57bcfSMattias Nilsson 57273180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 5733df57bcfSMattias Nilsson { 5743df57bcfSMattias Nilsson unsigned long flags; 5753df57bcfSMattias Nilsson 5763df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 5773df57bcfSMattias Nilsson 5783df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 579c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 5803df57bcfSMattias Nilsson cpu_relax(); 5813df57bcfSMattias Nilsson 582c72fe851SDaniel Willerud writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); 583c553b3caSMattias Nilsson writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); 584c553b3caSMattias Nilsson writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); 5853df57bcfSMattias Nilsson 5863df57bcfSMattias Nilsson /* Release the HW semaphore. */ 587c553b3caSMattias Nilsson writel(0, PRCM_SEM); 5883df57bcfSMattias Nilsson 5893df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 5903df57bcfSMattias Nilsson 5913df57bcfSMattias Nilsson return 0; 5923df57bcfSMattias Nilsson } 5933df57bcfSMattias Nilsson 5943df57bcfSMattias Nilsson /** 5953df57bcfSMattias Nilsson * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. 5963df57bcfSMattias Nilsson */ 5973df57bcfSMattias Nilsson void prcmu_enable_spi2(void) 5983df57bcfSMattias Nilsson { 5993df57bcfSMattias Nilsson u32 reg; 6003df57bcfSMattias Nilsson unsigned long flags; 6013df57bcfSMattias Nilsson 6023df57bcfSMattias Nilsson spin_lock_irqsave(&gpiocr_lock, flags); 603c553b3caSMattias Nilsson reg = readl(PRCM_GPIOCR); 604c553b3caSMattias Nilsson writel(reg | PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); 6053df57bcfSMattias Nilsson spin_unlock_irqrestore(&gpiocr_lock, flags); 6063df57bcfSMattias Nilsson } 6073df57bcfSMattias Nilsson 6083df57bcfSMattias Nilsson /** 6093df57bcfSMattias Nilsson * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. 6103df57bcfSMattias Nilsson */ 6113df57bcfSMattias Nilsson void prcmu_disable_spi2(void) 6123df57bcfSMattias Nilsson { 6133df57bcfSMattias Nilsson u32 reg; 6143df57bcfSMattias Nilsson unsigned long flags; 6153df57bcfSMattias Nilsson 6163df57bcfSMattias Nilsson spin_lock_irqsave(&gpiocr_lock, flags); 617c553b3caSMattias Nilsson reg = readl(PRCM_GPIOCR); 618c553b3caSMattias Nilsson writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); 6193df57bcfSMattias Nilsson spin_unlock_irqrestore(&gpiocr_lock, flags); 6203df57bcfSMattias Nilsson } 6213df57bcfSMattias Nilsson 6223df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6233df57bcfSMattias Nilsson { 6243df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6253df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6263df57bcfSMattias Nilsson } 6273df57bcfSMattias Nilsson 6283df57bcfSMattias Nilsson /** 6293df57bcfSMattias Nilsson * prcmu_get_boot_status - PRCMU boot status checking 6303df57bcfSMattias Nilsson * Returns: the current PRCMU boot status 6313df57bcfSMattias Nilsson */ 6323df57bcfSMattias Nilsson int prcmu_get_boot_status(void) 6333df57bcfSMattias Nilsson { 6343df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_BOOT_STATUS); 6353df57bcfSMattias Nilsson } 6363df57bcfSMattias Nilsson 6373df57bcfSMattias Nilsson /** 6383df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6393df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6403df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6413df57bcfSMattias Nilsson * 6423df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6433df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6443df57bcfSMattias Nilsson */ 6453df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6463df57bcfSMattias Nilsson { 6473df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 6483df57bcfSMattias Nilsson return -EINVAL; 6493df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 6503df57bcfSMattias Nilsson return 0; 6513df57bcfSMattias Nilsson } 6523df57bcfSMattias Nilsson 6533df57bcfSMattias Nilsson /** 6543df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 6553df57bcfSMattias Nilsson * Returns: the power transition that has last happened 6563df57bcfSMattias Nilsson * 6573df57bcfSMattias Nilsson * This function can return the following transitions- 6583df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6593df57bcfSMattias Nilsson */ 6603df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 6613df57bcfSMattias Nilsson { 6623df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 6633df57bcfSMattias Nilsson } 6643df57bcfSMattias Nilsson 6653df57bcfSMattias Nilsson /** 6663df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 6673df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 6683df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 6693df57bcfSMattias Nilsson */ 6703df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 6713df57bcfSMattias Nilsson { 6723df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 6733df57bcfSMattias Nilsson } 6743df57bcfSMattias Nilsson 6753df57bcfSMattias Nilsson /** 6763df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 6773df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 6783df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 6793df57bcfSMattias Nilsson * @div: The divider to be applied. 6803df57bcfSMattias Nilsson * 6813df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 6823df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 6833df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 6843df57bcfSMattias Nilsson */ 6853df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 6863df57bcfSMattias Nilsson { 6873df57bcfSMattias Nilsson static int requests[2]; 6883df57bcfSMattias Nilsson int r = 0; 6893df57bcfSMattias Nilsson unsigned long flags; 6903df57bcfSMattias Nilsson u32 val; 6913df57bcfSMattias Nilsson u32 bits; 6923df57bcfSMattias Nilsson u32 mask; 6933df57bcfSMattias Nilsson u32 div_mask; 6943df57bcfSMattias Nilsson 6953df57bcfSMattias Nilsson BUG_ON(clkout > 1); 6963df57bcfSMattias Nilsson BUG_ON(div > 63); 6973df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 6983df57bcfSMattias Nilsson 6993df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7003df57bcfSMattias Nilsson return -EINVAL; 7013df57bcfSMattias Nilsson 7023df57bcfSMattias Nilsson switch (clkout) { 7033df57bcfSMattias Nilsson case 0: 7043df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7053df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7063df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7073df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 7083df57bcfSMattias Nilsson break; 7093df57bcfSMattias Nilsson case 1: 7103df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7113df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7123df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7133df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7143df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7153df57bcfSMattias Nilsson break; 7163df57bcfSMattias Nilsson } 7173df57bcfSMattias Nilsson bits &= mask; 7183df57bcfSMattias Nilsson 7193df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7203df57bcfSMattias Nilsson 721c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7223df57bcfSMattias Nilsson if (val & div_mask) { 7233df57bcfSMattias Nilsson if (div) { 7243df57bcfSMattias Nilsson if ((val & mask) != bits) { 7253df57bcfSMattias Nilsson r = -EBUSY; 7263df57bcfSMattias Nilsson goto unlock_and_return; 7273df57bcfSMattias Nilsson } 7283df57bcfSMattias Nilsson } else { 7293df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7303df57bcfSMattias Nilsson r = -EINVAL; 7313df57bcfSMattias Nilsson goto unlock_and_return; 7323df57bcfSMattias Nilsson } 7333df57bcfSMattias Nilsson } 7343df57bcfSMattias Nilsson } 735c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7363df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7373df57bcfSMattias Nilsson 7383df57bcfSMattias Nilsson unlock_and_return: 7393df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7403df57bcfSMattias Nilsson 7413df57bcfSMattias Nilsson return r; 7423df57bcfSMattias Nilsson } 7433df57bcfSMattias Nilsson 74473180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7453df57bcfSMattias Nilsson { 7463df57bcfSMattias Nilsson unsigned long flags; 7473df57bcfSMattias Nilsson 7483df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 7493df57bcfSMattias Nilsson 7503df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 7513df57bcfSMattias Nilsson 752c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 7533df57bcfSMattias Nilsson cpu_relax(); 7543df57bcfSMattias Nilsson 7553df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 7563df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 7573df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 7583df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 7593df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 7603df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 761c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 7623df57bcfSMattias Nilsson 7633df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 7643df57bcfSMattias Nilsson 7653df57bcfSMattias Nilsson return 0; 7663df57bcfSMattias Nilsson } 7673df57bcfSMattias Nilsson 7683df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 7693df57bcfSMattias Nilsson static void config_wakeups(void) 7703df57bcfSMattias Nilsson { 7713df57bcfSMattias Nilsson const u8 header[2] = { 7723df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 7733df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 7743df57bcfSMattias Nilsson }; 7753df57bcfSMattias Nilsson static u32 last_dbb_events; 7763df57bcfSMattias Nilsson static u32 last_abb_events; 7773df57bcfSMattias Nilsson u32 dbb_events; 7783df57bcfSMattias Nilsson u32 abb_events; 7793df57bcfSMattias Nilsson unsigned int i; 7803df57bcfSMattias Nilsson 7813df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 7823df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 7833df57bcfSMattias Nilsson 7843df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 7853df57bcfSMattias Nilsson 7863df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 7873df57bcfSMattias Nilsson return; 7883df57bcfSMattias Nilsson 7893df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 790c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 7913df57bcfSMattias Nilsson cpu_relax(); 7923df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 7933df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 7943df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 795c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 7963df57bcfSMattias Nilsson } 7973df57bcfSMattias Nilsson last_dbb_events = dbb_events; 7983df57bcfSMattias Nilsson last_abb_events = abb_events; 7993df57bcfSMattias Nilsson } 8003df57bcfSMattias Nilsson 80173180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 8023df57bcfSMattias Nilsson { 8033df57bcfSMattias Nilsson unsigned long flags; 8043df57bcfSMattias Nilsson u32 bits; 8053df57bcfSMattias Nilsson int i; 8063df57bcfSMattias Nilsson 8073df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 8083df57bcfSMattias Nilsson 8093df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 8103df57bcfSMattias Nilsson if (wakeups & BIT(i)) 8113df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 8123df57bcfSMattias Nilsson } 8133df57bcfSMattias Nilsson 8143df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8153df57bcfSMattias Nilsson 8163df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 8173df57bcfSMattias Nilsson config_wakeups(); 8183df57bcfSMattias Nilsson 8193df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8203df57bcfSMattias Nilsson } 8213df57bcfSMattias Nilsson 82273180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 8233df57bcfSMattias Nilsson { 8243df57bcfSMattias Nilsson unsigned long flags; 8253df57bcfSMattias Nilsson 8263df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8273df57bcfSMattias Nilsson 8283df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 8293df57bcfSMattias Nilsson config_wakeups(); 8303df57bcfSMattias Nilsson 8313df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8323df57bcfSMattias Nilsson } 8333df57bcfSMattias Nilsson 83473180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 8353df57bcfSMattias Nilsson { 8363df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 8373df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 8383df57bcfSMattias Nilsson else 8393df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 8403df57bcfSMattias Nilsson } 8413df57bcfSMattias Nilsson 8423df57bcfSMattias Nilsson /** 84373180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 8443df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 8453df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 8463df57bcfSMattias Nilsson * 8473df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 8483df57bcfSMattias Nilsson */ 84973180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 8503df57bcfSMattias Nilsson { 8513df57bcfSMattias Nilsson int r; 8523df57bcfSMattias Nilsson 8533df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 8543df57bcfSMattias Nilsson return -EINVAL; 8553df57bcfSMattias Nilsson 8563df57bcfSMattias Nilsson r = 0; 8573df57bcfSMattias Nilsson 8583df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 8593df57bcfSMattias Nilsson 860c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 8613df57bcfSMattias Nilsson cpu_relax(); 8623df57bcfSMattias Nilsson 8633df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 8643df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 8653df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 8663df57bcfSMattias Nilsson 867c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 8683df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 8693df57bcfSMattias Nilsson 8703df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 8713df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 8723df57bcfSMattias Nilsson r = -EIO; 8733df57bcfSMattias Nilsson 8743df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 8753df57bcfSMattias Nilsson 8763df57bcfSMattias Nilsson return r; 8773df57bcfSMattias Nilsson } 8783df57bcfSMattias Nilsson 8793df57bcfSMattias Nilsson /** 88073180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 8813df57bcfSMattias Nilsson * 8823df57bcfSMattias Nilsson * Returns: the current ARM OPP 8833df57bcfSMattias Nilsson */ 88473180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 8853df57bcfSMattias Nilsson { 8863df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 8873df57bcfSMattias Nilsson } 8883df57bcfSMattias Nilsson 8893df57bcfSMattias Nilsson /** 8903df57bcfSMattias Nilsson * prcmu_get_ddr_opp - get the current DDR OPP 8913df57bcfSMattias Nilsson * 8923df57bcfSMattias Nilsson * Returns: the current DDR OPP 8933df57bcfSMattias Nilsson */ 8943df57bcfSMattias Nilsson int prcmu_get_ddr_opp(void) 8953df57bcfSMattias Nilsson { 896c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 8973df57bcfSMattias Nilsson } 8983df57bcfSMattias Nilsson 8993df57bcfSMattias Nilsson /** 9003df57bcfSMattias Nilsson * set_ddr_opp - set the appropriate DDR OPP 9013df57bcfSMattias Nilsson * @opp: The new DDR operating point to which transition is to be made 9023df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9033df57bcfSMattias Nilsson * 9043df57bcfSMattias Nilsson * This function sets the operating point of the DDR. 9053df57bcfSMattias Nilsson */ 9063df57bcfSMattias Nilsson int prcmu_set_ddr_opp(u8 opp) 9073df57bcfSMattias Nilsson { 9083df57bcfSMattias Nilsson if (opp < DDR_100_OPP || opp > DDR_25_OPP) 9093df57bcfSMattias Nilsson return -EINVAL; 9103df57bcfSMattias Nilsson /* Changing the DDR OPP can hang the hardware pre-v21 */ 9113df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) 912c553b3caSMattias Nilsson writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 9133df57bcfSMattias Nilsson 9143df57bcfSMattias Nilsson return 0; 9153df57bcfSMattias Nilsson } 9163df57bcfSMattias Nilsson /** 9173df57bcfSMattias Nilsson * set_ape_opp - set the appropriate APE OPP 9183df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 9193df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9203df57bcfSMattias Nilsson * 9213df57bcfSMattias Nilsson * This function sets the operating point of the APE. 9223df57bcfSMattias Nilsson */ 9233df57bcfSMattias Nilsson int prcmu_set_ape_opp(u8 opp) 9243df57bcfSMattias Nilsson { 9253df57bcfSMattias Nilsson int r = 0; 9263df57bcfSMattias Nilsson 9273df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 9283df57bcfSMattias Nilsson 929c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 9303df57bcfSMattias Nilsson cpu_relax(); 9313df57bcfSMattias Nilsson 9323df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 9333df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 9343df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 9353df57bcfSMattias Nilsson 936c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 9373df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 9383df57bcfSMattias Nilsson 9393df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 9403df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 9413df57bcfSMattias Nilsson r = -EIO; 9423df57bcfSMattias Nilsson 9433df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 9443df57bcfSMattias Nilsson 9453df57bcfSMattias Nilsson return r; 9463df57bcfSMattias Nilsson } 9473df57bcfSMattias Nilsson 9483df57bcfSMattias Nilsson /** 9493df57bcfSMattias Nilsson * prcmu_get_ape_opp - get the current APE OPP 9503df57bcfSMattias Nilsson * 9513df57bcfSMattias Nilsson * Returns: the current APE OPP 9523df57bcfSMattias Nilsson */ 9533df57bcfSMattias Nilsson int prcmu_get_ape_opp(void) 9543df57bcfSMattias Nilsson { 9553df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 9563df57bcfSMattias Nilsson } 9573df57bcfSMattias Nilsson 9583df57bcfSMattias Nilsson /** 9593df57bcfSMattias Nilsson * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 9603df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 9613df57bcfSMattias Nilsson * 9623df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 9633df57bcfSMattias Nilsson */ 9643df57bcfSMattias Nilsson int prcmu_request_ape_opp_100_voltage(bool enable) 9653df57bcfSMattias Nilsson { 9663df57bcfSMattias Nilsson int r = 0; 9673df57bcfSMattias Nilsson u8 header; 9683df57bcfSMattias Nilsson static unsigned int requests; 9693df57bcfSMattias Nilsson 9703df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 9713df57bcfSMattias Nilsson 9723df57bcfSMattias Nilsson if (enable) { 9733df57bcfSMattias Nilsson if (0 != requests++) 9743df57bcfSMattias Nilsson goto unlock_and_return; 9753df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 9763df57bcfSMattias Nilsson } else { 9773df57bcfSMattias Nilsson if (requests == 0) { 9783df57bcfSMattias Nilsson r = -EIO; 9793df57bcfSMattias Nilsson goto unlock_and_return; 9803df57bcfSMattias Nilsson } else if (1 != requests--) { 9813df57bcfSMattias Nilsson goto unlock_and_return; 9823df57bcfSMattias Nilsson } 9833df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 9843df57bcfSMattias Nilsson } 9853df57bcfSMattias Nilsson 986c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 9873df57bcfSMattias Nilsson cpu_relax(); 9883df57bcfSMattias Nilsson 9893df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 9903df57bcfSMattias Nilsson 991c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 9923df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 9933df57bcfSMattias Nilsson 9943df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 9953df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 9963df57bcfSMattias Nilsson r = -EIO; 9973df57bcfSMattias Nilsson 9983df57bcfSMattias Nilsson unlock_and_return: 9993df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10003df57bcfSMattias Nilsson 10013df57bcfSMattias Nilsson return r; 10023df57bcfSMattias Nilsson } 10033df57bcfSMattias Nilsson 10043df57bcfSMattias Nilsson /** 10053df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 10063df57bcfSMattias Nilsson * 10073df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 10083df57bcfSMattias Nilsson */ 10093df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 10103df57bcfSMattias Nilsson { 10113df57bcfSMattias Nilsson int r = 0; 10123df57bcfSMattias Nilsson 10133df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10143df57bcfSMattias Nilsson 1015c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10163df57bcfSMattias Nilsson cpu_relax(); 10173df57bcfSMattias Nilsson 10183df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 10193df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10203df57bcfSMattias Nilsson 1021c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10223df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10233df57bcfSMattias Nilsson 10243df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 10253df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 10263df57bcfSMattias Nilsson r = -EIO; 10273df57bcfSMattias Nilsson 10283df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10293df57bcfSMattias Nilsson 10303df57bcfSMattias Nilsson return r; 10313df57bcfSMattias Nilsson } 10323df57bcfSMattias Nilsson 10330837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 10340837bb72SMattias Nilsson { 10350837bb72SMattias Nilsson int r = 0; 10360837bb72SMattias Nilsson 10370837bb72SMattias Nilsson if (clock == PRCMU_PLLSOC1) 10380837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 10390837bb72SMattias Nilsson else 10400837bb72SMattias Nilsson return -EINVAL; 10410837bb72SMattias Nilsson 10420837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 10430837bb72SMattias Nilsson 10440837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10450837bb72SMattias Nilsson cpu_relax(); 10460837bb72SMattias Nilsson 10470837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10480837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 10490837bb72SMattias Nilsson 10500837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10510837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 10520837bb72SMattias Nilsson 10530837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 10540837bb72SMattias Nilsson r = -EIO; 10550837bb72SMattias Nilsson 10560837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10570837bb72SMattias Nilsson 10580837bb72SMattias Nilsson return r; 10590837bb72SMattias Nilsson } 10600837bb72SMattias Nilsson 10613df57bcfSMattias Nilsson /** 10620b9199e3SBengt Jonsson * prcmu_set_hwacc - set the power state of a h/w accelerator 10630b9199e3SBengt Jonsson * @hwacc_dev: The hardware accelerator (enum hw_acc_dev). 10640b9199e3SBengt Jonsson * @state: The new power state (enum hw_acc_state). 10650b9199e3SBengt Jonsson * 10660b9199e3SBengt Jonsson * This function sets the power state of a hardware accelerator. 10670b9199e3SBengt Jonsson * This function should not be called from interrupt context. 10680b9199e3SBengt Jonsson * 10690b9199e3SBengt Jonsson * NOTE! Deprecated, to be removed when all users switched over to use the 10700b9199e3SBengt Jonsson * regulator framework API. 10710b9199e3SBengt Jonsson */ 10720b9199e3SBengt Jonsson int prcmu_set_hwacc(u16 hwacc_dev, u8 state) 10730b9199e3SBengt Jonsson { 10740b9199e3SBengt Jonsson int r = 0; 10750b9199e3SBengt Jonsson bool ram_retention = false; 10760b9199e3SBengt Jonsson bool enable, enable_ret; 10770b9199e3SBengt Jonsson 10780b9199e3SBengt Jonsson /* check argument */ 10790b9199e3SBengt Jonsson BUG_ON(hwacc_dev >= NUM_HW_ACC); 10800b9199e3SBengt Jonsson 10810b9199e3SBengt Jonsson /* get state of switches */ 10820b9199e3SBengt Jonsson enable = hwacc_enabled[hwacc_dev]; 10830b9199e3SBengt Jonsson enable_ret = hwacc_ret_enabled[hwacc_dev]; 10840b9199e3SBengt Jonsson 10850b9199e3SBengt Jonsson /* set flag if retention is possible */ 10860b9199e3SBengt Jonsson switch (hwacc_dev) { 10870b9199e3SBengt Jonsson case HW_ACC_SVAMMDSP: 10880b9199e3SBengt Jonsson case HW_ACC_SIAMMDSP: 10890b9199e3SBengt Jonsson case HW_ACC_ESRAM1: 10900b9199e3SBengt Jonsson case HW_ACC_ESRAM2: 10910b9199e3SBengt Jonsson case HW_ACC_ESRAM3: 10920b9199e3SBengt Jonsson case HW_ACC_ESRAM4: 10930b9199e3SBengt Jonsson ram_retention = true; 10940b9199e3SBengt Jonsson break; 10950b9199e3SBengt Jonsson } 10960b9199e3SBengt Jonsson 10970b9199e3SBengt Jonsson /* check argument */ 10980b9199e3SBengt Jonsson BUG_ON(state > HW_ON); 10990b9199e3SBengt Jonsson BUG_ON(state == HW_OFF_RAMRET && !ram_retention); 11000b9199e3SBengt Jonsson 11010b9199e3SBengt Jonsson /* modify enable flags */ 11020b9199e3SBengt Jonsson switch (state) { 11030b9199e3SBengt Jonsson case HW_OFF: 11040b9199e3SBengt Jonsson enable_ret = false; 11050b9199e3SBengt Jonsson enable = false; 11060b9199e3SBengt Jonsson break; 11070b9199e3SBengt Jonsson case HW_ON: 11080b9199e3SBengt Jonsson enable = true; 11090b9199e3SBengt Jonsson break; 11100b9199e3SBengt Jonsson case HW_OFF_RAMRET: 11110b9199e3SBengt Jonsson enable_ret = true; 11120b9199e3SBengt Jonsson enable = false; 11130b9199e3SBengt Jonsson break; 11140b9199e3SBengt Jonsson } 11150b9199e3SBengt Jonsson 11160b9199e3SBengt Jonsson /* get regulator (lazy) */ 11170b9199e3SBengt Jonsson if (hwacc_regulator[hwacc_dev] == NULL) { 11180b9199e3SBengt Jonsson hwacc_regulator[hwacc_dev] = regulator_get(NULL, 11190b9199e3SBengt Jonsson hwacc_regulator_name[hwacc_dev]); 11200b9199e3SBengt Jonsson if (IS_ERR(hwacc_regulator[hwacc_dev])) { 11210b9199e3SBengt Jonsson pr_err("prcmu: failed to get supply %s\n", 11220b9199e3SBengt Jonsson hwacc_regulator_name[hwacc_dev]); 11230b9199e3SBengt Jonsson r = PTR_ERR(hwacc_regulator[hwacc_dev]); 11240b9199e3SBengt Jonsson goto out; 11250b9199e3SBengt Jonsson } 11260b9199e3SBengt Jonsson } 11270b9199e3SBengt Jonsson 11280b9199e3SBengt Jonsson if (ram_retention) { 11290b9199e3SBengt Jonsson if (hwacc_ret_regulator[hwacc_dev] == NULL) { 11300b9199e3SBengt Jonsson hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL, 11310b9199e3SBengt Jonsson hwacc_ret_regulator_name[hwacc_dev]); 11320b9199e3SBengt Jonsson if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) { 11330b9199e3SBengt Jonsson pr_err("prcmu: failed to get supply %s\n", 11340b9199e3SBengt Jonsson hwacc_ret_regulator_name[hwacc_dev]); 11350b9199e3SBengt Jonsson r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]); 11360b9199e3SBengt Jonsson goto out; 11370b9199e3SBengt Jonsson } 11380b9199e3SBengt Jonsson } 11390b9199e3SBengt Jonsson } 11400b9199e3SBengt Jonsson 11410b9199e3SBengt Jonsson /* set regulators */ 11420b9199e3SBengt Jonsson if (ram_retention) { 11430b9199e3SBengt Jonsson if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) { 11440b9199e3SBengt Jonsson r = regulator_enable(hwacc_ret_regulator[hwacc_dev]); 11450b9199e3SBengt Jonsson if (r < 0) { 11460b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: ret enable failed\n"); 11470b9199e3SBengt Jonsson goto out; 11480b9199e3SBengt Jonsson } 11490b9199e3SBengt Jonsson hwacc_ret_enabled[hwacc_dev] = true; 11500b9199e3SBengt Jonsson } 11510b9199e3SBengt Jonsson } 11520b9199e3SBengt Jonsson 11530b9199e3SBengt Jonsson if (enable && !hwacc_enabled[hwacc_dev]) { 11540b9199e3SBengt Jonsson r = regulator_enable(hwacc_regulator[hwacc_dev]); 11550b9199e3SBengt Jonsson if (r < 0) { 11560b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: enable failed\n"); 11570b9199e3SBengt Jonsson goto out; 11580b9199e3SBengt Jonsson } 11590b9199e3SBengt Jonsson hwacc_enabled[hwacc_dev] = true; 11600b9199e3SBengt Jonsson } 11610b9199e3SBengt Jonsson 11620b9199e3SBengt Jonsson if (!enable && hwacc_enabled[hwacc_dev]) { 11630b9199e3SBengt Jonsson r = regulator_disable(hwacc_regulator[hwacc_dev]); 11640b9199e3SBengt Jonsson if (r < 0) { 11650b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: disable failed\n"); 11660b9199e3SBengt Jonsson goto out; 11670b9199e3SBengt Jonsson } 11680b9199e3SBengt Jonsson hwacc_enabled[hwacc_dev] = false; 11690b9199e3SBengt Jonsson } 11700b9199e3SBengt Jonsson 11710b9199e3SBengt Jonsson if (ram_retention) { 11720b9199e3SBengt Jonsson if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) { 11730b9199e3SBengt Jonsson r = regulator_disable(hwacc_ret_regulator[hwacc_dev]); 11740b9199e3SBengt Jonsson if (r < 0) { 11750b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: ret disable failed\n"); 11760b9199e3SBengt Jonsson goto out; 11770b9199e3SBengt Jonsson } 11780b9199e3SBengt Jonsson hwacc_ret_enabled[hwacc_dev] = false; 11790b9199e3SBengt Jonsson } 11800b9199e3SBengt Jonsson } 11810b9199e3SBengt Jonsson 11820b9199e3SBengt Jonsson out: 11830b9199e3SBengt Jonsson return r; 11840b9199e3SBengt Jonsson } 11850b9199e3SBengt Jonsson EXPORT_SYMBOL(prcmu_set_hwacc); 11860b9199e3SBengt Jonsson 11870b9199e3SBengt Jonsson /** 118873180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 11893df57bcfSMattias Nilsson * @epod_id: The EPOD to set 11903df57bcfSMattias Nilsson * @epod_state: The new EPOD state 11913df57bcfSMattias Nilsson * 11923df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 11933df57bcfSMattias Nilsson * from interrupt context. 11943df57bcfSMattias Nilsson */ 119573180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 11963df57bcfSMattias Nilsson { 11973df57bcfSMattias Nilsson int r = 0; 11983df57bcfSMattias Nilsson bool ram_retention = false; 11993df57bcfSMattias Nilsson int i; 12003df57bcfSMattias Nilsson 12013df57bcfSMattias Nilsson /* check argument */ 12023df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 12033df57bcfSMattias Nilsson 12043df57bcfSMattias Nilsson /* set flag if retention is possible */ 12053df57bcfSMattias Nilsson switch (epod_id) { 12063df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 12073df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 12083df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 12093df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 12103df57bcfSMattias Nilsson ram_retention = true; 12113df57bcfSMattias Nilsson break; 12123df57bcfSMattias Nilsson } 12133df57bcfSMattias Nilsson 12143df57bcfSMattias Nilsson /* check argument */ 12153df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 12163df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 12173df57bcfSMattias Nilsson 12183df57bcfSMattias Nilsson /* get lock */ 12193df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 12203df57bcfSMattias Nilsson 12213df57bcfSMattias Nilsson /* wait for mailbox */ 1222c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 12233df57bcfSMattias Nilsson cpu_relax(); 12243df57bcfSMattias Nilsson 12253df57bcfSMattias Nilsson /* fill in mailbox */ 12263df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 12273df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 12283df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 12293df57bcfSMattias Nilsson 12303df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 12313df57bcfSMattias Nilsson 1232c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 12333df57bcfSMattias Nilsson 12343df57bcfSMattias Nilsson /* 12353df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 12363df57bcfSMattias Nilsson * and we cannot recover if there is an error. 12373df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 12383df57bcfSMattias Nilsson */ 12393df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 12403df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 12413df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 12423df57bcfSMattias Nilsson __func__); 12433df57bcfSMattias Nilsson r = -EIO; 12443df57bcfSMattias Nilsson goto unlock_and_return; 12453df57bcfSMattias Nilsson } 12463df57bcfSMattias Nilsson 12473df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 12483df57bcfSMattias Nilsson r = -EIO; 12493df57bcfSMattias Nilsson 12503df57bcfSMattias Nilsson unlock_and_return: 12513df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 12523df57bcfSMattias Nilsson return r; 12533df57bcfSMattias Nilsson } 12543df57bcfSMattias Nilsson 12553df57bcfSMattias Nilsson /** 12563df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 12573df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 12583df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 12593df57bcfSMattias Nilsson */ 12603df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 12613df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 12623df57bcfSMattias Nilsson { 12633df57bcfSMattias Nilsson u32 sleep_cfg; 12643df57bcfSMattias Nilsson u32 idle_cfg; 12653df57bcfSMattias Nilsson unsigned long flags; 12663df57bcfSMattias Nilsson 12673df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 12683df57bcfSMattias Nilsson 12693df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 12703df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 12713df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 12723df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 12733df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 12743df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 12753df57bcfSMattias Nilsson 12763df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 12773df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 12783df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 12793df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 12803df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 12813df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 12823df57bcfSMattias Nilsson 12833df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 12843df57bcfSMattias Nilsson 12853df57bcfSMattias Nilsson /* 12863df57bcfSMattias Nilsson * The autonomous power management configuration is done through 12873df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 12883df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 12893df57bcfSMattias Nilsson */ 12903df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 12913df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 12923df57bcfSMattias Nilsson 12933df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 12943df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12953df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12963df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12973df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 12983df57bcfSMattias Nilsson 12993df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 13003df57bcfSMattias Nilsson } 13013df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 13023df57bcfSMattias Nilsson 13033df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 13043df57bcfSMattias Nilsson { 13053df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 13063df57bcfSMattias Nilsson } 13073df57bcfSMattias Nilsson 13083df57bcfSMattias Nilsson static int request_sysclk(bool enable) 13093df57bcfSMattias Nilsson { 13103df57bcfSMattias Nilsson int r; 13113df57bcfSMattias Nilsson unsigned long flags; 13123df57bcfSMattias Nilsson 13133df57bcfSMattias Nilsson r = 0; 13143df57bcfSMattias Nilsson 13153df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 13163df57bcfSMattias Nilsson 13173df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 13183df57bcfSMattias Nilsson 1319c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 13203df57bcfSMattias Nilsson cpu_relax(); 13213df57bcfSMattias Nilsson 13223df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 13233df57bcfSMattias Nilsson 13243df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1325c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 13263df57bcfSMattias Nilsson 13273df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 13283df57bcfSMattias Nilsson 13293df57bcfSMattias Nilsson /* 13303df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 13313df57bcfSMattias Nilsson * SysClk, and it succeeds. 13323df57bcfSMattias Nilsson */ 13333df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 13343df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 13353df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 13363df57bcfSMattias Nilsson __func__); 13373df57bcfSMattias Nilsson r = -EIO; 13383df57bcfSMattias Nilsson } 13393df57bcfSMattias Nilsson 13403df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 13413df57bcfSMattias Nilsson 13423df57bcfSMattias Nilsson return r; 13433df57bcfSMattias Nilsson } 13443df57bcfSMattias Nilsson 13453df57bcfSMattias Nilsson static int request_timclk(bool enable) 13463df57bcfSMattias Nilsson { 13473df57bcfSMattias Nilsson u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 13483df57bcfSMattias Nilsson 13493df57bcfSMattias Nilsson if (!enable) 13503df57bcfSMattias Nilsson val |= PRCM_TCR_STOP_TIMERS; 1351c553b3caSMattias Nilsson writel(val, PRCM_TCR); 13523df57bcfSMattias Nilsson 13533df57bcfSMattias Nilsson return 0; 13543df57bcfSMattias Nilsson } 13553df57bcfSMattias Nilsson 13563df57bcfSMattias Nilsson static int request_reg_clock(u8 clock, bool enable) 13573df57bcfSMattias Nilsson { 13583df57bcfSMattias Nilsson u32 val; 13593df57bcfSMattias Nilsson unsigned long flags; 13603df57bcfSMattias Nilsson 13613df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 13623df57bcfSMattias Nilsson 13633df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1364c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 13653df57bcfSMattias Nilsson cpu_relax(); 13663df57bcfSMattias Nilsson 13673df57bcfSMattias Nilsson val = readl(_PRCMU_BASE + clk_mgt[clock].offset); 13683df57bcfSMattias Nilsson if (enable) { 13693df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 13703df57bcfSMattias Nilsson } else { 13713df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 13723df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 13733df57bcfSMattias Nilsson } 13743df57bcfSMattias Nilsson writel(val, (_PRCMU_BASE + clk_mgt[clock].offset)); 13753df57bcfSMattias Nilsson 13763df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1377c553b3caSMattias Nilsson writel(0, PRCM_SEM); 13783df57bcfSMattias Nilsson 13793df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 13803df57bcfSMattias Nilsson 13813df57bcfSMattias Nilsson return 0; 13823df57bcfSMattias Nilsson } 13833df57bcfSMattias Nilsson 13840837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 13850837bb72SMattias Nilsson { 13860837bb72SMattias Nilsson u32 val; 13870837bb72SMattias Nilsson int ret; 13880837bb72SMattias Nilsson 13890837bb72SMattias Nilsson if (enable) { 13900837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13910837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13920837bb72SMattias Nilsson } 13930837bb72SMattias Nilsson 13940837bb72SMattias Nilsson ret = request_reg_clock(clock, enable); 13950837bb72SMattias Nilsson 13960837bb72SMattias Nilsson if (!ret && !enable) { 13970837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13980837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13990837bb72SMattias Nilsson } 14000837bb72SMattias Nilsson 14010837bb72SMattias Nilsson return ret; 14020837bb72SMattias Nilsson } 14030837bb72SMattias Nilsson 14043df57bcfSMattias Nilsson /** 140573180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 14063df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 14073df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 14083df57bcfSMattias Nilsson * 14093df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 14103df57bcfSMattias Nilsson * Do not use it from any other place! 14113df57bcfSMattias Nilsson */ 141273180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 14133df57bcfSMattias Nilsson { 1414e62ccf3aSLinus Walleij switch(clock) { 1415e62ccf3aSLinus Walleij case PRCMU_SGACLK: 14160837bb72SMattias Nilsson return request_sga_clock(clock, enable); 1417e62ccf3aSLinus Walleij case PRCMU_TIMCLK: 14183df57bcfSMattias Nilsson return request_timclk(enable); 1419e62ccf3aSLinus Walleij case PRCMU_SYSCLK: 14203df57bcfSMattias Nilsson return request_sysclk(enable); 1421e62ccf3aSLinus Walleij case PRCMU_PLLSOC1: 14220837bb72SMattias Nilsson return request_pll(clock, enable); 1423e62ccf3aSLinus Walleij default: 1424e62ccf3aSLinus Walleij break; 1425e62ccf3aSLinus Walleij } 1426e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 1427e62ccf3aSLinus Walleij return request_reg_clock(clock, enable); 14283df57bcfSMattias Nilsson return -EINVAL; 14293df57bcfSMattias Nilsson } 14303df57bcfSMattias Nilsson 143173180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 14323df57bcfSMattias Nilsson { 14333df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 14343df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 14353df57bcfSMattias Nilsson return -EINVAL; 14363df57bcfSMattias Nilsson 14373df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 14383df57bcfSMattias Nilsson 1439c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 14403df57bcfSMattias Nilsson cpu_relax(); 14413df57bcfSMattias Nilsson 14423df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 14433df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 14443df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 14453df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 14463df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 14473df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 14483df57bcfSMattias Nilsson 1449c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 14503df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 14513df57bcfSMattias Nilsson 14523df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 14533df57bcfSMattias Nilsson 14543df57bcfSMattias Nilsson return 0; 14553df57bcfSMattias Nilsson } 14563df57bcfSMattias Nilsson 14573df57bcfSMattias Nilsson int prcmu_config_hotdog(u8 threshold) 14583df57bcfSMattias Nilsson { 14593df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 14603df57bcfSMattias Nilsson 1461c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 14623df57bcfSMattias Nilsson cpu_relax(); 14633df57bcfSMattias Nilsson 14643df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 14653df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 14663df57bcfSMattias Nilsson 1467c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 14683df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 14693df57bcfSMattias Nilsson 14703df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 14713df57bcfSMattias Nilsson 14723df57bcfSMattias Nilsson return 0; 14733df57bcfSMattias Nilsson } 14743df57bcfSMattias Nilsson 14753df57bcfSMattias Nilsson int prcmu_config_hotmon(u8 low, u8 high) 14763df57bcfSMattias Nilsson { 14773df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 14783df57bcfSMattias Nilsson 1479c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 14803df57bcfSMattias Nilsson cpu_relax(); 14813df57bcfSMattias Nilsson 14823df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 14833df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 14843df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 14853df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 14863df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 14873df57bcfSMattias Nilsson 1488c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 14893df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 14903df57bcfSMattias Nilsson 14913df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 14923df57bcfSMattias Nilsson 14933df57bcfSMattias Nilsson return 0; 14943df57bcfSMattias Nilsson } 14953df57bcfSMattias Nilsson 14963df57bcfSMattias Nilsson static int config_hot_period(u16 val) 14973df57bcfSMattias Nilsson { 14983df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 14993df57bcfSMattias Nilsson 1500c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 15013df57bcfSMattias Nilsson cpu_relax(); 15023df57bcfSMattias Nilsson 15033df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 15043df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 15053df57bcfSMattias Nilsson 1506c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 15073df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 15083df57bcfSMattias Nilsson 15093df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 15103df57bcfSMattias Nilsson 15113df57bcfSMattias Nilsson return 0; 15123df57bcfSMattias Nilsson } 15133df57bcfSMattias Nilsson 15143df57bcfSMattias Nilsson int prcmu_start_temp_sense(u16 cycles32k) 15153df57bcfSMattias Nilsson { 15163df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 15173df57bcfSMattias Nilsson return -EINVAL; 15183df57bcfSMattias Nilsson 15193df57bcfSMattias Nilsson return config_hot_period(cycles32k); 15203df57bcfSMattias Nilsson } 15213df57bcfSMattias Nilsson 15223df57bcfSMattias Nilsson int prcmu_stop_temp_sense(void) 15233df57bcfSMattias Nilsson { 15243df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 15253df57bcfSMattias Nilsson } 15263df57bcfSMattias Nilsson 152784165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 152884165b80SJonas Aberg { 152984165b80SJonas Aberg 153084165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 153184165b80SJonas Aberg 153284165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 153384165b80SJonas Aberg cpu_relax(); 153484165b80SJonas Aberg 153584165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 153684165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 153784165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 153884165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 153984165b80SJonas Aberg 154084165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 154184165b80SJonas Aberg 154284165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 154384165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 154484165b80SJonas Aberg 154584165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 154684165b80SJonas Aberg 154784165b80SJonas Aberg return 0; 154884165b80SJonas Aberg 154984165b80SJonas Aberg } 155084165b80SJonas Aberg 155184165b80SJonas Aberg int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 155284165b80SJonas Aberg { 155384165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 155484165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 155584165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 155684165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 155784165b80SJonas Aberg } 155884165b80SJonas Aberg 155984165b80SJonas Aberg int prcmu_enable_a9wdog(u8 id) 156084165b80SJonas Aberg { 156184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 156284165b80SJonas Aberg } 156384165b80SJonas Aberg 156484165b80SJonas Aberg int prcmu_disable_a9wdog(u8 id) 156584165b80SJonas Aberg { 156684165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 156784165b80SJonas Aberg } 156884165b80SJonas Aberg 156984165b80SJonas Aberg int prcmu_kick_a9wdog(u8 id) 157084165b80SJonas Aberg { 157184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 157284165b80SJonas Aberg } 157384165b80SJonas Aberg 157484165b80SJonas Aberg /* 157584165b80SJonas Aberg * timeout is 28 bit, in ms. 157684165b80SJonas Aberg */ 157784165b80SJonas Aberg #define MAX_WATCHDOG_TIMEOUT 131000 157884165b80SJonas Aberg int prcmu_load_a9wdog(u8 id, u32 timeout) 157984165b80SJonas Aberg { 158084165b80SJonas Aberg if (timeout > MAX_WATCHDOG_TIMEOUT) 158184165b80SJonas Aberg /* 158284165b80SJonas Aberg * Due to calculation bug in prcmu fw, timeouts 158384165b80SJonas Aberg * can't be bigger than 131 seconds. 158484165b80SJonas Aberg */ 158584165b80SJonas Aberg return -EINVAL; 158684165b80SJonas Aberg 158784165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 158884165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 158984165b80SJonas Aberg /* 159084165b80SJonas Aberg * Put the lowest 28 bits of timeout at 159184165b80SJonas Aberg * offset 4. Four first bits are used for id. 159284165b80SJonas Aberg */ 159384165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 159484165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 159584165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 159684165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 159784165b80SJonas Aberg } 159884165b80SJonas Aberg 15993df57bcfSMattias Nilsson /** 16003df57bcfSMattias Nilsson * prcmu_set_clock_divider() - Configure the clock divider. 16013df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 16023df57bcfSMattias Nilsson * @divider: The clock divider. (< 32) 16033df57bcfSMattias Nilsson * 16043df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 16053df57bcfSMattias Nilsson * Do not use it from any other place! 16063df57bcfSMattias Nilsson */ 16073df57bcfSMattias Nilsson int prcmu_set_clock_divider(u8 clock, u8 divider) 16083df57bcfSMattias Nilsson { 16093df57bcfSMattias Nilsson u32 val; 16103df57bcfSMattias Nilsson unsigned long flags; 16113df57bcfSMattias Nilsson 16123df57bcfSMattias Nilsson if ((clock >= PRCMU_NUM_REG_CLOCKS) || (divider < 1) || (31 < divider)) 16133df57bcfSMattias Nilsson return -EINVAL; 16143df57bcfSMattias Nilsson 16153df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 16163df57bcfSMattias Nilsson 16173df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1618c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 16193df57bcfSMattias Nilsson cpu_relax(); 16203df57bcfSMattias Nilsson 16213df57bcfSMattias Nilsson val = readl(_PRCMU_BASE + clk_mgt[clock].offset); 16223df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK); 16233df57bcfSMattias Nilsson val |= (u32)divider; 16243df57bcfSMattias Nilsson writel(val, (_PRCMU_BASE + clk_mgt[clock].offset)); 16253df57bcfSMattias Nilsson 16263df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1627c553b3caSMattias Nilsson writel(0, PRCM_SEM); 16283df57bcfSMattias Nilsson 16293df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 16303df57bcfSMattias Nilsson 16313df57bcfSMattias Nilsson return 0; 16323df57bcfSMattias Nilsson } 16333df57bcfSMattias Nilsson 1634650c2a21SLinus Walleij /** 1635650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 1636650c2a21SLinus Walleij * @slave: The I2C slave address. 1637650c2a21SLinus Walleij * @reg: The (start) register address. 1638650c2a21SLinus Walleij * @value: The read out value(s). 1639650c2a21SLinus Walleij * @size: The number of registers to read. 1640650c2a21SLinus Walleij * 1641650c2a21SLinus Walleij * Reads register value(s) from the ABB. 1642650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 1643650c2a21SLinus Walleij */ 1644650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 1645650c2a21SLinus Walleij { 1646650c2a21SLinus Walleij int r; 1647650c2a21SLinus Walleij 1648650c2a21SLinus Walleij if (size != 1) 1649650c2a21SLinus Walleij return -EINVAL; 1650650c2a21SLinus Walleij 16513df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 1652650c2a21SLinus Walleij 1653c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 1654650c2a21SLinus Walleij cpu_relax(); 1655650c2a21SLinus Walleij 16563df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 16573df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 16583df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 16593df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 1660650c2a21SLinus Walleij 1661c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 16623df57bcfSMattias Nilsson 1663650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 16643df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 16653df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 16663df57bcfSMattias Nilsson __func__); 1667650c2a21SLinus Walleij r = -EIO; 16683df57bcfSMattias Nilsson } else { 1669650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 16703df57bcfSMattias Nilsson } 16713df57bcfSMattias Nilsson 1672650c2a21SLinus Walleij if (!r) 1673650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 1674650c2a21SLinus Walleij 1675650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 16763df57bcfSMattias Nilsson 1677650c2a21SLinus Walleij return r; 1678650c2a21SLinus Walleij } 1679650c2a21SLinus Walleij 1680650c2a21SLinus Walleij /** 1681650c2a21SLinus Walleij * prcmu_abb_write() - Write register value(s) to the ABB. 1682650c2a21SLinus Walleij * @slave: The I2C slave address. 1683650c2a21SLinus Walleij * @reg: The (start) register address. 1684650c2a21SLinus Walleij * @value: The value(s) to write. 1685650c2a21SLinus Walleij * @size: The number of registers to write. 1686650c2a21SLinus Walleij * 1687650c2a21SLinus Walleij * Reads register value(s) from the ABB. 1688650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 1689650c2a21SLinus Walleij */ 1690650c2a21SLinus Walleij int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 1691650c2a21SLinus Walleij { 1692650c2a21SLinus Walleij int r; 1693650c2a21SLinus Walleij 1694650c2a21SLinus Walleij if (size != 1) 1695650c2a21SLinus Walleij return -EINVAL; 1696650c2a21SLinus Walleij 16973df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 1698650c2a21SLinus Walleij 1699c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 1700650c2a21SLinus Walleij cpu_relax(); 1701650c2a21SLinus Walleij 17023df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 17033df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 17043df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 17053df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 1706650c2a21SLinus Walleij 1707c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 17083df57bcfSMattias Nilsson 1709650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 17103df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 17113df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 17123df57bcfSMattias Nilsson __func__); 1713650c2a21SLinus Walleij r = -EIO; 17143df57bcfSMattias Nilsson } else { 1715650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 17163df57bcfSMattias Nilsson } 17173df57bcfSMattias Nilsson 17183df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 17193df57bcfSMattias Nilsson 17203df57bcfSMattias Nilsson return r; 17213df57bcfSMattias Nilsson } 17223df57bcfSMattias Nilsson 17233df57bcfSMattias Nilsson /** 17243df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 17253df57bcfSMattias Nilsson */ 17263df57bcfSMattias Nilsson void prcmu_ac_wake_req(void) 17273df57bcfSMattias Nilsson { 17283df57bcfSMattias Nilsson u32 val; 1729d6e3002eSMattias Nilsson u32 status; 17303df57bcfSMattias Nilsson 17313df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 17323df57bcfSMattias Nilsson 1733c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 17343df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 17353df57bcfSMattias Nilsson goto unlock_and_return; 17363df57bcfSMattias Nilsson 17373df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 17383df57bcfSMattias Nilsson 1739d6e3002eSMattias Nilsson retry: 1740c553b3caSMattias Nilsson writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); 17413df57bcfSMattias Nilsson 17423df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 1743d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 174457265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 1745d6e3002eSMattias Nilsson __func__); 1746d6e3002eSMattias Nilsson goto unlock_and_return; 1747d6e3002eSMattias Nilsson } 1748d6e3002eSMattias Nilsson 1749d6e3002eSMattias Nilsson /* 1750d6e3002eSMattias Nilsson * The modem can generate an AC_WAKE_ACK, and then still go to sleep. 1751d6e3002eSMattias Nilsson * As a workaround, we wait, and then check that the modem is indeed 1752d6e3002eSMattias Nilsson * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS 1753d6e3002eSMattias Nilsson * register, which may not be the whole truth). 1754d6e3002eSMattias Nilsson */ 1755d6e3002eSMattias Nilsson udelay(400); 1756d6e3002eSMattias Nilsson status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2)); 1757d6e3002eSMattias Nilsson if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE | 1758d6e3002eSMattias Nilsson PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) { 1759d6e3002eSMattias Nilsson pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n", 1760d6e3002eSMattias Nilsson __func__, status); 1761d6e3002eSMattias Nilsson udelay(1200); 1762d6e3002eSMattias Nilsson writel(val, PRCM_HOSTACCESS_REQ); 1763d6e3002eSMattias Nilsson if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 1764d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) 1765d6e3002eSMattias Nilsson goto retry; 176657265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n", 17673df57bcfSMattias Nilsson __func__); 17683df57bcfSMattias Nilsson } 1769650c2a21SLinus Walleij 1770650c2a21SLinus Walleij unlock_and_return: 17713df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 1772650c2a21SLinus Walleij } 1773650c2a21SLinus Walleij 17743df57bcfSMattias Nilsson /** 17753df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 17763df57bcfSMattias Nilsson */ 17773df57bcfSMattias Nilsson void prcmu_ac_sleep_req() 1778650c2a21SLinus Walleij { 17793df57bcfSMattias Nilsson u32 val; 1780650c2a21SLinus Walleij 17813df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 1782650c2a21SLinus Walleij 1783c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 17843df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 17853df57bcfSMattias Nilsson goto unlock_and_return; 17863df57bcfSMattias Nilsson 17873df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 1788c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 17893df57bcfSMattias Nilsson 17903df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 1791d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 179257265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 17933df57bcfSMattias Nilsson __func__); 17943df57bcfSMattias Nilsson } 17953df57bcfSMattias Nilsson 17963df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 17973df57bcfSMattias Nilsson 17983df57bcfSMattias Nilsson unlock_and_return: 17993df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 18003df57bcfSMattias Nilsson } 18013df57bcfSMattias Nilsson 180273180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 18033df57bcfSMattias Nilsson { 18043df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 18053df57bcfSMattias Nilsson } 18063df57bcfSMattias Nilsson 18073df57bcfSMattias Nilsson /** 180873180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 18093df57bcfSMattias Nilsson * 181073180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 18113df57bcfSMattias Nilsson * fires interrupt to fw 18123df57bcfSMattias Nilsson */ 181373180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 18143df57bcfSMattias Nilsson { 18153df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 1816c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 18173df57bcfSMattias Nilsson } 18183df57bcfSMattias Nilsson 18193df57bcfSMattias Nilsson /** 1820597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 1821597045deSSebastian Rasmussen * 1822597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 1823597045deSSebastian Rasmussen * last restart. 1824597045deSSebastian Rasmussen */ 1825597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 1826597045deSSebastian Rasmussen { 1827597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 1828597045deSSebastian Rasmussen } 1829597045deSSebastian Rasmussen 1830597045deSSebastian Rasmussen /** 18313df57bcfSMattias Nilsson * prcmu_reset_modem - ask the PRCMU to reset modem 18323df57bcfSMattias Nilsson */ 18333df57bcfSMattias Nilsson void prcmu_modem_reset(void) 18343df57bcfSMattias Nilsson { 1835650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 1836650c2a21SLinus Walleij 1837c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 1838650c2a21SLinus Walleij cpu_relax(); 1839650c2a21SLinus Walleij 18403df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 1841c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 1842650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 18433df57bcfSMattias Nilsson 18443df57bcfSMattias Nilsson /* 18453df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 18463df57bcfSMattias Nilsson * This state is already managed by upper layer 18473df57bcfSMattias Nilsson */ 1848650c2a21SLinus Walleij 1849650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 1850650c2a21SLinus Walleij } 1851650c2a21SLinus Walleij 18523df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 1853650c2a21SLinus Walleij { 18543df57bcfSMattias Nilsson unsigned long flags; 1855650c2a21SLinus Walleij 18563df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 1857650c2a21SLinus Walleij 1858c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 18593df57bcfSMattias Nilsson cpu_relax(); 1860650c2a21SLinus Walleij 18613df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 1862c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 1863650c2a21SLinus Walleij 18643df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 1865650c2a21SLinus Walleij } 1866650c2a21SLinus Walleij 18673df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 1868650c2a21SLinus Walleij { 18693df57bcfSMattias Nilsson pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 18703df57bcfSMattias Nilsson header, n); 1871650c2a21SLinus Walleij } 1872650c2a21SLinus Walleij 18733df57bcfSMattias Nilsson static bool read_mailbox_0(void) 1874650c2a21SLinus Walleij { 18753df57bcfSMattias Nilsson bool r; 18763df57bcfSMattias Nilsson u32 ev; 18773df57bcfSMattias Nilsson unsigned int n; 18783df57bcfSMattias Nilsson u8 header; 18793df57bcfSMattias Nilsson 18803df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 18813df57bcfSMattias Nilsson switch (header) { 18823df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 18833df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 18843df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 18853df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 18863df57bcfSMattias Nilsson else 18873df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 18883df57bcfSMattias Nilsson 18893df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 18903df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 18913df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 18923df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 18933df57bcfSMattias Nilsson 18943df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 18953df57bcfSMattias Nilsson 18963df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 18973df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 18983df57bcfSMattias Nilsson generic_handle_irq(IRQ_PRCMU_BASE + n); 18993df57bcfSMattias Nilsson } 19003df57bcfSMattias Nilsson r = true; 19013df57bcfSMattias Nilsson break; 19023df57bcfSMattias Nilsson default: 19033df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 19043df57bcfSMattias Nilsson r = false; 19053df57bcfSMattias Nilsson break; 19063df57bcfSMattias Nilsson } 1907c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 19083df57bcfSMattias Nilsson return r; 19093df57bcfSMattias Nilsson } 19103df57bcfSMattias Nilsson 19113df57bcfSMattias Nilsson static bool read_mailbox_1(void) 19123df57bcfSMattias Nilsson { 19133df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 19143df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 19153df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 19163df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 19173df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 19183df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 19193df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 1920c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 1921650c2a21SLinus Walleij complete(&mb1_transfer.work); 19223df57bcfSMattias Nilsson return false; 1923650c2a21SLinus Walleij } 1924650c2a21SLinus Walleij 19253df57bcfSMattias Nilsson static bool read_mailbox_2(void) 1926650c2a21SLinus Walleij { 19273df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 1928c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 19293df57bcfSMattias Nilsson complete(&mb2_transfer.work); 19303df57bcfSMattias Nilsson return false; 1931650c2a21SLinus Walleij } 1932650c2a21SLinus Walleij 19333df57bcfSMattias Nilsson static bool read_mailbox_3(void) 1934650c2a21SLinus Walleij { 1935c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 19363df57bcfSMattias Nilsson return false; 1937650c2a21SLinus Walleij } 1938650c2a21SLinus Walleij 19393df57bcfSMattias Nilsson static bool read_mailbox_4(void) 1940650c2a21SLinus Walleij { 19413df57bcfSMattias Nilsson u8 header; 19423df57bcfSMattias Nilsson bool do_complete = true; 19433df57bcfSMattias Nilsson 19443df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 19453df57bcfSMattias Nilsson switch (header) { 19463df57bcfSMattias Nilsson case MB4H_MEM_ST: 19473df57bcfSMattias Nilsson case MB4H_HOTDOG: 19483df57bcfSMattias Nilsson case MB4H_HOTMON: 19493df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 1950a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 1951a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 1952a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 1953a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 1954a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 19553df57bcfSMattias Nilsson break; 19563df57bcfSMattias Nilsson default: 19573df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 19583df57bcfSMattias Nilsson do_complete = false; 19593df57bcfSMattias Nilsson break; 1960650c2a21SLinus Walleij } 1961650c2a21SLinus Walleij 1962c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 19633df57bcfSMattias Nilsson 19643df57bcfSMattias Nilsson if (do_complete) 19653df57bcfSMattias Nilsson complete(&mb4_transfer.work); 19663df57bcfSMattias Nilsson 19673df57bcfSMattias Nilsson return false; 19683df57bcfSMattias Nilsson } 19693df57bcfSMattias Nilsson 19703df57bcfSMattias Nilsson static bool read_mailbox_5(void) 1971650c2a21SLinus Walleij { 19723df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 19733df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 1974c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 1975650c2a21SLinus Walleij complete(&mb5_transfer.work); 19763df57bcfSMattias Nilsson return false; 1977650c2a21SLinus Walleij } 1978650c2a21SLinus Walleij 19793df57bcfSMattias Nilsson static bool read_mailbox_6(void) 1980650c2a21SLinus Walleij { 1981c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 19823df57bcfSMattias Nilsson return false; 1983650c2a21SLinus Walleij } 1984650c2a21SLinus Walleij 19853df57bcfSMattias Nilsson static bool read_mailbox_7(void) 1986650c2a21SLinus Walleij { 1987c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 19883df57bcfSMattias Nilsson return false; 1989650c2a21SLinus Walleij } 1990650c2a21SLinus Walleij 19913df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 1992650c2a21SLinus Walleij read_mailbox_0, 1993650c2a21SLinus Walleij read_mailbox_1, 1994650c2a21SLinus Walleij read_mailbox_2, 1995650c2a21SLinus Walleij read_mailbox_3, 1996650c2a21SLinus Walleij read_mailbox_4, 1997650c2a21SLinus Walleij read_mailbox_5, 1998650c2a21SLinus Walleij read_mailbox_6, 1999650c2a21SLinus Walleij read_mailbox_7 2000650c2a21SLinus Walleij }; 2001650c2a21SLinus Walleij 2002650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2003650c2a21SLinus Walleij { 2004650c2a21SLinus Walleij u32 bits; 2005650c2a21SLinus Walleij u8 n; 20063df57bcfSMattias Nilsson irqreturn_t r; 2007650c2a21SLinus Walleij 2008c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2009650c2a21SLinus Walleij if (unlikely(!bits)) 2010650c2a21SLinus Walleij return IRQ_NONE; 2011650c2a21SLinus Walleij 20123df57bcfSMattias Nilsson r = IRQ_HANDLED; 2013650c2a21SLinus Walleij for (n = 0; bits; n++) { 2014650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2015650c2a21SLinus Walleij bits -= MBOX_BIT(n); 20163df57bcfSMattias Nilsson if (read_mailbox[n]()) 20173df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2018650c2a21SLinus Walleij } 2019650c2a21SLinus Walleij } 20203df57bcfSMattias Nilsson return r; 20213df57bcfSMattias Nilsson } 20223df57bcfSMattias Nilsson 20233df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 20243df57bcfSMattias Nilsson { 20253df57bcfSMattias Nilsson ack_dbb_wakeup(); 2026650c2a21SLinus Walleij return IRQ_HANDLED; 2027650c2a21SLinus Walleij } 2028650c2a21SLinus Walleij 20293df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 20303df57bcfSMattias Nilsson { 20313df57bcfSMattias Nilsson unsigned long flags; 20323df57bcfSMattias Nilsson 20333df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 20343df57bcfSMattias Nilsson 20353df57bcfSMattias Nilsson config_wakeups(); 20363df57bcfSMattias Nilsson 20373df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 20383df57bcfSMattias Nilsson } 20393df57bcfSMattias Nilsson 20403df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 20413df57bcfSMattias Nilsson { 20423df57bcfSMattias Nilsson unsigned long flags; 20433df57bcfSMattias Nilsson 20443df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 20453df57bcfSMattias Nilsson 20463df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 20473df57bcfSMattias Nilsson 20483df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 20493df57bcfSMattias Nilsson 20503df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 20513df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 20523df57bcfSMattias Nilsson } 20533df57bcfSMattias Nilsson 20543df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 20553df57bcfSMattias Nilsson { 20563df57bcfSMattias Nilsson unsigned long flags; 20573df57bcfSMattias Nilsson 20583df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 20593df57bcfSMattias Nilsson 20603df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 20613df57bcfSMattias Nilsson 20623df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 20633df57bcfSMattias Nilsson 20643df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 20653df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 20663df57bcfSMattias Nilsson } 20673df57bcfSMattias Nilsson 20683df57bcfSMattias Nilsson static void noop(struct irq_data *d) 20693df57bcfSMattias Nilsson { 20703df57bcfSMattias Nilsson } 20713df57bcfSMattias Nilsson 20723df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 20733df57bcfSMattias Nilsson .name = "prcmu", 20743df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 20753df57bcfSMattias Nilsson .irq_ack = noop, 20763df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 20773df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 20783df57bcfSMattias Nilsson }; 20793df57bcfSMattias Nilsson 208073180f85SMattias Nilsson void __init db8500_prcmu_early_init(void) 2081650c2a21SLinus Walleij { 20823df57bcfSMattias Nilsson unsigned int i; 20833e2762c8SLinus Walleij if (cpu_is_u8500v2()) { 20843df57bcfSMattias Nilsson void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); 20853df57bcfSMattias Nilsson 20863df57bcfSMattias Nilsson if (tcpm_base != NULL) { 20873e2762c8SLinus Walleij u32 version; 20883df57bcfSMattias Nilsson version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); 20893df57bcfSMattias Nilsson prcmu_version.project_number = version & 0xFF; 20903df57bcfSMattias Nilsson prcmu_version.api_version = (version >> 8) & 0xFF; 20913df57bcfSMattias Nilsson prcmu_version.func_version = (version >> 16) & 0xFF; 20923df57bcfSMattias Nilsson prcmu_version.errata = (version >> 24) & 0xFF; 20933df57bcfSMattias Nilsson pr_info("PRCMU firmware version %d.%d.%d\n", 20943df57bcfSMattias Nilsson (version >> 8) & 0xFF, (version >> 16) & 0xFF, 20953df57bcfSMattias Nilsson (version >> 24) & 0xFF); 20963df57bcfSMattias Nilsson iounmap(tcpm_base); 20973df57bcfSMattias Nilsson } 20983df57bcfSMattias Nilsson 2099650c2a21SLinus Walleij tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); 2100650c2a21SLinus Walleij } else { 2101650c2a21SLinus Walleij pr_err("prcmu: Unsupported chip version\n"); 2102650c2a21SLinus Walleij BUG(); 2103650c2a21SLinus Walleij } 2104650c2a21SLinus Walleij 21053df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 21063df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 21073df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 21083df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2109650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2110650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 21113df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 21123df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 21133df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 21143df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 21153df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 21163df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 21173df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 21183df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2119650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2120650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2121650c2a21SLinus Walleij 21223df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2123650c2a21SLinus Walleij 21243df57bcfSMattias Nilsson /* Initalize irqs. */ 21253df57bcfSMattias Nilsson for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { 21263df57bcfSMattias Nilsson unsigned int irq; 21273df57bcfSMattias Nilsson 21283df57bcfSMattias Nilsson irq = IRQ_PRCMU_BASE + i; 21293df57bcfSMattias Nilsson irq_set_chip_and_handler(irq, &prcmu_irq_chip, 21303df57bcfSMattias Nilsson handle_simple_irq); 21313df57bcfSMattias Nilsson set_irq_flags(irq, IRQF_VALID); 21323df57bcfSMattias Nilsson } 2133650c2a21SLinus Walleij } 2134650c2a21SLinus Walleij 21351934dae2SLinus Walleij static void __init db8500_prcmu_init_clkforce(void) 2136d65e12d7SMattias Nilsson { 2137d65e12d7SMattias Nilsson u32 val; 2138d65e12d7SMattias Nilsson 2139d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2140d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2141d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2142d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2143d65e12d7SMattias Nilsson } 2144d65e12d7SMattias Nilsson 21451032fbfdSBengt Jonsson /* 21461032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 21471032fbfdSBengt Jonsson */ 21481032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 21491032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 21501032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 21511032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 21521032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 21531032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 21541032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 21551032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 21561032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 21571032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 21581032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 21591032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 21601032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 21611032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 21621032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 21631032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 21641032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 21651032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 21661032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 21671032fbfdSBengt Jonsson }; 21681032fbfdSBengt Jonsson 21691032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 21701032fbfdSBengt Jonsson /* CG2900 and CW1200 power to off-chip peripherals */ 21711032fbfdSBengt Jonsson REGULATOR_SUPPLY("gbf_1v8", "cg2900-uart.0"), 21721032fbfdSBengt Jonsson REGULATOR_SUPPLY("wlan_1v8", "cw1200.0"), 21731032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 21741032fbfdSBengt Jonsson /* AV8100 regulator */ 21751032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 21761032fbfdSBengt Jonsson }; 21771032fbfdSBengt Jonsson 21781032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 21791032fbfdSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2.0"), 2180624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2181624e87c2SBengt Jonsson }; 2182624e87c2SBengt Jonsson 2183624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2184624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2185624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2186624e87c2SBengt Jonsson }; 2187624e87c2SBengt Jonsson 2188624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2189624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2190624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2191624e87c2SBengt Jonsson }; 2192624e87c2SBengt Jonsson 2193624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2194624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2195624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2196624e87c2SBengt Jonsson }; 2197624e87c2SBengt Jonsson 2198624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2199624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2200624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2201624e87c2SBengt Jonsson }; 2202624e87c2SBengt Jonsson 2203624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2204624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2205624e87c2SBengt Jonsson }; 2206624e87c2SBengt Jonsson 2207624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2208624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2209624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2210624e87c2SBengt Jonsson }; 2211624e87c2SBengt Jonsson 2212624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2213624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2214624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2215624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 22161032fbfdSBengt Jonsson }; 22171032fbfdSBengt Jonsson 22181032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 22191032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 22201032fbfdSBengt Jonsson .constraints = { 22211032fbfdSBengt Jonsson .name = "db8500-vape", 22221032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22231032fbfdSBengt Jonsson }, 22241032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 22251032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 22261032fbfdSBengt Jonsson }, 22271032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 22281032fbfdSBengt Jonsson .constraints = { 22291032fbfdSBengt Jonsson .name = "db8500-varm", 22301032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22311032fbfdSBengt Jonsson }, 22321032fbfdSBengt Jonsson }, 22331032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 22341032fbfdSBengt Jonsson .constraints = { 22351032fbfdSBengt Jonsson .name = "db8500-vmodem", 22361032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22371032fbfdSBengt Jonsson }, 22381032fbfdSBengt Jonsson }, 22391032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 22401032fbfdSBengt Jonsson .constraints = { 22411032fbfdSBengt Jonsson .name = "db8500-vpll", 22421032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22431032fbfdSBengt Jonsson }, 22441032fbfdSBengt Jonsson }, 22451032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 22461032fbfdSBengt Jonsson .constraints = { 22471032fbfdSBengt Jonsson .name = "db8500-vsmps1", 22481032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22491032fbfdSBengt Jonsson }, 22501032fbfdSBengt Jonsson }, 22511032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 22521032fbfdSBengt Jonsson .constraints = { 22531032fbfdSBengt Jonsson .name = "db8500-vsmps2", 22541032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22551032fbfdSBengt Jonsson }, 22561032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 22571032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 22581032fbfdSBengt Jonsson }, 22591032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 22601032fbfdSBengt Jonsson .constraints = { 22611032fbfdSBengt Jonsson .name = "db8500-vsmps3", 22621032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22631032fbfdSBengt Jonsson }, 22641032fbfdSBengt Jonsson }, 22651032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 22661032fbfdSBengt Jonsson .constraints = { 22671032fbfdSBengt Jonsson .name = "db8500-vrf1", 22681032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22691032fbfdSBengt Jonsson }, 22701032fbfdSBengt Jonsson }, 22711032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 22721032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 22731032fbfdSBengt Jonsson .constraints = { 22741032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 22751032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22761032fbfdSBengt Jonsson }, 2277624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2278624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 22791032fbfdSBengt Jonsson }, 22801032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 22811032fbfdSBengt Jonsson .constraints = { 22821032fbfdSBengt Jonsson /* "ret" means "retention" */ 22831032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 22841032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22851032fbfdSBengt Jonsson }, 22861032fbfdSBengt Jonsson }, 22871032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 22881032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 22891032fbfdSBengt Jonsson .constraints = { 22901032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 22911032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 22921032fbfdSBengt Jonsson }, 2293624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2294624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 22951032fbfdSBengt Jonsson }, 22961032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 22971032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 22981032fbfdSBengt Jonsson .constraints = { 22991032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 23001032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23011032fbfdSBengt Jonsson }, 2302624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2303624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 23041032fbfdSBengt Jonsson }, 23051032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 23061032fbfdSBengt Jonsson .constraints = { 23071032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 23081032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23091032fbfdSBengt Jonsson }, 23101032fbfdSBengt Jonsson }, 23111032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 23121032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 23131032fbfdSBengt Jonsson .constraints = { 23141032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 23151032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23161032fbfdSBengt Jonsson }, 2317624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 2318624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 23191032fbfdSBengt Jonsson }, 23201032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 23211032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 23221032fbfdSBengt Jonsson .constraints = { 23231032fbfdSBengt Jonsson .name = "db8500-sga", 23241032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23251032fbfdSBengt Jonsson }, 2326624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 2327624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2328624e87c2SBengt Jonsson 23291032fbfdSBengt Jonsson }, 23301032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 23311032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 23321032fbfdSBengt Jonsson .constraints = { 23331032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 23341032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23351032fbfdSBengt Jonsson }, 23361032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 23371032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 23381032fbfdSBengt Jonsson }, 23391032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 23401032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 23411032fbfdSBengt Jonsson .constraints = { 23421032fbfdSBengt Jonsson .name = "db8500-esram12", 23431032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23441032fbfdSBengt Jonsson }, 2345624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 2346624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 23471032fbfdSBengt Jonsson }, 23481032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 23491032fbfdSBengt Jonsson .constraints = { 23501032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 23511032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23521032fbfdSBengt Jonsson }, 23531032fbfdSBengt Jonsson }, 23541032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 23551032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 23561032fbfdSBengt Jonsson .constraints = { 23571032fbfdSBengt Jonsson .name = "db8500-esram34", 23581032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23591032fbfdSBengt Jonsson }, 2360624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 2361624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 23621032fbfdSBengt Jonsson }, 23631032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 23641032fbfdSBengt Jonsson .constraints = { 23651032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 23661032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 23671032fbfdSBengt Jonsson }, 23681032fbfdSBengt Jonsson }, 23691032fbfdSBengt Jonsson }; 23701032fbfdSBengt Jonsson 23713df57bcfSMattias Nilsson static struct mfd_cell db8500_prcmu_devs[] = { 23723df57bcfSMattias Nilsson { 23733df57bcfSMattias Nilsson .name = "db8500-prcmu-regulators", 23741ed7891fSMattias Wallin .platform_data = &db8500_regulators, 23751ed7891fSMattias Wallin .pdata_size = sizeof(db8500_regulators), 23763df57bcfSMattias Nilsson }, 23773df57bcfSMattias Nilsson { 23783df57bcfSMattias Nilsson .name = "cpufreq-u8500", 23793df57bcfSMattias Nilsson }, 23803df57bcfSMattias Nilsson }; 23813df57bcfSMattias Nilsson 23823df57bcfSMattias Nilsson /** 23833df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 23843df57bcfSMattias Nilsson * 23853df57bcfSMattias Nilsson */ 23863df57bcfSMattias Nilsson static int __init db8500_prcmu_probe(struct platform_device *pdev) 23873df57bcfSMattias Nilsson { 23883df57bcfSMattias Nilsson int err = 0; 23893df57bcfSMattias Nilsson 23903df57bcfSMattias Nilsson if (ux500_is_svp()) 23913df57bcfSMattias Nilsson return -ENODEV; 23923df57bcfSMattias Nilsson 23931934dae2SLinus Walleij db8500_prcmu_init_clkforce(); 2394d65e12d7SMattias Nilsson 23953df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 2396c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 23973df57bcfSMattias Nilsson 23983df57bcfSMattias Nilsson err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 23993df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 24003df57bcfSMattias Nilsson if (err < 0) { 24013df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 24023df57bcfSMattias Nilsson err = -EBUSY; 24033df57bcfSMattias Nilsson goto no_irq_return; 24043df57bcfSMattias Nilsson } 24053df57bcfSMattias Nilsson 24063df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later()) 24073df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 24083df57bcfSMattias Nilsson 24093df57bcfSMattias Nilsson err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 24103df57bcfSMattias Nilsson ARRAY_SIZE(db8500_prcmu_devs), NULL, 24113df57bcfSMattias Nilsson 0); 24123df57bcfSMattias Nilsson 24133df57bcfSMattias Nilsson if (err) 24143df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 24153df57bcfSMattias Nilsson else 24163df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 24173df57bcfSMattias Nilsson 24183df57bcfSMattias Nilsson no_irq_return: 24193df57bcfSMattias Nilsson return err; 24203df57bcfSMattias Nilsson } 24213df57bcfSMattias Nilsson 24223df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 24233df57bcfSMattias Nilsson .driver = { 24243df57bcfSMattias Nilsson .name = "db8500-prcmu", 24253df57bcfSMattias Nilsson .owner = THIS_MODULE, 24263df57bcfSMattias Nilsson }, 24273df57bcfSMattias Nilsson }; 24283df57bcfSMattias Nilsson 24293df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 24303df57bcfSMattias Nilsson { 24313df57bcfSMattias Nilsson return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe); 24323df57bcfSMattias Nilsson } 24333df57bcfSMattias Nilsson 24343df57bcfSMattias Nilsson arch_initcall(db8500_prcmu_init); 24353df57bcfSMattias Nilsson 24363df57bcfSMattias Nilsson MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 24373df57bcfSMattias Nilsson MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 24383df57bcfSMattias Nilsson MODULE_LICENSE("GPL v2"); 2439