1650c2a21SLinus Walleij /* 2650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 3650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 4650c2a21SLinus Walleij * 5650c2a21SLinus Walleij * License Terms: GNU General Public License v2 6650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9650c2a21SLinus Walleij * 10650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij */ 13650c2a21SLinus Walleij #include <linux/module.h> 143df57bcfSMattias Nilsson #include <linux/kernel.h> 153df57bcfSMattias Nilsson #include <linux/delay.h> 16650c2a21SLinus Walleij #include <linux/errno.h> 17650c2a21SLinus Walleij #include <linux/err.h> 183df57bcfSMattias Nilsson #include <linux/spinlock.h> 19650c2a21SLinus Walleij #include <linux/io.h> 203df57bcfSMattias Nilsson #include <linux/slab.h> 21650c2a21SLinus Walleij #include <linux/mutex.h> 22650c2a21SLinus Walleij #include <linux/completion.h> 233df57bcfSMattias Nilsson #include <linux/irq.h> 24650c2a21SLinus Walleij #include <linux/jiffies.h> 25650c2a21SLinus Walleij #include <linux/bitops.h> 263df57bcfSMattias Nilsson #include <linux/fs.h> 27d98a5384SLee Jones #include <linux/of.h> 283df57bcfSMattias Nilsson #include <linux/platform_device.h> 293df57bcfSMattias Nilsson #include <linux/uaccess.h> 303df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3173180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 323a8e39c9SLee Jones #include <linux/mfd/abx500/ab8500.h> 331032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 341032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 35c280f45fSUlf Hansson #include <linux/cpufreq.h> 36b3aac62bSFabio Baltieri #include <linux/platform_data/ux500_wdt.h> 3755b175d7SArnd Bergmann #include <linux/platform_data/db8500_thermal.h> 3873180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 39650c2a21SLinus Walleij 403df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 413df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 423df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 433df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 443df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 453df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 463df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 473df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 483df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 493df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 503df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 513df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 523df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 533df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 543df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 55650c2a21SLinus Walleij 563df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 573df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 583df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 593df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 60650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 61650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 62650c2a21SLinus Walleij 633df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 643df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 653df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 663df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 67650c2a21SLinus Walleij 683df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 693df57bcfSMattias Nilsson 703df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 713df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 723df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 733df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 743df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 753df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 783df57bcfSMattias Nilsson 793df57bcfSMattias Nilsson /* Req Mailboxes */ 803df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 813df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 823df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 833df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 843df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 853df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 863df57bcfSMattias Nilsson 873df57bcfSMattias Nilsson /* Ack Mailboxes */ 883df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 893df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 903df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 913df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 923df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 933df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 943df57bcfSMattias Nilsson 953df57bcfSMattias Nilsson /* Mailbox 0 headers */ 963df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 973df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 983df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 993df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1003df57bcfSMattias Nilsson 1013df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1023df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1033df57bcfSMattias Nilsson 1043df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1053df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1063df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1073df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1083df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1093df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1113df57bcfSMattias Nilsson 1123df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1133df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1143df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1153df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1163df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1173df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1203df57bcfSMattias Nilsson 1213df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1223df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1233df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1243df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1253df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1263df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 127a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1283df57bcfSMattias Nilsson 1293df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1303df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1313df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 132a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 1336b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1 1346b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2 135a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 136a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1373df57bcfSMattias Nilsson 1383df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1393df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1403df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1413df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1423df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1433df57bcfSMattias Nilsson 1443df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1453df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1463df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1473df57bcfSMattias Nilsson 1483df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1493df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1503df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1513df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1523df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1533df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1593df57bcfSMattias Nilsson 1603df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1613df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1623df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1633df57bcfSMattias Nilsson 1643df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1653df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1663df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1673df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1683df57bcfSMattias Nilsson 1693df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1703df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1713df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1723df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1733df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1743df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1773df57bcfSMattias Nilsson 1783df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1793df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1803df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1813df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1823df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1833df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 184a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 185a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 186a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 187a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 188a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1893df57bcfSMattias Nilsson 1903df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1913df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1923df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1933df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1943df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 1953df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 1993df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2003df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 201a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 202a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 203a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 204a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 205a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 206a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 207a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2083df57bcfSMattias Nilsson 2093df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2103df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2113df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2123df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2133df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2147a4f2609SLinus Walleij #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) 2157a4f2609SLinus Walleij #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) 2163df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2173df57bcfSMattias Nilsson 2183df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2193df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2203df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2213df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2223df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2233df57bcfSMattias Nilsson 2243df57bcfSMattias Nilsson #define NUM_MB 8 2253df57bcfSMattias Nilsson #define MBOX_BIT BIT 2263df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2273df57bcfSMattias Nilsson 2283df57bcfSMattias Nilsson /* 2293df57bcfSMattias Nilsson * Wakeups/IRQs 2303df57bcfSMattias Nilsson */ 2313df57bcfSMattias Nilsson 2323df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2333df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2343df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2353df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2363df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2373df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2383df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2613df57bcfSMattias Nilsson 262b58d12feSMattias Nilsson static struct { 263b58d12feSMattias Nilsson bool valid; 264b58d12feSMattias Nilsson struct prcmu_fw_version version; 265b58d12feSMattias Nilsson } fw_info; 266b58d12feSMattias Nilsson 267f3f1f0a1SLee Jones static struct irq_domain *db8500_irq_domain; 268f3f1f0a1SLee Jones 2693df57bcfSMattias Nilsson /* 2703df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2713df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2723df57bcfSMattias Nilsson * 2733df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2743df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2753df57bcfSMattias Nilsson * around, to further complicate matters.) 2763df57bcfSMattias Nilsson */ 27755b175d7SArnd Bergmann #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name)) 2783df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 27955b175d7SArnd Bergmann 28055b175d7SArnd Bergmann #define IRQ_PRCMU_RTC 0 28155b175d7SArnd Bergmann #define IRQ_PRCMU_RTT0 1 28255b175d7SArnd Bergmann #define IRQ_PRCMU_RTT1 2 28355b175d7SArnd Bergmann #define IRQ_PRCMU_HSI0 3 28455b175d7SArnd Bergmann #define IRQ_PRCMU_HSI1 4 28555b175d7SArnd Bergmann #define IRQ_PRCMU_CA_WAKE 5 28655b175d7SArnd Bergmann #define IRQ_PRCMU_USB 6 28755b175d7SArnd Bergmann #define IRQ_PRCMU_ABB 7 28855b175d7SArnd Bergmann #define IRQ_PRCMU_ABB_FIFO 8 28955b175d7SArnd Bergmann #define IRQ_PRCMU_ARM 9 29055b175d7SArnd Bergmann #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10 29155b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO0 11 29255b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO1 12 29355b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO2 13 29455b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO3 14 29555b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO4 15 29655b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO5 16 29755b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO6 17 29855b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO7 18 29955b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO8 19 30055b175d7SArnd Bergmann #define IRQ_PRCMU_CA_SLEEP 20 30155b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_LOW 21 30255b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_HIGH 22 30355b175d7SArnd Bergmann #define NUM_PRCMU_WAKEUPS 23 30455b175d7SArnd Bergmann 3053df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 3063df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 3073df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 3083df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 3093df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 3103df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 3113df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 3123df57bcfSMattias Nilsson IRQ_ENTRY(USB), 3133df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 3143df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 3153df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 3163df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 3173df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 3183df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 3193df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 3203df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 3213df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 3223df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 3233df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 3243df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 3253df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3263df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3273df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3283df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 329650c2a21SLinus Walleij }; 330650c2a21SLinus Walleij 3313df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3323df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3333df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3343df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3353df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3363df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3373df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3383df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3393df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3403df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3413df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3423df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3433df57bcfSMattias Nilsson }; 3443df57bcfSMattias Nilsson 3453df57bcfSMattias Nilsson /* 3463df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3473df57bcfSMattias Nilsson * @lock: The transaction lock. 3483df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3493df57bcfSMattias Nilsson * the request data. 3503df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3513df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3523df57bcfSMattias Nilsson */ 3533df57bcfSMattias Nilsson static struct { 3543df57bcfSMattias Nilsson spinlock_t lock; 3553df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3563df57bcfSMattias Nilsson struct work_struct mask_work; 3573df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3583df57bcfSMattias Nilsson struct completion ac_wake_work; 3593df57bcfSMattias Nilsson struct { 3603df57bcfSMattias Nilsson u32 dbb_irqs; 3613df57bcfSMattias Nilsson u32 dbb_wakeups; 3623df57bcfSMattias Nilsson u32 abb_events; 3633df57bcfSMattias Nilsson } req; 3643df57bcfSMattias Nilsson } mb0_transfer; 3653df57bcfSMattias Nilsson 3663df57bcfSMattias Nilsson /* 3673df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3683df57bcfSMattias Nilsson * @lock: The transaction lock. 3693df57bcfSMattias Nilsson * @work: The transaction completion structure. 3704d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP. 3713df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3723df57bcfSMattias Nilsson */ 373650c2a21SLinus Walleij static struct { 374650c2a21SLinus Walleij struct mutex lock; 375650c2a21SLinus Walleij struct completion work; 3764d64d2e3SMattias Nilsson u8 ape_opp; 377650c2a21SLinus Walleij struct { 3783df57bcfSMattias Nilsson u8 header; 379650c2a21SLinus Walleij u8 arm_opp; 380650c2a21SLinus Walleij u8 ape_opp; 3813df57bcfSMattias Nilsson u8 ape_voltage_status; 382650c2a21SLinus Walleij } ack; 383650c2a21SLinus Walleij } mb1_transfer; 384650c2a21SLinus Walleij 3853df57bcfSMattias Nilsson /* 3863df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3873df57bcfSMattias Nilsson * @lock: The transaction lock. 3883df57bcfSMattias Nilsson * @work: The transaction completion structure. 3893df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3903df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3913df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3923df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3933df57bcfSMattias Nilsson */ 394650c2a21SLinus Walleij static struct { 395650c2a21SLinus Walleij struct mutex lock; 396650c2a21SLinus Walleij struct completion work; 3973df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 3983df57bcfSMattias Nilsson bool auto_pm_enabled; 3993df57bcfSMattias Nilsson struct { 4003df57bcfSMattias Nilsson u8 status; 4013df57bcfSMattias Nilsson } ack; 4023df57bcfSMattias Nilsson } mb2_transfer; 4033df57bcfSMattias Nilsson 4043df57bcfSMattias Nilsson /* 4053df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 4063df57bcfSMattias Nilsson * @lock: The request lock. 4073df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 4083df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 4093df57bcfSMattias Nilsson */ 4103df57bcfSMattias Nilsson static struct { 4113df57bcfSMattias Nilsson spinlock_t lock; 4123df57bcfSMattias Nilsson struct mutex sysclk_lock; 4133df57bcfSMattias Nilsson struct completion sysclk_work; 4143df57bcfSMattias Nilsson } mb3_transfer; 4153df57bcfSMattias Nilsson 4163df57bcfSMattias Nilsson /* 4173df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 4183df57bcfSMattias Nilsson * @lock: The transaction lock. 4193df57bcfSMattias Nilsson * @work: The transaction completion structure. 4203df57bcfSMattias Nilsson */ 4213df57bcfSMattias Nilsson static struct { 4223df57bcfSMattias Nilsson struct mutex lock; 4233df57bcfSMattias Nilsson struct completion work; 4243df57bcfSMattias Nilsson } mb4_transfer; 4253df57bcfSMattias Nilsson 4263df57bcfSMattias Nilsson /* 4273df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4283df57bcfSMattias Nilsson * @lock: The transaction lock. 4293df57bcfSMattias Nilsson * @work: The transaction completion structure. 4303df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4313df57bcfSMattias Nilsson */ 4323df57bcfSMattias Nilsson static struct { 4333df57bcfSMattias Nilsson struct mutex lock; 4343df57bcfSMattias Nilsson struct completion work; 435650c2a21SLinus Walleij struct { 436650c2a21SLinus Walleij u8 status; 437650c2a21SLinus Walleij u8 value; 438650c2a21SLinus Walleij } ack; 439650c2a21SLinus Walleij } mb5_transfer; 440650c2a21SLinus Walleij 4413df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4423df57bcfSMattias Nilsson 4433df57bcfSMattias Nilsson /* Spinlocks */ 444b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock); 4453df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4463df57bcfSMattias Nilsson 4473df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4483df57bcfSMattias Nilsson static __iomem void *tcdm_base; 449b047d981SLinus Walleij static __iomem void *prcmu_base; 4503df57bcfSMattias Nilsson 4513df57bcfSMattias Nilsson struct clk_mgt { 452b047d981SLinus Walleij u32 offset; 4533df57bcfSMattias Nilsson u32 pllsw; 4546b6fae2bSMattias Nilsson int branch; 4556b6fae2bSMattias Nilsson bool clk38div; 4566b6fae2bSMattias Nilsson }; 4576b6fae2bSMattias Nilsson 4586b6fae2bSMattias Nilsson enum { 4596b6fae2bSMattias Nilsson PLL_RAW, 4606b6fae2bSMattias Nilsson PLL_FIX, 4616b6fae2bSMattias Nilsson PLL_DIV 4623df57bcfSMattias Nilsson }; 4633df57bcfSMattias Nilsson 4643df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4653df57bcfSMattias Nilsson 4666b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 4676b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 4683df57bcfSMattias Nilsson struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4696b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 4706b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 4736b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 4746b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 4756b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 4766b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 4776b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 4786b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 4796b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 4806b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 4816b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 4826b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 4836b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 4846b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 4856b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 4866b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 4876b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 4886b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 4896b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 4906b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 4916b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 4926b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 4936b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 4946b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 4956b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 4966b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 4976b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 4986b6fae2bSMattias Nilsson }; 4996b6fae2bSMattias Nilsson 5006b6fae2bSMattias Nilsson struct dsiclk { 5016b6fae2bSMattias Nilsson u32 divsel_mask; 5026b6fae2bSMattias Nilsson u32 divsel_shift; 5036b6fae2bSMattias Nilsson u32 divsel; 5046b6fae2bSMattias Nilsson }; 5056b6fae2bSMattias Nilsson 5066b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = { 5076b6fae2bSMattias Nilsson { 5086b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 5096b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 5106b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 5116b6fae2bSMattias Nilsson }, 5126b6fae2bSMattias Nilsson { 5136b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 5146b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 5156b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 5166b6fae2bSMattias Nilsson } 5176b6fae2bSMattias Nilsson }; 5186b6fae2bSMattias Nilsson 5196b6fae2bSMattias Nilsson struct dsiescclk { 5206b6fae2bSMattias Nilsson u32 en; 5216b6fae2bSMattias Nilsson u32 div_mask; 5226b6fae2bSMattias Nilsson u32 div_shift; 5236b6fae2bSMattias Nilsson }; 5246b6fae2bSMattias Nilsson 5256b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = { 5266b6fae2bSMattias Nilsson { 5276b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 5286b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 5296b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 5306b6fae2bSMattias Nilsson }, 5316b6fae2bSMattias Nilsson { 5326b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 5336b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 5346b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 5356b6fae2bSMattias Nilsson }, 5366b6fae2bSMattias Nilsson { 5376b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 5386b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 5396b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 5406b6fae2bSMattias Nilsson } 5413df57bcfSMattias Nilsson }; 5423df57bcfSMattias Nilsson 54320aee5b6SMichel Jaouen 5443df57bcfSMattias Nilsson /* 5453df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 5463df57bcfSMattias Nilsson */ 5473df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 5483df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 5493df57bcfSMattias Nilsson 5503df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 5513df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 5523df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5533df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5543df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5553df57bcfSMattias Nilsson 5563df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5573df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5583df57bcfSMattias Nilsson 5593df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5603df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5613df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5623df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5633df57bcfSMattias Nilsson 5643df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5653df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5663df57bcfSMattias Nilsson 5673df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5683df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5693df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5703df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5713df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5723df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5733df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5743df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5753df57bcfSMattias Nilsson 5763df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5773df57bcfSMattias Nilsson 57873180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5793df57bcfSMattias Nilsson { 5803df57bcfSMattias Nilsson int i; 5813df57bcfSMattias Nilsson 5823df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 583c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5843df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 585c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5863df57bcfSMattias Nilsson 5873df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 588c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 589c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5903df57bcfSMattias Nilsson /* Enable Escape clocks */ 591c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5923df57bcfSMattias Nilsson 5933df57bcfSMattias Nilsson /* Start DSI PLL */ 594c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5953df57bcfSMattias Nilsson /* Reset DSI PLL */ 596c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 5973df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 598c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 5993df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 6003df57bcfSMattias Nilsson break; 6013df57bcfSMattias Nilsson udelay(100); 6023df57bcfSMattias Nilsson } 6033df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 604c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 6053df57bcfSMattias Nilsson return 0; 6063df57bcfSMattias Nilsson } 6073df57bcfSMattias Nilsson 60873180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 6093df57bcfSMattias Nilsson { 6103df57bcfSMattias Nilsson /* Disable dsi pll */ 611c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 6123df57bcfSMattias Nilsson /* Disable escapeclock */ 613c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 6143df57bcfSMattias Nilsson return 0; 6153df57bcfSMattias Nilsson } 6163df57bcfSMattias Nilsson 61773180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 6183df57bcfSMattias Nilsson { 6193df57bcfSMattias Nilsson unsigned long flags; 6203df57bcfSMattias Nilsson 6213df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 6223df57bcfSMattias Nilsson 6233df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 624c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 6253df57bcfSMattias Nilsson cpu_relax(); 6263df57bcfSMattias Nilsson 627b047d981SLinus Walleij writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); 628b047d981SLinus Walleij writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); 629b047d981SLinus Walleij writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); 6303df57bcfSMattias Nilsson 6313df57bcfSMattias Nilsson /* Release the HW semaphore. */ 632c553b3caSMattias Nilsson writel(0, PRCM_SEM); 6333df57bcfSMattias Nilsson 6343df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 6353df57bcfSMattias Nilsson 6363df57bcfSMattias Nilsson return 0; 6373df57bcfSMattias Nilsson } 6383df57bcfSMattias Nilsson 639b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg) 6403df57bcfSMattias Nilsson { 641b047d981SLinus Walleij return readl(prcmu_base + reg); 6423df57bcfSMattias Nilsson } 6433df57bcfSMattias Nilsson 644b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value) 6453df57bcfSMattias Nilsson { 6463df57bcfSMattias Nilsson unsigned long flags; 6473df57bcfSMattias Nilsson 648b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 649b047d981SLinus Walleij writel(value, (prcmu_base + reg)); 650b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 651b4a6dbd5SMattias Nilsson } 652b4a6dbd5SMattias Nilsson 653b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 654b4a6dbd5SMattias Nilsson { 655b4a6dbd5SMattias Nilsson u32 val; 656b4a6dbd5SMattias Nilsson unsigned long flags; 657b4a6dbd5SMattias Nilsson 658b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 659b047d981SLinus Walleij val = readl(prcmu_base + reg); 660b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask)); 661b047d981SLinus Walleij writel(val, (prcmu_base + reg)); 662b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 6633df57bcfSMattias Nilsson } 6643df57bcfSMattias Nilsson 665b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void) 666b58d12feSMattias Nilsson { 667b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL; 668b58d12feSMattias Nilsson } 669b58d12feSMattias Nilsson 6703df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6713df57bcfSMattias Nilsson { 6723df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6733df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6743df57bcfSMattias Nilsson } 6753df57bcfSMattias Nilsson 6763df57bcfSMattias Nilsson /** 6773df57bcfSMattias Nilsson * prcmu_get_boot_status - PRCMU boot status checking 6783df57bcfSMattias Nilsson * Returns: the current PRCMU boot status 6793df57bcfSMattias Nilsson */ 6803df57bcfSMattias Nilsson int prcmu_get_boot_status(void) 6813df57bcfSMattias Nilsson { 6823df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_BOOT_STATUS); 6833df57bcfSMattias Nilsson } 6843df57bcfSMattias Nilsson 6853df57bcfSMattias Nilsson /** 6863df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6873df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6883df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6893df57bcfSMattias Nilsson * 6903df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6913df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6923df57bcfSMattias Nilsson */ 6933df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6943df57bcfSMattias Nilsson { 6953df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 6963df57bcfSMattias Nilsson return -EINVAL; 6973df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 6983df57bcfSMattias Nilsson return 0; 6993df57bcfSMattias Nilsson } 7003df57bcfSMattias Nilsson 7013df57bcfSMattias Nilsson /** 7023df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 7033df57bcfSMattias Nilsson * Returns: the power transition that has last happened 7043df57bcfSMattias Nilsson * 7053df57bcfSMattias Nilsson * This function can return the following transitions- 7063df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 7073df57bcfSMattias Nilsson */ 7083df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 7093df57bcfSMattias Nilsson { 7103df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 7113df57bcfSMattias Nilsson } 7123df57bcfSMattias Nilsson 7133df57bcfSMattias Nilsson /** 7143df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 7153df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 7163df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 7173df57bcfSMattias Nilsson */ 7183df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 7193df57bcfSMattias Nilsson { 7203df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 7213df57bcfSMattias Nilsson } 7223df57bcfSMattias Nilsson 7233df57bcfSMattias Nilsson /** 7243df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 7253df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 7263df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 7273df57bcfSMattias Nilsson * @div: The divider to be applied. 7283df57bcfSMattias Nilsson * 7293df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 7303df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 7313df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 7323df57bcfSMattias Nilsson */ 7333df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 7343df57bcfSMattias Nilsson { 7353df57bcfSMattias Nilsson static int requests[2]; 7363df57bcfSMattias Nilsson int r = 0; 7373df57bcfSMattias Nilsson unsigned long flags; 7383df57bcfSMattias Nilsson u32 val; 7393df57bcfSMattias Nilsson u32 bits; 7403df57bcfSMattias Nilsson u32 mask; 7413df57bcfSMattias Nilsson u32 div_mask; 7423df57bcfSMattias Nilsson 7433df57bcfSMattias Nilsson BUG_ON(clkout > 1); 7443df57bcfSMattias Nilsson BUG_ON(div > 63); 7453df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 7463df57bcfSMattias Nilsson 7473df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7483df57bcfSMattias Nilsson return -EINVAL; 7493df57bcfSMattias Nilsson 7503df57bcfSMattias Nilsson switch (clkout) { 7513df57bcfSMattias Nilsson case 0: 7523df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7533df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7543df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7553df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 7563df57bcfSMattias Nilsson break; 7573df57bcfSMattias Nilsson case 1: 7583df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7593df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7603df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7613df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7623df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7633df57bcfSMattias Nilsson break; 7643df57bcfSMattias Nilsson } 7653df57bcfSMattias Nilsson bits &= mask; 7663df57bcfSMattias Nilsson 7673df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7683df57bcfSMattias Nilsson 769c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7703df57bcfSMattias Nilsson if (val & div_mask) { 7713df57bcfSMattias Nilsson if (div) { 7723df57bcfSMattias Nilsson if ((val & mask) != bits) { 7733df57bcfSMattias Nilsson r = -EBUSY; 7743df57bcfSMattias Nilsson goto unlock_and_return; 7753df57bcfSMattias Nilsson } 7763df57bcfSMattias Nilsson } else { 7773df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7783df57bcfSMattias Nilsson r = -EINVAL; 7793df57bcfSMattias Nilsson goto unlock_and_return; 7803df57bcfSMattias Nilsson } 7813df57bcfSMattias Nilsson } 7823df57bcfSMattias Nilsson } 783c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7843df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7853df57bcfSMattias Nilsson 7863df57bcfSMattias Nilsson unlock_and_return: 7873df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7883df57bcfSMattias Nilsson 7893df57bcfSMattias Nilsson return r; 7903df57bcfSMattias Nilsson } 7913df57bcfSMattias Nilsson 79273180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7933df57bcfSMattias Nilsson { 7943df57bcfSMattias Nilsson unsigned long flags; 7953df57bcfSMattias Nilsson 7963df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 7973df57bcfSMattias Nilsson 7983df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 7993df57bcfSMattias Nilsson 800c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 8013df57bcfSMattias Nilsson cpu_relax(); 8023df57bcfSMattias Nilsson 8033df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 8043df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 8053df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 8063df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 8073df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 8083df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 809c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8103df57bcfSMattias Nilsson 8113df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8123df57bcfSMattias Nilsson 8133df57bcfSMattias Nilsson return 0; 8143df57bcfSMattias Nilsson } 8153df57bcfSMattias Nilsson 8164d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void) 8174d64d2e3SMattias Nilsson { 8184d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 8194d64d2e3SMattias Nilsson } 8204d64d2e3SMattias Nilsson 8213df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 8223df57bcfSMattias Nilsson static void config_wakeups(void) 8233df57bcfSMattias Nilsson { 8243df57bcfSMattias Nilsson const u8 header[2] = { 8253df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 8263df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 8273df57bcfSMattias Nilsson }; 8283df57bcfSMattias Nilsson static u32 last_dbb_events; 8293df57bcfSMattias Nilsson static u32 last_abb_events; 8303df57bcfSMattias Nilsson u32 dbb_events; 8313df57bcfSMattias Nilsson u32 abb_events; 8323df57bcfSMattias Nilsson unsigned int i; 8333df57bcfSMattias Nilsson 8343df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 8353df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 8363df57bcfSMattias Nilsson 8373df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 8383df57bcfSMattias Nilsson 8393df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 8403df57bcfSMattias Nilsson return; 8413df57bcfSMattias Nilsson 8423df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 843c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 8443df57bcfSMattias Nilsson cpu_relax(); 8453df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 8463df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 8473df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 848c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8493df57bcfSMattias Nilsson } 8503df57bcfSMattias Nilsson last_dbb_events = dbb_events; 8513df57bcfSMattias Nilsson last_abb_events = abb_events; 8523df57bcfSMattias Nilsson } 8533df57bcfSMattias Nilsson 85473180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 8553df57bcfSMattias Nilsson { 8563df57bcfSMattias Nilsson unsigned long flags; 8573df57bcfSMattias Nilsson u32 bits; 8583df57bcfSMattias Nilsson int i; 8593df57bcfSMattias Nilsson 8603df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 8613df57bcfSMattias Nilsson 8623df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 8633df57bcfSMattias Nilsson if (wakeups & BIT(i)) 8643df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 8653df57bcfSMattias Nilsson } 8663df57bcfSMattias Nilsson 8673df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8683df57bcfSMattias Nilsson 8693df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 8703df57bcfSMattias Nilsson config_wakeups(); 8713df57bcfSMattias Nilsson 8723df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8733df57bcfSMattias Nilsson } 8743df57bcfSMattias Nilsson 87573180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 8763df57bcfSMattias Nilsson { 8773df57bcfSMattias Nilsson unsigned long flags; 8783df57bcfSMattias Nilsson 8793df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8803df57bcfSMattias Nilsson 8813df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 8823df57bcfSMattias Nilsson config_wakeups(); 8833df57bcfSMattias Nilsson 8843df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8853df57bcfSMattias Nilsson } 8863df57bcfSMattias Nilsson 88773180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 8883df57bcfSMattias Nilsson { 8893df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 8903df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 8913df57bcfSMattias Nilsson else 8923df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 8933df57bcfSMattias Nilsson } 8943df57bcfSMattias Nilsson 8953df57bcfSMattias Nilsson /** 89673180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 8973df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 8983df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 8993df57bcfSMattias Nilsson * 9003df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 9013df57bcfSMattias Nilsson */ 90273180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 9033df57bcfSMattias Nilsson { 9043df57bcfSMattias Nilsson int r; 9053df57bcfSMattias Nilsson 9063df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 9073df57bcfSMattias Nilsson return -EINVAL; 9083df57bcfSMattias Nilsson 9093df57bcfSMattias Nilsson r = 0; 9103df57bcfSMattias Nilsson 9113df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 9123df57bcfSMattias Nilsson 913c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 9143df57bcfSMattias Nilsson cpu_relax(); 9153df57bcfSMattias Nilsson 9163df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 9173df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 9183df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 9193df57bcfSMattias Nilsson 920c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 9213df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 9223df57bcfSMattias Nilsson 9233df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 9243df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 9253df57bcfSMattias Nilsson r = -EIO; 9263df57bcfSMattias Nilsson 9273df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 9283df57bcfSMattias Nilsson 9293df57bcfSMattias Nilsson return r; 9303df57bcfSMattias Nilsson } 9313df57bcfSMattias Nilsson 9323df57bcfSMattias Nilsson /** 93373180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 9343df57bcfSMattias Nilsson * 9353df57bcfSMattias Nilsson * Returns: the current ARM OPP 9363df57bcfSMattias Nilsson */ 93773180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 9383df57bcfSMattias Nilsson { 9393df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 9403df57bcfSMattias Nilsson } 9413df57bcfSMattias Nilsson 9423df57bcfSMattias Nilsson /** 9430508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP 9443df57bcfSMattias Nilsson * 9453df57bcfSMattias Nilsson * Returns: the current DDR OPP 9463df57bcfSMattias Nilsson */ 9470508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void) 9483df57bcfSMattias Nilsson { 949c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 9503df57bcfSMattias Nilsson } 9513df57bcfSMattias Nilsson 9523df57bcfSMattias Nilsson /** 9530508901cSMattias Nilsson * db8500_set_ddr_opp - set the appropriate DDR OPP 9543df57bcfSMattias Nilsson * @opp: The new DDR operating point to which transition is to be made 9553df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9563df57bcfSMattias Nilsson * 9573df57bcfSMattias Nilsson * This function sets the operating point of the DDR. 9583df57bcfSMattias Nilsson */ 9597a4f2609SLinus Walleij static bool enable_set_ddr_opp; 9600508901cSMattias Nilsson int db8500_prcmu_set_ddr_opp(u8 opp) 9613df57bcfSMattias Nilsson { 9623df57bcfSMattias Nilsson if (opp < DDR_100_OPP || opp > DDR_25_OPP) 9633df57bcfSMattias Nilsson return -EINVAL; 9643df57bcfSMattias Nilsson /* Changing the DDR OPP can hang the hardware pre-v21 */ 9657a4f2609SLinus Walleij if (enable_set_ddr_opp) 966c553b3caSMattias Nilsson writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 9673df57bcfSMattias Nilsson 9683df57bcfSMattias Nilsson return 0; 9693df57bcfSMattias Nilsson } 9706b6fae2bSMattias Nilsson 9714d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 9724d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable) 9734d64d2e3SMattias Nilsson { 974b047d981SLinus Walleij u32 clock_reg[] = { 9754d64d2e3SMattias Nilsson PRCM_ACLK_MGT, 9764d64d2e3SMattias Nilsson PRCM_DMACLK_MGT 9774d64d2e3SMattias Nilsson }; 9784d64d2e3SMattias Nilsson unsigned long flags; 9794d64d2e3SMattias Nilsson unsigned int i; 9804d64d2e3SMattias Nilsson 9814d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 9824d64d2e3SMattias Nilsson 9834d64d2e3SMattias Nilsson /* Grab the HW semaphore. */ 9844d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 9854d64d2e3SMattias Nilsson cpu_relax(); 9864d64d2e3SMattias Nilsson 9874d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 9884d64d2e3SMattias Nilsson u32 val; 9894d64d2e3SMattias Nilsson u32 div; 9904d64d2e3SMattias Nilsson 991b047d981SLinus Walleij val = readl(prcmu_base + clock_reg[i]); 9924d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 9934d64d2e3SMattias Nilsson if (enable) { 9944d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) { 9954d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n", 9964d64d2e3SMattias Nilsson div, __func__); 9974d64d2e3SMattias Nilsson goto unlock_and_return; 9984d64d2e3SMattias Nilsson } 9994d64d2e3SMattias Nilsson div <<= 1; 10004d64d2e3SMattias Nilsson } else { 10014d64d2e3SMattias Nilsson if (div <= 2) 10024d64d2e3SMattias Nilsson goto unlock_and_return; 10034d64d2e3SMattias Nilsson div >>= 1; 10044d64d2e3SMattias Nilsson } 10054d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 10064d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 1007b047d981SLinus Walleij writel(val, prcmu_base + clock_reg[i]); 10084d64d2e3SMattias Nilsson } 10094d64d2e3SMattias Nilsson 10104d64d2e3SMattias Nilsson unlock_and_return: 10114d64d2e3SMattias Nilsson /* Release the HW semaphore. */ 10124d64d2e3SMattias Nilsson writel(0, PRCM_SEM); 10134d64d2e3SMattias Nilsson 10144d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 10154d64d2e3SMattias Nilsson } 10164d64d2e3SMattias Nilsson 10173df57bcfSMattias Nilsson /** 10180508901cSMattias Nilsson * db8500_set_ape_opp - set the appropriate APE OPP 10193df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 10203df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10213df57bcfSMattias Nilsson * 10223df57bcfSMattias Nilsson * This function sets the operating point of the APE. 10233df57bcfSMattias Nilsson */ 10240508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp) 10253df57bcfSMattias Nilsson { 10263df57bcfSMattias Nilsson int r = 0; 10273df57bcfSMattias Nilsson 10284d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp) 10294d64d2e3SMattias Nilsson return 0; 10304d64d2e3SMattias Nilsson 10313df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10323df57bcfSMattias Nilsson 10334d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 10344d64d2e3SMattias Nilsson request_even_slower_clocks(false); 10354d64d2e3SMattias Nilsson 10364d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 10374d64d2e3SMattias Nilsson goto skip_message; 10384d64d2e3SMattias Nilsson 1039c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10403df57bcfSMattias Nilsson cpu_relax(); 10413df57bcfSMattias Nilsson 10423df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10433df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 10444d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 10454d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 10463df57bcfSMattias Nilsson 1047c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10483df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10493df57bcfSMattias Nilsson 10503df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 10513df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 10523df57bcfSMattias Nilsson r = -EIO; 10533df57bcfSMattias Nilsson 10544d64d2e3SMattias Nilsson skip_message: 10554d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 10564d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 10574d64d2e3SMattias Nilsson request_even_slower_clocks(true); 10584d64d2e3SMattias Nilsson if (!r) 10594d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp; 10604d64d2e3SMattias Nilsson 10613df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10623df57bcfSMattias Nilsson 10633df57bcfSMattias Nilsson return r; 10643df57bcfSMattias Nilsson } 10653df57bcfSMattias Nilsson 10663df57bcfSMattias Nilsson /** 10670508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP 10683df57bcfSMattias Nilsson * 10693df57bcfSMattias Nilsson * Returns: the current APE OPP 10703df57bcfSMattias Nilsson */ 10710508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void) 10723df57bcfSMattias Nilsson { 10733df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 10743df57bcfSMattias Nilsson } 10753df57bcfSMattias Nilsson 10763df57bcfSMattias Nilsson /** 1077686f871bSUlf Hansson * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 10783df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 10793df57bcfSMattias Nilsson * 10803df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 10813df57bcfSMattias Nilsson */ 1082686f871bSUlf Hansson int db8500_prcmu_request_ape_opp_100_voltage(bool enable) 10833df57bcfSMattias Nilsson { 10843df57bcfSMattias Nilsson int r = 0; 10853df57bcfSMattias Nilsson u8 header; 10863df57bcfSMattias Nilsson static unsigned int requests; 10873df57bcfSMattias Nilsson 10883df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10893df57bcfSMattias Nilsson 10903df57bcfSMattias Nilsson if (enable) { 10913df57bcfSMattias Nilsson if (0 != requests++) 10923df57bcfSMattias Nilsson goto unlock_and_return; 10933df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 10943df57bcfSMattias Nilsson } else { 10953df57bcfSMattias Nilsson if (requests == 0) { 10963df57bcfSMattias Nilsson r = -EIO; 10973df57bcfSMattias Nilsson goto unlock_and_return; 10983df57bcfSMattias Nilsson } else if (1 != requests--) { 10993df57bcfSMattias Nilsson goto unlock_and_return; 11003df57bcfSMattias Nilsson } 11013df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 11023df57bcfSMattias Nilsson } 11033df57bcfSMattias Nilsson 1104c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11053df57bcfSMattias Nilsson cpu_relax(); 11063df57bcfSMattias Nilsson 11073df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11083df57bcfSMattias Nilsson 1109c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11103df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11113df57bcfSMattias Nilsson 11123df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 11133df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 11143df57bcfSMattias Nilsson r = -EIO; 11153df57bcfSMattias Nilsson 11163df57bcfSMattias Nilsson unlock_and_return: 11173df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11183df57bcfSMattias Nilsson 11193df57bcfSMattias Nilsson return r; 11203df57bcfSMattias Nilsson } 11213df57bcfSMattias Nilsson 11223df57bcfSMattias Nilsson /** 11233df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 11243df57bcfSMattias Nilsson * 11253df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 11263df57bcfSMattias Nilsson */ 11273df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 11283df57bcfSMattias Nilsson { 11293df57bcfSMattias Nilsson int r = 0; 11303df57bcfSMattias Nilsson 11313df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11323df57bcfSMattias Nilsson 1133c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11343df57bcfSMattias Nilsson cpu_relax(); 11353df57bcfSMattias Nilsson 11363df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 11373df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11383df57bcfSMattias Nilsson 1139c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11403df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11413df57bcfSMattias Nilsson 11423df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 11433df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 11443df57bcfSMattias Nilsson r = -EIO; 11453df57bcfSMattias Nilsson 11463df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11473df57bcfSMattias Nilsson 11483df57bcfSMattias Nilsson return r; 11493df57bcfSMattias Nilsson } 11503df57bcfSMattias Nilsson 11510837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 11520837bb72SMattias Nilsson { 11530837bb72SMattias Nilsson int r = 0; 11540837bb72SMattias Nilsson 11556b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0) 11566b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 11576b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 11580837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 11590837bb72SMattias Nilsson else 11600837bb72SMattias Nilsson return -EINVAL; 11610837bb72SMattias Nilsson 11620837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 11630837bb72SMattias Nilsson 11640837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11650837bb72SMattias Nilsson cpu_relax(); 11660837bb72SMattias Nilsson 11670837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11680837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 11690837bb72SMattias Nilsson 11700837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11710837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 11720837bb72SMattias Nilsson 11730837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 11740837bb72SMattias Nilsson r = -EIO; 11750837bb72SMattias Nilsson 11760837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11770837bb72SMattias Nilsson 11780837bb72SMattias Nilsson return r; 11790837bb72SMattias Nilsson } 11800837bb72SMattias Nilsson 11813df57bcfSMattias Nilsson /** 118273180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 11833df57bcfSMattias Nilsson * @epod_id: The EPOD to set 11843df57bcfSMattias Nilsson * @epod_state: The new EPOD state 11853df57bcfSMattias Nilsson * 11863df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 11873df57bcfSMattias Nilsson * from interrupt context. 11883df57bcfSMattias Nilsson */ 118973180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 11903df57bcfSMattias Nilsson { 11913df57bcfSMattias Nilsson int r = 0; 11923df57bcfSMattias Nilsson bool ram_retention = false; 11933df57bcfSMattias Nilsson int i; 11943df57bcfSMattias Nilsson 11953df57bcfSMattias Nilsson /* check argument */ 11963df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 11973df57bcfSMattias Nilsson 11983df57bcfSMattias Nilsson /* set flag if retention is possible */ 11993df57bcfSMattias Nilsson switch (epod_id) { 12003df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 12013df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 12023df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 12033df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 12043df57bcfSMattias Nilsson ram_retention = true; 12053df57bcfSMattias Nilsson break; 12063df57bcfSMattias Nilsson } 12073df57bcfSMattias Nilsson 12083df57bcfSMattias Nilsson /* check argument */ 12093df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 12103df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 12113df57bcfSMattias Nilsson 12123df57bcfSMattias Nilsson /* get lock */ 12133df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 12143df57bcfSMattias Nilsson 12153df57bcfSMattias Nilsson /* wait for mailbox */ 1216c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 12173df57bcfSMattias Nilsson cpu_relax(); 12183df57bcfSMattias Nilsson 12193df57bcfSMattias Nilsson /* fill in mailbox */ 12203df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 12213df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 12223df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 12233df57bcfSMattias Nilsson 12243df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 12253df57bcfSMattias Nilsson 1226c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 12273df57bcfSMattias Nilsson 12283df57bcfSMattias Nilsson /* 12293df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 12303df57bcfSMattias Nilsson * and we cannot recover if there is an error. 12313df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 12323df57bcfSMattias Nilsson */ 12333df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 12343df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 12353df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 12363df57bcfSMattias Nilsson __func__); 12373df57bcfSMattias Nilsson r = -EIO; 12383df57bcfSMattias Nilsson goto unlock_and_return; 12393df57bcfSMattias Nilsson } 12403df57bcfSMattias Nilsson 12413df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 12423df57bcfSMattias Nilsson r = -EIO; 12433df57bcfSMattias Nilsson 12443df57bcfSMattias Nilsson unlock_and_return: 12453df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 12463df57bcfSMattias Nilsson return r; 12473df57bcfSMattias Nilsson } 12483df57bcfSMattias Nilsson 12493df57bcfSMattias Nilsson /** 12503df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 12513df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 12523df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 12533df57bcfSMattias Nilsson */ 12543df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 12553df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 12563df57bcfSMattias Nilsson { 12573df57bcfSMattias Nilsson u32 sleep_cfg; 12583df57bcfSMattias Nilsson u32 idle_cfg; 12593df57bcfSMattias Nilsson unsigned long flags; 12603df57bcfSMattias Nilsson 12613df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 12623df57bcfSMattias Nilsson 12633df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 12643df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 12653df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 12663df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 12673df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 12683df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 12693df57bcfSMattias Nilsson 12703df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 12713df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 12723df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 12733df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 12743df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 12753df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 12763df57bcfSMattias Nilsson 12773df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 12783df57bcfSMattias Nilsson 12793df57bcfSMattias Nilsson /* 12803df57bcfSMattias Nilsson * The autonomous power management configuration is done through 12813df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 12823df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 12833df57bcfSMattias Nilsson */ 12843df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 12853df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 12863df57bcfSMattias Nilsson 12873df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 12883df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12893df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12903df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12913df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 12923df57bcfSMattias Nilsson 12933df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 12943df57bcfSMattias Nilsson } 12953df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 12963df57bcfSMattias Nilsson 12973df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 12983df57bcfSMattias Nilsson { 12993df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 13003df57bcfSMattias Nilsson } 13013df57bcfSMattias Nilsson 13023df57bcfSMattias Nilsson static int request_sysclk(bool enable) 13033df57bcfSMattias Nilsson { 13043df57bcfSMattias Nilsson int r; 13053df57bcfSMattias Nilsson unsigned long flags; 13063df57bcfSMattias Nilsson 13073df57bcfSMattias Nilsson r = 0; 13083df57bcfSMattias Nilsson 13093df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 13103df57bcfSMattias Nilsson 13113df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 13123df57bcfSMattias Nilsson 1313c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 13143df57bcfSMattias Nilsson cpu_relax(); 13153df57bcfSMattias Nilsson 13163df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 13173df57bcfSMattias Nilsson 13183df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1319c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 13203df57bcfSMattias Nilsson 13213df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 13223df57bcfSMattias Nilsson 13233df57bcfSMattias Nilsson /* 13243df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 13253df57bcfSMattias Nilsson * SysClk, and it succeeds. 13263df57bcfSMattias Nilsson */ 13273df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 13283df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 13293df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 13303df57bcfSMattias Nilsson __func__); 13313df57bcfSMattias Nilsson r = -EIO; 13323df57bcfSMattias Nilsson } 13333df57bcfSMattias Nilsson 13343df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 13353df57bcfSMattias Nilsson 13363df57bcfSMattias Nilsson return r; 13373df57bcfSMattias Nilsson } 13383df57bcfSMattias Nilsson 13393df57bcfSMattias Nilsson static int request_timclk(bool enable) 13403df57bcfSMattias Nilsson { 13413df57bcfSMattias Nilsson u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 13423df57bcfSMattias Nilsson 13433df57bcfSMattias Nilsson if (!enable) 13443df57bcfSMattias Nilsson val |= PRCM_TCR_STOP_TIMERS; 1345c553b3caSMattias Nilsson writel(val, PRCM_TCR); 13463df57bcfSMattias Nilsson 13473df57bcfSMattias Nilsson return 0; 13483df57bcfSMattias Nilsson } 13493df57bcfSMattias Nilsson 13506b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable) 13513df57bcfSMattias Nilsson { 13523df57bcfSMattias Nilsson u32 val; 13533df57bcfSMattias Nilsson unsigned long flags; 13543df57bcfSMattias Nilsson 13553df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 13563df57bcfSMattias Nilsson 13573df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1358c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 13593df57bcfSMattias Nilsson cpu_relax(); 13603df57bcfSMattias Nilsson 1361b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 13623df57bcfSMattias Nilsson if (enable) { 13633df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 13643df57bcfSMattias Nilsson } else { 13653df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 13663df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 13673df57bcfSMattias Nilsson } 1368b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset); 13693df57bcfSMattias Nilsson 13703df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1371c553b3caSMattias Nilsson writel(0, PRCM_SEM); 13723df57bcfSMattias Nilsson 13733df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 13743df57bcfSMattias Nilsson 13753df57bcfSMattias Nilsson return 0; 13763df57bcfSMattias Nilsson } 13773df57bcfSMattias Nilsson 13780837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 13790837bb72SMattias Nilsson { 13800837bb72SMattias Nilsson u32 val; 13810837bb72SMattias Nilsson int ret; 13820837bb72SMattias Nilsson 13830837bb72SMattias Nilsson if (enable) { 13840837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13850837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13860837bb72SMattias Nilsson } 13870837bb72SMattias Nilsson 13886b6fae2bSMattias Nilsson ret = request_clock(clock, enable); 13890837bb72SMattias Nilsson 13900837bb72SMattias Nilsson if (!ret && !enable) { 13910837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13920837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13930837bb72SMattias Nilsson } 13940837bb72SMattias Nilsson 13950837bb72SMattias Nilsson return ret; 13960837bb72SMattias Nilsson } 13970837bb72SMattias Nilsson 13986b6fae2bSMattias Nilsson static inline bool plldsi_locked(void) 13996b6fae2bSMattias Nilsson { 14006b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) & 14016b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 14026b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 14036b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 14046b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 14056b6fae2bSMattias Nilsson } 14066b6fae2bSMattias Nilsson 14076b6fae2bSMattias Nilsson static int request_plldsi(bool enable) 14086b6fae2bSMattias Nilsson { 14096b6fae2bSMattias Nilsson int r = 0; 14106b6fae2bSMattias Nilsson u32 val; 14116b6fae2bSMattias Nilsson 14126b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 14136b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 14146b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 14156b6fae2bSMattias Nilsson 14166b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE); 14176b6fae2bSMattias Nilsson if (enable) 14186b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14196b6fae2bSMattias Nilsson else 14206b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14216b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 14226b6fae2bSMattias Nilsson 14236b6fae2bSMattias Nilsson if (enable) { 14246b6fae2bSMattias Nilsson unsigned int i; 14256b6fae2bSMattias Nilsson bool locked = plldsi_locked(); 14266b6fae2bSMattias Nilsson 14276b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) { 14286b6fae2bSMattias Nilsson udelay(100); 14296b6fae2bSMattias Nilsson locked = plldsi_locked(); 14306b6fae2bSMattias Nilsson } 14316b6fae2bSMattias Nilsson if (locked) { 14326b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, 14336b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET); 14346b6fae2bSMattias Nilsson } else { 14356b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 14366b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 14376b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET); 14386b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14396b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 14406b6fae2bSMattias Nilsson r = -EAGAIN; 14416b6fae2bSMattias Nilsson } 14426b6fae2bSMattias Nilsson } else { 14436b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 14446b6fae2bSMattias Nilsson } 14456b6fae2bSMattias Nilsson return r; 14466b6fae2bSMattias Nilsson } 14476b6fae2bSMattias Nilsson 14486b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable) 14496b6fae2bSMattias Nilsson { 14506b6fae2bSMattias Nilsson u32 val; 14516b6fae2bSMattias Nilsson 14526b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 14536b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 14546b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 14556b6fae2bSMattias Nilsson dsiclk[n].divsel_shift); 14566b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 14576b6fae2bSMattias Nilsson return 0; 14586b6fae2bSMattias Nilsson } 14596b6fae2bSMattias Nilsson 14606b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable) 14616b6fae2bSMattias Nilsson { 14626b6fae2bSMattias Nilsson u32 val; 14636b6fae2bSMattias Nilsson 14646b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 14656b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 14666b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 14676b6fae2bSMattias Nilsson return 0; 14686b6fae2bSMattias Nilsson } 14696b6fae2bSMattias Nilsson 14703df57bcfSMattias Nilsson /** 147173180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 14723df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 14733df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 14743df57bcfSMattias Nilsson * 14753df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 14763df57bcfSMattias Nilsson * Do not use it from any other place! 14773df57bcfSMattias Nilsson */ 147873180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 14793df57bcfSMattias Nilsson { 14806b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK) 14810837bb72SMattias Nilsson return request_sga_clock(clock, enable); 14826b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS) 14836b6fae2bSMattias Nilsson return request_clock(clock, enable); 14846b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 14853df57bcfSMattias Nilsson return request_timclk(enable); 14866b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 14876b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 14886b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 14896b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 14906b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 14916b6fae2bSMattias Nilsson return request_plldsi(enable); 14926b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 14933df57bcfSMattias Nilsson return request_sysclk(enable); 14946b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 14950837bb72SMattias Nilsson return request_pll(clock, enable); 14966b6fae2bSMattias Nilsson else 14976b6fae2bSMattias Nilsson return -EINVAL; 14986b6fae2bSMattias Nilsson } 14996b6fae2bSMattias Nilsson 15006b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 15016b6fae2bSMattias Nilsson int branch) 15026b6fae2bSMattias Nilsson { 15036b6fae2bSMattias Nilsson u64 rate; 15046b6fae2bSMattias Nilsson u32 val; 15056b6fae2bSMattias Nilsson u32 d; 15066b6fae2bSMattias Nilsson u32 div = 1; 15076b6fae2bSMattias Nilsson 15086b6fae2bSMattias Nilsson val = readl(reg); 15096b6fae2bSMattias Nilsson 15106b6fae2bSMattias Nilsson rate = src_rate; 15116b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 15126b6fae2bSMattias Nilsson 15136b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 15146b6fae2bSMattias Nilsson if (d > 1) 15156b6fae2bSMattias Nilsson div *= d; 15166b6fae2bSMattias Nilsson 15176b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 15186b6fae2bSMattias Nilsson if (d > 1) 15196b6fae2bSMattias Nilsson div *= d; 15206b6fae2bSMattias Nilsson 15216b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2) 15226b6fae2bSMattias Nilsson div *= 2; 15236b6fae2bSMattias Nilsson 15246b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 15256b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) && 15266b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) || 152720aee5b6SMichel Jaouen (reg == PRCM_PLLARM_FREQ) || 15286b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ)))) 15296b6fae2bSMattias Nilsson div *= 2; 15306b6fae2bSMattias Nilsson 15316b6fae2bSMattias Nilsson (void)do_div(rate, div); 15326b6fae2bSMattias Nilsson 15336b6fae2bSMattias Nilsson return (unsigned long)rate; 15346b6fae2bSMattias Nilsson } 15356b6fae2bSMattias Nilsson 15366b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000 15376b6fae2bSMattias Nilsson 15386b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock) 15396b6fae2bSMattias Nilsson { 15406b6fae2bSMattias Nilsson u32 val; 15416b6fae2bSMattias Nilsson u32 pllsw; 15426b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE; 15436b6fae2bSMattias Nilsson 1544b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 15456b6fae2bSMattias Nilsson 15466b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 15476b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 15486b6fae2bSMattias Nilsson rate /= 2; 15496b6fae2bSMattias Nilsson return rate; 15506b6fae2bSMattias Nilsson } 15516b6fae2bSMattias Nilsson 15526b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw; 15536b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 15546b6fae2bSMattias Nilsson 15556b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 15566b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 15576b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 15586b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 15596b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 15606b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 15616b6fae2bSMattias Nilsson else 15626b6fae2bSMattias Nilsson return 0; 15636b6fae2bSMattias Nilsson 15646b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) && 15656b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 15666b6fae2bSMattias Nilsson u64 r = (rate * 10); 15676b6fae2bSMattias Nilsson 15686b6fae2bSMattias Nilsson (void)do_div(r, 25); 15696b6fae2bSMattias Nilsson return (unsigned long)r; 15706b6fae2bSMattias Nilsson } 15716b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 15726b6fae2bSMattias Nilsson if (val) 15736b6fae2bSMattias Nilsson return rate / val; 15746b6fae2bSMattias Nilsson else 15756b6fae2bSMattias Nilsson return 0; 15766b6fae2bSMattias Nilsson } 157720aee5b6SMichel Jaouen 1578b2302c87SUlf Hansson static unsigned long armss_rate(void) 157920aee5b6SMichel Jaouen { 158020aee5b6SMichel Jaouen u32 r; 158120aee5b6SMichel Jaouen unsigned long rate; 158220aee5b6SMichel Jaouen 158320aee5b6SMichel Jaouen r = readl(PRCM_ARM_CHGCLKREQ); 158420aee5b6SMichel Jaouen 158520aee5b6SMichel Jaouen if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { 158620aee5b6SMichel Jaouen /* External ARMCLKFIX clock */ 158720aee5b6SMichel Jaouen 158820aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); 158920aee5b6SMichel Jaouen 159020aee5b6SMichel Jaouen /* Check PRCM_ARM_CHGCLKREQ divider */ 159120aee5b6SMichel Jaouen if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) 159220aee5b6SMichel Jaouen rate /= 2; 159320aee5b6SMichel Jaouen 159420aee5b6SMichel Jaouen /* Check PRCM_ARMCLKFIX_MGT divider */ 159520aee5b6SMichel Jaouen r = readl(PRCM_ARMCLKFIX_MGT); 159620aee5b6SMichel Jaouen r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 159720aee5b6SMichel Jaouen rate /= r; 159820aee5b6SMichel Jaouen 159920aee5b6SMichel Jaouen } else {/* ARM PLL */ 160020aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); 160120aee5b6SMichel Jaouen } 160220aee5b6SMichel Jaouen 1603b2302c87SUlf Hansson return rate; 160420aee5b6SMichel Jaouen } 16056b6fae2bSMattias Nilsson 16066b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n) 16076b6fae2bSMattias Nilsson { 16086b6fae2bSMattias Nilsson u32 divsel; 16096b6fae2bSMattias Nilsson u32 div = 1; 16106b6fae2bSMattias Nilsson 16116b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL); 16126b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 16136b6fae2bSMattias Nilsson 16146b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 16156b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel; 16166b6fae2bSMattias Nilsson 16176b6fae2bSMattias Nilsson switch (divsel) { 16186b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4: 16196b6fae2bSMattias Nilsson div *= 2; 16206b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2: 16216b6fae2bSMattias Nilsson div *= 2; 16226b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI: 16236b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 16246b6fae2bSMattias Nilsson PLL_RAW) / div; 1625e62ccf3aSLinus Walleij default: 16266b6fae2bSMattias Nilsson return 0; 16276b6fae2bSMattias Nilsson } 16286b6fae2bSMattias Nilsson } 16296b6fae2bSMattias Nilsson 16306b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n) 16316b6fae2bSMattias Nilsson { 16326b6fae2bSMattias Nilsson u32 div; 16336b6fae2bSMattias Nilsson 16346b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV); 16356b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 16366b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 16376b6fae2bSMattias Nilsson } 16386b6fae2bSMattias Nilsson 16396b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock) 16406b6fae2bSMattias Nilsson { 16416b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 16426b6fae2bSMattias Nilsson return clock_rate(clock); 16436b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 16446b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE / 16; 16456b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 16466b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 16476b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0) 16486b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 16496b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 16506b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 165120aee5b6SMichel Jaouen else if (clock == PRCMU_ARMSS) 165220aee5b6SMichel Jaouen return armss_rate(); 16536b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR) 16546b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 16556b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 16566b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 16576b6fae2bSMattias Nilsson PLL_RAW); 16586b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 16596b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK); 16606b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 16616b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 16626b6fae2bSMattias Nilsson else 16636b6fae2bSMattias Nilsson return 0; 16646b6fae2bSMattias Nilsson } 16656b6fae2bSMattias Nilsson 16666b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 16676b6fae2bSMattias Nilsson { 16686b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 16696b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 16706b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 16716b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 16726b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 16736b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 16746b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 16756b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 16766b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 16776b6fae2bSMattias Nilsson else 16786b6fae2bSMattias Nilsson return 0; 16796b6fae2bSMattias Nilsson } 16806b6fae2bSMattias Nilsson 16816b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate) 16826b6fae2bSMattias Nilsson { 16836b6fae2bSMattias Nilsson u32 div; 16846b6fae2bSMattias Nilsson 16856b6fae2bSMattias Nilsson div = (src_rate / rate); 16866b6fae2bSMattias Nilsson if (div == 0) 16876b6fae2bSMattias Nilsson return 1; 16886b6fae2bSMattias Nilsson if (rate < (src_rate / div)) 16896b6fae2bSMattias Nilsson div++; 16906b6fae2bSMattias Nilsson return div; 16916b6fae2bSMattias Nilsson } 16926b6fae2bSMattias Nilsson 16936b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate) 16946b6fae2bSMattias Nilsson { 16956b6fae2bSMattias Nilsson u32 val; 16966b6fae2bSMattias Nilsson u32 div; 16976b6fae2bSMattias Nilsson unsigned long src_rate; 16986b6fae2bSMattias Nilsson long rounded_rate; 16996b6fae2bSMattias Nilsson 1700b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 17016b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 17026b6fae2bSMattias Nilsson clk_mgt[clock].branch); 17036b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 17046b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 17056b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 17066b6fae2bSMattias Nilsson if (div > 2) 17076b6fae2bSMattias Nilsson div = 2; 17086b6fae2bSMattias Nilsson } else { 17096b6fae2bSMattias Nilsson div = 1; 17106b6fae2bSMattias Nilsson } 17116b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 17126b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 17136b6fae2bSMattias Nilsson 17146b6fae2bSMattias Nilsson (void)do_div(r, 25); 17156b6fae2bSMattias Nilsson if (r <= rate) 17166b6fae2bSMattias Nilsson return (unsigned long)r; 17176b6fae2bSMattias Nilsson } 17186b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31)); 17196b6fae2bSMattias Nilsson 17206b6fae2bSMattias Nilsson return rounded_rate; 17216b6fae2bSMattias Nilsson } 17226b6fae2bSMattias Nilsson 1723b2302c87SUlf Hansson /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ 1724b2302c87SUlf Hansson static struct cpufreq_frequency_table db8500_cpufreq_table[] = { 1725b2302c87SUlf Hansson { .frequency = 200000, .index = ARM_EXTCLK,}, 1726b2302c87SUlf Hansson { .frequency = 400000, .index = ARM_50_OPP,}, 1727b2302c87SUlf Hansson { .frequency = 800000, .index = ARM_100_OPP,}, 1728b2302c87SUlf Hansson { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ 1729b2302c87SUlf Hansson { .frequency = CPUFREQ_TABLE_END,}, 1730b2302c87SUlf Hansson }; 1731b2302c87SUlf Hansson 1732b2302c87SUlf Hansson static long round_armss_rate(unsigned long rate) 1733b2302c87SUlf Hansson { 1734b2302c87SUlf Hansson long freq = 0; 1735b2302c87SUlf Hansson int i = 0; 1736b2302c87SUlf Hansson 1737b2302c87SUlf Hansson /* cpufreq table frequencies is in KHz. */ 1738b2302c87SUlf Hansson rate = rate / 1000; 1739b2302c87SUlf Hansson 1740b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1741b2302c87SUlf Hansson while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { 1742b2302c87SUlf Hansson freq = db8500_cpufreq_table[i].frequency; 1743b2302c87SUlf Hansson if (freq == rate) 1744b2302c87SUlf Hansson break; 1745b2302c87SUlf Hansson i++; 1746b2302c87SUlf Hansson } 1747b2302c87SUlf Hansson 1748b2302c87SUlf Hansson /* Return the last valid value, even if a match was not found. */ 1749b2302c87SUlf Hansson return freq * 1000; 1750b2302c87SUlf Hansson } 1751b2302c87SUlf Hansson 17526b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL 17536b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL 17546b6fae2bSMattias Nilsson 17556b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate) 17566b6fae2bSMattias Nilsson { 17576b6fae2bSMattias Nilsson long rounded_rate = 0; 17586b6fae2bSMattias Nilsson unsigned long src_rate; 17596b6fae2bSMattias Nilsson unsigned long rem; 17606b6fae2bSMattias Nilsson u32 r; 17616b6fae2bSMattias Nilsson 17626b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 17636b6fae2bSMattias Nilsson rem = rate; 17646b6fae2bSMattias Nilsson 17656b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 17666b6fae2bSMattias Nilsson u64 d; 17676b6fae2bSMattias Nilsson 17686b6fae2bSMattias Nilsson d = (r * rate); 17696b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 17706b6fae2bSMattias Nilsson if (d < 6) 17716b6fae2bSMattias Nilsson d = 6; 17726b6fae2bSMattias Nilsson else if (d > 255) 17736b6fae2bSMattias Nilsson d = 255; 17746b6fae2bSMattias Nilsson d *= src_rate; 17756b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 17766b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d))) 17776b6fae2bSMattias Nilsson continue; 17786b6fae2bSMattias Nilsson (void)do_div(d, r); 17796b6fae2bSMattias Nilsson if (rate < d) { 17806b6fae2bSMattias Nilsson if (rounded_rate == 0) 17816b6fae2bSMattias Nilsson rounded_rate = (long)d; 1782e62ccf3aSLinus Walleij break; 1783e62ccf3aSLinus Walleij } 17846b6fae2bSMattias Nilsson if ((rate - d) < rem) { 17856b6fae2bSMattias Nilsson rem = (rate - d); 17866b6fae2bSMattias Nilsson rounded_rate = (long)d; 17876b6fae2bSMattias Nilsson } 17886b6fae2bSMattias Nilsson } 17896b6fae2bSMattias Nilsson return rounded_rate; 17906b6fae2bSMattias Nilsson } 17916b6fae2bSMattias Nilsson 17926b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate) 17936b6fae2bSMattias Nilsson { 17946b6fae2bSMattias Nilsson u32 div; 17956b6fae2bSMattias Nilsson unsigned long src_rate; 17966b6fae2bSMattias Nilsson long rounded_rate; 17976b6fae2bSMattias Nilsson 17986b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 17996b6fae2bSMattias Nilsson PLL_RAW); 18006b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18016b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 18026b6fae2bSMattias Nilsson 18036b6fae2bSMattias Nilsson return rounded_rate; 18046b6fae2bSMattias Nilsson } 18056b6fae2bSMattias Nilsson 18066b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate) 18076b6fae2bSMattias Nilsson { 18086b6fae2bSMattias Nilsson u32 div; 18096b6fae2bSMattias Nilsson unsigned long src_rate; 18106b6fae2bSMattias Nilsson long rounded_rate; 18116b6fae2bSMattias Nilsson 18126b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK); 18136b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18146b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255)); 18156b6fae2bSMattias Nilsson 18166b6fae2bSMattias Nilsson return rounded_rate; 18176b6fae2bSMattias Nilsson } 18186b6fae2bSMattias Nilsson 18196b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate) 18206b6fae2bSMattias Nilsson { 1821e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 18226b6fae2bSMattias Nilsson return round_clock_rate(clock, rate); 1823b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 1824b2302c87SUlf Hansson return round_armss_rate(rate); 18256b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 18266b6fae2bSMattias Nilsson return round_plldsi_rate(rate); 18276b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 18286b6fae2bSMattias Nilsson return round_dsiclk_rate(rate); 18296b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 18306b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate); 18316b6fae2bSMattias Nilsson else 18326b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock); 18336b6fae2bSMattias Nilsson } 18346b6fae2bSMattias Nilsson 18356b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate) 18366b6fae2bSMattias Nilsson { 18376b6fae2bSMattias Nilsson u32 val; 18386b6fae2bSMattias Nilsson u32 div; 18396b6fae2bSMattias Nilsson unsigned long src_rate; 18406b6fae2bSMattias Nilsson unsigned long flags; 18416b6fae2bSMattias Nilsson 18426b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 18436b6fae2bSMattias Nilsson 18446b6fae2bSMattias Nilsson /* Grab the HW semaphore. */ 18456b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 18466b6fae2bSMattias Nilsson cpu_relax(); 18476b6fae2bSMattias Nilsson 1848b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 18496b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 18506b6fae2bSMattias Nilsson clk_mgt[clock].branch); 18516b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18526b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 18536b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 18546b6fae2bSMattias Nilsson if (div > 1) 18556b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV; 18566b6fae2bSMattias Nilsson else 18576b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV; 18586b6fae2bSMattias Nilsson } 18596b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) { 18606b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 18616b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 18626b6fae2bSMattias Nilsson if (div == 3) { 18636b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 18646b6fae2bSMattias Nilsson 18656b6fae2bSMattias Nilsson (void)do_div(r, 25); 18666b6fae2bSMattias Nilsson if (r <= rate) { 18676b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 18686b6fae2bSMattias Nilsson div = 0; 18696b6fae2bSMattias Nilsson } 18706b6fae2bSMattias Nilsson } 18716b6fae2bSMattias Nilsson val |= min(div, (u32)31); 18726b6fae2bSMattias Nilsson } else { 18736b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 18746b6fae2bSMattias Nilsson val |= min(div, (u32)31); 18756b6fae2bSMattias Nilsson } 1876b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset); 18776b6fae2bSMattias Nilsson 18786b6fae2bSMattias Nilsson /* Release the HW semaphore. */ 18796b6fae2bSMattias Nilsson writel(0, PRCM_SEM); 18806b6fae2bSMattias Nilsson 18816b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 18826b6fae2bSMattias Nilsson } 18836b6fae2bSMattias Nilsson 1884b2302c87SUlf Hansson static int set_armss_rate(unsigned long rate) 1885b2302c87SUlf Hansson { 1886b2302c87SUlf Hansson int i = 0; 1887b2302c87SUlf Hansson 1888b2302c87SUlf Hansson /* cpufreq table frequencies is in KHz. */ 1889b2302c87SUlf Hansson rate = rate / 1000; 1890b2302c87SUlf Hansson 1891b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1892b2302c87SUlf Hansson while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { 1893b2302c87SUlf Hansson if (db8500_cpufreq_table[i].frequency == rate) 1894b2302c87SUlf Hansson break; 1895b2302c87SUlf Hansson i++; 1896b2302c87SUlf Hansson } 1897b2302c87SUlf Hansson 1898b2302c87SUlf Hansson if (db8500_cpufreq_table[i].frequency != rate) 1899b2302c87SUlf Hansson return -EINVAL; 1900b2302c87SUlf Hansson 1901b2302c87SUlf Hansson /* Set the new arm opp. */ 1902b2302c87SUlf Hansson return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index); 1903b2302c87SUlf Hansson } 1904b2302c87SUlf Hansson 19056b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate) 19066b6fae2bSMattias Nilsson { 19076b6fae2bSMattias Nilsson unsigned long src_rate; 19086b6fae2bSMattias Nilsson unsigned long rem; 19096b6fae2bSMattias Nilsson u32 pll_freq = 0; 19106b6fae2bSMattias Nilsson u32 r; 19116b6fae2bSMattias Nilsson 19126b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 19136b6fae2bSMattias Nilsson rem = rate; 19146b6fae2bSMattias Nilsson 19156b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 19166b6fae2bSMattias Nilsson u64 d; 19176b6fae2bSMattias Nilsson u64 hwrate; 19186b6fae2bSMattias Nilsson 19196b6fae2bSMattias Nilsson d = (r * rate); 19206b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 19216b6fae2bSMattias Nilsson if (d < 6) 19226b6fae2bSMattias Nilsson d = 6; 19236b6fae2bSMattias Nilsson else if (d > 255) 19246b6fae2bSMattias Nilsson d = 255; 19256b6fae2bSMattias Nilsson hwrate = (d * src_rate); 19266b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 19276b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 19286b6fae2bSMattias Nilsson continue; 19296b6fae2bSMattias Nilsson (void)do_div(hwrate, r); 19306b6fae2bSMattias Nilsson if (rate < hwrate) { 19316b6fae2bSMattias Nilsson if (pll_freq == 0) 19326b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19336b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19346b6fae2bSMattias Nilsson break; 19356b6fae2bSMattias Nilsson } 19366b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) { 19376b6fae2bSMattias Nilsson rem = (rate - hwrate); 19386b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19396b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19406b6fae2bSMattias Nilsson } 19416b6fae2bSMattias Nilsson } 19426b6fae2bSMattias Nilsson if (pll_freq == 0) 19433df57bcfSMattias Nilsson return -EINVAL; 19446b6fae2bSMattias Nilsson 19456b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 19466b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ); 19476b6fae2bSMattias Nilsson 19486b6fae2bSMattias Nilsson return 0; 19496b6fae2bSMattias Nilsson } 19506b6fae2bSMattias Nilsson 19516b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate) 19526b6fae2bSMattias Nilsson { 19536b6fae2bSMattias Nilsson u32 val; 19546b6fae2bSMattias Nilsson u32 div; 19556b6fae2bSMattias Nilsson 19566b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 19576b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 19586b6fae2bSMattias Nilsson 19596b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 19606b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 19616b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 19626b6fae2bSMattias Nilsson 19636b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 19646b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 19656b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 19666b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 19676b6fae2bSMattias Nilsson } 19686b6fae2bSMattias Nilsson 19696b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate) 19706b6fae2bSMattias Nilsson { 19716b6fae2bSMattias Nilsson u32 val; 19726b6fae2bSMattias Nilsson u32 div; 19736b6fae2bSMattias Nilsson 19746b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 19756b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 19766b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask; 19776b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 19786b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 19796b6fae2bSMattias Nilsson } 19806b6fae2bSMattias Nilsson 19816b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate) 19826b6fae2bSMattias Nilsson { 19836b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 19846b6fae2bSMattias Nilsson set_clock_rate(clock, rate); 1985b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 1986b2302c87SUlf Hansson return set_armss_rate(rate); 19876b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 19886b6fae2bSMattias Nilsson return set_plldsi_rate(rate); 19896b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 19906b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 19916b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 19926b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 19936b6fae2bSMattias Nilsson return 0; 19943df57bcfSMattias Nilsson } 19953df57bcfSMattias Nilsson 199673180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 19973df57bcfSMattias Nilsson { 19983df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 19993df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 20003df57bcfSMattias Nilsson return -EINVAL; 20013df57bcfSMattias Nilsson 20023df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20033df57bcfSMattias Nilsson 2004c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20053df57bcfSMattias Nilsson cpu_relax(); 20063df57bcfSMattias Nilsson 20073df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20083df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 20093df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 20103df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 20113df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 20123df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 20133df57bcfSMattias Nilsson 2014c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20153df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20163df57bcfSMattias Nilsson 20173df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20183df57bcfSMattias Nilsson 20193df57bcfSMattias Nilsson return 0; 20203df57bcfSMattias Nilsson } 20213df57bcfSMattias Nilsson 20220508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold) 20233df57bcfSMattias Nilsson { 20243df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20253df57bcfSMattias Nilsson 2026c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20273df57bcfSMattias Nilsson cpu_relax(); 20283df57bcfSMattias Nilsson 20293df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 20303df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20313df57bcfSMattias Nilsson 2032c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20333df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20343df57bcfSMattias Nilsson 20353df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20363df57bcfSMattias Nilsson 20373df57bcfSMattias Nilsson return 0; 20383df57bcfSMattias Nilsson } 20393df57bcfSMattias Nilsson 20400508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high) 20413df57bcfSMattias Nilsson { 20423df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20433df57bcfSMattias Nilsson 2044c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20453df57bcfSMattias Nilsson cpu_relax(); 20463df57bcfSMattias Nilsson 20473df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 20483df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 20493df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 20503df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 20513df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20523df57bcfSMattias Nilsson 2053c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20543df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20553df57bcfSMattias Nilsson 20563df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20573df57bcfSMattias Nilsson 20583df57bcfSMattias Nilsson return 0; 20593df57bcfSMattias Nilsson } 20603df57bcfSMattias Nilsson 20613df57bcfSMattias Nilsson static int config_hot_period(u16 val) 20623df57bcfSMattias Nilsson { 20633df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20643df57bcfSMattias Nilsson 2065c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20663df57bcfSMattias Nilsson cpu_relax(); 20673df57bcfSMattias Nilsson 20683df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 20693df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20703df57bcfSMattias Nilsson 2071c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20723df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20733df57bcfSMattias Nilsson 20743df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20753df57bcfSMattias Nilsson 20763df57bcfSMattias Nilsson return 0; 20773df57bcfSMattias Nilsson } 20783df57bcfSMattias Nilsson 20790508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k) 20803df57bcfSMattias Nilsson { 20813df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 20823df57bcfSMattias Nilsson return -EINVAL; 20833df57bcfSMattias Nilsson 20843df57bcfSMattias Nilsson return config_hot_period(cycles32k); 20853df57bcfSMattias Nilsson } 20863df57bcfSMattias Nilsson 20870508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void) 20883df57bcfSMattias Nilsson { 20893df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 20903df57bcfSMattias Nilsson } 20913df57bcfSMattias Nilsson 209284165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 209384165b80SJonas Aberg { 209484165b80SJonas Aberg 209584165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 209684165b80SJonas Aberg 209784165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 209884165b80SJonas Aberg cpu_relax(); 209984165b80SJonas Aberg 210084165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 210184165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 210284165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 210384165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 210484165b80SJonas Aberg 210584165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 210684165b80SJonas Aberg 210784165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 210884165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 210984165b80SJonas Aberg 211084165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 211184165b80SJonas Aberg 211284165b80SJonas Aberg return 0; 211384165b80SJonas Aberg 211484165b80SJonas Aberg } 211584165b80SJonas Aberg 21160508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 211784165b80SJonas Aberg { 211884165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 211984165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 212084165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 212184165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 212284165b80SJonas Aberg } 21236f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); 212484165b80SJonas Aberg 21250508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id) 212684165b80SJonas Aberg { 212784165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 212884165b80SJonas Aberg } 21296f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); 213084165b80SJonas Aberg 21310508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id) 213284165b80SJonas Aberg { 213384165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 213484165b80SJonas Aberg } 21356f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); 213684165b80SJonas Aberg 21370508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id) 213884165b80SJonas Aberg { 213984165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 214084165b80SJonas Aberg } 21416f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); 214284165b80SJonas Aberg 214384165b80SJonas Aberg /* 214484165b80SJonas Aberg * timeout is 28 bit, in ms. 214584165b80SJonas Aberg */ 21460508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 214784165b80SJonas Aberg { 214884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 214984165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 215084165b80SJonas Aberg /* 215184165b80SJonas Aberg * Put the lowest 28 bits of timeout at 215284165b80SJonas Aberg * offset 4. Four first bits are used for id. 215384165b80SJonas Aberg */ 215484165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 215584165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 215684165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 215784165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 215884165b80SJonas Aberg } 21596f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); 216084165b80SJonas Aberg 21613df57bcfSMattias Nilsson /** 2162650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 2163650c2a21SLinus Walleij * @slave: The I2C slave address. 2164650c2a21SLinus Walleij * @reg: The (start) register address. 2165650c2a21SLinus Walleij * @value: The read out value(s). 2166650c2a21SLinus Walleij * @size: The number of registers to read. 2167650c2a21SLinus Walleij * 2168650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2169650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2170650c2a21SLinus Walleij */ 2171650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2172650c2a21SLinus Walleij { 2173650c2a21SLinus Walleij int r; 2174650c2a21SLinus Walleij 2175650c2a21SLinus Walleij if (size != 1) 2176650c2a21SLinus Walleij return -EINVAL; 2177650c2a21SLinus Walleij 21783df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2179650c2a21SLinus Walleij 2180c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2181650c2a21SLinus Walleij cpu_relax(); 2182650c2a21SLinus Walleij 21833c3e4898SMattias Nilsson writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 21843df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 21853df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 21863df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 21873df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2188650c2a21SLinus Walleij 2189c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 21903df57bcfSMattias Nilsson 2191650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 21923df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 21933df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 21943df57bcfSMattias Nilsson __func__); 2195650c2a21SLinus Walleij r = -EIO; 21963df57bcfSMattias Nilsson } else { 2197650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 21983df57bcfSMattias Nilsson } 21993df57bcfSMattias Nilsson 2200650c2a21SLinus Walleij if (!r) 2201650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 2202650c2a21SLinus Walleij 2203650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 22043df57bcfSMattias Nilsson 2205650c2a21SLinus Walleij return r; 2206650c2a21SLinus Walleij } 2207650c2a21SLinus Walleij 2208650c2a21SLinus Walleij /** 22093c3e4898SMattias Nilsson * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. 2210650c2a21SLinus Walleij * @slave: The I2C slave address. 2211650c2a21SLinus Walleij * @reg: The (start) register address. 2212650c2a21SLinus Walleij * @value: The value(s) to write. 22133c3e4898SMattias Nilsson * @mask: The mask(s) to use. 2214650c2a21SLinus Walleij * @size: The number of registers to write. 2215650c2a21SLinus Walleij * 22163c3e4898SMattias Nilsson * Writes masked register value(s) to the ABB. 22173c3e4898SMattias Nilsson * For each @value, only the bits set to 1 in the corresponding @mask 22183c3e4898SMattias Nilsson * will be written. The other bits are not changed. 2219650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2220650c2a21SLinus Walleij */ 22213c3e4898SMattias Nilsson int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) 2222650c2a21SLinus Walleij { 2223650c2a21SLinus Walleij int r; 2224650c2a21SLinus Walleij 2225650c2a21SLinus Walleij if (size != 1) 2226650c2a21SLinus Walleij return -EINVAL; 2227650c2a21SLinus Walleij 22283df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2229650c2a21SLinus Walleij 2230c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2231650c2a21SLinus Walleij cpu_relax(); 2232650c2a21SLinus Walleij 22333c3e4898SMattias Nilsson writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 22343df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22353df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22363df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22373df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2238650c2a21SLinus Walleij 2239c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 22403df57bcfSMattias Nilsson 2241650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 22423df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 22433df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 22443df57bcfSMattias Nilsson __func__); 2245650c2a21SLinus Walleij r = -EIO; 22463df57bcfSMattias Nilsson } else { 2247650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 22483df57bcfSMattias Nilsson } 22493df57bcfSMattias Nilsson 22503df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 22513df57bcfSMattias Nilsson 22523df57bcfSMattias Nilsson return r; 22533df57bcfSMattias Nilsson } 22543df57bcfSMattias Nilsson 22553df57bcfSMattias Nilsson /** 22563c3e4898SMattias Nilsson * prcmu_abb_write() - Write register value(s) to the ABB. 22573c3e4898SMattias Nilsson * @slave: The I2C slave address. 22583c3e4898SMattias Nilsson * @reg: The (start) register address. 22593c3e4898SMattias Nilsson * @value: The value(s) to write. 22603c3e4898SMattias Nilsson * @size: The number of registers to write. 22613c3e4898SMattias Nilsson * 22623c3e4898SMattias Nilsson * Writes register value(s) to the ABB. 22633c3e4898SMattias Nilsson * @size has to be 1 for the current firmware version. 22643c3e4898SMattias Nilsson */ 22653c3e4898SMattias Nilsson int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 22663c3e4898SMattias Nilsson { 22673c3e4898SMattias Nilsson u8 mask = ~0; 22683c3e4898SMattias Nilsson 22693c3e4898SMattias Nilsson return prcmu_abb_write_masked(slave, reg, value, &mask, size); 22703c3e4898SMattias Nilsson } 22713c3e4898SMattias Nilsson 22723c3e4898SMattias Nilsson /** 22733df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 22743df57bcfSMattias Nilsson */ 22755261e101SArun Murthy int prcmu_ac_wake_req(void) 22763df57bcfSMattias Nilsson { 22773df57bcfSMattias Nilsson u32 val; 22785261e101SArun Murthy int ret = 0; 22793df57bcfSMattias Nilsson 22803df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 22813df57bcfSMattias Nilsson 2282c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 22833df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 22843df57bcfSMattias Nilsson goto unlock_and_return; 22853df57bcfSMattias Nilsson 22863df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 22873df57bcfSMattias Nilsson 22885261e101SArun Murthy /* 22895261e101SArun Murthy * Force Modem Wake-up before hostaccess_req ping-pong. 22905261e101SArun Murthy * It prevents Modem to enter in Sleep while acking the hostaccess 22915261e101SArun Murthy * request. The 31us delay has been calculated by HWI. 22925261e101SArun Murthy */ 22935261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; 22945261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 22955261e101SArun Murthy 22965261e101SArun Murthy udelay(31); 22975261e101SArun Murthy 22985261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; 22995261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 23003df57bcfSMattias Nilsson 23013df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2302d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 23035261e101SArun Murthy #if defined(CONFIG_DBX500_PRCMU_DEBUG) 23045261e101SArun Murthy db8500_prcmu_debug_dump(__func__, true, true); 23055261e101SArun Murthy #endif 230657265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2307d6e3002eSMattias Nilsson __func__); 23085261e101SArun Murthy ret = -EFAULT; 23093df57bcfSMattias Nilsson } 2310650c2a21SLinus Walleij 2311650c2a21SLinus Walleij unlock_and_return: 23123df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23135261e101SArun Murthy return ret; 2314650c2a21SLinus Walleij } 2315650c2a21SLinus Walleij 23163df57bcfSMattias Nilsson /** 23173df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 23183df57bcfSMattias Nilsson */ 23193df57bcfSMattias Nilsson void prcmu_ac_sleep_req() 2320650c2a21SLinus Walleij { 23213df57bcfSMattias Nilsson u32 val; 2322650c2a21SLinus Walleij 23233df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 2324650c2a21SLinus Walleij 2325c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23263df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 23273df57bcfSMattias Nilsson goto unlock_and_return; 23283df57bcfSMattias Nilsson 23293df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2330c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 23313df57bcfSMattias Nilsson 23323df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2333d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 233457265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 23353df57bcfSMattias Nilsson __func__); 23363df57bcfSMattias Nilsson } 23373df57bcfSMattias Nilsson 23383df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 23393df57bcfSMattias Nilsson 23403df57bcfSMattias Nilsson unlock_and_return: 23413df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23423df57bcfSMattias Nilsson } 23433df57bcfSMattias Nilsson 234473180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 23453df57bcfSMattias Nilsson { 23463df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 23473df57bcfSMattias Nilsson } 23483df57bcfSMattias Nilsson 23493df57bcfSMattias Nilsson /** 235073180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 23513df57bcfSMattias Nilsson * 235273180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 23533df57bcfSMattias Nilsson * fires interrupt to fw 23543df57bcfSMattias Nilsson */ 235573180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 23563df57bcfSMattias Nilsson { 23573df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2358c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 23593df57bcfSMattias Nilsson } 23603df57bcfSMattias Nilsson 23613df57bcfSMattias Nilsson /** 2362597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2363597045deSSebastian Rasmussen * 2364597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 2365597045deSSebastian Rasmussen * last restart. 2366597045deSSebastian Rasmussen */ 2367597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 2368597045deSSebastian Rasmussen { 2369597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 2370597045deSSebastian Rasmussen } 2371597045deSSebastian Rasmussen 2372597045deSSebastian Rasmussen /** 23730508901cSMattias Nilsson * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 23743df57bcfSMattias Nilsson */ 23750508901cSMattias Nilsson void db8500_prcmu_modem_reset(void) 23763df57bcfSMattias Nilsson { 2377650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 2378650c2a21SLinus Walleij 2379c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2380650c2a21SLinus Walleij cpu_relax(); 2381650c2a21SLinus Walleij 23823df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2383c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2384650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 23853df57bcfSMattias Nilsson 23863df57bcfSMattias Nilsson /* 23873df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 23883df57bcfSMattias Nilsson * This state is already managed by upper layer 23893df57bcfSMattias Nilsson */ 2390650c2a21SLinus Walleij 2391650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 2392650c2a21SLinus Walleij } 2393650c2a21SLinus Walleij 23943df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 2395650c2a21SLinus Walleij { 23963df57bcfSMattias Nilsson unsigned long flags; 2397650c2a21SLinus Walleij 23983df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 2399650c2a21SLinus Walleij 2400c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 24013df57bcfSMattias Nilsson cpu_relax(); 2402650c2a21SLinus Walleij 24033df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2404c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2405650c2a21SLinus Walleij 24063df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2407650c2a21SLinus Walleij } 2408650c2a21SLinus Walleij 24093df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 2410650c2a21SLinus Walleij { 24113df57bcfSMattias Nilsson pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 24123df57bcfSMattias Nilsson header, n); 2413650c2a21SLinus Walleij } 2414650c2a21SLinus Walleij 24153df57bcfSMattias Nilsson static bool read_mailbox_0(void) 2416650c2a21SLinus Walleij { 24173df57bcfSMattias Nilsson bool r; 24183df57bcfSMattias Nilsson u32 ev; 24193df57bcfSMattias Nilsson unsigned int n; 24203df57bcfSMattias Nilsson u8 header; 24213df57bcfSMattias Nilsson 24223df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 24233df57bcfSMattias Nilsson switch (header) { 24243df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 24253df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 24263df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 24273df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 24283df57bcfSMattias Nilsson else 24293df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 24303df57bcfSMattias Nilsson 24313df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 24323df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 24333df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 24343df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 24353df57bcfSMattias Nilsson 24363df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 24373df57bcfSMattias Nilsson 24383df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 24393df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 244089d9b1c9SLinus Walleij generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); 24413df57bcfSMattias Nilsson } 24423df57bcfSMattias Nilsson r = true; 24433df57bcfSMattias Nilsson break; 24443df57bcfSMattias Nilsson default: 24453df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 24463df57bcfSMattias Nilsson r = false; 24473df57bcfSMattias Nilsson break; 24483df57bcfSMattias Nilsson } 2449c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 24503df57bcfSMattias Nilsson return r; 24513df57bcfSMattias Nilsson } 24523df57bcfSMattias Nilsson 24533df57bcfSMattias Nilsson static bool read_mailbox_1(void) 24543df57bcfSMattias Nilsson { 24553df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 24563df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 24573df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 24583df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 24593df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 24603df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 24613df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2462c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2463650c2a21SLinus Walleij complete(&mb1_transfer.work); 24643df57bcfSMattias Nilsson return false; 2465650c2a21SLinus Walleij } 2466650c2a21SLinus Walleij 24673df57bcfSMattias Nilsson static bool read_mailbox_2(void) 2468650c2a21SLinus Walleij { 24693df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2470c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 24713df57bcfSMattias Nilsson complete(&mb2_transfer.work); 24723df57bcfSMattias Nilsson return false; 2473650c2a21SLinus Walleij } 2474650c2a21SLinus Walleij 24753df57bcfSMattias Nilsson static bool read_mailbox_3(void) 2476650c2a21SLinus Walleij { 2477c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 24783df57bcfSMattias Nilsson return false; 2479650c2a21SLinus Walleij } 2480650c2a21SLinus Walleij 24813df57bcfSMattias Nilsson static bool read_mailbox_4(void) 2482650c2a21SLinus Walleij { 24833df57bcfSMattias Nilsson u8 header; 24843df57bcfSMattias Nilsson bool do_complete = true; 24853df57bcfSMattias Nilsson 24863df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 24873df57bcfSMattias Nilsson switch (header) { 24883df57bcfSMattias Nilsson case MB4H_MEM_ST: 24893df57bcfSMattias Nilsson case MB4H_HOTDOG: 24903df57bcfSMattias Nilsson case MB4H_HOTMON: 24913df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 2492a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 2493a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 2494a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 2495a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 2496a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 24973df57bcfSMattias Nilsson break; 24983df57bcfSMattias Nilsson default: 24993df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 25003df57bcfSMattias Nilsson do_complete = false; 25013df57bcfSMattias Nilsson break; 2502650c2a21SLinus Walleij } 2503650c2a21SLinus Walleij 2504c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 25053df57bcfSMattias Nilsson 25063df57bcfSMattias Nilsson if (do_complete) 25073df57bcfSMattias Nilsson complete(&mb4_transfer.work); 25083df57bcfSMattias Nilsson 25093df57bcfSMattias Nilsson return false; 25103df57bcfSMattias Nilsson } 25113df57bcfSMattias Nilsson 25123df57bcfSMattias Nilsson static bool read_mailbox_5(void) 2513650c2a21SLinus Walleij { 25143df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 25153df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2516c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2517650c2a21SLinus Walleij complete(&mb5_transfer.work); 25183df57bcfSMattias Nilsson return false; 2519650c2a21SLinus Walleij } 2520650c2a21SLinus Walleij 25213df57bcfSMattias Nilsson static bool read_mailbox_6(void) 2522650c2a21SLinus Walleij { 2523c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 25243df57bcfSMattias Nilsson return false; 2525650c2a21SLinus Walleij } 2526650c2a21SLinus Walleij 25273df57bcfSMattias Nilsson static bool read_mailbox_7(void) 2528650c2a21SLinus Walleij { 2529c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 25303df57bcfSMattias Nilsson return false; 2531650c2a21SLinus Walleij } 2532650c2a21SLinus Walleij 25333df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 2534650c2a21SLinus Walleij read_mailbox_0, 2535650c2a21SLinus Walleij read_mailbox_1, 2536650c2a21SLinus Walleij read_mailbox_2, 2537650c2a21SLinus Walleij read_mailbox_3, 2538650c2a21SLinus Walleij read_mailbox_4, 2539650c2a21SLinus Walleij read_mailbox_5, 2540650c2a21SLinus Walleij read_mailbox_6, 2541650c2a21SLinus Walleij read_mailbox_7 2542650c2a21SLinus Walleij }; 2543650c2a21SLinus Walleij 2544650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2545650c2a21SLinus Walleij { 2546650c2a21SLinus Walleij u32 bits; 2547650c2a21SLinus Walleij u8 n; 25483df57bcfSMattias Nilsson irqreturn_t r; 2549650c2a21SLinus Walleij 2550c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2551650c2a21SLinus Walleij if (unlikely(!bits)) 2552650c2a21SLinus Walleij return IRQ_NONE; 2553650c2a21SLinus Walleij 25543df57bcfSMattias Nilsson r = IRQ_HANDLED; 2555650c2a21SLinus Walleij for (n = 0; bits; n++) { 2556650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2557650c2a21SLinus Walleij bits -= MBOX_BIT(n); 25583df57bcfSMattias Nilsson if (read_mailbox[n]()) 25593df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2560650c2a21SLinus Walleij } 2561650c2a21SLinus Walleij } 25623df57bcfSMattias Nilsson return r; 25633df57bcfSMattias Nilsson } 25643df57bcfSMattias Nilsson 25653df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 25663df57bcfSMattias Nilsson { 25673df57bcfSMattias Nilsson ack_dbb_wakeup(); 2568650c2a21SLinus Walleij return IRQ_HANDLED; 2569650c2a21SLinus Walleij } 2570650c2a21SLinus Walleij 25713df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 25723df57bcfSMattias Nilsson { 25733df57bcfSMattias Nilsson unsigned long flags; 25743df57bcfSMattias Nilsson 25753df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 25763df57bcfSMattias Nilsson 25773df57bcfSMattias Nilsson config_wakeups(); 25783df57bcfSMattias Nilsson 25793df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 25803df57bcfSMattias Nilsson } 25813df57bcfSMattias Nilsson 25823df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 25833df57bcfSMattias Nilsson { 25843df57bcfSMattias Nilsson unsigned long flags; 25853df57bcfSMattias Nilsson 25863df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 25873df57bcfSMattias Nilsson 2588f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; 25893df57bcfSMattias Nilsson 25903df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 25913df57bcfSMattias Nilsson 25923df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 25933df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 25943df57bcfSMattias Nilsson } 25953df57bcfSMattias Nilsson 25963df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 25973df57bcfSMattias Nilsson { 25983df57bcfSMattias Nilsson unsigned long flags; 25993df57bcfSMattias Nilsson 26003df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26013df57bcfSMattias Nilsson 2602f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; 26033df57bcfSMattias Nilsson 26043df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26053df57bcfSMattias Nilsson 26063df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26073df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26083df57bcfSMattias Nilsson } 26093df57bcfSMattias Nilsson 26103df57bcfSMattias Nilsson static void noop(struct irq_data *d) 26113df57bcfSMattias Nilsson { 26123df57bcfSMattias Nilsson } 26133df57bcfSMattias Nilsson 26143df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 26153df57bcfSMattias Nilsson .name = "prcmu", 26163df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 26173df57bcfSMattias Nilsson .irq_ack = noop, 26183df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 26193df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 26203df57bcfSMattias Nilsson }; 26213df57bcfSMattias Nilsson 262205ec260eSLinus Walleij static __init char *fw_project_name(u32 project) 2623b58d12feSMattias Nilsson { 2624b58d12feSMattias Nilsson switch (project) { 2625b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500: 2626b58d12feSMattias Nilsson return "U8500"; 262705ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8400: 262805ec260eSLinus Walleij return "U8400"; 2629b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500: 2630b58d12feSMattias Nilsson return "U9500"; 263105ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBB: 263205ec260eSLinus Walleij return "U8500 MBB"; 263305ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C1: 263405ec260eSLinus Walleij return "U8500 C1"; 263505ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C2: 263605ec260eSLinus Walleij return "U8500 C2"; 263705ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C3: 263805ec260eSLinus Walleij return "U8500 C3"; 263905ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C4: 264005ec260eSLinus Walleij return "U8500 C4"; 264105ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9500_MBL: 264205ec260eSLinus Walleij return "U9500 MBL"; 264305ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBL: 264405ec260eSLinus Walleij return "U8500 MBL"; 264505ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBL2: 264605ec260eSLinus Walleij return "U8500 MBL2"; 26475f96a1a6SBengt Jonsson case PRCMU_FW_PROJECT_U8520: 264805ec260eSLinus Walleij return "U8520 MBL"; 26491927ddf6SBengt Jonsson case PRCMU_FW_PROJECT_U8420: 26501927ddf6SBengt Jonsson return "U8420"; 265105ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9540: 265205ec260eSLinus Walleij return "U9540"; 265305ec260eSLinus Walleij case PRCMU_FW_PROJECT_A9420: 265405ec260eSLinus Walleij return "A9420"; 265505ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8540: 265605ec260eSLinus Walleij return "L8540"; 265705ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8580: 265805ec260eSLinus Walleij return "L8580"; 2659b58d12feSMattias Nilsson default: 2660b58d12feSMattias Nilsson return "Unknown"; 2661b58d12feSMattias Nilsson } 2662b58d12feSMattias Nilsson } 2663b58d12feSMattias Nilsson 2664f3f1f0a1SLee Jones static int db8500_irq_map(struct irq_domain *d, unsigned int virq, 2665f3f1f0a1SLee Jones irq_hw_number_t hwirq) 2666f3f1f0a1SLee Jones { 2667f3f1f0a1SLee Jones irq_set_chip_and_handler(virq, &prcmu_irq_chip, 2668f3f1f0a1SLee Jones handle_simple_irq); 2669f3f1f0a1SLee Jones set_irq_flags(virq, IRQF_VALID); 2670f3f1f0a1SLee Jones 2671f3f1f0a1SLee Jones return 0; 2672f3f1f0a1SLee Jones } 2673f3f1f0a1SLee Jones 2674f3f1f0a1SLee Jones static struct irq_domain_ops db8500_irq_ops = { 2675f3f1f0a1SLee Jones .map = db8500_irq_map, 2676f3f1f0a1SLee Jones .xlate = irq_domain_xlate_twocell, 2677f3f1f0a1SLee Jones }; 2678f3f1f0a1SLee Jones 267955b175d7SArnd Bergmann static int db8500_irq_init(struct device_node *np, int irq_base) 2680f3f1f0a1SLee Jones { 268189d9b1c9SLinus Walleij int i; 2682a7238e43SLinus Walleij 2683a7238e43SLinus Walleij /* In the device tree case, just take some IRQs */ 268455b175d7SArnd Bergmann if (np) 268555b175d7SArnd Bergmann irq_base = 0; 2686a7238e43SLinus Walleij 2687a7238e43SLinus Walleij db8500_irq_domain = irq_domain_add_simple( 2688a7238e43SLinus Walleij np, NUM_PRCMU_WAKEUPS, irq_base, 2689a7238e43SLinus Walleij &db8500_irq_ops, NULL); 2690f3f1f0a1SLee Jones 2691f3f1f0a1SLee Jones if (!db8500_irq_domain) { 2692f3f1f0a1SLee Jones pr_err("Failed to create irqdomain\n"); 2693f3f1f0a1SLee Jones return -ENOSYS; 2694f3f1f0a1SLee Jones } 2695f3f1f0a1SLee Jones 269689d9b1c9SLinus Walleij /* All wakeups will be used, so create mappings for all */ 269789d9b1c9SLinus Walleij for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) 269889d9b1c9SLinus Walleij irq_create_mapping(db8500_irq_domain, i); 269989d9b1c9SLinus Walleij 2700f3f1f0a1SLee Jones return 0; 2701f3f1f0a1SLee Jones } 2702f3f1f0a1SLee Jones 270305ec260eSLinus Walleij static void dbx500_fw_version_init(struct platform_device *pdev, 270405ec260eSLinus Walleij u32 version_offset) 2705650c2a21SLinus Walleij { 270605ec260eSLinus Walleij struct resource *res; 270705ec260eSLinus Walleij void __iomem *tcpm_base; 2708741cdecfSLee Jones u32 version; 27093df57bcfSMattias Nilsson 271005ec260eSLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 271105ec260eSLinus Walleij "prcmu-tcpm"); 271205ec260eSLinus Walleij if (!res) { 271305ec260eSLinus Walleij dev_err(&pdev->dev, 271405ec260eSLinus Walleij "Error: no prcmu tcpm memory region provided\n"); 271505ec260eSLinus Walleij return; 271605ec260eSLinus Walleij } 271705ec260eSLinus Walleij tcpm_base = ioremap(res->start, resource_size(res)); 2718741cdecfSLee Jones if (!tcpm_base) { 2719741cdecfSLee Jones dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n"); 2720741cdecfSLee Jones return; 2721741cdecfSLee Jones } 272205ec260eSLinus Walleij 272305ec260eSLinus Walleij version = readl(tcpm_base + version_offset); 272405ec260eSLinus Walleij fw_info.version.project = (version & 0xFF); 2725b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF; 2726b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF; 2727b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF; 272805ec260eSLinus Walleij strncpy(fw_info.version.project_name, 2729b58d12feSMattias Nilsson fw_project_name(fw_info.version.project), 273005ec260eSLinus Walleij PRCMU_FW_PROJECT_NAME_LEN); 273105ec260eSLinus Walleij fw_info.valid = true; 273205ec260eSLinus Walleij pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", 273305ec260eSLinus Walleij fw_info.version.project_name, 273405ec260eSLinus Walleij fw_info.version.project, 273505ec260eSLinus Walleij fw_info.version.api_version, 273605ec260eSLinus Walleij fw_info.version.func_version, 273705ec260eSLinus Walleij fw_info.version.errata); 27383df57bcfSMattias Nilsson iounmap(tcpm_base); 27393df57bcfSMattias Nilsson } 2740650c2a21SLinus Walleij 27419a47a8dcSLinus Walleij void __init db8500_prcmu_early_init(u32 phy_base, u32 size) 274205ec260eSLinus Walleij { 27439a47a8dcSLinus Walleij /* 27449a47a8dcSLinus Walleij * This is a temporary remap to bring up the clocks. It is 27459a47a8dcSLinus Walleij * subsequently replaces with a real remap. After the merge of 27469a47a8dcSLinus Walleij * the mailbox subsystem all of this early code goes away, and the 27479a47a8dcSLinus Walleij * clock driver can probe independently. An early initcall will 27489a47a8dcSLinus Walleij * still be needed, but it can be diverted into drivers/clk/ux500. 27499a47a8dcSLinus Walleij */ 27509a47a8dcSLinus Walleij prcmu_base = ioremap(phy_base, size); 27519a47a8dcSLinus Walleij if (!prcmu_base) 27529a47a8dcSLinus Walleij pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); 27539a47a8dcSLinus Walleij 27543df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 27553df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 27563df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 27573df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2758650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2759650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 27604d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE; 27613df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 27623df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 27633df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 27643df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 27653df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 27663df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 27673df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 27683df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2769650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2770650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2771650c2a21SLinus Walleij 27723df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2773650c2a21SLinus Walleij } 2774650c2a21SLinus Walleij 27750508901cSMattias Nilsson static void __init init_prcm_registers(void) 2776d65e12d7SMattias Nilsson { 2777d65e12d7SMattias Nilsson u32 val; 2778d65e12d7SMattias Nilsson 2779d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2780d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2781d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2782d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2783d65e12d7SMattias Nilsson } 2784d65e12d7SMattias Nilsson 27851032fbfdSBengt Jonsson /* 27861032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 27871032fbfdSBengt Jonsson */ 27881032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 27891032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 27901032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 27911032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 27921032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 27931032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 2794ae840635SLee Jones REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), 27951032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 27961032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 27971032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 27981032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 27991032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 28001032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 28011032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 28021032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 28031032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 28041032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 28051032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 28061032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 28071032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2808992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 2809bc367481SLee Jones REGULATOR_SUPPLY("vddvario", "smsc911x.0"), 28101032fbfdSBengt Jonsson }; 28111032fbfdSBengt Jonsson 28121032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 28131032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 28141032fbfdSBengt Jonsson /* AV8100 regulator */ 28151032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 28161032fbfdSBengt Jonsson }; 28171032fbfdSBengt Jonsson 28181032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2819992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2820624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2821624e87c2SBengt Jonsson }; 2822624e87c2SBengt Jonsson 2823624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2824624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2825624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2826624e87c2SBengt Jonsson }; 2827624e87c2SBengt Jonsson 2828624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2829624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2830624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2831624e87c2SBengt Jonsson }; 2832624e87c2SBengt Jonsson 2833624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2834624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2835624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2836624e87c2SBengt Jonsson }; 2837624e87c2SBengt Jonsson 2838624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2839624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2840624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2841624e87c2SBengt Jonsson }; 2842624e87c2SBengt Jonsson 2843624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2844624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2845624e87c2SBengt Jonsson }; 2846624e87c2SBengt Jonsson 2847624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2848624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2849624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2850624e87c2SBengt Jonsson }; 2851624e87c2SBengt Jonsson 2852624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2853624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2854624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2855624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 2856992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 28571032fbfdSBengt Jonsson }; 28581032fbfdSBengt Jonsson 28591032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 28601032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 28611032fbfdSBengt Jonsson .constraints = { 28621032fbfdSBengt Jonsson .name = "db8500-vape", 28631032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28641e45860fSMark Brown .always_on = true, 28651032fbfdSBengt Jonsson }, 28661032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 28671032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 28681032fbfdSBengt Jonsson }, 28691032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 28701032fbfdSBengt Jonsson .constraints = { 28711032fbfdSBengt Jonsson .name = "db8500-varm", 28721032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28731032fbfdSBengt Jonsson }, 28741032fbfdSBengt Jonsson }, 28751032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 28761032fbfdSBengt Jonsson .constraints = { 28771032fbfdSBengt Jonsson .name = "db8500-vmodem", 28781032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28791032fbfdSBengt Jonsson }, 28801032fbfdSBengt Jonsson }, 28811032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 28821032fbfdSBengt Jonsson .constraints = { 28831032fbfdSBengt Jonsson .name = "db8500-vpll", 28841032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28851032fbfdSBengt Jonsson }, 28861032fbfdSBengt Jonsson }, 28871032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 28881032fbfdSBengt Jonsson .constraints = { 28891032fbfdSBengt Jonsson .name = "db8500-vsmps1", 28901032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28911032fbfdSBengt Jonsson }, 28921032fbfdSBengt Jonsson }, 28931032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 28941032fbfdSBengt Jonsson .constraints = { 28951032fbfdSBengt Jonsson .name = "db8500-vsmps2", 28961032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28971032fbfdSBengt Jonsson }, 28981032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 28991032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 29001032fbfdSBengt Jonsson }, 29011032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 29021032fbfdSBengt Jonsson .constraints = { 29031032fbfdSBengt Jonsson .name = "db8500-vsmps3", 29041032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29051032fbfdSBengt Jonsson }, 29061032fbfdSBengt Jonsson }, 29071032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 29081032fbfdSBengt Jonsson .constraints = { 29091032fbfdSBengt Jonsson .name = "db8500-vrf1", 29101032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29111032fbfdSBengt Jonsson }, 29121032fbfdSBengt Jonsson }, 29131032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2914992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29151032fbfdSBengt Jonsson .constraints = { 29161032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 29171032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29181032fbfdSBengt Jonsson }, 2919624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2920624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 29211032fbfdSBengt Jonsson }, 29221032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 29231032fbfdSBengt Jonsson .constraints = { 29241032fbfdSBengt Jonsson /* "ret" means "retention" */ 29251032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 29261032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29271032fbfdSBengt Jonsson }, 29281032fbfdSBengt Jonsson }, 29291032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2930992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29311032fbfdSBengt Jonsson .constraints = { 29321032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 29331032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29341032fbfdSBengt Jonsson }, 2935624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2936624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 29371032fbfdSBengt Jonsson }, 29381032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2939992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29401032fbfdSBengt Jonsson .constraints = { 29411032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 29421032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29431032fbfdSBengt Jonsson }, 2944624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2945624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 29461032fbfdSBengt Jonsson }, 29471032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 29481032fbfdSBengt Jonsson .constraints = { 29491032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 29501032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29511032fbfdSBengt Jonsson }, 29521032fbfdSBengt Jonsson }, 29531032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2954992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29551032fbfdSBengt Jonsson .constraints = { 29561032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 29571032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29581032fbfdSBengt Jonsson }, 2959624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 2960624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 29611032fbfdSBengt Jonsson }, 29621032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 29631032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29641032fbfdSBengt Jonsson .constraints = { 29651032fbfdSBengt Jonsson .name = "db8500-sga", 29661032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29671032fbfdSBengt Jonsson }, 2968624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 2969624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2970624e87c2SBengt Jonsson 29711032fbfdSBengt Jonsson }, 29721032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 29731032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29741032fbfdSBengt Jonsson .constraints = { 29751032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 29761032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29771032fbfdSBengt Jonsson }, 29781032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 29791032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 29801032fbfdSBengt Jonsson }, 29811032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 2982992b133aSBengt Jonsson /* 2983992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off, 2984992b133aSBengt Jonsson * no need to hold Vape 2985992b133aSBengt Jonsson */ 29861032fbfdSBengt Jonsson .constraints = { 29871032fbfdSBengt Jonsson .name = "db8500-esram12", 29881032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29891032fbfdSBengt Jonsson }, 2990624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 2991624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 29921032fbfdSBengt Jonsson }, 29931032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 29941032fbfdSBengt Jonsson .constraints = { 29951032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 29961032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29971032fbfdSBengt Jonsson }, 29981032fbfdSBengt Jonsson }, 29991032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 3000992b133aSBengt Jonsson /* 3001992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off, 3002992b133aSBengt Jonsson * no need to hold Vape 3003992b133aSBengt Jonsson */ 30041032fbfdSBengt Jonsson .constraints = { 30051032fbfdSBengt Jonsson .name = "db8500-esram34", 30061032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30071032fbfdSBengt Jonsson }, 3008624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 3009624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 30101032fbfdSBengt Jonsson }, 30111032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 30121032fbfdSBengt Jonsson .constraints = { 30131032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 30141032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30151032fbfdSBengt Jonsson }, 30161032fbfdSBengt Jonsson }, 30171032fbfdSBengt Jonsson }; 30181032fbfdSBengt Jonsson 3019b3aac62bSFabio Baltieri static struct ux500_wdt_data db8500_wdt_pdata = { 3020b3aac62bSFabio Baltieri .timeout = 600, /* 10 minutes */ 3021b3aac62bSFabio Baltieri .has_28_bits_resolution = true, 3022b3aac62bSFabio Baltieri }; 302355b175d7SArnd Bergmann /* 302455b175d7SArnd Bergmann * Thermal Sensor 302555b175d7SArnd Bergmann */ 302655b175d7SArnd Bergmann 302755b175d7SArnd Bergmann static struct resource db8500_thsens_resources[] = { 302855b175d7SArnd Bergmann { 302955b175d7SArnd Bergmann .name = "IRQ_HOTMON_LOW", 303055b175d7SArnd Bergmann .start = IRQ_PRCMU_HOTMON_LOW, 303155b175d7SArnd Bergmann .end = IRQ_PRCMU_HOTMON_LOW, 303255b175d7SArnd Bergmann .flags = IORESOURCE_IRQ, 303355b175d7SArnd Bergmann }, 303455b175d7SArnd Bergmann { 303555b175d7SArnd Bergmann .name = "IRQ_HOTMON_HIGH", 303655b175d7SArnd Bergmann .start = IRQ_PRCMU_HOTMON_HIGH, 303755b175d7SArnd Bergmann .end = IRQ_PRCMU_HOTMON_HIGH, 303855b175d7SArnd Bergmann .flags = IORESOURCE_IRQ, 303955b175d7SArnd Bergmann }, 304055b175d7SArnd Bergmann }; 304155b175d7SArnd Bergmann 304255b175d7SArnd Bergmann static struct db8500_thsens_platform_data db8500_thsens_data = { 304355b175d7SArnd Bergmann .trip_points[0] = { 304455b175d7SArnd Bergmann .temp = 70000, 304555b175d7SArnd Bergmann .type = THERMAL_TRIP_ACTIVE, 304655b175d7SArnd Bergmann .cdev_name = { 304755b175d7SArnd Bergmann [0] = "thermal-cpufreq-0", 304855b175d7SArnd Bergmann }, 304955b175d7SArnd Bergmann }, 305055b175d7SArnd Bergmann .trip_points[1] = { 305155b175d7SArnd Bergmann .temp = 75000, 305255b175d7SArnd Bergmann .type = THERMAL_TRIP_ACTIVE, 305355b175d7SArnd Bergmann .cdev_name = { 305455b175d7SArnd Bergmann [0] = "thermal-cpufreq-0", 305555b175d7SArnd Bergmann }, 305655b175d7SArnd Bergmann }, 305755b175d7SArnd Bergmann .trip_points[2] = { 305855b175d7SArnd Bergmann .temp = 80000, 305955b175d7SArnd Bergmann .type = THERMAL_TRIP_ACTIVE, 306055b175d7SArnd Bergmann .cdev_name = { 306155b175d7SArnd Bergmann [0] = "thermal-cpufreq-0", 306255b175d7SArnd Bergmann }, 306355b175d7SArnd Bergmann }, 306455b175d7SArnd Bergmann .trip_points[3] = { 306555b175d7SArnd Bergmann .temp = 85000, 306655b175d7SArnd Bergmann .type = THERMAL_TRIP_CRITICAL, 306755b175d7SArnd Bergmann }, 306855b175d7SArnd Bergmann .num_trips = 4, 306955b175d7SArnd Bergmann }; 3070b3aac62bSFabio Baltieri 3071d98a5384SLee Jones static struct mfd_cell common_prcmu_devs[] = { 3072d98a5384SLee Jones { 3073d98a5384SLee Jones .name = "ux500_wdt", 3074d98a5384SLee Jones .platform_data = &db8500_wdt_pdata, 3075d98a5384SLee Jones .pdata_size = sizeof(db8500_wdt_pdata), 3076d98a5384SLee Jones .id = -1, 3077d98a5384SLee Jones }, 3078d98a5384SLee Jones }; 3079d98a5384SLee Jones 30803df57bcfSMattias Nilsson static struct mfd_cell db8500_prcmu_devs[] = { 30813df57bcfSMattias Nilsson { 30823df57bcfSMattias Nilsson .name = "db8500-prcmu-regulators", 30835d90322bSLee Jones .of_compatible = "stericsson,db8500-prcmu-regulator", 30841ed7891fSMattias Wallin .platform_data = &db8500_regulators, 30851ed7891fSMattias Wallin .pdata_size = sizeof(db8500_regulators), 30863df57bcfSMattias Nilsson }, 30873df57bcfSMattias Nilsson { 308884c7c20fSLee Jones .name = "cpufreq-ux500", 308984c7c20fSLee Jones .of_compatible = "stericsson,cpufreq-ux500", 3090c280f45fSUlf Hansson .platform_data = &db8500_cpufreq_table, 3091c280f45fSUlf Hansson .pdata_size = sizeof(db8500_cpufreq_table), 30923df57bcfSMattias Nilsson }, 30936d11d135SLee Jones { 309455b175d7SArnd Bergmann .name = "db8500-thermal", 309555b175d7SArnd Bergmann .num_resources = ARRAY_SIZE(db8500_thsens_resources), 309655b175d7SArnd Bergmann .resources = db8500_thsens_resources, 309755b175d7SArnd Bergmann .platform_data = &db8500_thsens_data, 3098a3ef0debSLee Jones .pdata_size = sizeof(db8500_thsens_data), 30996d11d135SLee Jones }, 31003df57bcfSMattias Nilsson }; 31013df57bcfSMattias Nilsson 3102c280f45fSUlf Hansson static void db8500_prcmu_update_cpufreq(void) 3103c280f45fSUlf Hansson { 3104c280f45fSUlf Hansson if (prcmu_has_arm_maxopp()) { 3105c280f45fSUlf Hansson db8500_cpufreq_table[3].frequency = 1000000; 3106c280f45fSUlf Hansson db8500_cpufreq_table[3].index = ARM_MAX_OPP; 3107c280f45fSUlf Hansson } 3108c280f45fSUlf Hansson } 3109c280f45fSUlf Hansson 311055b175d7SArnd Bergmann static int db8500_prcmu_register_ab8500(struct device *parent, 311155b175d7SArnd Bergmann struct ab8500_platform_data *pdata, 311255b175d7SArnd Bergmann int irq) 311355b175d7SArnd Bergmann { 311455b175d7SArnd Bergmann struct resource ab8500_resource = DEFINE_RES_IRQ(irq); 311555b175d7SArnd Bergmann struct mfd_cell ab8500_cell = { 311655b175d7SArnd Bergmann .name = "ab8500-core", 311755b175d7SArnd Bergmann .of_compatible = "stericsson,ab8500", 311855b175d7SArnd Bergmann .id = AB8500_VERSION_AB8500, 311955b175d7SArnd Bergmann .platform_data = pdata, 312055b175d7SArnd Bergmann .pdata_size = sizeof(struct ab8500_platform_data), 312155b175d7SArnd Bergmann .resources = &ab8500_resource, 312255b175d7SArnd Bergmann .num_resources = 1, 312355b175d7SArnd Bergmann }; 312455b175d7SArnd Bergmann 312555b175d7SArnd Bergmann return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL); 312655b175d7SArnd Bergmann } 312755b175d7SArnd Bergmann 31283df57bcfSMattias Nilsson /** 31293df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 31303df57bcfSMattias Nilsson * 31313df57bcfSMattias Nilsson */ 3132f791be49SBill Pemberton static int db8500_prcmu_probe(struct platform_device *pdev) 31333df57bcfSMattias Nilsson { 3134ca7edd16SLee Jones struct device_node *np = pdev->dev.of_node; 313505ec260eSLinus Walleij struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev); 313655b175d7SArnd Bergmann int irq = 0, err = 0; 313705ec260eSLinus Walleij struct resource *res; 31383df57bcfSMattias Nilsson 3139b047d981SLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); 3140b047d981SLinus Walleij if (!res) { 3141b047d981SLinus Walleij dev_err(&pdev->dev, "no prcmu memory region provided\n"); 3142b047d981SLinus Walleij return -ENOENT; 3143b047d981SLinus Walleij } 3144b047d981SLinus Walleij prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 3145b047d981SLinus Walleij if (!prcmu_base) { 3146b047d981SLinus Walleij dev_err(&pdev->dev, 3147b047d981SLinus Walleij "failed to ioremap prcmu register memory\n"); 3148b047d981SLinus Walleij return -ENOENT; 3149b047d981SLinus Walleij } 31500508901cSMattias Nilsson init_prcm_registers(); 315105ec260eSLinus Walleij dbx500_fw_version_init(pdev, pdata->version_offset); 315205ec260eSLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); 315305ec260eSLinus Walleij if (!res) { 315405ec260eSLinus Walleij dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); 315505ec260eSLinus Walleij return -ENOENT; 315605ec260eSLinus Walleij } 315705ec260eSLinus Walleij tcdm_base = devm_ioremap(&pdev->dev, res->start, 315805ec260eSLinus Walleij resource_size(res)); 315905ec260eSLinus Walleij 31603df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 3161c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 31623df57bcfSMattias Nilsson 3163ca7edd16SLee Jones irq = platform_get_irq(pdev, 0); 316405ec260eSLinus Walleij if (irq <= 0) { 316505ec260eSLinus Walleij dev_err(&pdev->dev, "no prcmu irq provided\n"); 316605ec260eSLinus Walleij return -ENOENT; 316705ec260eSLinus Walleij } 3168ca7edd16SLee Jones 3169ca7edd16SLee Jones err = request_threaded_irq(irq, prcmu_irq_handler, 31703df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 31713df57bcfSMattias Nilsson if (err < 0) { 31723df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 31733df57bcfSMattias Nilsson err = -EBUSY; 31743df57bcfSMattias Nilsson goto no_irq_return; 31753df57bcfSMattias Nilsson } 31763df57bcfSMattias Nilsson 317755b175d7SArnd Bergmann db8500_irq_init(np, pdata->irq_base); 31783a8e39c9SLee Jones 31793df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 31803df57bcfSMattias Nilsson 3181c280f45fSUlf Hansson db8500_prcmu_update_cpufreq(); 3182c280f45fSUlf Hansson 3183d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs, 3184d98a5384SLee Jones ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain); 3185ca7edd16SLee Jones if (err) { 31863df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 3187ca7edd16SLee Jones return err; 3188ca7edd16SLee Jones } 3189ca7edd16SLee Jones 3190d98a5384SLee Jones /* TODO: Remove restriction when clk definitions are available. */ 3191d98a5384SLee Jones if (!of_machine_is_compatible("st-ericsson,u8540")) { 3192d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3193d98a5384SLee Jones ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, 3194d98a5384SLee Jones db8500_irq_domain); 3195d98a5384SLee Jones if (err) { 3196d98a5384SLee Jones mfd_remove_devices(&pdev->dev); 3197d98a5384SLee Jones pr_err("prcmu: Failed to add subdevices\n"); 3198d98a5384SLee Jones goto no_irq_return; 3199d98a5384SLee Jones } 3200d98a5384SLee Jones } 3201d98a5384SLee Jones 320255b175d7SArnd Bergmann err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata, 320355b175d7SArnd Bergmann pdata->ab_irq); 320455b175d7SArnd Bergmann if (err) { 320555b175d7SArnd Bergmann mfd_remove_devices(&pdev->dev); 320655b175d7SArnd Bergmann pr_err("prcmu: Failed to add ab8500 subdevice\n"); 320755b175d7SArnd Bergmann goto no_irq_return; 320855b175d7SArnd Bergmann } 320955b175d7SArnd Bergmann 32103df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 32113df57bcfSMattias Nilsson 32123df57bcfSMattias Nilsson no_irq_return: 32133df57bcfSMattias Nilsson return err; 32143df57bcfSMattias Nilsson } 32153c144762SLee Jones static const struct of_device_id db8500_prcmu_match[] = { 32163c144762SLee Jones { .compatible = "stericsson,db8500-prcmu"}, 32173c144762SLee Jones { }, 32183c144762SLee Jones }; 32193df57bcfSMattias Nilsson 32203df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 32213df57bcfSMattias Nilsson .driver = { 32223df57bcfSMattias Nilsson .name = "db8500-prcmu", 32233df57bcfSMattias Nilsson .owner = THIS_MODULE, 32243c144762SLee Jones .of_match_table = db8500_prcmu_match, 32253df57bcfSMattias Nilsson }, 32269fc63f67SLee Jones .probe = db8500_prcmu_probe, 32273df57bcfSMattias Nilsson }; 32283df57bcfSMattias Nilsson 32293df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 32303df57bcfSMattias Nilsson { 32319fc63f67SLee Jones return platform_driver_register(&db8500_prcmu_driver); 32323df57bcfSMattias Nilsson } 32333df57bcfSMattias Nilsson 3234a661aca4SLee Jones core_initcall(db8500_prcmu_init); 32353df57bcfSMattias Nilsson 32363df57bcfSMattias Nilsson MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 32373df57bcfSMattias Nilsson MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 32383df57bcfSMattias Nilsson MODULE_LICENSE("GPL v2"); 3239