1650c2a21SLinus Walleij /* 2650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 3650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 4650c2a21SLinus Walleij * 5650c2a21SLinus Walleij * License Terms: GNU General Public License v2 6650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9650c2a21SLinus Walleij * 10650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij */ 13650c2a21SLinus Walleij #include <linux/module.h> 143df57bcfSMattias Nilsson #include <linux/kernel.h> 153df57bcfSMattias Nilsson #include <linux/delay.h> 16650c2a21SLinus Walleij #include <linux/errno.h> 17650c2a21SLinus Walleij #include <linux/err.h> 183df57bcfSMattias Nilsson #include <linux/spinlock.h> 19650c2a21SLinus Walleij #include <linux/io.h> 203df57bcfSMattias Nilsson #include <linux/slab.h> 21650c2a21SLinus Walleij #include <linux/mutex.h> 22650c2a21SLinus Walleij #include <linux/completion.h> 233df57bcfSMattias Nilsson #include <linux/irq.h> 24650c2a21SLinus Walleij #include <linux/jiffies.h> 25650c2a21SLinus Walleij #include <linux/bitops.h> 263df57bcfSMattias Nilsson #include <linux/fs.h> 273df57bcfSMattias Nilsson #include <linux/platform_device.h> 283df57bcfSMattias Nilsson #include <linux/uaccess.h> 293df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3073180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 311032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 321032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 33cc9a0f68SDaniel Lezcano #include <asm/hardware/gic.h> 34650c2a21SLinus Walleij #include <mach/hardware.h> 353df57bcfSMattias Nilsson #include <mach/irqs.h> 363df57bcfSMattias Nilsson #include <mach/db8500-regs.h> 373df57bcfSMattias Nilsson #include <mach/id.h> 3873180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 39650c2a21SLinus Walleij 403df57bcfSMattias Nilsson /* Offset for the firmware version within the TCPM */ 413df57bcfSMattias Nilsson #define PRCMU_FW_VERSION_OFFSET 0xA4 42650c2a21SLinus Walleij 433df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 443df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 453df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 463df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 473df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 483df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 493df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 503df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 513df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 523df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 533df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 543df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 553df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 563df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 573df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 58650c2a21SLinus Walleij 593df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 603df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 613df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 623df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 63650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 64650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 65650c2a21SLinus Walleij 663df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 673df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 683df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 693df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 70650c2a21SLinus Walleij 713df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 723df57bcfSMattias Nilsson 733df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 743df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 753df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 793df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 803df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 813df57bcfSMattias Nilsson 823df57bcfSMattias Nilsson /* Req Mailboxes */ 833df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 843df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 853df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 863df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 873df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 883df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 893df57bcfSMattias Nilsson 903df57bcfSMattias Nilsson /* Ack Mailboxes */ 913df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 923df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 933df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 943df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 953df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 963df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 973df57bcfSMattias Nilsson 983df57bcfSMattias Nilsson /* Mailbox 0 headers */ 993df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 1003df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 1013df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 1023df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1033df57bcfSMattias Nilsson 1043df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1053df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1063df57bcfSMattias Nilsson 1073df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1083df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1093df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1113df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1123df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1133df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1143df57bcfSMattias Nilsson 1153df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1163df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1173df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1213df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1223df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1233df57bcfSMattias Nilsson 1243df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1253df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1263df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1273df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1283df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1293df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 130a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1313df57bcfSMattias Nilsson 1323df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1333df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1343df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 135a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 1366b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1 1376b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2 138a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 139a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1403df57bcfSMattias Nilsson 1413df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1423df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1433df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1443df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1453df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1463df57bcfSMattias Nilsson 1473df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1483df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1493df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1503df57bcfSMattias Nilsson 1513df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1523df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1533df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1603df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1613df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1623df57bcfSMattias Nilsson 1633df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1643df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1653df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1663df57bcfSMattias Nilsson 1673df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1683df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1693df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1703df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1713df57bcfSMattias Nilsson 1723df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1733df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1743df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1783df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1793df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1803df57bcfSMattias Nilsson 1813df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1823df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1833df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1843df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1853df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1863df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 187a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 188a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 190a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 191a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1923df57bcfSMattias Nilsson 1933df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1943df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1953df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 2003df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 2013df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 2023df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2033df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 204a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 205a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 206a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 207a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 208a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 209a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 210a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2113df57bcfSMattias Nilsson 2123df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2133df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2143df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2153df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2163df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2173df57bcfSMattias Nilsson #define PRCMU_I2C_WRITE(slave) \ 2183df57bcfSMattias Nilsson (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2193df57bcfSMattias Nilsson #define PRCMU_I2C_READ(slave) \ 2203df57bcfSMattias Nilsson (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2213df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2223df57bcfSMattias Nilsson 2233df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2243df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2253df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2263df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2273df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2283df57bcfSMattias Nilsson 2293df57bcfSMattias Nilsson #define NUM_MB 8 2303df57bcfSMattias Nilsson #define MBOX_BIT BIT 2313df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2323df57bcfSMattias Nilsson 2333df57bcfSMattias Nilsson /* 2343df57bcfSMattias Nilsson * Wakeups/IRQs 2353df57bcfSMattias Nilsson */ 2363df57bcfSMattias Nilsson 2373df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2383df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2623df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2633df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2643df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2653df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2663df57bcfSMattias Nilsson 267b58d12feSMattias Nilsson static struct { 268b58d12feSMattias Nilsson bool valid; 269b58d12feSMattias Nilsson struct prcmu_fw_version version; 270b58d12feSMattias Nilsson } fw_info; 271b58d12feSMattias Nilsson 2723df57bcfSMattias Nilsson /* 2733df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2743df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2753df57bcfSMattias Nilsson * 2763df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2773df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2783df57bcfSMattias Nilsson * around, to further complicate matters.) 2793df57bcfSMattias Nilsson */ 2803df57bcfSMattias Nilsson #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) 2813df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 2823df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 2833df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 2843df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 2853df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 2863df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 2873df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 2883df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 2893df57bcfSMattias Nilsson IRQ_ENTRY(USB), 2903df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 2913df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 2923df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 2933df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 2943df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 2953df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 2963df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 2973df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 2983df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 2993df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 3003df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 3013df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 3023df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3033df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3043df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3053df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 306650c2a21SLinus Walleij }; 307650c2a21SLinus Walleij 3083df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3093df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3103df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3113df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3123df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3133df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3143df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3153df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3163df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3173df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3183df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3193df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3203df57bcfSMattias Nilsson }; 3213df57bcfSMattias Nilsson 3223df57bcfSMattias Nilsson /* 3233df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3243df57bcfSMattias Nilsson * @lock: The transaction lock. 3253df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3263df57bcfSMattias Nilsson * the request data. 3273df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3283df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3293df57bcfSMattias Nilsson */ 3303df57bcfSMattias Nilsson static struct { 3313df57bcfSMattias Nilsson spinlock_t lock; 3323df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3333df57bcfSMattias Nilsson struct work_struct mask_work; 3343df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3353df57bcfSMattias Nilsson struct completion ac_wake_work; 3363df57bcfSMattias Nilsson struct { 3373df57bcfSMattias Nilsson u32 dbb_irqs; 3383df57bcfSMattias Nilsson u32 dbb_wakeups; 3393df57bcfSMattias Nilsson u32 abb_events; 3403df57bcfSMattias Nilsson } req; 3413df57bcfSMattias Nilsson } mb0_transfer; 3423df57bcfSMattias Nilsson 3433df57bcfSMattias Nilsson /* 3443df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3453df57bcfSMattias Nilsson * @lock: The transaction lock. 3463df57bcfSMattias Nilsson * @work: The transaction completion structure. 3474d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP. 3483df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3493df57bcfSMattias Nilsson */ 350650c2a21SLinus Walleij static struct { 351650c2a21SLinus Walleij struct mutex lock; 352650c2a21SLinus Walleij struct completion work; 3534d64d2e3SMattias Nilsson u8 ape_opp; 354650c2a21SLinus Walleij struct { 3553df57bcfSMattias Nilsson u8 header; 356650c2a21SLinus Walleij u8 arm_opp; 357650c2a21SLinus Walleij u8 ape_opp; 3583df57bcfSMattias Nilsson u8 ape_voltage_status; 359650c2a21SLinus Walleij } ack; 360650c2a21SLinus Walleij } mb1_transfer; 361650c2a21SLinus Walleij 3623df57bcfSMattias Nilsson /* 3633df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3643df57bcfSMattias Nilsson * @lock: The transaction lock. 3653df57bcfSMattias Nilsson * @work: The transaction completion structure. 3663df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3673df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3683df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3693df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3703df57bcfSMattias Nilsson */ 371650c2a21SLinus Walleij static struct { 372650c2a21SLinus Walleij struct mutex lock; 373650c2a21SLinus Walleij struct completion work; 3743df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 3753df57bcfSMattias Nilsson bool auto_pm_enabled; 3763df57bcfSMattias Nilsson struct { 3773df57bcfSMattias Nilsson u8 status; 3783df57bcfSMattias Nilsson } ack; 3793df57bcfSMattias Nilsson } mb2_transfer; 3803df57bcfSMattias Nilsson 3813df57bcfSMattias Nilsson /* 3823df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 3833df57bcfSMattias Nilsson * @lock: The request lock. 3843df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 3853df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 3863df57bcfSMattias Nilsson */ 3873df57bcfSMattias Nilsson static struct { 3883df57bcfSMattias Nilsson spinlock_t lock; 3893df57bcfSMattias Nilsson struct mutex sysclk_lock; 3903df57bcfSMattias Nilsson struct completion sysclk_work; 3913df57bcfSMattias Nilsson } mb3_transfer; 3923df57bcfSMattias Nilsson 3933df57bcfSMattias Nilsson /* 3943df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 3953df57bcfSMattias Nilsson * @lock: The transaction lock. 3963df57bcfSMattias Nilsson * @work: The transaction completion structure. 3973df57bcfSMattias Nilsson */ 3983df57bcfSMattias Nilsson static struct { 3993df57bcfSMattias Nilsson struct mutex lock; 4003df57bcfSMattias Nilsson struct completion work; 4013df57bcfSMattias Nilsson } mb4_transfer; 4023df57bcfSMattias Nilsson 4033df57bcfSMattias Nilsson /* 4043df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4053df57bcfSMattias Nilsson * @lock: The transaction lock. 4063df57bcfSMattias Nilsson * @work: The transaction completion structure. 4073df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4083df57bcfSMattias Nilsson */ 4093df57bcfSMattias Nilsson static struct { 4103df57bcfSMattias Nilsson struct mutex lock; 4113df57bcfSMattias Nilsson struct completion work; 412650c2a21SLinus Walleij struct { 413650c2a21SLinus Walleij u8 status; 414650c2a21SLinus Walleij u8 value; 415650c2a21SLinus Walleij } ack; 416650c2a21SLinus Walleij } mb5_transfer; 417650c2a21SLinus Walleij 4183df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4193df57bcfSMattias Nilsson 4203df57bcfSMattias Nilsson /* Spinlocks */ 421b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock); 4223df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4233df57bcfSMattias Nilsson 4243df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4253df57bcfSMattias Nilsson static __iomem void *tcdm_base; 4263df57bcfSMattias Nilsson 4273df57bcfSMattias Nilsson struct clk_mgt { 4286b6fae2bSMattias Nilsson void __iomem *reg; 4293df57bcfSMattias Nilsson u32 pllsw; 4306b6fae2bSMattias Nilsson int branch; 4316b6fae2bSMattias Nilsson bool clk38div; 4326b6fae2bSMattias Nilsson }; 4336b6fae2bSMattias Nilsson 4346b6fae2bSMattias Nilsson enum { 4356b6fae2bSMattias Nilsson PLL_RAW, 4366b6fae2bSMattias Nilsson PLL_FIX, 4376b6fae2bSMattias Nilsson PLL_DIV 4383df57bcfSMattias Nilsson }; 4393df57bcfSMattias Nilsson 4403df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4413df57bcfSMattias Nilsson 4426b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 4436b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 4443df57bcfSMattias Nilsson struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4456b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 4466b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 4476b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 4486b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 4496b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 4506b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 4516b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 4526b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 4536b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 4546b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 4556b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 4566b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 4576b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 4586b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 4596b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 4606b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 4616b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 4626b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 4636b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 4646b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 4656b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 4666b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 4676b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 4686b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 4696b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 4706b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 4736b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 4746b6fae2bSMattias Nilsson }; 4756b6fae2bSMattias Nilsson 4766b6fae2bSMattias Nilsson struct dsiclk { 4776b6fae2bSMattias Nilsson u32 divsel_mask; 4786b6fae2bSMattias Nilsson u32 divsel_shift; 4796b6fae2bSMattias Nilsson u32 divsel; 4806b6fae2bSMattias Nilsson }; 4816b6fae2bSMattias Nilsson 4826b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = { 4836b6fae2bSMattias Nilsson { 4846b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 4856b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 4866b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4876b6fae2bSMattias Nilsson }, 4886b6fae2bSMattias Nilsson { 4896b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 4906b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 4916b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4926b6fae2bSMattias Nilsson } 4936b6fae2bSMattias Nilsson }; 4946b6fae2bSMattias Nilsson 4956b6fae2bSMattias Nilsson struct dsiescclk { 4966b6fae2bSMattias Nilsson u32 en; 4976b6fae2bSMattias Nilsson u32 div_mask; 4986b6fae2bSMattias Nilsson u32 div_shift; 4996b6fae2bSMattias Nilsson }; 5006b6fae2bSMattias Nilsson 5016b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = { 5026b6fae2bSMattias Nilsson { 5036b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 5046b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 5056b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 5066b6fae2bSMattias Nilsson }, 5076b6fae2bSMattias Nilsson { 5086b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 5096b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 5106b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 5116b6fae2bSMattias Nilsson }, 5126b6fae2bSMattias Nilsson { 5136b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 5146b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 5156b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 5166b6fae2bSMattias Nilsson } 5173df57bcfSMattias Nilsson }; 5183df57bcfSMattias Nilsson 5190837bb72SMattias Nilsson static struct regulator *hwacc_regulator[NUM_HW_ACC]; 5200837bb72SMattias Nilsson static struct regulator *hwacc_ret_regulator[NUM_HW_ACC]; 5210837bb72SMattias Nilsson 5220837bb72SMattias Nilsson static bool hwacc_enabled[NUM_HW_ACC]; 5230837bb72SMattias Nilsson static bool hwacc_ret_enabled[NUM_HW_ACC]; 5240837bb72SMattias Nilsson 5250837bb72SMattias Nilsson static const char *hwacc_regulator_name[NUM_HW_ACC] = { 5260837bb72SMattias Nilsson [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp", 5270837bb72SMattias Nilsson [HW_ACC_SVAPIPE] = "hwacc-sva-pipe", 5280837bb72SMattias Nilsson [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp", 5290837bb72SMattias Nilsson [HW_ACC_SIAPIPE] = "hwacc-sia-pipe", 5300837bb72SMattias Nilsson [HW_ACC_SGA] = "hwacc-sga", 5310837bb72SMattias Nilsson [HW_ACC_B2R2] = "hwacc-b2r2", 5320837bb72SMattias Nilsson [HW_ACC_MCDE] = "hwacc-mcde", 5330837bb72SMattias Nilsson [HW_ACC_ESRAM1] = "hwacc-esram1", 5340837bb72SMattias Nilsson [HW_ACC_ESRAM2] = "hwacc-esram2", 5350837bb72SMattias Nilsson [HW_ACC_ESRAM3] = "hwacc-esram3", 5360837bb72SMattias Nilsson [HW_ACC_ESRAM4] = "hwacc-esram4", 5370837bb72SMattias Nilsson }; 5380837bb72SMattias Nilsson 5390837bb72SMattias Nilsson static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { 5400837bb72SMattias Nilsson [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp-ret", 5410837bb72SMattias Nilsson [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp-ret", 5420837bb72SMattias Nilsson [HW_ACC_ESRAM1] = "hwacc-esram1-ret", 5430837bb72SMattias Nilsson [HW_ACC_ESRAM2] = "hwacc-esram2-ret", 5440837bb72SMattias Nilsson [HW_ACC_ESRAM3] = "hwacc-esram3-ret", 5450837bb72SMattias Nilsson [HW_ACC_ESRAM4] = "hwacc-esram4-ret", 5460837bb72SMattias Nilsson }; 5470837bb72SMattias Nilsson 5483df57bcfSMattias Nilsson /* 5493df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 5503df57bcfSMattias Nilsson */ 5513df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 5523df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 5533df57bcfSMattias Nilsson 5543df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 5553df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 5563df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5573df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5583df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5593df57bcfSMattias Nilsson 5603df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5613df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5623df57bcfSMattias Nilsson 5633df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5643df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5653df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5663df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5673df57bcfSMattias Nilsson 5683df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5693df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5703df57bcfSMattias Nilsson 5713df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5723df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5733df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5743df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5753df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5763df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5773df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5783df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5793df57bcfSMattias Nilsson 5803df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5813df57bcfSMattias Nilsson 58273180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5833df57bcfSMattias Nilsson { 5843df57bcfSMattias Nilsson int i; 5853df57bcfSMattias Nilsson 5863df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 587c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5883df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 589c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5903df57bcfSMattias Nilsson 5913df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 592c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 593c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5943df57bcfSMattias Nilsson /* Enable Escape clocks */ 595c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5963df57bcfSMattias Nilsson 5973df57bcfSMattias Nilsson /* Start DSI PLL */ 598c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5993df57bcfSMattias Nilsson /* Reset DSI PLL */ 600c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 6013df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 602c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 6033df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 6043df57bcfSMattias Nilsson break; 6053df57bcfSMattias Nilsson udelay(100); 6063df57bcfSMattias Nilsson } 6073df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 608c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 6093df57bcfSMattias Nilsson return 0; 6103df57bcfSMattias Nilsson } 6113df57bcfSMattias Nilsson 61273180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 6133df57bcfSMattias Nilsson { 6143df57bcfSMattias Nilsson /* Disable dsi pll */ 615c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 6163df57bcfSMattias Nilsson /* Disable escapeclock */ 617c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 6183df57bcfSMattias Nilsson return 0; 6193df57bcfSMattias Nilsson } 6203df57bcfSMattias Nilsson 62173180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 6223df57bcfSMattias Nilsson { 6233df57bcfSMattias Nilsson unsigned long flags; 6243df57bcfSMattias Nilsson 6253df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 6263df57bcfSMattias Nilsson 6273df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 628c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 6293df57bcfSMattias Nilsson cpu_relax(); 6303df57bcfSMattias Nilsson 631c72fe851SDaniel Willerud writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); 632c553b3caSMattias Nilsson writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); 633c553b3caSMattias Nilsson writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); 6343df57bcfSMattias Nilsson 6353df57bcfSMattias Nilsson /* Release the HW semaphore. */ 636c553b3caSMattias Nilsson writel(0, PRCM_SEM); 6373df57bcfSMattias Nilsson 6383df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 6393df57bcfSMattias Nilsson 6403df57bcfSMattias Nilsson return 0; 6413df57bcfSMattias Nilsson } 6423df57bcfSMattias Nilsson 643b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg) 6443df57bcfSMattias Nilsson { 645b4a6dbd5SMattias Nilsson return readl(_PRCMU_BASE + reg); 6463df57bcfSMattias Nilsson } 6473df57bcfSMattias Nilsson 648b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value) 6493df57bcfSMattias Nilsson { 6503df57bcfSMattias Nilsson unsigned long flags; 6513df57bcfSMattias Nilsson 652b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 653b4a6dbd5SMattias Nilsson writel(value, (_PRCMU_BASE + reg)); 654b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 655b4a6dbd5SMattias Nilsson } 656b4a6dbd5SMattias Nilsson 657b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 658b4a6dbd5SMattias Nilsson { 659b4a6dbd5SMattias Nilsson u32 val; 660b4a6dbd5SMattias Nilsson unsigned long flags; 661b4a6dbd5SMattias Nilsson 662b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 663b4a6dbd5SMattias Nilsson val = readl(_PRCMU_BASE + reg); 664b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask)); 665b4a6dbd5SMattias Nilsson writel(val, (_PRCMU_BASE + reg)); 666b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 6673df57bcfSMattias Nilsson } 6683df57bcfSMattias Nilsson 669b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void) 670b58d12feSMattias Nilsson { 671b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL; 672b58d12feSMattias Nilsson } 673b58d12feSMattias Nilsson 6743df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6753df57bcfSMattias Nilsson { 6763df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6773df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6783df57bcfSMattias Nilsson } 6793df57bcfSMattias Nilsson 6803df57bcfSMattias Nilsson /** 6813df57bcfSMattias Nilsson * prcmu_get_boot_status - PRCMU boot status checking 6823df57bcfSMattias Nilsson * Returns: the current PRCMU boot status 6833df57bcfSMattias Nilsson */ 6843df57bcfSMattias Nilsson int prcmu_get_boot_status(void) 6853df57bcfSMattias Nilsson { 6863df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_BOOT_STATUS); 6873df57bcfSMattias Nilsson } 6883df57bcfSMattias Nilsson 6893df57bcfSMattias Nilsson /** 6903df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6913df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6923df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6933df57bcfSMattias Nilsson * 6943df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6953df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6963df57bcfSMattias Nilsson */ 6973df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6983df57bcfSMattias Nilsson { 6993df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 7003df57bcfSMattias Nilsson return -EINVAL; 7013df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 7023df57bcfSMattias Nilsson return 0; 7033df57bcfSMattias Nilsson } 7043df57bcfSMattias Nilsson 7053df57bcfSMattias Nilsson /** 7063df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 7073df57bcfSMattias Nilsson * Returns: the power transition that has last happened 7083df57bcfSMattias Nilsson * 7093df57bcfSMattias Nilsson * This function can return the following transitions- 7103df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 7113df57bcfSMattias Nilsson */ 7123df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 7133df57bcfSMattias Nilsson { 7143df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 7153df57bcfSMattias Nilsson } 7163df57bcfSMattias Nilsson 7173df57bcfSMattias Nilsson /** 7183df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 7193df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 7203df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 7213df57bcfSMattias Nilsson */ 7223df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 7233df57bcfSMattias Nilsson { 7243df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 7253df57bcfSMattias Nilsson } 7263df57bcfSMattias Nilsson 7273df57bcfSMattias Nilsson /** 7283df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 7293df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 7303df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 7313df57bcfSMattias Nilsson * @div: The divider to be applied. 7323df57bcfSMattias Nilsson * 7333df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 7343df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 7353df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 7363df57bcfSMattias Nilsson */ 7373df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 7383df57bcfSMattias Nilsson { 7393df57bcfSMattias Nilsson static int requests[2]; 7403df57bcfSMattias Nilsson int r = 0; 7413df57bcfSMattias Nilsson unsigned long flags; 7423df57bcfSMattias Nilsson u32 val; 7433df57bcfSMattias Nilsson u32 bits; 7443df57bcfSMattias Nilsson u32 mask; 7453df57bcfSMattias Nilsson u32 div_mask; 7463df57bcfSMattias Nilsson 7473df57bcfSMattias Nilsson BUG_ON(clkout > 1); 7483df57bcfSMattias Nilsson BUG_ON(div > 63); 7493df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 7503df57bcfSMattias Nilsson 7513df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7523df57bcfSMattias Nilsson return -EINVAL; 7533df57bcfSMattias Nilsson 7543df57bcfSMattias Nilsson switch (clkout) { 7553df57bcfSMattias Nilsson case 0: 7563df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7573df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7583df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7593df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 7603df57bcfSMattias Nilsson break; 7613df57bcfSMattias Nilsson case 1: 7623df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7633df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7643df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7653df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7663df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7673df57bcfSMattias Nilsson break; 7683df57bcfSMattias Nilsson } 7693df57bcfSMattias Nilsson bits &= mask; 7703df57bcfSMattias Nilsson 7713df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7723df57bcfSMattias Nilsson 773c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7743df57bcfSMattias Nilsson if (val & div_mask) { 7753df57bcfSMattias Nilsson if (div) { 7763df57bcfSMattias Nilsson if ((val & mask) != bits) { 7773df57bcfSMattias Nilsson r = -EBUSY; 7783df57bcfSMattias Nilsson goto unlock_and_return; 7793df57bcfSMattias Nilsson } 7803df57bcfSMattias Nilsson } else { 7813df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7823df57bcfSMattias Nilsson r = -EINVAL; 7833df57bcfSMattias Nilsson goto unlock_and_return; 7843df57bcfSMattias Nilsson } 7853df57bcfSMattias Nilsson } 7863df57bcfSMattias Nilsson } 787c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7883df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7893df57bcfSMattias Nilsson 7903df57bcfSMattias Nilsson unlock_and_return: 7913df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7923df57bcfSMattias Nilsson 7933df57bcfSMattias Nilsson return r; 7943df57bcfSMattias Nilsson } 7953df57bcfSMattias Nilsson 79673180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7973df57bcfSMattias Nilsson { 7983df57bcfSMattias Nilsson unsigned long flags; 7993df57bcfSMattias Nilsson 8003df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 8013df57bcfSMattias Nilsson 8023df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8033df57bcfSMattias Nilsson 804c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 8053df57bcfSMattias Nilsson cpu_relax(); 8063df57bcfSMattias Nilsson 8073df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 8083df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 8093df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 8103df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 8113df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 8123df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 813c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8143df57bcfSMattias Nilsson 8153df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8163df57bcfSMattias Nilsson 8173df57bcfSMattias Nilsson return 0; 8183df57bcfSMattias Nilsson } 8193df57bcfSMattias Nilsson 8204d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void) 8214d64d2e3SMattias Nilsson { 8224d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 8234d64d2e3SMattias Nilsson } 8244d64d2e3SMattias Nilsson 825485540dcSDaniel Lezcano /* This function decouple the gic from the prcmu */ 826485540dcSDaniel Lezcano int db8500_prcmu_gic_decouple(void) 827485540dcSDaniel Lezcano { 828801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 829485540dcSDaniel Lezcano 830485540dcSDaniel Lezcano /* Set bit 0 register value to 1 */ 831801448e0SDaniel Lezcano writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, 832801448e0SDaniel Lezcano PRCM_A9_MASK_REQ); 833485540dcSDaniel Lezcano 834485540dcSDaniel Lezcano /* Make sure the register is updated */ 835801448e0SDaniel Lezcano readl(PRCM_A9_MASK_REQ); 836485540dcSDaniel Lezcano 837485540dcSDaniel Lezcano /* Wait a few cycles for the gic mask completion */ 838801448e0SDaniel Lezcano udelay(1); 839485540dcSDaniel Lezcano 840485540dcSDaniel Lezcano return 0; 841485540dcSDaniel Lezcano } 842485540dcSDaniel Lezcano 843485540dcSDaniel Lezcano /* This function recouple the gic with the prcmu */ 844485540dcSDaniel Lezcano int db8500_prcmu_gic_recouple(void) 845485540dcSDaniel Lezcano { 846801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 847485540dcSDaniel Lezcano 848485540dcSDaniel Lezcano /* Set bit 0 register value to 0 */ 849801448e0SDaniel Lezcano writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); 850485540dcSDaniel Lezcano 851485540dcSDaniel Lezcano return 0; 852485540dcSDaniel Lezcano } 853485540dcSDaniel Lezcano 854cc9a0f68SDaniel Lezcano #define PRCMU_GIC_NUMBER_REGS 5 855cc9a0f68SDaniel Lezcano 856cc9a0f68SDaniel Lezcano /* 857cc9a0f68SDaniel Lezcano * This function checks if there are pending irq on the gic. It only 858cc9a0f68SDaniel Lezcano * makes sense if the gic has been decoupled before with the 859cc9a0f68SDaniel Lezcano * db8500_prcmu_gic_decouple function. Disabling an interrupt only 860cc9a0f68SDaniel Lezcano * disables the forwarding of the interrupt to any CPU interface. It 861cc9a0f68SDaniel Lezcano * does not prevent the interrupt from changing state, for example 862cc9a0f68SDaniel Lezcano * becoming pending, or active and pending if it is already 863cc9a0f68SDaniel Lezcano * active. Hence, we have to check the interrupt is pending *and* is 864cc9a0f68SDaniel Lezcano * active. 865cc9a0f68SDaniel Lezcano */ 866cc9a0f68SDaniel Lezcano bool db8500_prcmu_gic_pending_irq(void) 867cc9a0f68SDaniel Lezcano { 868cc9a0f68SDaniel Lezcano u32 pr; /* Pending register */ 869cc9a0f68SDaniel Lezcano u32 er; /* Enable register */ 870cc9a0f68SDaniel Lezcano void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 871cc9a0f68SDaniel Lezcano int i; 872cc9a0f68SDaniel Lezcano 873cc9a0f68SDaniel Lezcano /* 5 registers. STI & PPI not skipped */ 874cc9a0f68SDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { 875cc9a0f68SDaniel Lezcano 876cc9a0f68SDaniel Lezcano pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); 877cc9a0f68SDaniel Lezcano er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 878cc9a0f68SDaniel Lezcano 879cc9a0f68SDaniel Lezcano if (pr & er) 880cc9a0f68SDaniel Lezcano return true; /* There is a pending interrupt */ 881cc9a0f68SDaniel Lezcano } 882cc9a0f68SDaniel Lezcano 883cc9a0f68SDaniel Lezcano return false; 884cc9a0f68SDaniel Lezcano } 885cc9a0f68SDaniel Lezcano 8869f60d33eSDaniel Lezcano /* 8879ab492e1SDaniel Lezcano * This function checks if there are pending interrupt on the 8889ab492e1SDaniel Lezcano * prcmu which has been delegated to monitor the irqs with the 8899ab492e1SDaniel Lezcano * db8500_prcmu_copy_gic_settings function. 8909ab492e1SDaniel Lezcano */ 8919ab492e1SDaniel Lezcano bool db8500_prcmu_pending_irq(void) 8929ab492e1SDaniel Lezcano { 8939ab492e1SDaniel Lezcano u32 it, im; 8949ab492e1SDaniel Lezcano int i; 8959ab492e1SDaniel Lezcano 8969ab492e1SDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 8979ab492e1SDaniel Lezcano it = readl(PRCM_ARMITVAL31TO0 + i * 4); 8989ab492e1SDaniel Lezcano im = readl(PRCM_ARMITMSK31TO0 + i * 4); 8999ab492e1SDaniel Lezcano if (it & im) 9009ab492e1SDaniel Lezcano return true; /* There is a pending interrupt */ 9019ab492e1SDaniel Lezcano } 9029ab492e1SDaniel Lezcano 9039ab492e1SDaniel Lezcano return false; 9049ab492e1SDaniel Lezcano } 9059ab492e1SDaniel Lezcano 9069ab492e1SDaniel Lezcano /* 9079f60d33eSDaniel Lezcano * This function copies the gic SPI settings to the prcmu in order to 9089f60d33eSDaniel Lezcano * monitor them and abort/finish the retention/off sequence or state. 9099f60d33eSDaniel Lezcano */ 9109f60d33eSDaniel Lezcano int db8500_prcmu_copy_gic_settings(void) 9119f60d33eSDaniel Lezcano { 9129f60d33eSDaniel Lezcano u32 er; /* Enable register */ 9139f60d33eSDaniel Lezcano void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 9149f60d33eSDaniel Lezcano int i; 9159f60d33eSDaniel Lezcano 9169f60d33eSDaniel Lezcano /* We skip the STI and PPI */ 9179f60d33eSDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 9189f60d33eSDaniel Lezcano er = readl_relaxed(dist_base + 9199f60d33eSDaniel Lezcano GIC_DIST_ENABLE_SET + (i + 1) * 4); 9209f60d33eSDaniel Lezcano writel(er, PRCM_ARMITMSK31TO0 + i * 4); 9219f60d33eSDaniel Lezcano } 9229f60d33eSDaniel Lezcano 9239f60d33eSDaniel Lezcano return 0; 9249f60d33eSDaniel Lezcano } 9259f60d33eSDaniel Lezcano 9263df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 9273df57bcfSMattias Nilsson static void config_wakeups(void) 9283df57bcfSMattias Nilsson { 9293df57bcfSMattias Nilsson const u8 header[2] = { 9303df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 9313df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 9323df57bcfSMattias Nilsson }; 9333df57bcfSMattias Nilsson static u32 last_dbb_events; 9343df57bcfSMattias Nilsson static u32 last_abb_events; 9353df57bcfSMattias Nilsson u32 dbb_events; 9363df57bcfSMattias Nilsson u32 abb_events; 9373df57bcfSMattias Nilsson unsigned int i; 9383df57bcfSMattias Nilsson 9393df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 9403df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 9413df57bcfSMattias Nilsson 9423df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 9433df57bcfSMattias Nilsson 9443df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 9453df57bcfSMattias Nilsson return; 9463df57bcfSMattias Nilsson 9473df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 948c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 9493df57bcfSMattias Nilsson cpu_relax(); 9503df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 9513df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 9523df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 953c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 9543df57bcfSMattias Nilsson } 9553df57bcfSMattias Nilsson last_dbb_events = dbb_events; 9563df57bcfSMattias Nilsson last_abb_events = abb_events; 9573df57bcfSMattias Nilsson } 9583df57bcfSMattias Nilsson 95973180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 9603df57bcfSMattias Nilsson { 9613df57bcfSMattias Nilsson unsigned long flags; 9623df57bcfSMattias Nilsson u32 bits; 9633df57bcfSMattias Nilsson int i; 9643df57bcfSMattias Nilsson 9653df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 9663df57bcfSMattias Nilsson 9673df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 9683df57bcfSMattias Nilsson if (wakeups & BIT(i)) 9693df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 9703df57bcfSMattias Nilsson } 9713df57bcfSMattias Nilsson 9723df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9733df57bcfSMattias Nilsson 9743df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 9753df57bcfSMattias Nilsson config_wakeups(); 9763df57bcfSMattias Nilsson 9773df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9783df57bcfSMattias Nilsson } 9793df57bcfSMattias Nilsson 98073180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 9813df57bcfSMattias Nilsson { 9823df57bcfSMattias Nilsson unsigned long flags; 9833df57bcfSMattias Nilsson 9843df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9853df57bcfSMattias Nilsson 9863df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 9873df57bcfSMattias Nilsson config_wakeups(); 9883df57bcfSMattias Nilsson 9893df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9903df57bcfSMattias Nilsson } 9913df57bcfSMattias Nilsson 99273180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 9933df57bcfSMattias Nilsson { 9943df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 9953df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 9963df57bcfSMattias Nilsson else 9973df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 9983df57bcfSMattias Nilsson } 9993df57bcfSMattias Nilsson 10003df57bcfSMattias Nilsson /** 100173180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 10023df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 10033df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10043df57bcfSMattias Nilsson * 10053df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 10063df57bcfSMattias Nilsson */ 100773180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 10083df57bcfSMattias Nilsson { 10093df57bcfSMattias Nilsson int r; 10103df57bcfSMattias Nilsson 10113df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 10123df57bcfSMattias Nilsson return -EINVAL; 10133df57bcfSMattias Nilsson 10143df57bcfSMattias Nilsson r = 0; 10153df57bcfSMattias Nilsson 10163df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10173df57bcfSMattias Nilsson 1018c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10193df57bcfSMattias Nilsson cpu_relax(); 10203df57bcfSMattias Nilsson 10213df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10223df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 10233df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 10243df57bcfSMattias Nilsson 1025c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10263df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10273df57bcfSMattias Nilsson 10283df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 10293df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 10303df57bcfSMattias Nilsson r = -EIO; 10313df57bcfSMattias Nilsson 10323df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10333df57bcfSMattias Nilsson 10343df57bcfSMattias Nilsson return r; 10353df57bcfSMattias Nilsson } 10363df57bcfSMattias Nilsson 10373df57bcfSMattias Nilsson /** 103873180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 10393df57bcfSMattias Nilsson * 10403df57bcfSMattias Nilsson * Returns: the current ARM OPP 10413df57bcfSMattias Nilsson */ 104273180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 10433df57bcfSMattias Nilsson { 10443df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 10453df57bcfSMattias Nilsson } 10463df57bcfSMattias Nilsson 10473df57bcfSMattias Nilsson /** 10480508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP 10493df57bcfSMattias Nilsson * 10503df57bcfSMattias Nilsson * Returns: the current DDR OPP 10513df57bcfSMattias Nilsson */ 10520508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void) 10533df57bcfSMattias Nilsson { 1054c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 10553df57bcfSMattias Nilsson } 10563df57bcfSMattias Nilsson 10573df57bcfSMattias Nilsson /** 10580508901cSMattias Nilsson * db8500_set_ddr_opp - set the appropriate DDR OPP 10593df57bcfSMattias Nilsson * @opp: The new DDR operating point to which transition is to be made 10603df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10613df57bcfSMattias Nilsson * 10623df57bcfSMattias Nilsson * This function sets the operating point of the DDR. 10633df57bcfSMattias Nilsson */ 10640508901cSMattias Nilsson int db8500_prcmu_set_ddr_opp(u8 opp) 10653df57bcfSMattias Nilsson { 10663df57bcfSMattias Nilsson if (opp < DDR_100_OPP || opp > DDR_25_OPP) 10673df57bcfSMattias Nilsson return -EINVAL; 10683df57bcfSMattias Nilsson /* Changing the DDR OPP can hang the hardware pre-v21 */ 10693df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) 1070c553b3caSMattias Nilsson writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 10713df57bcfSMattias Nilsson 10723df57bcfSMattias Nilsson return 0; 10733df57bcfSMattias Nilsson } 10746b6fae2bSMattias Nilsson 10754d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 10764d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable) 10774d64d2e3SMattias Nilsson { 10784d64d2e3SMattias Nilsson void __iomem *clock_reg[] = { 10794d64d2e3SMattias Nilsson PRCM_ACLK_MGT, 10804d64d2e3SMattias Nilsson PRCM_DMACLK_MGT 10814d64d2e3SMattias Nilsson }; 10824d64d2e3SMattias Nilsson unsigned long flags; 10834d64d2e3SMattias Nilsson unsigned int i; 10844d64d2e3SMattias Nilsson 10854d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 10864d64d2e3SMattias Nilsson 10874d64d2e3SMattias Nilsson /* Grab the HW semaphore. */ 10884d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 10894d64d2e3SMattias Nilsson cpu_relax(); 10904d64d2e3SMattias Nilsson 10914d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 10924d64d2e3SMattias Nilsson u32 val; 10934d64d2e3SMattias Nilsson u32 div; 10944d64d2e3SMattias Nilsson 10954d64d2e3SMattias Nilsson val = readl(clock_reg[i]); 10964d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 10974d64d2e3SMattias Nilsson if (enable) { 10984d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) { 10994d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n", 11004d64d2e3SMattias Nilsson div, __func__); 11014d64d2e3SMattias Nilsson goto unlock_and_return; 11024d64d2e3SMattias Nilsson } 11034d64d2e3SMattias Nilsson div <<= 1; 11044d64d2e3SMattias Nilsson } else { 11054d64d2e3SMattias Nilsson if (div <= 2) 11064d64d2e3SMattias Nilsson goto unlock_and_return; 11074d64d2e3SMattias Nilsson div >>= 1; 11084d64d2e3SMattias Nilsson } 11094d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 11104d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 11114d64d2e3SMattias Nilsson writel(val, clock_reg[i]); 11124d64d2e3SMattias Nilsson } 11134d64d2e3SMattias Nilsson 11144d64d2e3SMattias Nilsson unlock_and_return: 11154d64d2e3SMattias Nilsson /* Release the HW semaphore. */ 11164d64d2e3SMattias Nilsson writel(0, PRCM_SEM); 11174d64d2e3SMattias Nilsson 11184d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 11194d64d2e3SMattias Nilsson } 11204d64d2e3SMattias Nilsson 11213df57bcfSMattias Nilsson /** 11220508901cSMattias Nilsson * db8500_set_ape_opp - set the appropriate APE OPP 11233df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 11243df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 11253df57bcfSMattias Nilsson * 11263df57bcfSMattias Nilsson * This function sets the operating point of the APE. 11273df57bcfSMattias Nilsson */ 11280508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp) 11293df57bcfSMattias Nilsson { 11303df57bcfSMattias Nilsson int r = 0; 11313df57bcfSMattias Nilsson 11324d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp) 11334d64d2e3SMattias Nilsson return 0; 11344d64d2e3SMattias Nilsson 11353df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11363df57bcfSMattias Nilsson 11374d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 11384d64d2e3SMattias Nilsson request_even_slower_clocks(false); 11394d64d2e3SMattias Nilsson 11404d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 11414d64d2e3SMattias Nilsson goto skip_message; 11424d64d2e3SMattias Nilsson 1143c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11443df57bcfSMattias Nilsson cpu_relax(); 11453df57bcfSMattias Nilsson 11463df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11473df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 11484d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 11494d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 11503df57bcfSMattias Nilsson 1151c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11523df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11533df57bcfSMattias Nilsson 11543df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 11553df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 11563df57bcfSMattias Nilsson r = -EIO; 11573df57bcfSMattias Nilsson 11584d64d2e3SMattias Nilsson skip_message: 11594d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 11604d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 11614d64d2e3SMattias Nilsson request_even_slower_clocks(true); 11624d64d2e3SMattias Nilsson if (!r) 11634d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp; 11644d64d2e3SMattias Nilsson 11653df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11663df57bcfSMattias Nilsson 11673df57bcfSMattias Nilsson return r; 11683df57bcfSMattias Nilsson } 11693df57bcfSMattias Nilsson 11703df57bcfSMattias Nilsson /** 11710508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP 11723df57bcfSMattias Nilsson * 11733df57bcfSMattias Nilsson * Returns: the current APE OPP 11743df57bcfSMattias Nilsson */ 11750508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void) 11763df57bcfSMattias Nilsson { 11773df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 11783df57bcfSMattias Nilsson } 11793df57bcfSMattias Nilsson 11803df57bcfSMattias Nilsson /** 11813df57bcfSMattias Nilsson * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 11823df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 11833df57bcfSMattias Nilsson * 11843df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 11853df57bcfSMattias Nilsson */ 11863df57bcfSMattias Nilsson int prcmu_request_ape_opp_100_voltage(bool enable) 11873df57bcfSMattias Nilsson { 11883df57bcfSMattias Nilsson int r = 0; 11893df57bcfSMattias Nilsson u8 header; 11903df57bcfSMattias Nilsson static unsigned int requests; 11913df57bcfSMattias Nilsson 11923df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11933df57bcfSMattias Nilsson 11943df57bcfSMattias Nilsson if (enable) { 11953df57bcfSMattias Nilsson if (0 != requests++) 11963df57bcfSMattias Nilsson goto unlock_and_return; 11973df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 11983df57bcfSMattias Nilsson } else { 11993df57bcfSMattias Nilsson if (requests == 0) { 12003df57bcfSMattias Nilsson r = -EIO; 12013df57bcfSMattias Nilsson goto unlock_and_return; 12023df57bcfSMattias Nilsson } else if (1 != requests--) { 12033df57bcfSMattias Nilsson goto unlock_and_return; 12043df57bcfSMattias Nilsson } 12053df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 12063df57bcfSMattias Nilsson } 12073df57bcfSMattias Nilsson 1208c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 12093df57bcfSMattias Nilsson cpu_relax(); 12103df57bcfSMattias Nilsson 12113df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12123df57bcfSMattias Nilsson 1213c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12143df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 12153df57bcfSMattias Nilsson 12163df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 12173df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 12183df57bcfSMattias Nilsson r = -EIO; 12193df57bcfSMattias Nilsson 12203df57bcfSMattias Nilsson unlock_and_return: 12213df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12223df57bcfSMattias Nilsson 12233df57bcfSMattias Nilsson return r; 12243df57bcfSMattias Nilsson } 12253df57bcfSMattias Nilsson 12263df57bcfSMattias Nilsson /** 12273df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 12283df57bcfSMattias Nilsson * 12293df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 12303df57bcfSMattias Nilsson */ 12313df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 12323df57bcfSMattias Nilsson { 12333df57bcfSMattias Nilsson int r = 0; 12343df57bcfSMattias Nilsson 12353df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 12363df57bcfSMattias Nilsson 1237c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 12383df57bcfSMattias Nilsson cpu_relax(); 12393df57bcfSMattias Nilsson 12403df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 12413df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12423df57bcfSMattias Nilsson 1243c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12443df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 12453df57bcfSMattias Nilsson 12463df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 12473df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 12483df57bcfSMattias Nilsson r = -EIO; 12493df57bcfSMattias Nilsson 12503df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12513df57bcfSMattias Nilsson 12523df57bcfSMattias Nilsson return r; 12533df57bcfSMattias Nilsson } 12543df57bcfSMattias Nilsson 12550837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 12560837bb72SMattias Nilsson { 12570837bb72SMattias Nilsson int r = 0; 12580837bb72SMattias Nilsson 12596b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0) 12606b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 12616b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 12620837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 12630837bb72SMattias Nilsson else 12640837bb72SMattias Nilsson return -EINVAL; 12650837bb72SMattias Nilsson 12660837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 12670837bb72SMattias Nilsson 12680837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 12690837bb72SMattias Nilsson cpu_relax(); 12700837bb72SMattias Nilsson 12710837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12720837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 12730837bb72SMattias Nilsson 12740837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12750837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 12760837bb72SMattias Nilsson 12770837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 12780837bb72SMattias Nilsson r = -EIO; 12790837bb72SMattias Nilsson 12800837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12810837bb72SMattias Nilsson 12820837bb72SMattias Nilsson return r; 12830837bb72SMattias Nilsson } 12840837bb72SMattias Nilsson 12853df57bcfSMattias Nilsson /** 12860b9199e3SBengt Jonsson * prcmu_set_hwacc - set the power state of a h/w accelerator 12870b9199e3SBengt Jonsson * @hwacc_dev: The hardware accelerator (enum hw_acc_dev). 12880b9199e3SBengt Jonsson * @state: The new power state (enum hw_acc_state). 12890b9199e3SBengt Jonsson * 12900b9199e3SBengt Jonsson * This function sets the power state of a hardware accelerator. 12910b9199e3SBengt Jonsson * This function should not be called from interrupt context. 12920b9199e3SBengt Jonsson * 12930b9199e3SBengt Jonsson * NOTE! Deprecated, to be removed when all users switched over to use the 12940b9199e3SBengt Jonsson * regulator framework API. 12950b9199e3SBengt Jonsson */ 12960b9199e3SBengt Jonsson int prcmu_set_hwacc(u16 hwacc_dev, u8 state) 12970b9199e3SBengt Jonsson { 12980b9199e3SBengt Jonsson int r = 0; 12990b9199e3SBengt Jonsson bool ram_retention = false; 13000b9199e3SBengt Jonsson bool enable, enable_ret; 13010b9199e3SBengt Jonsson 13020b9199e3SBengt Jonsson /* check argument */ 13030b9199e3SBengt Jonsson BUG_ON(hwacc_dev >= NUM_HW_ACC); 13040b9199e3SBengt Jonsson 13050b9199e3SBengt Jonsson /* get state of switches */ 13060b9199e3SBengt Jonsson enable = hwacc_enabled[hwacc_dev]; 13070b9199e3SBengt Jonsson enable_ret = hwacc_ret_enabled[hwacc_dev]; 13080b9199e3SBengt Jonsson 13090b9199e3SBengt Jonsson /* set flag if retention is possible */ 13100b9199e3SBengt Jonsson switch (hwacc_dev) { 13110b9199e3SBengt Jonsson case HW_ACC_SVAMMDSP: 13120b9199e3SBengt Jonsson case HW_ACC_SIAMMDSP: 13130b9199e3SBengt Jonsson case HW_ACC_ESRAM1: 13140b9199e3SBengt Jonsson case HW_ACC_ESRAM2: 13150b9199e3SBengt Jonsson case HW_ACC_ESRAM3: 13160b9199e3SBengt Jonsson case HW_ACC_ESRAM4: 13170b9199e3SBengt Jonsson ram_retention = true; 13180b9199e3SBengt Jonsson break; 13190b9199e3SBengt Jonsson } 13200b9199e3SBengt Jonsson 13210b9199e3SBengt Jonsson /* check argument */ 13220b9199e3SBengt Jonsson BUG_ON(state > HW_ON); 13230b9199e3SBengt Jonsson BUG_ON(state == HW_OFF_RAMRET && !ram_retention); 13240b9199e3SBengt Jonsson 13250b9199e3SBengt Jonsson /* modify enable flags */ 13260b9199e3SBengt Jonsson switch (state) { 13270b9199e3SBengt Jonsson case HW_OFF: 13280b9199e3SBengt Jonsson enable_ret = false; 13290b9199e3SBengt Jonsson enable = false; 13300b9199e3SBengt Jonsson break; 13310b9199e3SBengt Jonsson case HW_ON: 13320b9199e3SBengt Jonsson enable = true; 13330b9199e3SBengt Jonsson break; 13340b9199e3SBengt Jonsson case HW_OFF_RAMRET: 13350b9199e3SBengt Jonsson enable_ret = true; 13360b9199e3SBengt Jonsson enable = false; 13370b9199e3SBengt Jonsson break; 13380b9199e3SBengt Jonsson } 13390b9199e3SBengt Jonsson 13400b9199e3SBengt Jonsson /* get regulator (lazy) */ 13410b9199e3SBengt Jonsson if (hwacc_regulator[hwacc_dev] == NULL) { 13420b9199e3SBengt Jonsson hwacc_regulator[hwacc_dev] = regulator_get(NULL, 13430b9199e3SBengt Jonsson hwacc_regulator_name[hwacc_dev]); 13440b9199e3SBengt Jonsson if (IS_ERR(hwacc_regulator[hwacc_dev])) { 13450b9199e3SBengt Jonsson pr_err("prcmu: failed to get supply %s\n", 13460b9199e3SBengt Jonsson hwacc_regulator_name[hwacc_dev]); 13470b9199e3SBengt Jonsson r = PTR_ERR(hwacc_regulator[hwacc_dev]); 13480b9199e3SBengt Jonsson goto out; 13490b9199e3SBengt Jonsson } 13500b9199e3SBengt Jonsson } 13510b9199e3SBengt Jonsson 13520b9199e3SBengt Jonsson if (ram_retention) { 13530b9199e3SBengt Jonsson if (hwacc_ret_regulator[hwacc_dev] == NULL) { 13540b9199e3SBengt Jonsson hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL, 13550b9199e3SBengt Jonsson hwacc_ret_regulator_name[hwacc_dev]); 13560b9199e3SBengt Jonsson if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) { 13570b9199e3SBengt Jonsson pr_err("prcmu: failed to get supply %s\n", 13580b9199e3SBengt Jonsson hwacc_ret_regulator_name[hwacc_dev]); 13590b9199e3SBengt Jonsson r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]); 13600b9199e3SBengt Jonsson goto out; 13610b9199e3SBengt Jonsson } 13620b9199e3SBengt Jonsson } 13630b9199e3SBengt Jonsson } 13640b9199e3SBengt Jonsson 13650b9199e3SBengt Jonsson /* set regulators */ 13660b9199e3SBengt Jonsson if (ram_retention) { 13670b9199e3SBengt Jonsson if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) { 13680b9199e3SBengt Jonsson r = regulator_enable(hwacc_ret_regulator[hwacc_dev]); 13690b9199e3SBengt Jonsson if (r < 0) { 13700b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: ret enable failed\n"); 13710b9199e3SBengt Jonsson goto out; 13720b9199e3SBengt Jonsson } 13730b9199e3SBengt Jonsson hwacc_ret_enabled[hwacc_dev] = true; 13740b9199e3SBengt Jonsson } 13750b9199e3SBengt Jonsson } 13760b9199e3SBengt Jonsson 13770b9199e3SBengt Jonsson if (enable && !hwacc_enabled[hwacc_dev]) { 13780b9199e3SBengt Jonsson r = regulator_enable(hwacc_regulator[hwacc_dev]); 13790b9199e3SBengt Jonsson if (r < 0) { 13800b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: enable failed\n"); 13810b9199e3SBengt Jonsson goto out; 13820b9199e3SBengt Jonsson } 13830b9199e3SBengt Jonsson hwacc_enabled[hwacc_dev] = true; 13840b9199e3SBengt Jonsson } 13850b9199e3SBengt Jonsson 13860b9199e3SBengt Jonsson if (!enable && hwacc_enabled[hwacc_dev]) { 13870b9199e3SBengt Jonsson r = regulator_disable(hwacc_regulator[hwacc_dev]); 13880b9199e3SBengt Jonsson if (r < 0) { 13890b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: disable failed\n"); 13900b9199e3SBengt Jonsson goto out; 13910b9199e3SBengt Jonsson } 13920b9199e3SBengt Jonsson hwacc_enabled[hwacc_dev] = false; 13930b9199e3SBengt Jonsson } 13940b9199e3SBengt Jonsson 13950b9199e3SBengt Jonsson if (ram_retention) { 13960b9199e3SBengt Jonsson if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) { 13970b9199e3SBengt Jonsson r = regulator_disable(hwacc_ret_regulator[hwacc_dev]); 13980b9199e3SBengt Jonsson if (r < 0) { 13990b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: ret disable failed\n"); 14000b9199e3SBengt Jonsson goto out; 14010b9199e3SBengt Jonsson } 14020b9199e3SBengt Jonsson hwacc_ret_enabled[hwacc_dev] = false; 14030b9199e3SBengt Jonsson } 14040b9199e3SBengt Jonsson } 14050b9199e3SBengt Jonsson 14060b9199e3SBengt Jonsson out: 14070b9199e3SBengt Jonsson return r; 14080b9199e3SBengt Jonsson } 14090b9199e3SBengt Jonsson EXPORT_SYMBOL(prcmu_set_hwacc); 14100b9199e3SBengt Jonsson 14110b9199e3SBengt Jonsson /** 141273180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 14133df57bcfSMattias Nilsson * @epod_id: The EPOD to set 14143df57bcfSMattias Nilsson * @epod_state: The new EPOD state 14153df57bcfSMattias Nilsson * 14163df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 14173df57bcfSMattias Nilsson * from interrupt context. 14183df57bcfSMattias Nilsson */ 141973180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 14203df57bcfSMattias Nilsson { 14213df57bcfSMattias Nilsson int r = 0; 14223df57bcfSMattias Nilsson bool ram_retention = false; 14233df57bcfSMattias Nilsson int i; 14243df57bcfSMattias Nilsson 14253df57bcfSMattias Nilsson /* check argument */ 14263df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 14273df57bcfSMattias Nilsson 14283df57bcfSMattias Nilsson /* set flag if retention is possible */ 14293df57bcfSMattias Nilsson switch (epod_id) { 14303df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 14313df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 14323df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 14333df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 14343df57bcfSMattias Nilsson ram_retention = true; 14353df57bcfSMattias Nilsson break; 14363df57bcfSMattias Nilsson } 14373df57bcfSMattias Nilsson 14383df57bcfSMattias Nilsson /* check argument */ 14393df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 14403df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 14413df57bcfSMattias Nilsson 14423df57bcfSMattias Nilsson /* get lock */ 14433df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 14443df57bcfSMattias Nilsson 14453df57bcfSMattias Nilsson /* wait for mailbox */ 1446c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 14473df57bcfSMattias Nilsson cpu_relax(); 14483df57bcfSMattias Nilsson 14493df57bcfSMattias Nilsson /* fill in mailbox */ 14503df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 14513df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 14523df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 14533df57bcfSMattias Nilsson 14543df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 14553df57bcfSMattias Nilsson 1456c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 14573df57bcfSMattias Nilsson 14583df57bcfSMattias Nilsson /* 14593df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 14603df57bcfSMattias Nilsson * and we cannot recover if there is an error. 14613df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 14623df57bcfSMattias Nilsson */ 14633df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 14643df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 14653df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 14663df57bcfSMattias Nilsson __func__); 14673df57bcfSMattias Nilsson r = -EIO; 14683df57bcfSMattias Nilsson goto unlock_and_return; 14693df57bcfSMattias Nilsson } 14703df57bcfSMattias Nilsson 14713df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 14723df57bcfSMattias Nilsson r = -EIO; 14733df57bcfSMattias Nilsson 14743df57bcfSMattias Nilsson unlock_and_return: 14753df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 14763df57bcfSMattias Nilsson return r; 14773df57bcfSMattias Nilsson } 14783df57bcfSMattias Nilsson 14793df57bcfSMattias Nilsson /** 14803df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 14813df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 14823df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 14833df57bcfSMattias Nilsson */ 14843df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 14853df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 14863df57bcfSMattias Nilsson { 14873df57bcfSMattias Nilsson u32 sleep_cfg; 14883df57bcfSMattias Nilsson u32 idle_cfg; 14893df57bcfSMattias Nilsson unsigned long flags; 14903df57bcfSMattias Nilsson 14913df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 14923df57bcfSMattias Nilsson 14933df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 14943df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 14953df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 14963df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 14973df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 14983df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 14993df57bcfSMattias Nilsson 15003df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 15013df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 15023df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 15033df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 15043df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 15053df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 15063df57bcfSMattias Nilsson 15073df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 15083df57bcfSMattias Nilsson 15093df57bcfSMattias Nilsson /* 15103df57bcfSMattias Nilsson * The autonomous power management configuration is done through 15113df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 15123df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 15133df57bcfSMattias Nilsson */ 15143df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 15153df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 15163df57bcfSMattias Nilsson 15173df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 15183df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 15193df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 15203df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 15213df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 15223df57bcfSMattias Nilsson 15233df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 15243df57bcfSMattias Nilsson } 15253df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 15263df57bcfSMattias Nilsson 15273df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 15283df57bcfSMattias Nilsson { 15293df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 15303df57bcfSMattias Nilsson } 15313df57bcfSMattias Nilsson 15323df57bcfSMattias Nilsson static int request_sysclk(bool enable) 15333df57bcfSMattias Nilsson { 15343df57bcfSMattias Nilsson int r; 15353df57bcfSMattias Nilsson unsigned long flags; 15363df57bcfSMattias Nilsson 15373df57bcfSMattias Nilsson r = 0; 15383df57bcfSMattias Nilsson 15393df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 15403df57bcfSMattias Nilsson 15413df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 15423df57bcfSMattias Nilsson 1543c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 15443df57bcfSMattias Nilsson cpu_relax(); 15453df57bcfSMattias Nilsson 15463df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 15473df57bcfSMattias Nilsson 15483df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1549c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 15503df57bcfSMattias Nilsson 15513df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 15523df57bcfSMattias Nilsson 15533df57bcfSMattias Nilsson /* 15543df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 15553df57bcfSMattias Nilsson * SysClk, and it succeeds. 15563df57bcfSMattias Nilsson */ 15573df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 15583df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 15593df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 15603df57bcfSMattias Nilsson __func__); 15613df57bcfSMattias Nilsson r = -EIO; 15623df57bcfSMattias Nilsson } 15633df57bcfSMattias Nilsson 15643df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 15653df57bcfSMattias Nilsson 15663df57bcfSMattias Nilsson return r; 15673df57bcfSMattias Nilsson } 15683df57bcfSMattias Nilsson 15693df57bcfSMattias Nilsson static int request_timclk(bool enable) 15703df57bcfSMattias Nilsson { 15713df57bcfSMattias Nilsson u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 15723df57bcfSMattias Nilsson 15733df57bcfSMattias Nilsson if (!enable) 15743df57bcfSMattias Nilsson val |= PRCM_TCR_STOP_TIMERS; 1575c553b3caSMattias Nilsson writel(val, PRCM_TCR); 15763df57bcfSMattias Nilsson 15773df57bcfSMattias Nilsson return 0; 15783df57bcfSMattias Nilsson } 15793df57bcfSMattias Nilsson 15806b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable) 15813df57bcfSMattias Nilsson { 15823df57bcfSMattias Nilsson u32 val; 15833df57bcfSMattias Nilsson unsigned long flags; 15843df57bcfSMattias Nilsson 15853df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 15863df57bcfSMattias Nilsson 15873df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1588c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 15893df57bcfSMattias Nilsson cpu_relax(); 15903df57bcfSMattias Nilsson 15916b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 15923df57bcfSMattias Nilsson if (enable) { 15933df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 15943df57bcfSMattias Nilsson } else { 15953df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 15963df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 15973df57bcfSMattias Nilsson } 15986b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 15993df57bcfSMattias Nilsson 16003df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1601c553b3caSMattias Nilsson writel(0, PRCM_SEM); 16023df57bcfSMattias Nilsson 16033df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 16043df57bcfSMattias Nilsson 16053df57bcfSMattias Nilsson return 0; 16063df57bcfSMattias Nilsson } 16073df57bcfSMattias Nilsson 16080837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 16090837bb72SMattias Nilsson { 16100837bb72SMattias Nilsson u32 val; 16110837bb72SMattias Nilsson int ret; 16120837bb72SMattias Nilsson 16130837bb72SMattias Nilsson if (enable) { 16140837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 16150837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 16160837bb72SMattias Nilsson } 16170837bb72SMattias Nilsson 16186b6fae2bSMattias Nilsson ret = request_clock(clock, enable); 16190837bb72SMattias Nilsson 16200837bb72SMattias Nilsson if (!ret && !enable) { 16210837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 16220837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 16230837bb72SMattias Nilsson } 16240837bb72SMattias Nilsson 16250837bb72SMattias Nilsson return ret; 16260837bb72SMattias Nilsson } 16270837bb72SMattias Nilsson 16286b6fae2bSMattias Nilsson static inline bool plldsi_locked(void) 16296b6fae2bSMattias Nilsson { 16306b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) & 16316b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 16326b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 16336b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 16346b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 16356b6fae2bSMattias Nilsson } 16366b6fae2bSMattias Nilsson 16376b6fae2bSMattias Nilsson static int request_plldsi(bool enable) 16386b6fae2bSMattias Nilsson { 16396b6fae2bSMattias Nilsson int r = 0; 16406b6fae2bSMattias Nilsson u32 val; 16416b6fae2bSMattias Nilsson 16426b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 16436b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 16446b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 16456b6fae2bSMattias Nilsson 16466b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE); 16476b6fae2bSMattias Nilsson if (enable) 16486b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 16496b6fae2bSMattias Nilsson else 16506b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 16516b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 16526b6fae2bSMattias Nilsson 16536b6fae2bSMattias Nilsson if (enable) { 16546b6fae2bSMattias Nilsson unsigned int i; 16556b6fae2bSMattias Nilsson bool locked = plldsi_locked(); 16566b6fae2bSMattias Nilsson 16576b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) { 16586b6fae2bSMattias Nilsson udelay(100); 16596b6fae2bSMattias Nilsson locked = plldsi_locked(); 16606b6fae2bSMattias Nilsson } 16616b6fae2bSMattias Nilsson if (locked) { 16626b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, 16636b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET); 16646b6fae2bSMattias Nilsson } else { 16656b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 16666b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 16676b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET); 16686b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 16696b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 16706b6fae2bSMattias Nilsson r = -EAGAIN; 16716b6fae2bSMattias Nilsson } 16726b6fae2bSMattias Nilsson } else { 16736b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 16746b6fae2bSMattias Nilsson } 16756b6fae2bSMattias Nilsson return r; 16766b6fae2bSMattias Nilsson } 16776b6fae2bSMattias Nilsson 16786b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable) 16796b6fae2bSMattias Nilsson { 16806b6fae2bSMattias Nilsson u32 val; 16816b6fae2bSMattias Nilsson 16826b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 16836b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 16846b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 16856b6fae2bSMattias Nilsson dsiclk[n].divsel_shift); 16866b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 16876b6fae2bSMattias Nilsson return 0; 16886b6fae2bSMattias Nilsson } 16896b6fae2bSMattias Nilsson 16906b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable) 16916b6fae2bSMattias Nilsson { 16926b6fae2bSMattias Nilsson u32 val; 16936b6fae2bSMattias Nilsson 16946b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 16956b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 16966b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 16976b6fae2bSMattias Nilsson return 0; 16986b6fae2bSMattias Nilsson } 16996b6fae2bSMattias Nilsson 17003df57bcfSMattias Nilsson /** 170173180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 17023df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 17033df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 17043df57bcfSMattias Nilsson * 17053df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 17063df57bcfSMattias Nilsson * Do not use it from any other place! 17073df57bcfSMattias Nilsson */ 170873180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 17093df57bcfSMattias Nilsson { 17106b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK) 17110837bb72SMattias Nilsson return request_sga_clock(clock, enable); 17126b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS) 17136b6fae2bSMattias Nilsson return request_clock(clock, enable); 17146b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 17153df57bcfSMattias Nilsson return request_timclk(enable); 17166b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 17176b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 17186b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 17196b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 17206b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 17216b6fae2bSMattias Nilsson return request_plldsi(enable); 17226b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 17233df57bcfSMattias Nilsson return request_sysclk(enable); 17246b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 17250837bb72SMattias Nilsson return request_pll(clock, enable); 17266b6fae2bSMattias Nilsson else 17276b6fae2bSMattias Nilsson return -EINVAL; 17286b6fae2bSMattias Nilsson } 17296b6fae2bSMattias Nilsson 17306b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 17316b6fae2bSMattias Nilsson int branch) 17326b6fae2bSMattias Nilsson { 17336b6fae2bSMattias Nilsson u64 rate; 17346b6fae2bSMattias Nilsson u32 val; 17356b6fae2bSMattias Nilsson u32 d; 17366b6fae2bSMattias Nilsson u32 div = 1; 17376b6fae2bSMattias Nilsson 17386b6fae2bSMattias Nilsson val = readl(reg); 17396b6fae2bSMattias Nilsson 17406b6fae2bSMattias Nilsson rate = src_rate; 17416b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 17426b6fae2bSMattias Nilsson 17436b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 17446b6fae2bSMattias Nilsson if (d > 1) 17456b6fae2bSMattias Nilsson div *= d; 17466b6fae2bSMattias Nilsson 17476b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 17486b6fae2bSMattias Nilsson if (d > 1) 17496b6fae2bSMattias Nilsson div *= d; 17506b6fae2bSMattias Nilsson 17516b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2) 17526b6fae2bSMattias Nilsson div *= 2; 17536b6fae2bSMattias Nilsson 17546b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 17556b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) && 17566b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) || 17576b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ)))) 17586b6fae2bSMattias Nilsson div *= 2; 17596b6fae2bSMattias Nilsson 17606b6fae2bSMattias Nilsson (void)do_div(rate, div); 17616b6fae2bSMattias Nilsson 17626b6fae2bSMattias Nilsson return (unsigned long)rate; 17636b6fae2bSMattias Nilsson } 17646b6fae2bSMattias Nilsson 17656b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000 17666b6fae2bSMattias Nilsson 17676b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock) 17686b6fae2bSMattias Nilsson { 17696b6fae2bSMattias Nilsson u32 val; 17706b6fae2bSMattias Nilsson u32 pllsw; 17716b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE; 17726b6fae2bSMattias Nilsson 17736b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 17746b6fae2bSMattias Nilsson 17756b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 17766b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 17776b6fae2bSMattias Nilsson rate /= 2; 17786b6fae2bSMattias Nilsson return rate; 17796b6fae2bSMattias Nilsson } 17806b6fae2bSMattias Nilsson 17816b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw; 17826b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 17836b6fae2bSMattias Nilsson 17846b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 17856b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 17866b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 17876b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 17886b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 17896b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 17906b6fae2bSMattias Nilsson else 17916b6fae2bSMattias Nilsson return 0; 17926b6fae2bSMattias Nilsson 17936b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) && 17946b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 17956b6fae2bSMattias Nilsson u64 r = (rate * 10); 17966b6fae2bSMattias Nilsson 17976b6fae2bSMattias Nilsson (void)do_div(r, 25); 17986b6fae2bSMattias Nilsson return (unsigned long)r; 17996b6fae2bSMattias Nilsson } 18006b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 18016b6fae2bSMattias Nilsson if (val) 18026b6fae2bSMattias Nilsson return rate / val; 18036b6fae2bSMattias Nilsson else 18046b6fae2bSMattias Nilsson return 0; 18056b6fae2bSMattias Nilsson } 18066b6fae2bSMattias Nilsson 18076b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n) 18086b6fae2bSMattias Nilsson { 18096b6fae2bSMattias Nilsson u32 divsel; 18106b6fae2bSMattias Nilsson u32 div = 1; 18116b6fae2bSMattias Nilsson 18126b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL); 18136b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 18146b6fae2bSMattias Nilsson 18156b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 18166b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel; 18176b6fae2bSMattias Nilsson 18186b6fae2bSMattias Nilsson switch (divsel) { 18196b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4: 18206b6fae2bSMattias Nilsson div *= 2; 18216b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2: 18226b6fae2bSMattias Nilsson div *= 2; 18236b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI: 18246b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 18256b6fae2bSMattias Nilsson PLL_RAW) / div; 1826e62ccf3aSLinus Walleij default: 18276b6fae2bSMattias Nilsson return 0; 18286b6fae2bSMattias Nilsson } 18296b6fae2bSMattias Nilsson } 18306b6fae2bSMattias Nilsson 18316b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n) 18326b6fae2bSMattias Nilsson { 18336b6fae2bSMattias Nilsson u32 div; 18346b6fae2bSMattias Nilsson 18356b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV); 18366b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 18376b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 18386b6fae2bSMattias Nilsson } 18396b6fae2bSMattias Nilsson 18406b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock) 18416b6fae2bSMattias Nilsson { 18426b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 18436b6fae2bSMattias Nilsson return clock_rate(clock); 18446b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 18456b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE / 16; 18466b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 18476b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 18486b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0) 18496b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 18506b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 18516b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 18526b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR) 18536b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 18546b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 18556b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 18566b6fae2bSMattias Nilsson PLL_RAW); 18576b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 18586b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK); 18596b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 18606b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 18616b6fae2bSMattias Nilsson else 18626b6fae2bSMattias Nilsson return 0; 18636b6fae2bSMattias Nilsson } 18646b6fae2bSMattias Nilsson 18656b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 18666b6fae2bSMattias Nilsson { 18676b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 18686b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 18696b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 18706b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 18716b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 18726b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 18736b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 18746b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 18756b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 18766b6fae2bSMattias Nilsson else 18776b6fae2bSMattias Nilsson return 0; 18786b6fae2bSMattias Nilsson } 18796b6fae2bSMattias Nilsson 18806b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate) 18816b6fae2bSMattias Nilsson { 18826b6fae2bSMattias Nilsson u32 div; 18836b6fae2bSMattias Nilsson 18846b6fae2bSMattias Nilsson div = (src_rate / rate); 18856b6fae2bSMattias Nilsson if (div == 0) 18866b6fae2bSMattias Nilsson return 1; 18876b6fae2bSMattias Nilsson if (rate < (src_rate / div)) 18886b6fae2bSMattias Nilsson div++; 18896b6fae2bSMattias Nilsson return div; 18906b6fae2bSMattias Nilsson } 18916b6fae2bSMattias Nilsson 18926b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate) 18936b6fae2bSMattias Nilsson { 18946b6fae2bSMattias Nilsson u32 val; 18956b6fae2bSMattias Nilsson u32 div; 18966b6fae2bSMattias Nilsson unsigned long src_rate; 18976b6fae2bSMattias Nilsson long rounded_rate; 18986b6fae2bSMattias Nilsson 18996b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 19006b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 19016b6fae2bSMattias Nilsson clk_mgt[clock].branch); 19026b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 19036b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 19046b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 19056b6fae2bSMattias Nilsson if (div > 2) 19066b6fae2bSMattias Nilsson div = 2; 19076b6fae2bSMattias Nilsson } else { 19086b6fae2bSMattias Nilsson div = 1; 19096b6fae2bSMattias Nilsson } 19106b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 19116b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 19126b6fae2bSMattias Nilsson 19136b6fae2bSMattias Nilsson (void)do_div(r, 25); 19146b6fae2bSMattias Nilsson if (r <= rate) 19156b6fae2bSMattias Nilsson return (unsigned long)r; 19166b6fae2bSMattias Nilsson } 19176b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31)); 19186b6fae2bSMattias Nilsson 19196b6fae2bSMattias Nilsson return rounded_rate; 19206b6fae2bSMattias Nilsson } 19216b6fae2bSMattias Nilsson 19226b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL 19236b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL 19246b6fae2bSMattias Nilsson 19256b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate) 19266b6fae2bSMattias Nilsson { 19276b6fae2bSMattias Nilsson long rounded_rate = 0; 19286b6fae2bSMattias Nilsson unsigned long src_rate; 19296b6fae2bSMattias Nilsson unsigned long rem; 19306b6fae2bSMattias Nilsson u32 r; 19316b6fae2bSMattias Nilsson 19326b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 19336b6fae2bSMattias Nilsson rem = rate; 19346b6fae2bSMattias Nilsson 19356b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 19366b6fae2bSMattias Nilsson u64 d; 19376b6fae2bSMattias Nilsson 19386b6fae2bSMattias Nilsson d = (r * rate); 19396b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 19406b6fae2bSMattias Nilsson if (d < 6) 19416b6fae2bSMattias Nilsson d = 6; 19426b6fae2bSMattias Nilsson else if (d > 255) 19436b6fae2bSMattias Nilsson d = 255; 19446b6fae2bSMattias Nilsson d *= src_rate; 19456b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 19466b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d))) 19476b6fae2bSMattias Nilsson continue; 19486b6fae2bSMattias Nilsson (void)do_div(d, r); 19496b6fae2bSMattias Nilsson if (rate < d) { 19506b6fae2bSMattias Nilsson if (rounded_rate == 0) 19516b6fae2bSMattias Nilsson rounded_rate = (long)d; 1952e62ccf3aSLinus Walleij break; 1953e62ccf3aSLinus Walleij } 19546b6fae2bSMattias Nilsson if ((rate - d) < rem) { 19556b6fae2bSMattias Nilsson rem = (rate - d); 19566b6fae2bSMattias Nilsson rounded_rate = (long)d; 19576b6fae2bSMattias Nilsson } 19586b6fae2bSMattias Nilsson } 19596b6fae2bSMattias Nilsson return rounded_rate; 19606b6fae2bSMattias Nilsson } 19616b6fae2bSMattias Nilsson 19626b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate) 19636b6fae2bSMattias Nilsson { 19646b6fae2bSMattias Nilsson u32 div; 19656b6fae2bSMattias Nilsson unsigned long src_rate; 19666b6fae2bSMattias Nilsson long rounded_rate; 19676b6fae2bSMattias Nilsson 19686b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 19696b6fae2bSMattias Nilsson PLL_RAW); 19706b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 19716b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 19726b6fae2bSMattias Nilsson 19736b6fae2bSMattias Nilsson return rounded_rate; 19746b6fae2bSMattias Nilsson } 19756b6fae2bSMattias Nilsson 19766b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate) 19776b6fae2bSMattias Nilsson { 19786b6fae2bSMattias Nilsson u32 div; 19796b6fae2bSMattias Nilsson unsigned long src_rate; 19806b6fae2bSMattias Nilsson long rounded_rate; 19816b6fae2bSMattias Nilsson 19826b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK); 19836b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 19846b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255)); 19856b6fae2bSMattias Nilsson 19866b6fae2bSMattias Nilsson return rounded_rate; 19876b6fae2bSMattias Nilsson } 19886b6fae2bSMattias Nilsson 19896b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate) 19906b6fae2bSMattias Nilsson { 1991e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 19926b6fae2bSMattias Nilsson return round_clock_rate(clock, rate); 19936b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 19946b6fae2bSMattias Nilsson return round_plldsi_rate(rate); 19956b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 19966b6fae2bSMattias Nilsson return round_dsiclk_rate(rate); 19976b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 19986b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate); 19996b6fae2bSMattias Nilsson else 20006b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock); 20016b6fae2bSMattias Nilsson } 20026b6fae2bSMattias Nilsson 20036b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate) 20046b6fae2bSMattias Nilsson { 20056b6fae2bSMattias Nilsson u32 val; 20066b6fae2bSMattias Nilsson u32 div; 20076b6fae2bSMattias Nilsson unsigned long src_rate; 20086b6fae2bSMattias Nilsson unsigned long flags; 20096b6fae2bSMattias Nilsson 20106b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 20116b6fae2bSMattias Nilsson 20126b6fae2bSMattias Nilsson /* Grab the HW semaphore. */ 20136b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 20146b6fae2bSMattias Nilsson cpu_relax(); 20156b6fae2bSMattias Nilsson 20166b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 20176b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 20186b6fae2bSMattias Nilsson clk_mgt[clock].branch); 20196b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 20206b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 20216b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 20226b6fae2bSMattias Nilsson if (div > 1) 20236b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV; 20246b6fae2bSMattias Nilsson else 20256b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV; 20266b6fae2bSMattias Nilsson } 20276b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) { 20286b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 20296b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 20306b6fae2bSMattias Nilsson if (div == 3) { 20316b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 20326b6fae2bSMattias Nilsson 20336b6fae2bSMattias Nilsson (void)do_div(r, 25); 20346b6fae2bSMattias Nilsson if (r <= rate) { 20356b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 20366b6fae2bSMattias Nilsson div = 0; 20376b6fae2bSMattias Nilsson } 20386b6fae2bSMattias Nilsson } 20396b6fae2bSMattias Nilsson val |= min(div, (u32)31); 20406b6fae2bSMattias Nilsson } else { 20416b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 20426b6fae2bSMattias Nilsson val |= min(div, (u32)31); 20436b6fae2bSMattias Nilsson } 20446b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 20456b6fae2bSMattias Nilsson 20466b6fae2bSMattias Nilsson /* Release the HW semaphore. */ 20476b6fae2bSMattias Nilsson writel(0, PRCM_SEM); 20486b6fae2bSMattias Nilsson 20496b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 20506b6fae2bSMattias Nilsson } 20516b6fae2bSMattias Nilsson 20526b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate) 20536b6fae2bSMattias Nilsson { 20546b6fae2bSMattias Nilsson unsigned long src_rate; 20556b6fae2bSMattias Nilsson unsigned long rem; 20566b6fae2bSMattias Nilsson u32 pll_freq = 0; 20576b6fae2bSMattias Nilsson u32 r; 20586b6fae2bSMattias Nilsson 20596b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 20606b6fae2bSMattias Nilsson rem = rate; 20616b6fae2bSMattias Nilsson 20626b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 20636b6fae2bSMattias Nilsson u64 d; 20646b6fae2bSMattias Nilsson u64 hwrate; 20656b6fae2bSMattias Nilsson 20666b6fae2bSMattias Nilsson d = (r * rate); 20676b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 20686b6fae2bSMattias Nilsson if (d < 6) 20696b6fae2bSMattias Nilsson d = 6; 20706b6fae2bSMattias Nilsson else if (d > 255) 20716b6fae2bSMattias Nilsson d = 255; 20726b6fae2bSMattias Nilsson hwrate = (d * src_rate); 20736b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 20746b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 20756b6fae2bSMattias Nilsson continue; 20766b6fae2bSMattias Nilsson (void)do_div(hwrate, r); 20776b6fae2bSMattias Nilsson if (rate < hwrate) { 20786b6fae2bSMattias Nilsson if (pll_freq == 0) 20796b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 20806b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 20816b6fae2bSMattias Nilsson break; 20826b6fae2bSMattias Nilsson } 20836b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) { 20846b6fae2bSMattias Nilsson rem = (rate - hwrate); 20856b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 20866b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 20876b6fae2bSMattias Nilsson } 20886b6fae2bSMattias Nilsson } 20896b6fae2bSMattias Nilsson if (pll_freq == 0) 20903df57bcfSMattias Nilsson return -EINVAL; 20916b6fae2bSMattias Nilsson 20926b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 20936b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ); 20946b6fae2bSMattias Nilsson 20956b6fae2bSMattias Nilsson return 0; 20966b6fae2bSMattias Nilsson } 20976b6fae2bSMattias Nilsson 20986b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate) 20996b6fae2bSMattias Nilsson { 21006b6fae2bSMattias Nilsson u32 val; 21016b6fae2bSMattias Nilsson u32 div; 21026b6fae2bSMattias Nilsson 21036b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 21046b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 21056b6fae2bSMattias Nilsson 21066b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 21076b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 21086b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 21096b6fae2bSMattias Nilsson 21106b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 21116b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 21126b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 21136b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 21146b6fae2bSMattias Nilsson } 21156b6fae2bSMattias Nilsson 21166b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate) 21176b6fae2bSMattias Nilsson { 21186b6fae2bSMattias Nilsson u32 val; 21196b6fae2bSMattias Nilsson u32 div; 21206b6fae2bSMattias Nilsson 21216b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 21226b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 21236b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask; 21246b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 21256b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 21266b6fae2bSMattias Nilsson } 21276b6fae2bSMattias Nilsson 21286b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate) 21296b6fae2bSMattias Nilsson { 21306b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 21316b6fae2bSMattias Nilsson set_clock_rate(clock, rate); 21326b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 21336b6fae2bSMattias Nilsson return set_plldsi_rate(rate); 21346b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 21356b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 21366b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 21376b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 21386b6fae2bSMattias Nilsson return 0; 21393df57bcfSMattias Nilsson } 21403df57bcfSMattias Nilsson 214173180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 21423df57bcfSMattias Nilsson { 21433df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 21443df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 21453df57bcfSMattias Nilsson return -EINVAL; 21463df57bcfSMattias Nilsson 21473df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21483df57bcfSMattias Nilsson 2149c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21503df57bcfSMattias Nilsson cpu_relax(); 21513df57bcfSMattias Nilsson 21523df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21533df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 21543df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 21553df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 21563df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 21573df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 21583df57bcfSMattias Nilsson 2159c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21603df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21613df57bcfSMattias Nilsson 21623df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21633df57bcfSMattias Nilsson 21643df57bcfSMattias Nilsson return 0; 21653df57bcfSMattias Nilsson } 21663df57bcfSMattias Nilsson 21670508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold) 21683df57bcfSMattias Nilsson { 21693df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21703df57bcfSMattias Nilsson 2171c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21723df57bcfSMattias Nilsson cpu_relax(); 21733df57bcfSMattias Nilsson 21743df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 21753df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21763df57bcfSMattias Nilsson 2177c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21783df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21793df57bcfSMattias Nilsson 21803df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21813df57bcfSMattias Nilsson 21823df57bcfSMattias Nilsson return 0; 21833df57bcfSMattias Nilsson } 21843df57bcfSMattias Nilsson 21850508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high) 21863df57bcfSMattias Nilsson { 21873df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21883df57bcfSMattias Nilsson 2189c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21903df57bcfSMattias Nilsson cpu_relax(); 21913df57bcfSMattias Nilsson 21923df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 21933df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 21943df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 21953df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 21963df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21973df57bcfSMattias Nilsson 2198c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21993df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 22003df57bcfSMattias Nilsson 22013df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 22023df57bcfSMattias Nilsson 22033df57bcfSMattias Nilsson return 0; 22043df57bcfSMattias Nilsson } 22053df57bcfSMattias Nilsson 22063df57bcfSMattias Nilsson static int config_hot_period(u16 val) 22073df57bcfSMattias Nilsson { 22083df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 22093df57bcfSMattias Nilsson 2210c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 22113df57bcfSMattias Nilsson cpu_relax(); 22123df57bcfSMattias Nilsson 22133df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 22143df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 22153df57bcfSMattias Nilsson 2216c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 22173df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 22183df57bcfSMattias Nilsson 22193df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 22203df57bcfSMattias Nilsson 22213df57bcfSMattias Nilsson return 0; 22223df57bcfSMattias Nilsson } 22233df57bcfSMattias Nilsson 22240508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k) 22253df57bcfSMattias Nilsson { 22263df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 22273df57bcfSMattias Nilsson return -EINVAL; 22283df57bcfSMattias Nilsson 22293df57bcfSMattias Nilsson return config_hot_period(cycles32k); 22303df57bcfSMattias Nilsson } 22313df57bcfSMattias Nilsson 22320508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void) 22333df57bcfSMattias Nilsson { 22343df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 22353df57bcfSMattias Nilsson } 22363df57bcfSMattias Nilsson 223784165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 223884165b80SJonas Aberg { 223984165b80SJonas Aberg 224084165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 224184165b80SJonas Aberg 224284165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 224384165b80SJonas Aberg cpu_relax(); 224484165b80SJonas Aberg 224584165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 224684165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 224784165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 224884165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 224984165b80SJonas Aberg 225084165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 225184165b80SJonas Aberg 225284165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 225384165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 225484165b80SJonas Aberg 225584165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 225684165b80SJonas Aberg 225784165b80SJonas Aberg return 0; 225884165b80SJonas Aberg 225984165b80SJonas Aberg } 226084165b80SJonas Aberg 22610508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 226284165b80SJonas Aberg { 226384165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 226484165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 226584165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 226684165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 226784165b80SJonas Aberg } 226884165b80SJonas Aberg 22690508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id) 227084165b80SJonas Aberg { 227184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 227284165b80SJonas Aberg } 227384165b80SJonas Aberg 22740508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id) 227584165b80SJonas Aberg { 227684165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 227784165b80SJonas Aberg } 227884165b80SJonas Aberg 22790508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id) 228084165b80SJonas Aberg { 228184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 228284165b80SJonas Aberg } 228384165b80SJonas Aberg 228484165b80SJonas Aberg /* 228584165b80SJonas Aberg * timeout is 28 bit, in ms. 228684165b80SJonas Aberg */ 22870508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 228884165b80SJonas Aberg { 228984165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 229084165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 229184165b80SJonas Aberg /* 229284165b80SJonas Aberg * Put the lowest 28 bits of timeout at 229384165b80SJonas Aberg * offset 4. Four first bits are used for id. 229484165b80SJonas Aberg */ 229584165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 229684165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 229784165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 229884165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 229984165b80SJonas Aberg } 230084165b80SJonas Aberg 23013df57bcfSMattias Nilsson /** 2302650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 2303650c2a21SLinus Walleij * @slave: The I2C slave address. 2304650c2a21SLinus Walleij * @reg: The (start) register address. 2305650c2a21SLinus Walleij * @value: The read out value(s). 2306650c2a21SLinus Walleij * @size: The number of registers to read. 2307650c2a21SLinus Walleij * 2308650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2309650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2310650c2a21SLinus Walleij */ 2311650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2312650c2a21SLinus Walleij { 2313650c2a21SLinus Walleij int r; 2314650c2a21SLinus Walleij 2315650c2a21SLinus Walleij if (size != 1) 2316650c2a21SLinus Walleij return -EINVAL; 2317650c2a21SLinus Walleij 23183df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2319650c2a21SLinus Walleij 2320c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2321650c2a21SLinus Walleij cpu_relax(); 2322650c2a21SLinus Walleij 23233df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 23243df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 23253df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 23263df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2327650c2a21SLinus Walleij 2328c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 23293df57bcfSMattias Nilsson 2330650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 23313df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 23323df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 23333df57bcfSMattias Nilsson __func__); 2334650c2a21SLinus Walleij r = -EIO; 23353df57bcfSMattias Nilsson } else { 2336650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 23373df57bcfSMattias Nilsson } 23383df57bcfSMattias Nilsson 2339650c2a21SLinus Walleij if (!r) 2340650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 2341650c2a21SLinus Walleij 2342650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 23433df57bcfSMattias Nilsson 2344650c2a21SLinus Walleij return r; 2345650c2a21SLinus Walleij } 2346650c2a21SLinus Walleij 2347650c2a21SLinus Walleij /** 2348650c2a21SLinus Walleij * prcmu_abb_write() - Write register value(s) to the ABB. 2349650c2a21SLinus Walleij * @slave: The I2C slave address. 2350650c2a21SLinus Walleij * @reg: The (start) register address. 2351650c2a21SLinus Walleij * @value: The value(s) to write. 2352650c2a21SLinus Walleij * @size: The number of registers to write. 2353650c2a21SLinus Walleij * 2354650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2355650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2356650c2a21SLinus Walleij */ 2357650c2a21SLinus Walleij int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 2358650c2a21SLinus Walleij { 2359650c2a21SLinus Walleij int r; 2360650c2a21SLinus Walleij 2361650c2a21SLinus Walleij if (size != 1) 2362650c2a21SLinus Walleij return -EINVAL; 2363650c2a21SLinus Walleij 23643df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2365650c2a21SLinus Walleij 2366c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2367650c2a21SLinus Walleij cpu_relax(); 2368650c2a21SLinus Walleij 23693df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 23703df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 23713df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 23723df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2373650c2a21SLinus Walleij 2374c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 23753df57bcfSMattias Nilsson 2376650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 23773df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 23783df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 23793df57bcfSMattias Nilsson __func__); 2380650c2a21SLinus Walleij r = -EIO; 23813df57bcfSMattias Nilsson } else { 2382650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 23833df57bcfSMattias Nilsson } 23843df57bcfSMattias Nilsson 23853df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 23863df57bcfSMattias Nilsson 23873df57bcfSMattias Nilsson return r; 23883df57bcfSMattias Nilsson } 23893df57bcfSMattias Nilsson 23903df57bcfSMattias Nilsson /** 23913df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 23923df57bcfSMattias Nilsson */ 23933df57bcfSMattias Nilsson void prcmu_ac_wake_req(void) 23943df57bcfSMattias Nilsson { 23953df57bcfSMattias Nilsson u32 val; 2396d6e3002eSMattias Nilsson u32 status; 23973df57bcfSMattias Nilsson 23983df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 23993df57bcfSMattias Nilsson 2400c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 24013df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 24023df57bcfSMattias Nilsson goto unlock_and_return; 24033df57bcfSMattias Nilsson 24043df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 24053df57bcfSMattias Nilsson 2406d6e3002eSMattias Nilsson retry: 2407c553b3caSMattias Nilsson writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); 24083df57bcfSMattias Nilsson 24093df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2410d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 241157265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2412d6e3002eSMattias Nilsson __func__); 2413d6e3002eSMattias Nilsson goto unlock_and_return; 2414d6e3002eSMattias Nilsson } 2415d6e3002eSMattias Nilsson 2416d6e3002eSMattias Nilsson /* 2417d6e3002eSMattias Nilsson * The modem can generate an AC_WAKE_ACK, and then still go to sleep. 2418d6e3002eSMattias Nilsson * As a workaround, we wait, and then check that the modem is indeed 2419d6e3002eSMattias Nilsson * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS 2420d6e3002eSMattias Nilsson * register, which may not be the whole truth). 2421d6e3002eSMattias Nilsson */ 2422d6e3002eSMattias Nilsson udelay(400); 2423d6e3002eSMattias Nilsson status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2)); 2424d6e3002eSMattias Nilsson if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE | 2425d6e3002eSMattias Nilsson PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) { 2426d6e3002eSMattias Nilsson pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n", 2427d6e3002eSMattias Nilsson __func__, status); 2428d6e3002eSMattias Nilsson udelay(1200); 2429d6e3002eSMattias Nilsson writel(val, PRCM_HOSTACCESS_REQ); 2430d6e3002eSMattias Nilsson if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2431d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) 2432d6e3002eSMattias Nilsson goto retry; 243357265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n", 24343df57bcfSMattias Nilsson __func__); 24353df57bcfSMattias Nilsson } 2436650c2a21SLinus Walleij 2437650c2a21SLinus Walleij unlock_and_return: 24383df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 2439650c2a21SLinus Walleij } 2440650c2a21SLinus Walleij 24413df57bcfSMattias Nilsson /** 24423df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 24433df57bcfSMattias Nilsson */ 24443df57bcfSMattias Nilsson void prcmu_ac_sleep_req() 2445650c2a21SLinus Walleij { 24463df57bcfSMattias Nilsson u32 val; 2447650c2a21SLinus Walleij 24483df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 2449650c2a21SLinus Walleij 2450c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 24513df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 24523df57bcfSMattias Nilsson goto unlock_and_return; 24533df57bcfSMattias Nilsson 24543df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2455c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 24563df57bcfSMattias Nilsson 24573df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2458d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 245957265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 24603df57bcfSMattias Nilsson __func__); 24613df57bcfSMattias Nilsson } 24623df57bcfSMattias Nilsson 24633df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 24643df57bcfSMattias Nilsson 24653df57bcfSMattias Nilsson unlock_and_return: 24663df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 24673df57bcfSMattias Nilsson } 24683df57bcfSMattias Nilsson 246973180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 24703df57bcfSMattias Nilsson { 24713df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 24723df57bcfSMattias Nilsson } 24733df57bcfSMattias Nilsson 24743df57bcfSMattias Nilsson /** 247573180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 24763df57bcfSMattias Nilsson * 247773180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 24783df57bcfSMattias Nilsson * fires interrupt to fw 24793df57bcfSMattias Nilsson */ 248073180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 24813df57bcfSMattias Nilsson { 24823df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2483c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 24843df57bcfSMattias Nilsson } 24853df57bcfSMattias Nilsson 24863df57bcfSMattias Nilsson /** 2487597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2488597045deSSebastian Rasmussen * 2489597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 2490597045deSSebastian Rasmussen * last restart. 2491597045deSSebastian Rasmussen */ 2492597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 2493597045deSSebastian Rasmussen { 2494597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 2495597045deSSebastian Rasmussen } 2496597045deSSebastian Rasmussen 2497597045deSSebastian Rasmussen /** 24980508901cSMattias Nilsson * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 24993df57bcfSMattias Nilsson */ 25000508901cSMattias Nilsson void db8500_prcmu_modem_reset(void) 25013df57bcfSMattias Nilsson { 2502650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 2503650c2a21SLinus Walleij 2504c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2505650c2a21SLinus Walleij cpu_relax(); 2506650c2a21SLinus Walleij 25073df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2508c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2509650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 25103df57bcfSMattias Nilsson 25113df57bcfSMattias Nilsson /* 25123df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 25133df57bcfSMattias Nilsson * This state is already managed by upper layer 25143df57bcfSMattias Nilsson */ 2515650c2a21SLinus Walleij 2516650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 2517650c2a21SLinus Walleij } 2518650c2a21SLinus Walleij 25193df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 2520650c2a21SLinus Walleij { 25213df57bcfSMattias Nilsson unsigned long flags; 2522650c2a21SLinus Walleij 25233df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 2524650c2a21SLinus Walleij 2525c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 25263df57bcfSMattias Nilsson cpu_relax(); 2527650c2a21SLinus Walleij 25283df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2529c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2530650c2a21SLinus Walleij 25313df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2532650c2a21SLinus Walleij } 2533650c2a21SLinus Walleij 25343df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 2535650c2a21SLinus Walleij { 25363df57bcfSMattias Nilsson pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 25373df57bcfSMattias Nilsson header, n); 2538650c2a21SLinus Walleij } 2539650c2a21SLinus Walleij 25403df57bcfSMattias Nilsson static bool read_mailbox_0(void) 2541650c2a21SLinus Walleij { 25423df57bcfSMattias Nilsson bool r; 25433df57bcfSMattias Nilsson u32 ev; 25443df57bcfSMattias Nilsson unsigned int n; 25453df57bcfSMattias Nilsson u8 header; 25463df57bcfSMattias Nilsson 25473df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 25483df57bcfSMattias Nilsson switch (header) { 25493df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 25503df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 25513df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 25523df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 25533df57bcfSMattias Nilsson else 25543df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 25553df57bcfSMattias Nilsson 25563df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 25573df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 25583df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 25593df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 25603df57bcfSMattias Nilsson 25613df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 25623df57bcfSMattias Nilsson 25633df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 25643df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 25653df57bcfSMattias Nilsson generic_handle_irq(IRQ_PRCMU_BASE + n); 25663df57bcfSMattias Nilsson } 25673df57bcfSMattias Nilsson r = true; 25683df57bcfSMattias Nilsson break; 25693df57bcfSMattias Nilsson default: 25703df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 25713df57bcfSMattias Nilsson r = false; 25723df57bcfSMattias Nilsson break; 25733df57bcfSMattias Nilsson } 2574c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 25753df57bcfSMattias Nilsson return r; 25763df57bcfSMattias Nilsson } 25773df57bcfSMattias Nilsson 25783df57bcfSMattias Nilsson static bool read_mailbox_1(void) 25793df57bcfSMattias Nilsson { 25803df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 25813df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 25823df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 25833df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 25843df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 25853df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 25863df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2587c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2588650c2a21SLinus Walleij complete(&mb1_transfer.work); 25893df57bcfSMattias Nilsson return false; 2590650c2a21SLinus Walleij } 2591650c2a21SLinus Walleij 25923df57bcfSMattias Nilsson static bool read_mailbox_2(void) 2593650c2a21SLinus Walleij { 25943df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2595c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 25963df57bcfSMattias Nilsson complete(&mb2_transfer.work); 25973df57bcfSMattias Nilsson return false; 2598650c2a21SLinus Walleij } 2599650c2a21SLinus Walleij 26003df57bcfSMattias Nilsson static bool read_mailbox_3(void) 2601650c2a21SLinus Walleij { 2602c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 26033df57bcfSMattias Nilsson return false; 2604650c2a21SLinus Walleij } 2605650c2a21SLinus Walleij 26063df57bcfSMattias Nilsson static bool read_mailbox_4(void) 2607650c2a21SLinus Walleij { 26083df57bcfSMattias Nilsson u8 header; 26093df57bcfSMattias Nilsson bool do_complete = true; 26103df57bcfSMattias Nilsson 26113df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 26123df57bcfSMattias Nilsson switch (header) { 26133df57bcfSMattias Nilsson case MB4H_MEM_ST: 26143df57bcfSMattias Nilsson case MB4H_HOTDOG: 26153df57bcfSMattias Nilsson case MB4H_HOTMON: 26163df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 2617a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 2618a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 2619a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 2620a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 2621a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 26223df57bcfSMattias Nilsson break; 26233df57bcfSMattias Nilsson default: 26243df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 26253df57bcfSMattias Nilsson do_complete = false; 26263df57bcfSMattias Nilsson break; 2627650c2a21SLinus Walleij } 2628650c2a21SLinus Walleij 2629c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 26303df57bcfSMattias Nilsson 26313df57bcfSMattias Nilsson if (do_complete) 26323df57bcfSMattias Nilsson complete(&mb4_transfer.work); 26333df57bcfSMattias Nilsson 26343df57bcfSMattias Nilsson return false; 26353df57bcfSMattias Nilsson } 26363df57bcfSMattias Nilsson 26373df57bcfSMattias Nilsson static bool read_mailbox_5(void) 2638650c2a21SLinus Walleij { 26393df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 26403df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2641c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2642650c2a21SLinus Walleij complete(&mb5_transfer.work); 26433df57bcfSMattias Nilsson return false; 2644650c2a21SLinus Walleij } 2645650c2a21SLinus Walleij 26463df57bcfSMattias Nilsson static bool read_mailbox_6(void) 2647650c2a21SLinus Walleij { 2648c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 26493df57bcfSMattias Nilsson return false; 2650650c2a21SLinus Walleij } 2651650c2a21SLinus Walleij 26523df57bcfSMattias Nilsson static bool read_mailbox_7(void) 2653650c2a21SLinus Walleij { 2654c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 26553df57bcfSMattias Nilsson return false; 2656650c2a21SLinus Walleij } 2657650c2a21SLinus Walleij 26583df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 2659650c2a21SLinus Walleij read_mailbox_0, 2660650c2a21SLinus Walleij read_mailbox_1, 2661650c2a21SLinus Walleij read_mailbox_2, 2662650c2a21SLinus Walleij read_mailbox_3, 2663650c2a21SLinus Walleij read_mailbox_4, 2664650c2a21SLinus Walleij read_mailbox_5, 2665650c2a21SLinus Walleij read_mailbox_6, 2666650c2a21SLinus Walleij read_mailbox_7 2667650c2a21SLinus Walleij }; 2668650c2a21SLinus Walleij 2669650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2670650c2a21SLinus Walleij { 2671650c2a21SLinus Walleij u32 bits; 2672650c2a21SLinus Walleij u8 n; 26733df57bcfSMattias Nilsson irqreturn_t r; 2674650c2a21SLinus Walleij 2675c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2676650c2a21SLinus Walleij if (unlikely(!bits)) 2677650c2a21SLinus Walleij return IRQ_NONE; 2678650c2a21SLinus Walleij 26793df57bcfSMattias Nilsson r = IRQ_HANDLED; 2680650c2a21SLinus Walleij for (n = 0; bits; n++) { 2681650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2682650c2a21SLinus Walleij bits -= MBOX_BIT(n); 26833df57bcfSMattias Nilsson if (read_mailbox[n]()) 26843df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2685650c2a21SLinus Walleij } 2686650c2a21SLinus Walleij } 26873df57bcfSMattias Nilsson return r; 26883df57bcfSMattias Nilsson } 26893df57bcfSMattias Nilsson 26903df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 26913df57bcfSMattias Nilsson { 26923df57bcfSMattias Nilsson ack_dbb_wakeup(); 2693650c2a21SLinus Walleij return IRQ_HANDLED; 2694650c2a21SLinus Walleij } 2695650c2a21SLinus Walleij 26963df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 26973df57bcfSMattias Nilsson { 26983df57bcfSMattias Nilsson unsigned long flags; 26993df57bcfSMattias Nilsson 27003df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 27013df57bcfSMattias Nilsson 27023df57bcfSMattias Nilsson config_wakeups(); 27033df57bcfSMattias Nilsson 27043df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 27053df57bcfSMattias Nilsson } 27063df57bcfSMattias Nilsson 27073df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 27083df57bcfSMattias Nilsson { 27093df57bcfSMattias Nilsson unsigned long flags; 27103df57bcfSMattias Nilsson 27113df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 27123df57bcfSMattias Nilsson 27133df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 27143df57bcfSMattias Nilsson 27153df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 27163df57bcfSMattias Nilsson 27173df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 27183df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 27193df57bcfSMattias Nilsson } 27203df57bcfSMattias Nilsson 27213df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 27223df57bcfSMattias Nilsson { 27233df57bcfSMattias Nilsson unsigned long flags; 27243df57bcfSMattias Nilsson 27253df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 27263df57bcfSMattias Nilsson 27273df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 27283df57bcfSMattias Nilsson 27293df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 27303df57bcfSMattias Nilsson 27313df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 27323df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 27333df57bcfSMattias Nilsson } 27343df57bcfSMattias Nilsson 27353df57bcfSMattias Nilsson static void noop(struct irq_data *d) 27363df57bcfSMattias Nilsson { 27373df57bcfSMattias Nilsson } 27383df57bcfSMattias Nilsson 27393df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 27403df57bcfSMattias Nilsson .name = "prcmu", 27413df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 27423df57bcfSMattias Nilsson .irq_ack = noop, 27433df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 27443df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 27453df57bcfSMattias Nilsson }; 27463df57bcfSMattias Nilsson 2747b58d12feSMattias Nilsson static char *fw_project_name(u8 project) 2748b58d12feSMattias Nilsson { 2749b58d12feSMattias Nilsson switch (project) { 2750b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500: 2751b58d12feSMattias Nilsson return "U8500"; 2752b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500_C2: 2753b58d12feSMattias Nilsson return "U8500 C2"; 2754b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500: 2755b58d12feSMattias Nilsson return "U9500"; 2756b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500_C2: 2757b58d12feSMattias Nilsson return "U9500 C2"; 2758b58d12feSMattias Nilsson default: 2759b58d12feSMattias Nilsson return "Unknown"; 2760b58d12feSMattias Nilsson } 2761b58d12feSMattias Nilsson } 2762b58d12feSMattias Nilsson 276373180f85SMattias Nilsson void __init db8500_prcmu_early_init(void) 2764650c2a21SLinus Walleij { 27653df57bcfSMattias Nilsson unsigned int i; 27663e2762c8SLinus Walleij if (cpu_is_u8500v2()) { 27673df57bcfSMattias Nilsson void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); 27683df57bcfSMattias Nilsson 27693df57bcfSMattias Nilsson if (tcpm_base != NULL) { 27703e2762c8SLinus Walleij u32 version; 27713df57bcfSMattias Nilsson version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); 2772b58d12feSMattias Nilsson fw_info.version.project = version & 0xFF; 2773b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF; 2774b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF; 2775b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF; 2776b58d12feSMattias Nilsson fw_info.valid = true; 2777b58d12feSMattias Nilsson pr_info("PRCMU firmware: %s, version %d.%d.%d\n", 2778b58d12feSMattias Nilsson fw_project_name(fw_info.version.project), 27793df57bcfSMattias Nilsson (version >> 8) & 0xFF, (version >> 16) & 0xFF, 27803df57bcfSMattias Nilsson (version >> 24) & 0xFF); 27813df57bcfSMattias Nilsson iounmap(tcpm_base); 27823df57bcfSMattias Nilsson } 27833df57bcfSMattias Nilsson 2784650c2a21SLinus Walleij tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); 2785650c2a21SLinus Walleij } else { 2786650c2a21SLinus Walleij pr_err("prcmu: Unsupported chip version\n"); 2787650c2a21SLinus Walleij BUG(); 2788650c2a21SLinus Walleij } 2789650c2a21SLinus Walleij 27903df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 27913df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 27923df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 27933df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2794650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2795650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 27964d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE; 27973df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 27983df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 27993df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 28003df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 28013df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 28023df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 28033df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 28043df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2805650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2806650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2807650c2a21SLinus Walleij 28083df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2809650c2a21SLinus Walleij 28103df57bcfSMattias Nilsson /* Initalize irqs. */ 28113df57bcfSMattias Nilsson for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { 28123df57bcfSMattias Nilsson unsigned int irq; 28133df57bcfSMattias Nilsson 28143df57bcfSMattias Nilsson irq = IRQ_PRCMU_BASE + i; 28153df57bcfSMattias Nilsson irq_set_chip_and_handler(irq, &prcmu_irq_chip, 28163df57bcfSMattias Nilsson handle_simple_irq); 28173df57bcfSMattias Nilsson set_irq_flags(irq, IRQF_VALID); 28183df57bcfSMattias Nilsson } 2819650c2a21SLinus Walleij } 2820650c2a21SLinus Walleij 28210508901cSMattias Nilsson static void __init init_prcm_registers(void) 2822d65e12d7SMattias Nilsson { 2823d65e12d7SMattias Nilsson u32 val; 2824d65e12d7SMattias Nilsson 2825d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2826d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2827d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2828d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2829d65e12d7SMattias Nilsson } 2830d65e12d7SMattias Nilsson 28311032fbfdSBengt Jonsson /* 28321032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 28331032fbfdSBengt Jonsson */ 28341032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 28351032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 28361032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 28371032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 28381032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 28391032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 28401032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 28411032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 28421032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 28431032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 28441032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 28451032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 28461032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 28471032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 28481032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 28491032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 28501032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 28511032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 28521032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2853992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 28541032fbfdSBengt Jonsson }; 28551032fbfdSBengt Jonsson 28561032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 28571032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 28581032fbfdSBengt Jonsson /* AV8100 regulator */ 28591032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 28601032fbfdSBengt Jonsson }; 28611032fbfdSBengt Jonsson 28621032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2863992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2864624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2865624e87c2SBengt Jonsson }; 2866624e87c2SBengt Jonsson 2867624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2868624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2869624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2870624e87c2SBengt Jonsson }; 2871624e87c2SBengt Jonsson 2872624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2873624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2874624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2875624e87c2SBengt Jonsson }; 2876624e87c2SBengt Jonsson 2877624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2878624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2879624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2880624e87c2SBengt Jonsson }; 2881624e87c2SBengt Jonsson 2882624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2883624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2884624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2885624e87c2SBengt Jonsson }; 2886624e87c2SBengt Jonsson 2887624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2888624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2889624e87c2SBengt Jonsson }; 2890624e87c2SBengt Jonsson 2891624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2892624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2893624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2894624e87c2SBengt Jonsson }; 2895624e87c2SBengt Jonsson 2896624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2897624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2898624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2899624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 2900992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 29011032fbfdSBengt Jonsson }; 29021032fbfdSBengt Jonsson 29031032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 29041032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 29051032fbfdSBengt Jonsson .constraints = { 29061032fbfdSBengt Jonsson .name = "db8500-vape", 29071032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29081032fbfdSBengt Jonsson }, 29091032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 29101032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 29111032fbfdSBengt Jonsson }, 29121032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 29131032fbfdSBengt Jonsson .constraints = { 29141032fbfdSBengt Jonsson .name = "db8500-varm", 29151032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29161032fbfdSBengt Jonsson }, 29171032fbfdSBengt Jonsson }, 29181032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 29191032fbfdSBengt Jonsson .constraints = { 29201032fbfdSBengt Jonsson .name = "db8500-vmodem", 29211032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29221032fbfdSBengt Jonsson }, 29231032fbfdSBengt Jonsson }, 29241032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 29251032fbfdSBengt Jonsson .constraints = { 29261032fbfdSBengt Jonsson .name = "db8500-vpll", 29271032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29281032fbfdSBengt Jonsson }, 29291032fbfdSBengt Jonsson }, 29301032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 29311032fbfdSBengt Jonsson .constraints = { 29321032fbfdSBengt Jonsson .name = "db8500-vsmps1", 29331032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29341032fbfdSBengt Jonsson }, 29351032fbfdSBengt Jonsson }, 29361032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 29371032fbfdSBengt Jonsson .constraints = { 29381032fbfdSBengt Jonsson .name = "db8500-vsmps2", 29391032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29401032fbfdSBengt Jonsson }, 29411032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 29421032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 29431032fbfdSBengt Jonsson }, 29441032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 29451032fbfdSBengt Jonsson .constraints = { 29461032fbfdSBengt Jonsson .name = "db8500-vsmps3", 29471032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29481032fbfdSBengt Jonsson }, 29491032fbfdSBengt Jonsson }, 29501032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 29511032fbfdSBengt Jonsson .constraints = { 29521032fbfdSBengt Jonsson .name = "db8500-vrf1", 29531032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29541032fbfdSBengt Jonsson }, 29551032fbfdSBengt Jonsson }, 29561032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2957992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29581032fbfdSBengt Jonsson .constraints = { 29591032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 29601032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29611032fbfdSBengt Jonsson }, 2962624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2963624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 29641032fbfdSBengt Jonsson }, 29651032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 29661032fbfdSBengt Jonsson .constraints = { 29671032fbfdSBengt Jonsson /* "ret" means "retention" */ 29681032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 29691032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29701032fbfdSBengt Jonsson }, 29711032fbfdSBengt Jonsson }, 29721032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2973992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29741032fbfdSBengt Jonsson .constraints = { 29751032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 29761032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29771032fbfdSBengt Jonsson }, 2978624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2979624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 29801032fbfdSBengt Jonsson }, 29811032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2982992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29831032fbfdSBengt Jonsson .constraints = { 29841032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 29851032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29861032fbfdSBengt Jonsson }, 2987624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2988624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 29891032fbfdSBengt Jonsson }, 29901032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 29911032fbfdSBengt Jonsson .constraints = { 29921032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 29931032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29941032fbfdSBengt Jonsson }, 29951032fbfdSBengt Jonsson }, 29961032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2997992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29981032fbfdSBengt Jonsson .constraints = { 29991032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 30001032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30011032fbfdSBengt Jonsson }, 3002624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 3003624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 30041032fbfdSBengt Jonsson }, 30051032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 30061032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 30071032fbfdSBengt Jonsson .constraints = { 30081032fbfdSBengt Jonsson .name = "db8500-sga", 30091032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30101032fbfdSBengt Jonsson }, 3011624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 3012624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 3013624e87c2SBengt Jonsson 30141032fbfdSBengt Jonsson }, 30151032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 30161032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 30171032fbfdSBengt Jonsson .constraints = { 30181032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 30191032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30201032fbfdSBengt Jonsson }, 30211032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 30221032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 30231032fbfdSBengt Jonsson }, 30241032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 3025992b133aSBengt Jonsson /* 3026992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off, 3027992b133aSBengt Jonsson * no need to hold Vape 3028992b133aSBengt Jonsson */ 30291032fbfdSBengt Jonsson .constraints = { 30301032fbfdSBengt Jonsson .name = "db8500-esram12", 30311032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30321032fbfdSBengt Jonsson }, 3033624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 3034624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 30351032fbfdSBengt Jonsson }, 30361032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 30371032fbfdSBengt Jonsson .constraints = { 30381032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 30391032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30401032fbfdSBengt Jonsson }, 30411032fbfdSBengt Jonsson }, 30421032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 3043992b133aSBengt Jonsson /* 3044992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off, 3045992b133aSBengt Jonsson * no need to hold Vape 3046992b133aSBengt Jonsson */ 30471032fbfdSBengt Jonsson .constraints = { 30481032fbfdSBengt Jonsson .name = "db8500-esram34", 30491032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30501032fbfdSBengt Jonsson }, 3051624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 3052624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 30531032fbfdSBengt Jonsson }, 30541032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 30551032fbfdSBengt Jonsson .constraints = { 30561032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 30571032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30581032fbfdSBengt Jonsson }, 30591032fbfdSBengt Jonsson }, 30601032fbfdSBengt Jonsson }; 30611032fbfdSBengt Jonsson 30623df57bcfSMattias Nilsson static struct mfd_cell db8500_prcmu_devs[] = { 30633df57bcfSMattias Nilsson { 30643df57bcfSMattias Nilsson .name = "db8500-prcmu-regulators", 30651ed7891fSMattias Wallin .platform_data = &db8500_regulators, 30661ed7891fSMattias Wallin .pdata_size = sizeof(db8500_regulators), 30673df57bcfSMattias Nilsson }, 30683df57bcfSMattias Nilsson { 30693df57bcfSMattias Nilsson .name = "cpufreq-u8500", 30703df57bcfSMattias Nilsson }, 30713df57bcfSMattias Nilsson }; 30723df57bcfSMattias Nilsson 30733df57bcfSMattias Nilsson /** 30743df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 30753df57bcfSMattias Nilsson * 30763df57bcfSMattias Nilsson */ 30773df57bcfSMattias Nilsson static int __init db8500_prcmu_probe(struct platform_device *pdev) 30783df57bcfSMattias Nilsson { 30793df57bcfSMattias Nilsson int err = 0; 30803df57bcfSMattias Nilsson 30813df57bcfSMattias Nilsson if (ux500_is_svp()) 30823df57bcfSMattias Nilsson return -ENODEV; 30833df57bcfSMattias Nilsson 30840508901cSMattias Nilsson init_prcm_registers(); 3085d65e12d7SMattias Nilsson 30863df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 3087c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 30883df57bcfSMattias Nilsson 30893df57bcfSMattias Nilsson err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 30903df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 30913df57bcfSMattias Nilsson if (err < 0) { 30923df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 30933df57bcfSMattias Nilsson err = -EBUSY; 30943df57bcfSMattias Nilsson goto no_irq_return; 30953df57bcfSMattias Nilsson } 30963df57bcfSMattias Nilsson 30973df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later()) 30983df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 30993df57bcfSMattias Nilsson 31003df57bcfSMattias Nilsson err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 31013df57bcfSMattias Nilsson ARRAY_SIZE(db8500_prcmu_devs), NULL, 31023df57bcfSMattias Nilsson 0); 31033df57bcfSMattias Nilsson 31043df57bcfSMattias Nilsson if (err) 31053df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 31063df57bcfSMattias Nilsson else 31073df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 31083df57bcfSMattias Nilsson 31093df57bcfSMattias Nilsson no_irq_return: 31103df57bcfSMattias Nilsson return err; 31113df57bcfSMattias Nilsson } 31123df57bcfSMattias Nilsson 31133df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 31143df57bcfSMattias Nilsson .driver = { 31153df57bcfSMattias Nilsson .name = "db8500-prcmu", 31163df57bcfSMattias Nilsson .owner = THIS_MODULE, 31173df57bcfSMattias Nilsson }, 31183df57bcfSMattias Nilsson }; 31193df57bcfSMattias Nilsson 31203df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 31213df57bcfSMattias Nilsson { 31223df57bcfSMattias Nilsson return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe); 31233df57bcfSMattias Nilsson } 31243df57bcfSMattias Nilsson 31253df57bcfSMattias Nilsson arch_initcall(db8500_prcmu_init); 31263df57bcfSMattias Nilsson 31273df57bcfSMattias Nilsson MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 31283df57bcfSMattias Nilsson MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 31293df57bcfSMattias Nilsson MODULE_LICENSE("GPL v2"); 3130