1650c2a21SLinus Walleij /* 2650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 3650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 4650c2a21SLinus Walleij * 5650c2a21SLinus Walleij * License Terms: GNU General Public License v2 6650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9650c2a21SLinus Walleij * 10650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij */ 13650c2a21SLinus Walleij #include <linux/module.h> 143df57bcfSMattias Nilsson #include <linux/kernel.h> 153df57bcfSMattias Nilsson #include <linux/delay.h> 16650c2a21SLinus Walleij #include <linux/errno.h> 17650c2a21SLinus Walleij #include <linux/err.h> 183df57bcfSMattias Nilsson #include <linux/spinlock.h> 19650c2a21SLinus Walleij #include <linux/io.h> 203df57bcfSMattias Nilsson #include <linux/slab.h> 21650c2a21SLinus Walleij #include <linux/mutex.h> 22650c2a21SLinus Walleij #include <linux/completion.h> 233df57bcfSMattias Nilsson #include <linux/irq.h> 24650c2a21SLinus Walleij #include <linux/jiffies.h> 25650c2a21SLinus Walleij #include <linux/bitops.h> 263df57bcfSMattias Nilsson #include <linux/fs.h> 273df57bcfSMattias Nilsson #include <linux/platform_device.h> 283df57bcfSMattias Nilsson #include <linux/uaccess.h> 293df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3073180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 313a8e39c9SLee Jones #include <linux/mfd/abx500/ab8500.h> 321032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 331032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 34c280f45fSUlf Hansson #include <linux/cpufreq.h> 35cc9a0f68SDaniel Lezcano #include <asm/hardware/gic.h> 36650c2a21SLinus Walleij #include <mach/hardware.h> 373df57bcfSMattias Nilsson #include <mach/irqs.h> 383df57bcfSMattias Nilsson #include <mach/db8500-regs.h> 393df57bcfSMattias Nilsson #include <mach/id.h> 4073180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 41650c2a21SLinus Walleij 423df57bcfSMattias Nilsson /* Offset for the firmware version within the TCPM */ 433df57bcfSMattias Nilsson #define PRCMU_FW_VERSION_OFFSET 0xA4 44650c2a21SLinus Walleij 453df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 463df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 473df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 483df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 493df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 503df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 513df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 523df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 533df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 543df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 553df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 563df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 573df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 583df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 593df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 60650c2a21SLinus Walleij 613df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 623df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 633df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 643df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 65650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 66650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 67650c2a21SLinus Walleij 683df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 693df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 703df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 713df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 72650c2a21SLinus Walleij 733df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 743df57bcfSMattias Nilsson 753df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 793df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 803df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 813df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 823df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 833df57bcfSMattias Nilsson 843df57bcfSMattias Nilsson /* Req Mailboxes */ 853df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 863df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 873df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 883df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 893df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 903df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 913df57bcfSMattias Nilsson 923df57bcfSMattias Nilsson /* Ack Mailboxes */ 933df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 943df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 953df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 963df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 973df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 983df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 993df57bcfSMattias Nilsson 1003df57bcfSMattias Nilsson /* Mailbox 0 headers */ 1013df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 1023df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 1033df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 1043df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1053df57bcfSMattias Nilsson 1063df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1073df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1083df57bcfSMattias Nilsson 1093df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1113df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1123df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1133df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1143df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1153df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1163df57bcfSMattias Nilsson 1173df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1213df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1223df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1233df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1243df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1253df57bcfSMattias Nilsson 1263df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1273df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1283df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1293df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1303df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1313df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 132a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1333df57bcfSMattias Nilsson 1343df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1353df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1363df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 137a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 1386b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1 1396b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2 140a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 141a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1423df57bcfSMattias Nilsson 1433df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1443df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1453df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1463df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1473df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1483df57bcfSMattias Nilsson 1493df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1503df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1513df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1523df57bcfSMattias Nilsson 1533df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1603df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1613df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1623df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1633df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1643df57bcfSMattias Nilsson 1653df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1663df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1673df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1683df57bcfSMattias Nilsson 1693df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1703df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1713df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1723df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1733df57bcfSMattias Nilsson 1743df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1783df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1793df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1803df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1813df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1823df57bcfSMattias Nilsson 1833df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1843df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1853df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1863df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1873df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1883df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 190a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 191a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 192a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 193a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1943df57bcfSMattias Nilsson 1953df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 2003df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 2013df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 2023df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 2033df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 2043df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2053df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 206a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 207a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 208a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 209a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 210a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 211a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 212a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2133df57bcfSMattias Nilsson 2143df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2153df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2163df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2173df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2183df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2193df57bcfSMattias Nilsson #define PRCMU_I2C_WRITE(slave) \ 2203df57bcfSMattias Nilsson (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2213df57bcfSMattias Nilsson #define PRCMU_I2C_READ(slave) \ 2223df57bcfSMattias Nilsson (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2233df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2243df57bcfSMattias Nilsson 2253df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2263df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2273df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2283df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2293df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2303df57bcfSMattias Nilsson 2313df57bcfSMattias Nilsson #define NUM_MB 8 2323df57bcfSMattias Nilsson #define MBOX_BIT BIT 2333df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2343df57bcfSMattias Nilsson 2353df57bcfSMattias Nilsson /* 2363df57bcfSMattias Nilsson * Wakeups/IRQs 2373df57bcfSMattias Nilsson */ 2383df57bcfSMattias Nilsson 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2623df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2633df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2643df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2653df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2663df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2673df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2683df57bcfSMattias Nilsson 269b58d12feSMattias Nilsson static struct { 270b58d12feSMattias Nilsson bool valid; 271b58d12feSMattias Nilsson struct prcmu_fw_version version; 272b58d12feSMattias Nilsson } fw_info; 273b58d12feSMattias Nilsson 274f3f1f0a1SLee Jones static struct irq_domain *db8500_irq_domain; 275f3f1f0a1SLee Jones 2763df57bcfSMattias Nilsson /* 2773df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2783df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2793df57bcfSMattias Nilsson * 2803df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2813df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2823df57bcfSMattias Nilsson * around, to further complicate matters.) 2833df57bcfSMattias Nilsson */ 2843df57bcfSMattias Nilsson #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) 2853df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 2863df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 2873df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 2883df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 2893df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 2903df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 2913df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 2923df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 2933df57bcfSMattias Nilsson IRQ_ENTRY(USB), 2943df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 2953df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 2963df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 2973df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 2983df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 2993df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 3003df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 3013df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 3023df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 3033df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 3043df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 3053df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 3063df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3073df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3083df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3093df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 310650c2a21SLinus Walleij }; 311650c2a21SLinus Walleij 3123df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3133df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3143df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3153df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3163df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3173df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3183df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3193df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3203df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3213df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3223df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3233df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3243df57bcfSMattias Nilsson }; 3253df57bcfSMattias Nilsson 3263df57bcfSMattias Nilsson /* 3273df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3283df57bcfSMattias Nilsson * @lock: The transaction lock. 3293df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3303df57bcfSMattias Nilsson * the request data. 3313df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3323df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3333df57bcfSMattias Nilsson */ 3343df57bcfSMattias Nilsson static struct { 3353df57bcfSMattias Nilsson spinlock_t lock; 3363df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3373df57bcfSMattias Nilsson struct work_struct mask_work; 3383df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3393df57bcfSMattias Nilsson struct completion ac_wake_work; 3403df57bcfSMattias Nilsson struct { 3413df57bcfSMattias Nilsson u32 dbb_irqs; 3423df57bcfSMattias Nilsson u32 dbb_wakeups; 3433df57bcfSMattias Nilsson u32 abb_events; 3443df57bcfSMattias Nilsson } req; 3453df57bcfSMattias Nilsson } mb0_transfer; 3463df57bcfSMattias Nilsson 3473df57bcfSMattias Nilsson /* 3483df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3493df57bcfSMattias Nilsson * @lock: The transaction lock. 3503df57bcfSMattias Nilsson * @work: The transaction completion structure. 3514d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP. 3523df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3533df57bcfSMattias Nilsson */ 354650c2a21SLinus Walleij static struct { 355650c2a21SLinus Walleij struct mutex lock; 356650c2a21SLinus Walleij struct completion work; 3574d64d2e3SMattias Nilsson u8 ape_opp; 358650c2a21SLinus Walleij struct { 3593df57bcfSMattias Nilsson u8 header; 360650c2a21SLinus Walleij u8 arm_opp; 361650c2a21SLinus Walleij u8 ape_opp; 3623df57bcfSMattias Nilsson u8 ape_voltage_status; 363650c2a21SLinus Walleij } ack; 364650c2a21SLinus Walleij } mb1_transfer; 365650c2a21SLinus Walleij 3663df57bcfSMattias Nilsson /* 3673df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3683df57bcfSMattias Nilsson * @lock: The transaction lock. 3693df57bcfSMattias Nilsson * @work: The transaction completion structure. 3703df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3713df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3723df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3733df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3743df57bcfSMattias Nilsson */ 375650c2a21SLinus Walleij static struct { 376650c2a21SLinus Walleij struct mutex lock; 377650c2a21SLinus Walleij struct completion work; 3783df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 3793df57bcfSMattias Nilsson bool auto_pm_enabled; 3803df57bcfSMattias Nilsson struct { 3813df57bcfSMattias Nilsson u8 status; 3823df57bcfSMattias Nilsson } ack; 3833df57bcfSMattias Nilsson } mb2_transfer; 3843df57bcfSMattias Nilsson 3853df57bcfSMattias Nilsson /* 3863df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 3873df57bcfSMattias Nilsson * @lock: The request lock. 3883df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 3893df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 3903df57bcfSMattias Nilsson */ 3913df57bcfSMattias Nilsson static struct { 3923df57bcfSMattias Nilsson spinlock_t lock; 3933df57bcfSMattias Nilsson struct mutex sysclk_lock; 3943df57bcfSMattias Nilsson struct completion sysclk_work; 3953df57bcfSMattias Nilsson } mb3_transfer; 3963df57bcfSMattias Nilsson 3973df57bcfSMattias Nilsson /* 3983df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 3993df57bcfSMattias Nilsson * @lock: The transaction lock. 4003df57bcfSMattias Nilsson * @work: The transaction completion structure. 4013df57bcfSMattias Nilsson */ 4023df57bcfSMattias Nilsson static struct { 4033df57bcfSMattias Nilsson struct mutex lock; 4043df57bcfSMattias Nilsson struct completion work; 4053df57bcfSMattias Nilsson } mb4_transfer; 4063df57bcfSMattias Nilsson 4073df57bcfSMattias Nilsson /* 4083df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4093df57bcfSMattias Nilsson * @lock: The transaction lock. 4103df57bcfSMattias Nilsson * @work: The transaction completion structure. 4113df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4123df57bcfSMattias Nilsson */ 4133df57bcfSMattias Nilsson static struct { 4143df57bcfSMattias Nilsson struct mutex lock; 4153df57bcfSMattias Nilsson struct completion work; 416650c2a21SLinus Walleij struct { 417650c2a21SLinus Walleij u8 status; 418650c2a21SLinus Walleij u8 value; 419650c2a21SLinus Walleij } ack; 420650c2a21SLinus Walleij } mb5_transfer; 421650c2a21SLinus Walleij 4223df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4233df57bcfSMattias Nilsson 4243df57bcfSMattias Nilsson /* Spinlocks */ 425b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock); 4263df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4273df57bcfSMattias Nilsson 4283df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4293df57bcfSMattias Nilsson static __iomem void *tcdm_base; 4303df57bcfSMattias Nilsson 4313df57bcfSMattias Nilsson struct clk_mgt { 4326b6fae2bSMattias Nilsson void __iomem *reg; 4333df57bcfSMattias Nilsson u32 pllsw; 4346b6fae2bSMattias Nilsson int branch; 4356b6fae2bSMattias Nilsson bool clk38div; 4366b6fae2bSMattias Nilsson }; 4376b6fae2bSMattias Nilsson 4386b6fae2bSMattias Nilsson enum { 4396b6fae2bSMattias Nilsson PLL_RAW, 4406b6fae2bSMattias Nilsson PLL_FIX, 4416b6fae2bSMattias Nilsson PLL_DIV 4423df57bcfSMattias Nilsson }; 4433df57bcfSMattias Nilsson 4443df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4453df57bcfSMattias Nilsson 4466b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 4476b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 4483df57bcfSMattias Nilsson struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4496b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 4506b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 4516b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 4526b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 4536b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 4546b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 4556b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 4566b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 4576b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 4586b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 4596b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 4606b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 4616b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 4626b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 4636b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 4646b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 4656b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 4666b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 4676b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 4686b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 4696b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 4706b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 4736b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 4746b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 4756b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 4766b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 4776b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 4786b6fae2bSMattias Nilsson }; 4796b6fae2bSMattias Nilsson 4806b6fae2bSMattias Nilsson struct dsiclk { 4816b6fae2bSMattias Nilsson u32 divsel_mask; 4826b6fae2bSMattias Nilsson u32 divsel_shift; 4836b6fae2bSMattias Nilsson u32 divsel; 4846b6fae2bSMattias Nilsson }; 4856b6fae2bSMattias Nilsson 4866b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = { 4876b6fae2bSMattias Nilsson { 4886b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 4896b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 4906b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4916b6fae2bSMattias Nilsson }, 4926b6fae2bSMattias Nilsson { 4936b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 4946b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 4956b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4966b6fae2bSMattias Nilsson } 4976b6fae2bSMattias Nilsson }; 4986b6fae2bSMattias Nilsson 4996b6fae2bSMattias Nilsson struct dsiescclk { 5006b6fae2bSMattias Nilsson u32 en; 5016b6fae2bSMattias Nilsson u32 div_mask; 5026b6fae2bSMattias Nilsson u32 div_shift; 5036b6fae2bSMattias Nilsson }; 5046b6fae2bSMattias Nilsson 5056b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = { 5066b6fae2bSMattias Nilsson { 5076b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 5086b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 5096b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 5106b6fae2bSMattias Nilsson }, 5116b6fae2bSMattias Nilsson { 5126b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 5136b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 5146b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 5156b6fae2bSMattias Nilsson }, 5166b6fae2bSMattias Nilsson { 5176b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 5186b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 5196b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 5206b6fae2bSMattias Nilsson } 5213df57bcfSMattias Nilsson }; 5223df57bcfSMattias Nilsson 52320aee5b6SMichel Jaouen 5243df57bcfSMattias Nilsson /* 5253df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 5263df57bcfSMattias Nilsson */ 5273df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 5283df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 5293df57bcfSMattias Nilsson 5303df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 5313df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 5323df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5333df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5343df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5353df57bcfSMattias Nilsson 5363df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5373df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5383df57bcfSMattias Nilsson 5393df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5403df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5413df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5423df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5433df57bcfSMattias Nilsson 5443df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5453df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5463df57bcfSMattias Nilsson 5473df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5483df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5493df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5503df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5513df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5523df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5533df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5543df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5553df57bcfSMattias Nilsson 5563df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5573df57bcfSMattias Nilsson 55873180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5593df57bcfSMattias Nilsson { 5603df57bcfSMattias Nilsson int i; 5613df57bcfSMattias Nilsson 5623df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 563c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5643df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 565c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5663df57bcfSMattias Nilsson 5673df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 568c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 569c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5703df57bcfSMattias Nilsson /* Enable Escape clocks */ 571c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5723df57bcfSMattias Nilsson 5733df57bcfSMattias Nilsson /* Start DSI PLL */ 574c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5753df57bcfSMattias Nilsson /* Reset DSI PLL */ 576c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 5773df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 578c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 5793df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 5803df57bcfSMattias Nilsson break; 5813df57bcfSMattias Nilsson udelay(100); 5823df57bcfSMattias Nilsson } 5833df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 584c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 5853df57bcfSMattias Nilsson return 0; 5863df57bcfSMattias Nilsson } 5873df57bcfSMattias Nilsson 58873180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 5893df57bcfSMattias Nilsson { 5903df57bcfSMattias Nilsson /* Disable dsi pll */ 591c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5923df57bcfSMattias Nilsson /* Disable escapeclock */ 593c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5943df57bcfSMattias Nilsson return 0; 5953df57bcfSMattias Nilsson } 5963df57bcfSMattias Nilsson 59773180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 5983df57bcfSMattias Nilsson { 5993df57bcfSMattias Nilsson unsigned long flags; 6003df57bcfSMattias Nilsson 6013df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 6023df57bcfSMattias Nilsson 6033df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 604c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 6053df57bcfSMattias Nilsson cpu_relax(); 6063df57bcfSMattias Nilsson 607c72fe851SDaniel Willerud writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); 608c553b3caSMattias Nilsson writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); 609c553b3caSMattias Nilsson writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); 6103df57bcfSMattias Nilsson 6113df57bcfSMattias Nilsson /* Release the HW semaphore. */ 612c553b3caSMattias Nilsson writel(0, PRCM_SEM); 6133df57bcfSMattias Nilsson 6143df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 6153df57bcfSMattias Nilsson 6163df57bcfSMattias Nilsson return 0; 6173df57bcfSMattias Nilsson } 6183df57bcfSMattias Nilsson 619b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg) 6203df57bcfSMattias Nilsson { 621b4a6dbd5SMattias Nilsson return readl(_PRCMU_BASE + reg); 6223df57bcfSMattias Nilsson } 6233df57bcfSMattias Nilsson 624b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value) 6253df57bcfSMattias Nilsson { 6263df57bcfSMattias Nilsson unsigned long flags; 6273df57bcfSMattias Nilsson 628b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 629b4a6dbd5SMattias Nilsson writel(value, (_PRCMU_BASE + reg)); 630b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 631b4a6dbd5SMattias Nilsson } 632b4a6dbd5SMattias Nilsson 633b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 634b4a6dbd5SMattias Nilsson { 635b4a6dbd5SMattias Nilsson u32 val; 636b4a6dbd5SMattias Nilsson unsigned long flags; 637b4a6dbd5SMattias Nilsson 638b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 639b4a6dbd5SMattias Nilsson val = readl(_PRCMU_BASE + reg); 640b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask)); 641b4a6dbd5SMattias Nilsson writel(val, (_PRCMU_BASE + reg)); 642b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 6433df57bcfSMattias Nilsson } 6443df57bcfSMattias Nilsson 645b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void) 646b58d12feSMattias Nilsson { 647b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL; 648b58d12feSMattias Nilsson } 649b58d12feSMattias Nilsson 6503df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6513df57bcfSMattias Nilsson { 6523df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6533df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6543df57bcfSMattias Nilsson } 6553df57bcfSMattias Nilsson 6563df57bcfSMattias Nilsson /** 6573df57bcfSMattias Nilsson * prcmu_get_boot_status - PRCMU boot status checking 6583df57bcfSMattias Nilsson * Returns: the current PRCMU boot status 6593df57bcfSMattias Nilsson */ 6603df57bcfSMattias Nilsson int prcmu_get_boot_status(void) 6613df57bcfSMattias Nilsson { 6623df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_BOOT_STATUS); 6633df57bcfSMattias Nilsson } 6643df57bcfSMattias Nilsson 6653df57bcfSMattias Nilsson /** 6663df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6673df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6683df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6693df57bcfSMattias Nilsson * 6703df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6713df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6723df57bcfSMattias Nilsson */ 6733df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6743df57bcfSMattias Nilsson { 6753df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 6763df57bcfSMattias Nilsson return -EINVAL; 6773df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 6783df57bcfSMattias Nilsson return 0; 6793df57bcfSMattias Nilsson } 6803df57bcfSMattias Nilsson 6813df57bcfSMattias Nilsson /** 6823df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 6833df57bcfSMattias Nilsson * Returns: the power transition that has last happened 6843df57bcfSMattias Nilsson * 6853df57bcfSMattias Nilsson * This function can return the following transitions- 6863df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6873df57bcfSMattias Nilsson */ 6883df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 6893df57bcfSMattias Nilsson { 6903df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 6913df57bcfSMattias Nilsson } 6923df57bcfSMattias Nilsson 6933df57bcfSMattias Nilsson /** 6943df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 6953df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 6963df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 6973df57bcfSMattias Nilsson */ 6983df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 6993df57bcfSMattias Nilsson { 7003df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 7013df57bcfSMattias Nilsson } 7023df57bcfSMattias Nilsson 7033df57bcfSMattias Nilsson /** 7043df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 7053df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 7063df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 7073df57bcfSMattias Nilsson * @div: The divider to be applied. 7083df57bcfSMattias Nilsson * 7093df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 7103df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 7113df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 7123df57bcfSMattias Nilsson */ 7133df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 7143df57bcfSMattias Nilsson { 7153df57bcfSMattias Nilsson static int requests[2]; 7163df57bcfSMattias Nilsson int r = 0; 7173df57bcfSMattias Nilsson unsigned long flags; 7183df57bcfSMattias Nilsson u32 val; 7193df57bcfSMattias Nilsson u32 bits; 7203df57bcfSMattias Nilsson u32 mask; 7213df57bcfSMattias Nilsson u32 div_mask; 7223df57bcfSMattias Nilsson 7233df57bcfSMattias Nilsson BUG_ON(clkout > 1); 7243df57bcfSMattias Nilsson BUG_ON(div > 63); 7253df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 7263df57bcfSMattias Nilsson 7273df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7283df57bcfSMattias Nilsson return -EINVAL; 7293df57bcfSMattias Nilsson 7303df57bcfSMattias Nilsson switch (clkout) { 7313df57bcfSMattias Nilsson case 0: 7323df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7333df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7343df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7353df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 7363df57bcfSMattias Nilsson break; 7373df57bcfSMattias Nilsson case 1: 7383df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7393df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7403df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7413df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7423df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7433df57bcfSMattias Nilsson break; 7443df57bcfSMattias Nilsson } 7453df57bcfSMattias Nilsson bits &= mask; 7463df57bcfSMattias Nilsson 7473df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7483df57bcfSMattias Nilsson 749c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7503df57bcfSMattias Nilsson if (val & div_mask) { 7513df57bcfSMattias Nilsson if (div) { 7523df57bcfSMattias Nilsson if ((val & mask) != bits) { 7533df57bcfSMattias Nilsson r = -EBUSY; 7543df57bcfSMattias Nilsson goto unlock_and_return; 7553df57bcfSMattias Nilsson } 7563df57bcfSMattias Nilsson } else { 7573df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7583df57bcfSMattias Nilsson r = -EINVAL; 7593df57bcfSMattias Nilsson goto unlock_and_return; 7603df57bcfSMattias Nilsson } 7613df57bcfSMattias Nilsson } 7623df57bcfSMattias Nilsson } 763c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7643df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7653df57bcfSMattias Nilsson 7663df57bcfSMattias Nilsson unlock_and_return: 7673df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7683df57bcfSMattias Nilsson 7693df57bcfSMattias Nilsson return r; 7703df57bcfSMattias Nilsson } 7713df57bcfSMattias Nilsson 77273180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7733df57bcfSMattias Nilsson { 7743df57bcfSMattias Nilsson unsigned long flags; 7753df57bcfSMattias Nilsson 7763df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 7773df57bcfSMattias Nilsson 7783df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 7793df57bcfSMattias Nilsson 780c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 7813df57bcfSMattias Nilsson cpu_relax(); 7823df57bcfSMattias Nilsson 7833df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 7843df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 7853df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 7863df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 7873df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 7883df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 789c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 7903df57bcfSMattias Nilsson 7913df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 7923df57bcfSMattias Nilsson 7933df57bcfSMattias Nilsson return 0; 7943df57bcfSMattias Nilsson } 7953df57bcfSMattias Nilsson 7964d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void) 7974d64d2e3SMattias Nilsson { 7984d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 7994d64d2e3SMattias Nilsson } 8004d64d2e3SMattias Nilsson 801485540dcSDaniel Lezcano /* This function decouple the gic from the prcmu */ 802485540dcSDaniel Lezcano int db8500_prcmu_gic_decouple(void) 803485540dcSDaniel Lezcano { 804801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 805485540dcSDaniel Lezcano 806485540dcSDaniel Lezcano /* Set bit 0 register value to 1 */ 807801448e0SDaniel Lezcano writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, 808801448e0SDaniel Lezcano PRCM_A9_MASK_REQ); 809485540dcSDaniel Lezcano 810485540dcSDaniel Lezcano /* Make sure the register is updated */ 811801448e0SDaniel Lezcano readl(PRCM_A9_MASK_REQ); 812485540dcSDaniel Lezcano 813485540dcSDaniel Lezcano /* Wait a few cycles for the gic mask completion */ 814801448e0SDaniel Lezcano udelay(1); 815485540dcSDaniel Lezcano 816485540dcSDaniel Lezcano return 0; 817485540dcSDaniel Lezcano } 818485540dcSDaniel Lezcano 819485540dcSDaniel Lezcano /* This function recouple the gic with the prcmu */ 820485540dcSDaniel Lezcano int db8500_prcmu_gic_recouple(void) 821485540dcSDaniel Lezcano { 822801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 823485540dcSDaniel Lezcano 824485540dcSDaniel Lezcano /* Set bit 0 register value to 0 */ 825801448e0SDaniel Lezcano writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); 826485540dcSDaniel Lezcano 827485540dcSDaniel Lezcano return 0; 828485540dcSDaniel Lezcano } 829485540dcSDaniel Lezcano 830cc9a0f68SDaniel Lezcano #define PRCMU_GIC_NUMBER_REGS 5 831cc9a0f68SDaniel Lezcano 832cc9a0f68SDaniel Lezcano /* 833cc9a0f68SDaniel Lezcano * This function checks if there are pending irq on the gic. It only 834cc9a0f68SDaniel Lezcano * makes sense if the gic has been decoupled before with the 835cc9a0f68SDaniel Lezcano * db8500_prcmu_gic_decouple function. Disabling an interrupt only 836cc9a0f68SDaniel Lezcano * disables the forwarding of the interrupt to any CPU interface. It 837cc9a0f68SDaniel Lezcano * does not prevent the interrupt from changing state, for example 838cc9a0f68SDaniel Lezcano * becoming pending, or active and pending if it is already 839cc9a0f68SDaniel Lezcano * active. Hence, we have to check the interrupt is pending *and* is 840cc9a0f68SDaniel Lezcano * active. 841cc9a0f68SDaniel Lezcano */ 842cc9a0f68SDaniel Lezcano bool db8500_prcmu_gic_pending_irq(void) 843cc9a0f68SDaniel Lezcano { 844cc9a0f68SDaniel Lezcano u32 pr; /* Pending register */ 845cc9a0f68SDaniel Lezcano u32 er; /* Enable register */ 846cc9a0f68SDaniel Lezcano void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 847cc9a0f68SDaniel Lezcano int i; 848cc9a0f68SDaniel Lezcano 849cc9a0f68SDaniel Lezcano /* 5 registers. STI & PPI not skipped */ 850cc9a0f68SDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { 851cc9a0f68SDaniel Lezcano 852cc9a0f68SDaniel Lezcano pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); 853cc9a0f68SDaniel Lezcano er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 854cc9a0f68SDaniel Lezcano 855cc9a0f68SDaniel Lezcano if (pr & er) 856cc9a0f68SDaniel Lezcano return true; /* There is a pending interrupt */ 857cc9a0f68SDaniel Lezcano } 858cc9a0f68SDaniel Lezcano 859cc9a0f68SDaniel Lezcano return false; 860cc9a0f68SDaniel Lezcano } 861cc9a0f68SDaniel Lezcano 8629f60d33eSDaniel Lezcano /* 8639ab492e1SDaniel Lezcano * This function checks if there are pending interrupt on the 8649ab492e1SDaniel Lezcano * prcmu which has been delegated to monitor the irqs with the 8659ab492e1SDaniel Lezcano * db8500_prcmu_copy_gic_settings function. 8669ab492e1SDaniel Lezcano */ 8679ab492e1SDaniel Lezcano bool db8500_prcmu_pending_irq(void) 8689ab492e1SDaniel Lezcano { 8699ab492e1SDaniel Lezcano u32 it, im; 8709ab492e1SDaniel Lezcano int i; 8719ab492e1SDaniel Lezcano 8729ab492e1SDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 8739ab492e1SDaniel Lezcano it = readl(PRCM_ARMITVAL31TO0 + i * 4); 8749ab492e1SDaniel Lezcano im = readl(PRCM_ARMITMSK31TO0 + i * 4); 8759ab492e1SDaniel Lezcano if (it & im) 8769ab492e1SDaniel Lezcano return true; /* There is a pending interrupt */ 8779ab492e1SDaniel Lezcano } 8789ab492e1SDaniel Lezcano 8799ab492e1SDaniel Lezcano return false; 8809ab492e1SDaniel Lezcano } 8819ab492e1SDaniel Lezcano 8829ab492e1SDaniel Lezcano /* 88334fe6f10SDaniel Lezcano * This function checks if the specified cpu is in in WFI. It's usage 88434fe6f10SDaniel Lezcano * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple 88534fe6f10SDaniel Lezcano * function. Of course passing smp_processor_id() to this function will 88634fe6f10SDaniel Lezcano * always return false... 88734fe6f10SDaniel Lezcano */ 88834fe6f10SDaniel Lezcano bool db8500_prcmu_is_cpu_in_wfi(int cpu) 88934fe6f10SDaniel Lezcano { 89034fe6f10SDaniel Lezcano return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : 89134fe6f10SDaniel Lezcano PRCM_ARM_WFI_STANDBY_WFI0; 89234fe6f10SDaniel Lezcano } 89334fe6f10SDaniel Lezcano 89434fe6f10SDaniel Lezcano /* 8959f60d33eSDaniel Lezcano * This function copies the gic SPI settings to the prcmu in order to 8969f60d33eSDaniel Lezcano * monitor them and abort/finish the retention/off sequence or state. 8979f60d33eSDaniel Lezcano */ 8989f60d33eSDaniel Lezcano int db8500_prcmu_copy_gic_settings(void) 8999f60d33eSDaniel Lezcano { 9009f60d33eSDaniel Lezcano u32 er; /* Enable register */ 9019f60d33eSDaniel Lezcano void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 9029f60d33eSDaniel Lezcano int i; 9039f60d33eSDaniel Lezcano 9049f60d33eSDaniel Lezcano /* We skip the STI and PPI */ 9059f60d33eSDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 9069f60d33eSDaniel Lezcano er = readl_relaxed(dist_base + 9079f60d33eSDaniel Lezcano GIC_DIST_ENABLE_SET + (i + 1) * 4); 9089f60d33eSDaniel Lezcano writel(er, PRCM_ARMITMSK31TO0 + i * 4); 9099f60d33eSDaniel Lezcano } 9109f60d33eSDaniel Lezcano 9119f60d33eSDaniel Lezcano return 0; 9129f60d33eSDaniel Lezcano } 9139f60d33eSDaniel Lezcano 9143df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 9153df57bcfSMattias Nilsson static void config_wakeups(void) 9163df57bcfSMattias Nilsson { 9173df57bcfSMattias Nilsson const u8 header[2] = { 9183df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 9193df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 9203df57bcfSMattias Nilsson }; 9213df57bcfSMattias Nilsson static u32 last_dbb_events; 9223df57bcfSMattias Nilsson static u32 last_abb_events; 9233df57bcfSMattias Nilsson u32 dbb_events; 9243df57bcfSMattias Nilsson u32 abb_events; 9253df57bcfSMattias Nilsson unsigned int i; 9263df57bcfSMattias Nilsson 9273df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 9283df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 9293df57bcfSMattias Nilsson 9303df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 9313df57bcfSMattias Nilsson 9323df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 9333df57bcfSMattias Nilsson return; 9343df57bcfSMattias Nilsson 9353df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 936c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 9373df57bcfSMattias Nilsson cpu_relax(); 9383df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 9393df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 9403df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 941c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 9423df57bcfSMattias Nilsson } 9433df57bcfSMattias Nilsson last_dbb_events = dbb_events; 9443df57bcfSMattias Nilsson last_abb_events = abb_events; 9453df57bcfSMattias Nilsson } 9463df57bcfSMattias Nilsson 94773180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 9483df57bcfSMattias Nilsson { 9493df57bcfSMattias Nilsson unsigned long flags; 9503df57bcfSMattias Nilsson u32 bits; 9513df57bcfSMattias Nilsson int i; 9523df57bcfSMattias Nilsson 9533df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 9543df57bcfSMattias Nilsson 9553df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 9563df57bcfSMattias Nilsson if (wakeups & BIT(i)) 9573df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 9583df57bcfSMattias Nilsson } 9593df57bcfSMattias Nilsson 9603df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9613df57bcfSMattias Nilsson 9623df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 9633df57bcfSMattias Nilsson config_wakeups(); 9643df57bcfSMattias Nilsson 9653df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9663df57bcfSMattias Nilsson } 9673df57bcfSMattias Nilsson 96873180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 9693df57bcfSMattias Nilsson { 9703df57bcfSMattias Nilsson unsigned long flags; 9713df57bcfSMattias Nilsson 9723df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9733df57bcfSMattias Nilsson 9743df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 9753df57bcfSMattias Nilsson config_wakeups(); 9763df57bcfSMattias Nilsson 9773df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9783df57bcfSMattias Nilsson } 9793df57bcfSMattias Nilsson 98073180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 9813df57bcfSMattias Nilsson { 9823df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 9833df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 9843df57bcfSMattias Nilsson else 9853df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 9863df57bcfSMattias Nilsson } 9873df57bcfSMattias Nilsson 9883df57bcfSMattias Nilsson /** 98973180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 9903df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 9913df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9923df57bcfSMattias Nilsson * 9933df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 9943df57bcfSMattias Nilsson */ 99573180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 9963df57bcfSMattias Nilsson { 9973df57bcfSMattias Nilsson int r; 9983df57bcfSMattias Nilsson 9993df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 10003df57bcfSMattias Nilsson return -EINVAL; 10013df57bcfSMattias Nilsson 10023df57bcfSMattias Nilsson r = 0; 10033df57bcfSMattias Nilsson 10043df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10053df57bcfSMattias Nilsson 1006c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10073df57bcfSMattias Nilsson cpu_relax(); 10083df57bcfSMattias Nilsson 10093df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10103df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 10113df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 10123df57bcfSMattias Nilsson 1013c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10143df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10153df57bcfSMattias Nilsson 10163df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 10173df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 10183df57bcfSMattias Nilsson r = -EIO; 10193df57bcfSMattias Nilsson 10203df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10213df57bcfSMattias Nilsson 10223df57bcfSMattias Nilsson return r; 10233df57bcfSMattias Nilsson } 10243df57bcfSMattias Nilsson 10253df57bcfSMattias Nilsson /** 102673180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 10273df57bcfSMattias Nilsson * 10283df57bcfSMattias Nilsson * Returns: the current ARM OPP 10293df57bcfSMattias Nilsson */ 103073180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 10313df57bcfSMattias Nilsson { 10323df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 10333df57bcfSMattias Nilsson } 10343df57bcfSMattias Nilsson 10353df57bcfSMattias Nilsson /** 10360508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP 10373df57bcfSMattias Nilsson * 10383df57bcfSMattias Nilsson * Returns: the current DDR OPP 10393df57bcfSMattias Nilsson */ 10400508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void) 10413df57bcfSMattias Nilsson { 1042c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 10433df57bcfSMattias Nilsson } 10443df57bcfSMattias Nilsson 10453df57bcfSMattias Nilsson /** 10460508901cSMattias Nilsson * db8500_set_ddr_opp - set the appropriate DDR OPP 10473df57bcfSMattias Nilsson * @opp: The new DDR operating point to which transition is to be made 10483df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10493df57bcfSMattias Nilsson * 10503df57bcfSMattias Nilsson * This function sets the operating point of the DDR. 10513df57bcfSMattias Nilsson */ 10520508901cSMattias Nilsson int db8500_prcmu_set_ddr_opp(u8 opp) 10533df57bcfSMattias Nilsson { 10543df57bcfSMattias Nilsson if (opp < DDR_100_OPP || opp > DDR_25_OPP) 10553df57bcfSMattias Nilsson return -EINVAL; 10563df57bcfSMattias Nilsson /* Changing the DDR OPP can hang the hardware pre-v21 */ 10573df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) 1058c553b3caSMattias Nilsson writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 10593df57bcfSMattias Nilsson 10603df57bcfSMattias Nilsson return 0; 10613df57bcfSMattias Nilsson } 10626b6fae2bSMattias Nilsson 10634d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 10644d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable) 10654d64d2e3SMattias Nilsson { 10664d64d2e3SMattias Nilsson void __iomem *clock_reg[] = { 10674d64d2e3SMattias Nilsson PRCM_ACLK_MGT, 10684d64d2e3SMattias Nilsson PRCM_DMACLK_MGT 10694d64d2e3SMattias Nilsson }; 10704d64d2e3SMattias Nilsson unsigned long flags; 10714d64d2e3SMattias Nilsson unsigned int i; 10724d64d2e3SMattias Nilsson 10734d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 10744d64d2e3SMattias Nilsson 10754d64d2e3SMattias Nilsson /* Grab the HW semaphore. */ 10764d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 10774d64d2e3SMattias Nilsson cpu_relax(); 10784d64d2e3SMattias Nilsson 10794d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 10804d64d2e3SMattias Nilsson u32 val; 10814d64d2e3SMattias Nilsson u32 div; 10824d64d2e3SMattias Nilsson 10834d64d2e3SMattias Nilsson val = readl(clock_reg[i]); 10844d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 10854d64d2e3SMattias Nilsson if (enable) { 10864d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) { 10874d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n", 10884d64d2e3SMattias Nilsson div, __func__); 10894d64d2e3SMattias Nilsson goto unlock_and_return; 10904d64d2e3SMattias Nilsson } 10914d64d2e3SMattias Nilsson div <<= 1; 10924d64d2e3SMattias Nilsson } else { 10934d64d2e3SMattias Nilsson if (div <= 2) 10944d64d2e3SMattias Nilsson goto unlock_and_return; 10954d64d2e3SMattias Nilsson div >>= 1; 10964d64d2e3SMattias Nilsson } 10974d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 10984d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 10994d64d2e3SMattias Nilsson writel(val, clock_reg[i]); 11004d64d2e3SMattias Nilsson } 11014d64d2e3SMattias Nilsson 11024d64d2e3SMattias Nilsson unlock_and_return: 11034d64d2e3SMattias Nilsson /* Release the HW semaphore. */ 11044d64d2e3SMattias Nilsson writel(0, PRCM_SEM); 11054d64d2e3SMattias Nilsson 11064d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 11074d64d2e3SMattias Nilsson } 11084d64d2e3SMattias Nilsson 11093df57bcfSMattias Nilsson /** 11100508901cSMattias Nilsson * db8500_set_ape_opp - set the appropriate APE OPP 11113df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 11123df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 11133df57bcfSMattias Nilsson * 11143df57bcfSMattias Nilsson * This function sets the operating point of the APE. 11153df57bcfSMattias Nilsson */ 11160508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp) 11173df57bcfSMattias Nilsson { 11183df57bcfSMattias Nilsson int r = 0; 11193df57bcfSMattias Nilsson 11204d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp) 11214d64d2e3SMattias Nilsson return 0; 11224d64d2e3SMattias Nilsson 11233df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11243df57bcfSMattias Nilsson 11254d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 11264d64d2e3SMattias Nilsson request_even_slower_clocks(false); 11274d64d2e3SMattias Nilsson 11284d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 11294d64d2e3SMattias Nilsson goto skip_message; 11304d64d2e3SMattias Nilsson 1131c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11323df57bcfSMattias Nilsson cpu_relax(); 11333df57bcfSMattias Nilsson 11343df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11353df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 11364d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 11374d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 11383df57bcfSMattias Nilsson 1139c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11403df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11413df57bcfSMattias Nilsson 11423df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 11433df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 11443df57bcfSMattias Nilsson r = -EIO; 11453df57bcfSMattias Nilsson 11464d64d2e3SMattias Nilsson skip_message: 11474d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 11484d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 11494d64d2e3SMattias Nilsson request_even_slower_clocks(true); 11504d64d2e3SMattias Nilsson if (!r) 11514d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp; 11524d64d2e3SMattias Nilsson 11533df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11543df57bcfSMattias Nilsson 11553df57bcfSMattias Nilsson return r; 11563df57bcfSMattias Nilsson } 11573df57bcfSMattias Nilsson 11583df57bcfSMattias Nilsson /** 11590508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP 11603df57bcfSMattias Nilsson * 11613df57bcfSMattias Nilsson * Returns: the current APE OPP 11623df57bcfSMattias Nilsson */ 11630508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void) 11643df57bcfSMattias Nilsson { 11653df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 11663df57bcfSMattias Nilsson } 11673df57bcfSMattias Nilsson 11683df57bcfSMattias Nilsson /** 1169686f871bSUlf Hansson * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 11703df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 11713df57bcfSMattias Nilsson * 11723df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 11733df57bcfSMattias Nilsson */ 1174686f871bSUlf Hansson int db8500_prcmu_request_ape_opp_100_voltage(bool enable) 11753df57bcfSMattias Nilsson { 11763df57bcfSMattias Nilsson int r = 0; 11773df57bcfSMattias Nilsson u8 header; 11783df57bcfSMattias Nilsson static unsigned int requests; 11793df57bcfSMattias Nilsson 11803df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11813df57bcfSMattias Nilsson 11823df57bcfSMattias Nilsson if (enable) { 11833df57bcfSMattias Nilsson if (0 != requests++) 11843df57bcfSMattias Nilsson goto unlock_and_return; 11853df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 11863df57bcfSMattias Nilsson } else { 11873df57bcfSMattias Nilsson if (requests == 0) { 11883df57bcfSMattias Nilsson r = -EIO; 11893df57bcfSMattias Nilsson goto unlock_and_return; 11903df57bcfSMattias Nilsson } else if (1 != requests--) { 11913df57bcfSMattias Nilsson goto unlock_and_return; 11923df57bcfSMattias Nilsson } 11933df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 11943df57bcfSMattias Nilsson } 11953df57bcfSMattias Nilsson 1196c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11973df57bcfSMattias Nilsson cpu_relax(); 11983df57bcfSMattias Nilsson 11993df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12003df57bcfSMattias Nilsson 1201c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12023df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 12033df57bcfSMattias Nilsson 12043df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 12053df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 12063df57bcfSMattias Nilsson r = -EIO; 12073df57bcfSMattias Nilsson 12083df57bcfSMattias Nilsson unlock_and_return: 12093df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12103df57bcfSMattias Nilsson 12113df57bcfSMattias Nilsson return r; 12123df57bcfSMattias Nilsson } 12133df57bcfSMattias Nilsson 12143df57bcfSMattias Nilsson /** 12153df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 12163df57bcfSMattias Nilsson * 12173df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 12183df57bcfSMattias Nilsson */ 12193df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 12203df57bcfSMattias Nilsson { 12213df57bcfSMattias Nilsson int r = 0; 12223df57bcfSMattias Nilsson 12233df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 12243df57bcfSMattias Nilsson 1225c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 12263df57bcfSMattias Nilsson cpu_relax(); 12273df57bcfSMattias Nilsson 12283df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 12293df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12303df57bcfSMattias Nilsson 1231c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12323df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 12333df57bcfSMattias Nilsson 12343df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 12353df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 12363df57bcfSMattias Nilsson r = -EIO; 12373df57bcfSMattias Nilsson 12383df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12393df57bcfSMattias Nilsson 12403df57bcfSMattias Nilsson return r; 12413df57bcfSMattias Nilsson } 12423df57bcfSMattias Nilsson 12430837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 12440837bb72SMattias Nilsson { 12450837bb72SMattias Nilsson int r = 0; 12460837bb72SMattias Nilsson 12476b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0) 12486b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 12496b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 12500837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 12510837bb72SMattias Nilsson else 12520837bb72SMattias Nilsson return -EINVAL; 12530837bb72SMattias Nilsson 12540837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 12550837bb72SMattias Nilsson 12560837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 12570837bb72SMattias Nilsson cpu_relax(); 12580837bb72SMattias Nilsson 12590837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12600837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 12610837bb72SMattias Nilsson 12620837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12630837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 12640837bb72SMattias Nilsson 12650837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 12660837bb72SMattias Nilsson r = -EIO; 12670837bb72SMattias Nilsson 12680837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12690837bb72SMattias Nilsson 12700837bb72SMattias Nilsson return r; 12710837bb72SMattias Nilsson } 12720837bb72SMattias Nilsson 12733df57bcfSMattias Nilsson /** 127473180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 12753df57bcfSMattias Nilsson * @epod_id: The EPOD to set 12763df57bcfSMattias Nilsson * @epod_state: The new EPOD state 12773df57bcfSMattias Nilsson * 12783df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 12793df57bcfSMattias Nilsson * from interrupt context. 12803df57bcfSMattias Nilsson */ 128173180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 12823df57bcfSMattias Nilsson { 12833df57bcfSMattias Nilsson int r = 0; 12843df57bcfSMattias Nilsson bool ram_retention = false; 12853df57bcfSMattias Nilsson int i; 12863df57bcfSMattias Nilsson 12873df57bcfSMattias Nilsson /* check argument */ 12883df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 12893df57bcfSMattias Nilsson 12903df57bcfSMattias Nilsson /* set flag if retention is possible */ 12913df57bcfSMattias Nilsson switch (epod_id) { 12923df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 12933df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 12943df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 12953df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 12963df57bcfSMattias Nilsson ram_retention = true; 12973df57bcfSMattias Nilsson break; 12983df57bcfSMattias Nilsson } 12993df57bcfSMattias Nilsson 13003df57bcfSMattias Nilsson /* check argument */ 13013df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 13023df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 13033df57bcfSMattias Nilsson 13043df57bcfSMattias Nilsson /* get lock */ 13053df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 13063df57bcfSMattias Nilsson 13073df57bcfSMattias Nilsson /* wait for mailbox */ 1308c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 13093df57bcfSMattias Nilsson cpu_relax(); 13103df57bcfSMattias Nilsson 13113df57bcfSMattias Nilsson /* fill in mailbox */ 13123df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 13133df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 13143df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 13153df57bcfSMattias Nilsson 13163df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 13173df57bcfSMattias Nilsson 1318c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 13193df57bcfSMattias Nilsson 13203df57bcfSMattias Nilsson /* 13213df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 13223df57bcfSMattias Nilsson * and we cannot recover if there is an error. 13233df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 13243df57bcfSMattias Nilsson */ 13253df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 13263df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 13273df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 13283df57bcfSMattias Nilsson __func__); 13293df57bcfSMattias Nilsson r = -EIO; 13303df57bcfSMattias Nilsson goto unlock_and_return; 13313df57bcfSMattias Nilsson } 13323df57bcfSMattias Nilsson 13333df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 13343df57bcfSMattias Nilsson r = -EIO; 13353df57bcfSMattias Nilsson 13363df57bcfSMattias Nilsson unlock_and_return: 13373df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 13383df57bcfSMattias Nilsson return r; 13393df57bcfSMattias Nilsson } 13403df57bcfSMattias Nilsson 13413df57bcfSMattias Nilsson /** 13423df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 13433df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 13443df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 13453df57bcfSMattias Nilsson */ 13463df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 13473df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 13483df57bcfSMattias Nilsson { 13493df57bcfSMattias Nilsson u32 sleep_cfg; 13503df57bcfSMattias Nilsson u32 idle_cfg; 13513df57bcfSMattias Nilsson unsigned long flags; 13523df57bcfSMattias Nilsson 13533df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 13543df57bcfSMattias Nilsson 13553df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 13563df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 13573df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 13583df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 13593df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 13603df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 13613df57bcfSMattias Nilsson 13623df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 13633df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 13643df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 13653df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 13663df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 13673df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 13683df57bcfSMattias Nilsson 13693df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 13703df57bcfSMattias Nilsson 13713df57bcfSMattias Nilsson /* 13723df57bcfSMattias Nilsson * The autonomous power management configuration is done through 13733df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 13743df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 13753df57bcfSMattias Nilsson */ 13763df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 13773df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 13783df57bcfSMattias Nilsson 13793df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 13803df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 13813df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 13823df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 13833df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 13843df57bcfSMattias Nilsson 13853df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 13863df57bcfSMattias Nilsson } 13873df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 13883df57bcfSMattias Nilsson 13893df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 13903df57bcfSMattias Nilsson { 13913df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 13923df57bcfSMattias Nilsson } 13933df57bcfSMattias Nilsson 13943df57bcfSMattias Nilsson static int request_sysclk(bool enable) 13953df57bcfSMattias Nilsson { 13963df57bcfSMattias Nilsson int r; 13973df57bcfSMattias Nilsson unsigned long flags; 13983df57bcfSMattias Nilsson 13993df57bcfSMattias Nilsson r = 0; 14003df57bcfSMattias Nilsson 14013df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 14023df57bcfSMattias Nilsson 14033df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 14043df57bcfSMattias Nilsson 1405c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 14063df57bcfSMattias Nilsson cpu_relax(); 14073df57bcfSMattias Nilsson 14083df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 14093df57bcfSMattias Nilsson 14103df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1411c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 14123df57bcfSMattias Nilsson 14133df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 14143df57bcfSMattias Nilsson 14153df57bcfSMattias Nilsson /* 14163df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 14173df57bcfSMattias Nilsson * SysClk, and it succeeds. 14183df57bcfSMattias Nilsson */ 14193df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 14203df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 14213df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 14223df57bcfSMattias Nilsson __func__); 14233df57bcfSMattias Nilsson r = -EIO; 14243df57bcfSMattias Nilsson } 14253df57bcfSMattias Nilsson 14263df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 14273df57bcfSMattias Nilsson 14283df57bcfSMattias Nilsson return r; 14293df57bcfSMattias Nilsson } 14303df57bcfSMattias Nilsson 14313df57bcfSMattias Nilsson static int request_timclk(bool enable) 14323df57bcfSMattias Nilsson { 14333df57bcfSMattias Nilsson u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 14343df57bcfSMattias Nilsson 14353df57bcfSMattias Nilsson if (!enable) 14363df57bcfSMattias Nilsson val |= PRCM_TCR_STOP_TIMERS; 1437c553b3caSMattias Nilsson writel(val, PRCM_TCR); 14383df57bcfSMattias Nilsson 14393df57bcfSMattias Nilsson return 0; 14403df57bcfSMattias Nilsson } 14413df57bcfSMattias Nilsson 14426b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable) 14433df57bcfSMattias Nilsson { 14443df57bcfSMattias Nilsson u32 val; 14453df57bcfSMattias Nilsson unsigned long flags; 14463df57bcfSMattias Nilsson 14473df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 14483df57bcfSMattias Nilsson 14493df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1450c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 14513df57bcfSMattias Nilsson cpu_relax(); 14523df57bcfSMattias Nilsson 14536b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 14543df57bcfSMattias Nilsson if (enable) { 14553df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 14563df57bcfSMattias Nilsson } else { 14573df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 14583df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 14593df57bcfSMattias Nilsson } 14606b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 14613df57bcfSMattias Nilsson 14623df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1463c553b3caSMattias Nilsson writel(0, PRCM_SEM); 14643df57bcfSMattias Nilsson 14653df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 14663df57bcfSMattias Nilsson 14673df57bcfSMattias Nilsson return 0; 14683df57bcfSMattias Nilsson } 14693df57bcfSMattias Nilsson 14700837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 14710837bb72SMattias Nilsson { 14720837bb72SMattias Nilsson u32 val; 14730837bb72SMattias Nilsson int ret; 14740837bb72SMattias Nilsson 14750837bb72SMattias Nilsson if (enable) { 14760837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 14770837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 14780837bb72SMattias Nilsson } 14790837bb72SMattias Nilsson 14806b6fae2bSMattias Nilsson ret = request_clock(clock, enable); 14810837bb72SMattias Nilsson 14820837bb72SMattias Nilsson if (!ret && !enable) { 14830837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 14840837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 14850837bb72SMattias Nilsson } 14860837bb72SMattias Nilsson 14870837bb72SMattias Nilsson return ret; 14880837bb72SMattias Nilsson } 14890837bb72SMattias Nilsson 14906b6fae2bSMattias Nilsson static inline bool plldsi_locked(void) 14916b6fae2bSMattias Nilsson { 14926b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) & 14936b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 14946b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 14956b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 14966b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 14976b6fae2bSMattias Nilsson } 14986b6fae2bSMattias Nilsson 14996b6fae2bSMattias Nilsson static int request_plldsi(bool enable) 15006b6fae2bSMattias Nilsson { 15016b6fae2bSMattias Nilsson int r = 0; 15026b6fae2bSMattias Nilsson u32 val; 15036b6fae2bSMattias Nilsson 15046b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 15056b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 15066b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 15076b6fae2bSMattias Nilsson 15086b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE); 15096b6fae2bSMattias Nilsson if (enable) 15106b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15116b6fae2bSMattias Nilsson else 15126b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15136b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 15146b6fae2bSMattias Nilsson 15156b6fae2bSMattias Nilsson if (enable) { 15166b6fae2bSMattias Nilsson unsigned int i; 15176b6fae2bSMattias Nilsson bool locked = plldsi_locked(); 15186b6fae2bSMattias Nilsson 15196b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) { 15206b6fae2bSMattias Nilsson udelay(100); 15216b6fae2bSMattias Nilsson locked = plldsi_locked(); 15226b6fae2bSMattias Nilsson } 15236b6fae2bSMattias Nilsson if (locked) { 15246b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, 15256b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET); 15266b6fae2bSMattias Nilsson } else { 15276b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 15286b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 15296b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET); 15306b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15316b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 15326b6fae2bSMattias Nilsson r = -EAGAIN; 15336b6fae2bSMattias Nilsson } 15346b6fae2bSMattias Nilsson } else { 15356b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 15366b6fae2bSMattias Nilsson } 15376b6fae2bSMattias Nilsson return r; 15386b6fae2bSMattias Nilsson } 15396b6fae2bSMattias Nilsson 15406b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable) 15416b6fae2bSMattias Nilsson { 15426b6fae2bSMattias Nilsson u32 val; 15436b6fae2bSMattias Nilsson 15446b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 15456b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 15466b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 15476b6fae2bSMattias Nilsson dsiclk[n].divsel_shift); 15486b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 15496b6fae2bSMattias Nilsson return 0; 15506b6fae2bSMattias Nilsson } 15516b6fae2bSMattias Nilsson 15526b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable) 15536b6fae2bSMattias Nilsson { 15546b6fae2bSMattias Nilsson u32 val; 15556b6fae2bSMattias Nilsson 15566b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 15576b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 15586b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 15596b6fae2bSMattias Nilsson return 0; 15606b6fae2bSMattias Nilsson } 15616b6fae2bSMattias Nilsson 15623df57bcfSMattias Nilsson /** 156373180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 15643df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 15653df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 15663df57bcfSMattias Nilsson * 15673df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 15683df57bcfSMattias Nilsson * Do not use it from any other place! 15693df57bcfSMattias Nilsson */ 157073180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 15713df57bcfSMattias Nilsson { 15726b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK) 15730837bb72SMattias Nilsson return request_sga_clock(clock, enable); 15746b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS) 15756b6fae2bSMattias Nilsson return request_clock(clock, enable); 15766b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 15773df57bcfSMattias Nilsson return request_timclk(enable); 15786b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 15796b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 15806b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 15816b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 15826b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 15836b6fae2bSMattias Nilsson return request_plldsi(enable); 15846b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 15853df57bcfSMattias Nilsson return request_sysclk(enable); 15866b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 15870837bb72SMattias Nilsson return request_pll(clock, enable); 15886b6fae2bSMattias Nilsson else 15896b6fae2bSMattias Nilsson return -EINVAL; 15906b6fae2bSMattias Nilsson } 15916b6fae2bSMattias Nilsson 15926b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 15936b6fae2bSMattias Nilsson int branch) 15946b6fae2bSMattias Nilsson { 15956b6fae2bSMattias Nilsson u64 rate; 15966b6fae2bSMattias Nilsson u32 val; 15976b6fae2bSMattias Nilsson u32 d; 15986b6fae2bSMattias Nilsson u32 div = 1; 15996b6fae2bSMattias Nilsson 16006b6fae2bSMattias Nilsson val = readl(reg); 16016b6fae2bSMattias Nilsson 16026b6fae2bSMattias Nilsson rate = src_rate; 16036b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 16046b6fae2bSMattias Nilsson 16056b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 16066b6fae2bSMattias Nilsson if (d > 1) 16076b6fae2bSMattias Nilsson div *= d; 16086b6fae2bSMattias Nilsson 16096b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 16106b6fae2bSMattias Nilsson if (d > 1) 16116b6fae2bSMattias Nilsson div *= d; 16126b6fae2bSMattias Nilsson 16136b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2) 16146b6fae2bSMattias Nilsson div *= 2; 16156b6fae2bSMattias Nilsson 16166b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 16176b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) && 16186b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) || 161920aee5b6SMichel Jaouen (reg == PRCM_PLLARM_FREQ) || 16206b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ)))) 16216b6fae2bSMattias Nilsson div *= 2; 16226b6fae2bSMattias Nilsson 16236b6fae2bSMattias Nilsson (void)do_div(rate, div); 16246b6fae2bSMattias Nilsson 16256b6fae2bSMattias Nilsson return (unsigned long)rate; 16266b6fae2bSMattias Nilsson } 16276b6fae2bSMattias Nilsson 16286b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000 16296b6fae2bSMattias Nilsson 16306b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock) 16316b6fae2bSMattias Nilsson { 16326b6fae2bSMattias Nilsson u32 val; 16336b6fae2bSMattias Nilsson u32 pllsw; 16346b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE; 16356b6fae2bSMattias Nilsson 16366b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 16376b6fae2bSMattias Nilsson 16386b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 16396b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 16406b6fae2bSMattias Nilsson rate /= 2; 16416b6fae2bSMattias Nilsson return rate; 16426b6fae2bSMattias Nilsson } 16436b6fae2bSMattias Nilsson 16446b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw; 16456b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 16466b6fae2bSMattias Nilsson 16476b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 16486b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 16496b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 16506b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 16516b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 16526b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 16536b6fae2bSMattias Nilsson else 16546b6fae2bSMattias Nilsson return 0; 16556b6fae2bSMattias Nilsson 16566b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) && 16576b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 16586b6fae2bSMattias Nilsson u64 r = (rate * 10); 16596b6fae2bSMattias Nilsson 16606b6fae2bSMattias Nilsson (void)do_div(r, 25); 16616b6fae2bSMattias Nilsson return (unsigned long)r; 16626b6fae2bSMattias Nilsson } 16636b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 16646b6fae2bSMattias Nilsson if (val) 16656b6fae2bSMattias Nilsson return rate / val; 16666b6fae2bSMattias Nilsson else 16676b6fae2bSMattias Nilsson return 0; 16686b6fae2bSMattias Nilsson } 166920aee5b6SMichel Jaouen 1670b2302c87SUlf Hansson static unsigned long armss_rate(void) 167120aee5b6SMichel Jaouen { 167220aee5b6SMichel Jaouen u32 r; 167320aee5b6SMichel Jaouen unsigned long rate; 167420aee5b6SMichel Jaouen 167520aee5b6SMichel Jaouen r = readl(PRCM_ARM_CHGCLKREQ); 167620aee5b6SMichel Jaouen 167720aee5b6SMichel Jaouen if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { 167820aee5b6SMichel Jaouen /* External ARMCLKFIX clock */ 167920aee5b6SMichel Jaouen 168020aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); 168120aee5b6SMichel Jaouen 168220aee5b6SMichel Jaouen /* Check PRCM_ARM_CHGCLKREQ divider */ 168320aee5b6SMichel Jaouen if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) 168420aee5b6SMichel Jaouen rate /= 2; 168520aee5b6SMichel Jaouen 168620aee5b6SMichel Jaouen /* Check PRCM_ARMCLKFIX_MGT divider */ 168720aee5b6SMichel Jaouen r = readl(PRCM_ARMCLKFIX_MGT); 168820aee5b6SMichel Jaouen r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 168920aee5b6SMichel Jaouen rate /= r; 169020aee5b6SMichel Jaouen 169120aee5b6SMichel Jaouen } else {/* ARM PLL */ 169220aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); 169320aee5b6SMichel Jaouen } 169420aee5b6SMichel Jaouen 1695b2302c87SUlf Hansson return rate; 169620aee5b6SMichel Jaouen } 16976b6fae2bSMattias Nilsson 16986b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n) 16996b6fae2bSMattias Nilsson { 17006b6fae2bSMattias Nilsson u32 divsel; 17016b6fae2bSMattias Nilsson u32 div = 1; 17026b6fae2bSMattias Nilsson 17036b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL); 17046b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 17056b6fae2bSMattias Nilsson 17066b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 17076b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel; 17086b6fae2bSMattias Nilsson 17096b6fae2bSMattias Nilsson switch (divsel) { 17106b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4: 17116b6fae2bSMattias Nilsson div *= 2; 17126b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2: 17136b6fae2bSMattias Nilsson div *= 2; 17146b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI: 17156b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 17166b6fae2bSMattias Nilsson PLL_RAW) / div; 1717e62ccf3aSLinus Walleij default: 17186b6fae2bSMattias Nilsson return 0; 17196b6fae2bSMattias Nilsson } 17206b6fae2bSMattias Nilsson } 17216b6fae2bSMattias Nilsson 17226b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n) 17236b6fae2bSMattias Nilsson { 17246b6fae2bSMattias Nilsson u32 div; 17256b6fae2bSMattias Nilsson 17266b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV); 17276b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 17286b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 17296b6fae2bSMattias Nilsson } 17306b6fae2bSMattias Nilsson 17316b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock) 17326b6fae2bSMattias Nilsson { 17336b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 17346b6fae2bSMattias Nilsson return clock_rate(clock); 17356b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 17366b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE / 16; 17376b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 17386b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 17396b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0) 17406b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17416b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 17426b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 174320aee5b6SMichel Jaouen else if (clock == PRCMU_ARMSS) 174420aee5b6SMichel Jaouen return armss_rate(); 17456b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR) 17466b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17476b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 17486b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 17496b6fae2bSMattias Nilsson PLL_RAW); 17506b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 17516b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK); 17526b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 17536b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 17546b6fae2bSMattias Nilsson else 17556b6fae2bSMattias Nilsson return 0; 17566b6fae2bSMattias Nilsson } 17576b6fae2bSMattias Nilsson 17586b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 17596b6fae2bSMattias Nilsson { 17606b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 17616b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 17626b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 17636b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 17646b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 17656b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 17666b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 17676b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 17686b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 17696b6fae2bSMattias Nilsson else 17706b6fae2bSMattias Nilsson return 0; 17716b6fae2bSMattias Nilsson } 17726b6fae2bSMattias Nilsson 17736b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate) 17746b6fae2bSMattias Nilsson { 17756b6fae2bSMattias Nilsson u32 div; 17766b6fae2bSMattias Nilsson 17776b6fae2bSMattias Nilsson div = (src_rate / rate); 17786b6fae2bSMattias Nilsson if (div == 0) 17796b6fae2bSMattias Nilsson return 1; 17806b6fae2bSMattias Nilsson if (rate < (src_rate / div)) 17816b6fae2bSMattias Nilsson div++; 17826b6fae2bSMattias Nilsson return div; 17836b6fae2bSMattias Nilsson } 17846b6fae2bSMattias Nilsson 17856b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate) 17866b6fae2bSMattias Nilsson { 17876b6fae2bSMattias Nilsson u32 val; 17886b6fae2bSMattias Nilsson u32 div; 17896b6fae2bSMattias Nilsson unsigned long src_rate; 17906b6fae2bSMattias Nilsson long rounded_rate; 17916b6fae2bSMattias Nilsson 17926b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 17936b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 17946b6fae2bSMattias Nilsson clk_mgt[clock].branch); 17956b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 17966b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 17976b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 17986b6fae2bSMattias Nilsson if (div > 2) 17996b6fae2bSMattias Nilsson div = 2; 18006b6fae2bSMattias Nilsson } else { 18016b6fae2bSMattias Nilsson div = 1; 18026b6fae2bSMattias Nilsson } 18036b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 18046b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 18056b6fae2bSMattias Nilsson 18066b6fae2bSMattias Nilsson (void)do_div(r, 25); 18076b6fae2bSMattias Nilsson if (r <= rate) 18086b6fae2bSMattias Nilsson return (unsigned long)r; 18096b6fae2bSMattias Nilsson } 18106b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31)); 18116b6fae2bSMattias Nilsson 18126b6fae2bSMattias Nilsson return rounded_rate; 18136b6fae2bSMattias Nilsson } 18146b6fae2bSMattias Nilsson 1815b2302c87SUlf Hansson /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ 1816b2302c87SUlf Hansson static struct cpufreq_frequency_table db8500_cpufreq_table[] = { 1817b2302c87SUlf Hansson { .frequency = 200000, .index = ARM_EXTCLK,}, 1818b2302c87SUlf Hansson { .frequency = 400000, .index = ARM_50_OPP,}, 1819b2302c87SUlf Hansson { .frequency = 800000, .index = ARM_100_OPP,}, 1820b2302c87SUlf Hansson { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ 1821b2302c87SUlf Hansson { .frequency = CPUFREQ_TABLE_END,}, 1822b2302c87SUlf Hansson }; 1823b2302c87SUlf Hansson 1824b2302c87SUlf Hansson static long round_armss_rate(unsigned long rate) 1825b2302c87SUlf Hansson { 1826b2302c87SUlf Hansson long freq = 0; 1827b2302c87SUlf Hansson int i = 0; 1828b2302c87SUlf Hansson 1829b2302c87SUlf Hansson /* cpufreq table frequencies is in KHz. */ 1830b2302c87SUlf Hansson rate = rate / 1000; 1831b2302c87SUlf Hansson 1832b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1833b2302c87SUlf Hansson while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { 1834b2302c87SUlf Hansson freq = db8500_cpufreq_table[i].frequency; 1835b2302c87SUlf Hansson if (freq == rate) 1836b2302c87SUlf Hansson break; 1837b2302c87SUlf Hansson i++; 1838b2302c87SUlf Hansson } 1839b2302c87SUlf Hansson 1840b2302c87SUlf Hansson /* Return the last valid value, even if a match was not found. */ 1841b2302c87SUlf Hansson return freq * 1000; 1842b2302c87SUlf Hansson } 1843b2302c87SUlf Hansson 18446b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL 18456b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL 18466b6fae2bSMattias Nilsson 18476b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate) 18486b6fae2bSMattias Nilsson { 18496b6fae2bSMattias Nilsson long rounded_rate = 0; 18506b6fae2bSMattias Nilsson unsigned long src_rate; 18516b6fae2bSMattias Nilsson unsigned long rem; 18526b6fae2bSMattias Nilsson u32 r; 18536b6fae2bSMattias Nilsson 18546b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 18556b6fae2bSMattias Nilsson rem = rate; 18566b6fae2bSMattias Nilsson 18576b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 18586b6fae2bSMattias Nilsson u64 d; 18596b6fae2bSMattias Nilsson 18606b6fae2bSMattias Nilsson d = (r * rate); 18616b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 18626b6fae2bSMattias Nilsson if (d < 6) 18636b6fae2bSMattias Nilsson d = 6; 18646b6fae2bSMattias Nilsson else if (d > 255) 18656b6fae2bSMattias Nilsson d = 255; 18666b6fae2bSMattias Nilsson d *= src_rate; 18676b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 18686b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d))) 18696b6fae2bSMattias Nilsson continue; 18706b6fae2bSMattias Nilsson (void)do_div(d, r); 18716b6fae2bSMattias Nilsson if (rate < d) { 18726b6fae2bSMattias Nilsson if (rounded_rate == 0) 18736b6fae2bSMattias Nilsson rounded_rate = (long)d; 1874e62ccf3aSLinus Walleij break; 1875e62ccf3aSLinus Walleij } 18766b6fae2bSMattias Nilsson if ((rate - d) < rem) { 18776b6fae2bSMattias Nilsson rem = (rate - d); 18786b6fae2bSMattias Nilsson rounded_rate = (long)d; 18796b6fae2bSMattias Nilsson } 18806b6fae2bSMattias Nilsson } 18816b6fae2bSMattias Nilsson return rounded_rate; 18826b6fae2bSMattias Nilsson } 18836b6fae2bSMattias Nilsson 18846b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate) 18856b6fae2bSMattias Nilsson { 18866b6fae2bSMattias Nilsson u32 div; 18876b6fae2bSMattias Nilsson unsigned long src_rate; 18886b6fae2bSMattias Nilsson long rounded_rate; 18896b6fae2bSMattias Nilsson 18906b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 18916b6fae2bSMattias Nilsson PLL_RAW); 18926b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18936b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 18946b6fae2bSMattias Nilsson 18956b6fae2bSMattias Nilsson return rounded_rate; 18966b6fae2bSMattias Nilsson } 18976b6fae2bSMattias Nilsson 18986b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate) 18996b6fae2bSMattias Nilsson { 19006b6fae2bSMattias Nilsson u32 div; 19016b6fae2bSMattias Nilsson unsigned long src_rate; 19026b6fae2bSMattias Nilsson long rounded_rate; 19036b6fae2bSMattias Nilsson 19046b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK); 19056b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 19066b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255)); 19076b6fae2bSMattias Nilsson 19086b6fae2bSMattias Nilsson return rounded_rate; 19096b6fae2bSMattias Nilsson } 19106b6fae2bSMattias Nilsson 19116b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate) 19126b6fae2bSMattias Nilsson { 1913e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 19146b6fae2bSMattias Nilsson return round_clock_rate(clock, rate); 1915b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 1916b2302c87SUlf Hansson return round_armss_rate(rate); 19176b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 19186b6fae2bSMattias Nilsson return round_plldsi_rate(rate); 19196b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 19206b6fae2bSMattias Nilsson return round_dsiclk_rate(rate); 19216b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 19226b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate); 19236b6fae2bSMattias Nilsson else 19246b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock); 19256b6fae2bSMattias Nilsson } 19266b6fae2bSMattias Nilsson 19276b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate) 19286b6fae2bSMattias Nilsson { 19296b6fae2bSMattias Nilsson u32 val; 19306b6fae2bSMattias Nilsson u32 div; 19316b6fae2bSMattias Nilsson unsigned long src_rate; 19326b6fae2bSMattias Nilsson unsigned long flags; 19336b6fae2bSMattias Nilsson 19346b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 19356b6fae2bSMattias Nilsson 19366b6fae2bSMattias Nilsson /* Grab the HW semaphore. */ 19376b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 19386b6fae2bSMattias Nilsson cpu_relax(); 19396b6fae2bSMattias Nilsson 19406b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 19416b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 19426b6fae2bSMattias Nilsson clk_mgt[clock].branch); 19436b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 19446b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 19456b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 19466b6fae2bSMattias Nilsson if (div > 1) 19476b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV; 19486b6fae2bSMattias Nilsson else 19496b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV; 19506b6fae2bSMattias Nilsson } 19516b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) { 19526b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 19536b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 19546b6fae2bSMattias Nilsson if (div == 3) { 19556b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 19566b6fae2bSMattias Nilsson 19576b6fae2bSMattias Nilsson (void)do_div(r, 25); 19586b6fae2bSMattias Nilsson if (r <= rate) { 19596b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 19606b6fae2bSMattias Nilsson div = 0; 19616b6fae2bSMattias Nilsson } 19626b6fae2bSMattias Nilsson } 19636b6fae2bSMattias Nilsson val |= min(div, (u32)31); 19646b6fae2bSMattias Nilsson } else { 19656b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 19666b6fae2bSMattias Nilsson val |= min(div, (u32)31); 19676b6fae2bSMattias Nilsson } 19686b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 19696b6fae2bSMattias Nilsson 19706b6fae2bSMattias Nilsson /* Release the HW semaphore. */ 19716b6fae2bSMattias Nilsson writel(0, PRCM_SEM); 19726b6fae2bSMattias Nilsson 19736b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 19746b6fae2bSMattias Nilsson } 19756b6fae2bSMattias Nilsson 1976b2302c87SUlf Hansson static int set_armss_rate(unsigned long rate) 1977b2302c87SUlf Hansson { 1978b2302c87SUlf Hansson int i = 0; 1979b2302c87SUlf Hansson 1980b2302c87SUlf Hansson /* cpufreq table frequencies is in KHz. */ 1981b2302c87SUlf Hansson rate = rate / 1000; 1982b2302c87SUlf Hansson 1983b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1984b2302c87SUlf Hansson while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) { 1985b2302c87SUlf Hansson if (db8500_cpufreq_table[i].frequency == rate) 1986b2302c87SUlf Hansson break; 1987b2302c87SUlf Hansson i++; 1988b2302c87SUlf Hansson } 1989b2302c87SUlf Hansson 1990b2302c87SUlf Hansson if (db8500_cpufreq_table[i].frequency != rate) 1991b2302c87SUlf Hansson return -EINVAL; 1992b2302c87SUlf Hansson 1993b2302c87SUlf Hansson /* Set the new arm opp. */ 1994b2302c87SUlf Hansson return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index); 1995b2302c87SUlf Hansson } 1996b2302c87SUlf Hansson 19976b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate) 19986b6fae2bSMattias Nilsson { 19996b6fae2bSMattias Nilsson unsigned long src_rate; 20006b6fae2bSMattias Nilsson unsigned long rem; 20016b6fae2bSMattias Nilsson u32 pll_freq = 0; 20026b6fae2bSMattias Nilsson u32 r; 20036b6fae2bSMattias Nilsson 20046b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 20056b6fae2bSMattias Nilsson rem = rate; 20066b6fae2bSMattias Nilsson 20076b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 20086b6fae2bSMattias Nilsson u64 d; 20096b6fae2bSMattias Nilsson u64 hwrate; 20106b6fae2bSMattias Nilsson 20116b6fae2bSMattias Nilsson d = (r * rate); 20126b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 20136b6fae2bSMattias Nilsson if (d < 6) 20146b6fae2bSMattias Nilsson d = 6; 20156b6fae2bSMattias Nilsson else if (d > 255) 20166b6fae2bSMattias Nilsson d = 255; 20176b6fae2bSMattias Nilsson hwrate = (d * src_rate); 20186b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 20196b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 20206b6fae2bSMattias Nilsson continue; 20216b6fae2bSMattias Nilsson (void)do_div(hwrate, r); 20226b6fae2bSMattias Nilsson if (rate < hwrate) { 20236b6fae2bSMattias Nilsson if (pll_freq == 0) 20246b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 20256b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 20266b6fae2bSMattias Nilsson break; 20276b6fae2bSMattias Nilsson } 20286b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) { 20296b6fae2bSMattias Nilsson rem = (rate - hwrate); 20306b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 20316b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 20326b6fae2bSMattias Nilsson } 20336b6fae2bSMattias Nilsson } 20346b6fae2bSMattias Nilsson if (pll_freq == 0) 20353df57bcfSMattias Nilsson return -EINVAL; 20366b6fae2bSMattias Nilsson 20376b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 20386b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ); 20396b6fae2bSMattias Nilsson 20406b6fae2bSMattias Nilsson return 0; 20416b6fae2bSMattias Nilsson } 20426b6fae2bSMattias Nilsson 20436b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate) 20446b6fae2bSMattias Nilsson { 20456b6fae2bSMattias Nilsson u32 val; 20466b6fae2bSMattias Nilsson u32 div; 20476b6fae2bSMattias Nilsson 20486b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 20496b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 20506b6fae2bSMattias Nilsson 20516b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 20526b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 20536b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 20546b6fae2bSMattias Nilsson 20556b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 20566b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 20576b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 20586b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 20596b6fae2bSMattias Nilsson } 20606b6fae2bSMattias Nilsson 20616b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate) 20626b6fae2bSMattias Nilsson { 20636b6fae2bSMattias Nilsson u32 val; 20646b6fae2bSMattias Nilsson u32 div; 20656b6fae2bSMattias Nilsson 20666b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 20676b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 20686b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask; 20696b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 20706b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 20716b6fae2bSMattias Nilsson } 20726b6fae2bSMattias Nilsson 20736b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate) 20746b6fae2bSMattias Nilsson { 20756b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 20766b6fae2bSMattias Nilsson set_clock_rate(clock, rate); 2077b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 2078b2302c87SUlf Hansson return set_armss_rate(rate); 20796b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 20806b6fae2bSMattias Nilsson return set_plldsi_rate(rate); 20816b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 20826b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 20836b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 20846b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 20856b6fae2bSMattias Nilsson return 0; 20863df57bcfSMattias Nilsson } 20873df57bcfSMattias Nilsson 208873180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 20893df57bcfSMattias Nilsson { 20903df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 20913df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 20923df57bcfSMattias Nilsson return -EINVAL; 20933df57bcfSMattias Nilsson 20943df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20953df57bcfSMattias Nilsson 2096c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20973df57bcfSMattias Nilsson cpu_relax(); 20983df57bcfSMattias Nilsson 20993df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21003df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 21013df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 21023df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 21033df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 21043df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 21053df57bcfSMattias Nilsson 2106c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21073df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21083df57bcfSMattias Nilsson 21093df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21103df57bcfSMattias Nilsson 21113df57bcfSMattias Nilsson return 0; 21123df57bcfSMattias Nilsson } 21133df57bcfSMattias Nilsson 21140508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold) 21153df57bcfSMattias Nilsson { 21163df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21173df57bcfSMattias Nilsson 2118c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21193df57bcfSMattias Nilsson cpu_relax(); 21203df57bcfSMattias Nilsson 21213df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 21223df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21233df57bcfSMattias Nilsson 2124c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21253df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21263df57bcfSMattias Nilsson 21273df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21283df57bcfSMattias Nilsson 21293df57bcfSMattias Nilsson return 0; 21303df57bcfSMattias Nilsson } 21313df57bcfSMattias Nilsson 21320508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high) 21333df57bcfSMattias Nilsson { 21343df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21353df57bcfSMattias Nilsson 2136c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21373df57bcfSMattias Nilsson cpu_relax(); 21383df57bcfSMattias Nilsson 21393df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 21403df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 21413df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 21423df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 21433df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21443df57bcfSMattias Nilsson 2145c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21463df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21473df57bcfSMattias Nilsson 21483df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21493df57bcfSMattias Nilsson 21503df57bcfSMattias Nilsson return 0; 21513df57bcfSMattias Nilsson } 21523df57bcfSMattias Nilsson 21533df57bcfSMattias Nilsson static int config_hot_period(u16 val) 21543df57bcfSMattias Nilsson { 21553df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21563df57bcfSMattias Nilsson 2157c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21583df57bcfSMattias Nilsson cpu_relax(); 21593df57bcfSMattias Nilsson 21603df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 21613df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21623df57bcfSMattias Nilsson 2163c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21643df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21653df57bcfSMattias Nilsson 21663df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21673df57bcfSMattias Nilsson 21683df57bcfSMattias Nilsson return 0; 21693df57bcfSMattias Nilsson } 21703df57bcfSMattias Nilsson 21710508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k) 21723df57bcfSMattias Nilsson { 21733df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 21743df57bcfSMattias Nilsson return -EINVAL; 21753df57bcfSMattias Nilsson 21763df57bcfSMattias Nilsson return config_hot_period(cycles32k); 21773df57bcfSMattias Nilsson } 21783df57bcfSMattias Nilsson 21790508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void) 21803df57bcfSMattias Nilsson { 21813df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 21823df57bcfSMattias Nilsson } 21833df57bcfSMattias Nilsson 218484165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 218584165b80SJonas Aberg { 218684165b80SJonas Aberg 218784165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 218884165b80SJonas Aberg 218984165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 219084165b80SJonas Aberg cpu_relax(); 219184165b80SJonas Aberg 219284165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 219384165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 219484165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 219584165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 219684165b80SJonas Aberg 219784165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 219884165b80SJonas Aberg 219984165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 220084165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 220184165b80SJonas Aberg 220284165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 220384165b80SJonas Aberg 220484165b80SJonas Aberg return 0; 220584165b80SJonas Aberg 220684165b80SJonas Aberg } 220784165b80SJonas Aberg 22080508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 220984165b80SJonas Aberg { 221084165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 221184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 221284165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 221384165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 221484165b80SJonas Aberg } 221584165b80SJonas Aberg 22160508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id) 221784165b80SJonas Aberg { 221884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 221984165b80SJonas Aberg } 222084165b80SJonas Aberg 22210508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id) 222284165b80SJonas Aberg { 222384165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 222484165b80SJonas Aberg } 222584165b80SJonas Aberg 22260508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id) 222784165b80SJonas Aberg { 222884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 222984165b80SJonas Aberg } 223084165b80SJonas Aberg 223184165b80SJonas Aberg /* 223284165b80SJonas Aberg * timeout is 28 bit, in ms. 223384165b80SJonas Aberg */ 22340508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 223584165b80SJonas Aberg { 223684165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 223784165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 223884165b80SJonas Aberg /* 223984165b80SJonas Aberg * Put the lowest 28 bits of timeout at 224084165b80SJonas Aberg * offset 4. Four first bits are used for id. 224184165b80SJonas Aberg */ 224284165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 224384165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 224484165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 224584165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 224684165b80SJonas Aberg } 224784165b80SJonas Aberg 22483df57bcfSMattias Nilsson /** 2249650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 2250650c2a21SLinus Walleij * @slave: The I2C slave address. 2251650c2a21SLinus Walleij * @reg: The (start) register address. 2252650c2a21SLinus Walleij * @value: The read out value(s). 2253650c2a21SLinus Walleij * @size: The number of registers to read. 2254650c2a21SLinus Walleij * 2255650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2256650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2257650c2a21SLinus Walleij */ 2258650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2259650c2a21SLinus Walleij { 2260650c2a21SLinus Walleij int r; 2261650c2a21SLinus Walleij 2262650c2a21SLinus Walleij if (size != 1) 2263650c2a21SLinus Walleij return -EINVAL; 2264650c2a21SLinus Walleij 22653df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2266650c2a21SLinus Walleij 2267c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2268650c2a21SLinus Walleij cpu_relax(); 2269650c2a21SLinus Walleij 22703c3e4898SMattias Nilsson writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 22713df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22723df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22733df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22743df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2275650c2a21SLinus Walleij 2276c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 22773df57bcfSMattias Nilsson 2278650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 22793df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 22803df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 22813df57bcfSMattias Nilsson __func__); 2282650c2a21SLinus Walleij r = -EIO; 22833df57bcfSMattias Nilsson } else { 2284650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 22853df57bcfSMattias Nilsson } 22863df57bcfSMattias Nilsson 2287650c2a21SLinus Walleij if (!r) 2288650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 2289650c2a21SLinus Walleij 2290650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 22913df57bcfSMattias Nilsson 2292650c2a21SLinus Walleij return r; 2293650c2a21SLinus Walleij } 2294650c2a21SLinus Walleij 2295650c2a21SLinus Walleij /** 22963c3e4898SMattias Nilsson * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. 2297650c2a21SLinus Walleij * @slave: The I2C slave address. 2298650c2a21SLinus Walleij * @reg: The (start) register address. 2299650c2a21SLinus Walleij * @value: The value(s) to write. 23003c3e4898SMattias Nilsson * @mask: The mask(s) to use. 2301650c2a21SLinus Walleij * @size: The number of registers to write. 2302650c2a21SLinus Walleij * 23033c3e4898SMattias Nilsson * Writes masked register value(s) to the ABB. 23043c3e4898SMattias Nilsson * For each @value, only the bits set to 1 in the corresponding @mask 23053c3e4898SMattias Nilsson * will be written. The other bits are not changed. 2306650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2307650c2a21SLinus Walleij */ 23083c3e4898SMattias Nilsson int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) 2309650c2a21SLinus Walleij { 2310650c2a21SLinus Walleij int r; 2311650c2a21SLinus Walleij 2312650c2a21SLinus Walleij if (size != 1) 2313650c2a21SLinus Walleij return -EINVAL; 2314650c2a21SLinus Walleij 23153df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2316650c2a21SLinus Walleij 2317c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2318650c2a21SLinus Walleij cpu_relax(); 2319650c2a21SLinus Walleij 23203c3e4898SMattias Nilsson writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 23213df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 23223df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 23233df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 23243df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2325650c2a21SLinus Walleij 2326c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 23273df57bcfSMattias Nilsson 2328650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 23293df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 23303df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 23313df57bcfSMattias Nilsson __func__); 2332650c2a21SLinus Walleij r = -EIO; 23333df57bcfSMattias Nilsson } else { 2334650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 23353df57bcfSMattias Nilsson } 23363df57bcfSMattias Nilsson 23373df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 23383df57bcfSMattias Nilsson 23393df57bcfSMattias Nilsson return r; 23403df57bcfSMattias Nilsson } 23413df57bcfSMattias Nilsson 23423df57bcfSMattias Nilsson /** 23433c3e4898SMattias Nilsson * prcmu_abb_write() - Write register value(s) to the ABB. 23443c3e4898SMattias Nilsson * @slave: The I2C slave address. 23453c3e4898SMattias Nilsson * @reg: The (start) register address. 23463c3e4898SMattias Nilsson * @value: The value(s) to write. 23473c3e4898SMattias Nilsson * @size: The number of registers to write. 23483c3e4898SMattias Nilsson * 23493c3e4898SMattias Nilsson * Writes register value(s) to the ABB. 23503c3e4898SMattias Nilsson * @size has to be 1 for the current firmware version. 23513c3e4898SMattias Nilsson */ 23523c3e4898SMattias Nilsson int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 23533c3e4898SMattias Nilsson { 23543c3e4898SMattias Nilsson u8 mask = ~0; 23553c3e4898SMattias Nilsson 23563c3e4898SMattias Nilsson return prcmu_abb_write_masked(slave, reg, value, &mask, size); 23573c3e4898SMattias Nilsson } 23583c3e4898SMattias Nilsson 23593c3e4898SMattias Nilsson /** 23603df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 23613df57bcfSMattias Nilsson */ 23625261e101SArun Murthy int prcmu_ac_wake_req(void) 23633df57bcfSMattias Nilsson { 23643df57bcfSMattias Nilsson u32 val; 23655261e101SArun Murthy int ret = 0; 23663df57bcfSMattias Nilsson 23673df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 23683df57bcfSMattias Nilsson 2369c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23703df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 23713df57bcfSMattias Nilsson goto unlock_and_return; 23723df57bcfSMattias Nilsson 23733df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 23743df57bcfSMattias Nilsson 23755261e101SArun Murthy /* 23765261e101SArun Murthy * Force Modem Wake-up before hostaccess_req ping-pong. 23775261e101SArun Murthy * It prevents Modem to enter in Sleep while acking the hostaccess 23785261e101SArun Murthy * request. The 31us delay has been calculated by HWI. 23795261e101SArun Murthy */ 23805261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; 23815261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 23825261e101SArun Murthy 23835261e101SArun Murthy udelay(31); 23845261e101SArun Murthy 23855261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; 23865261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 23873df57bcfSMattias Nilsson 23883df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2389d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 23905261e101SArun Murthy #if defined(CONFIG_DBX500_PRCMU_DEBUG) 23915261e101SArun Murthy db8500_prcmu_debug_dump(__func__, true, true); 23925261e101SArun Murthy #endif 239357265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2394d6e3002eSMattias Nilsson __func__); 23955261e101SArun Murthy ret = -EFAULT; 23963df57bcfSMattias Nilsson } 2397650c2a21SLinus Walleij 2398650c2a21SLinus Walleij unlock_and_return: 23993df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 24005261e101SArun Murthy return ret; 2401650c2a21SLinus Walleij } 2402650c2a21SLinus Walleij 24033df57bcfSMattias Nilsson /** 24043df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 24053df57bcfSMattias Nilsson */ 24063df57bcfSMattias Nilsson void prcmu_ac_sleep_req() 2407650c2a21SLinus Walleij { 24083df57bcfSMattias Nilsson u32 val; 2409650c2a21SLinus Walleij 24103df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 2411650c2a21SLinus Walleij 2412c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 24133df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 24143df57bcfSMattias Nilsson goto unlock_and_return; 24153df57bcfSMattias Nilsson 24163df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2417c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 24183df57bcfSMattias Nilsson 24193df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2420d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 242157265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 24223df57bcfSMattias Nilsson __func__); 24233df57bcfSMattias Nilsson } 24243df57bcfSMattias Nilsson 24253df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 24263df57bcfSMattias Nilsson 24273df57bcfSMattias Nilsson unlock_and_return: 24283df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 24293df57bcfSMattias Nilsson } 24303df57bcfSMattias Nilsson 243173180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 24323df57bcfSMattias Nilsson { 24333df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 24343df57bcfSMattias Nilsson } 24353df57bcfSMattias Nilsson 24363df57bcfSMattias Nilsson /** 243773180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 24383df57bcfSMattias Nilsson * 243973180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 24403df57bcfSMattias Nilsson * fires interrupt to fw 24413df57bcfSMattias Nilsson */ 244273180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 24433df57bcfSMattias Nilsson { 24443df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2445c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 24463df57bcfSMattias Nilsson } 24473df57bcfSMattias Nilsson 24483df57bcfSMattias Nilsson /** 2449597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2450597045deSSebastian Rasmussen * 2451597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 2452597045deSSebastian Rasmussen * last restart. 2453597045deSSebastian Rasmussen */ 2454597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 2455597045deSSebastian Rasmussen { 2456597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 2457597045deSSebastian Rasmussen } 2458597045deSSebastian Rasmussen 2459597045deSSebastian Rasmussen /** 24600508901cSMattias Nilsson * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 24613df57bcfSMattias Nilsson */ 24620508901cSMattias Nilsson void db8500_prcmu_modem_reset(void) 24633df57bcfSMattias Nilsson { 2464650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 2465650c2a21SLinus Walleij 2466c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2467650c2a21SLinus Walleij cpu_relax(); 2468650c2a21SLinus Walleij 24693df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2470c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2471650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 24723df57bcfSMattias Nilsson 24733df57bcfSMattias Nilsson /* 24743df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 24753df57bcfSMattias Nilsson * This state is already managed by upper layer 24763df57bcfSMattias Nilsson */ 2477650c2a21SLinus Walleij 2478650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 2479650c2a21SLinus Walleij } 2480650c2a21SLinus Walleij 24813df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 2482650c2a21SLinus Walleij { 24833df57bcfSMattias Nilsson unsigned long flags; 2484650c2a21SLinus Walleij 24853df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 2486650c2a21SLinus Walleij 2487c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 24883df57bcfSMattias Nilsson cpu_relax(); 2489650c2a21SLinus Walleij 24903df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2491c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2492650c2a21SLinus Walleij 24933df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2494650c2a21SLinus Walleij } 2495650c2a21SLinus Walleij 24963df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 2497650c2a21SLinus Walleij { 24983df57bcfSMattias Nilsson pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 24993df57bcfSMattias Nilsson header, n); 2500650c2a21SLinus Walleij } 2501650c2a21SLinus Walleij 25023df57bcfSMattias Nilsson static bool read_mailbox_0(void) 2503650c2a21SLinus Walleij { 25043df57bcfSMattias Nilsson bool r; 25053df57bcfSMattias Nilsson u32 ev; 25063df57bcfSMattias Nilsson unsigned int n; 25073df57bcfSMattias Nilsson u8 header; 25083df57bcfSMattias Nilsson 25093df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 25103df57bcfSMattias Nilsson switch (header) { 25113df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 25123df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 25133df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 25143df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 25153df57bcfSMattias Nilsson else 25163df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 25173df57bcfSMattias Nilsson 25183df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 25193df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 25203df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 25213df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 25223df57bcfSMattias Nilsson 25233df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 25243df57bcfSMattias Nilsson 25253df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 25263df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 25273df57bcfSMattias Nilsson generic_handle_irq(IRQ_PRCMU_BASE + n); 25283df57bcfSMattias Nilsson } 25293df57bcfSMattias Nilsson r = true; 25303df57bcfSMattias Nilsson break; 25313df57bcfSMattias Nilsson default: 25323df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 25333df57bcfSMattias Nilsson r = false; 25343df57bcfSMattias Nilsson break; 25353df57bcfSMattias Nilsson } 2536c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 25373df57bcfSMattias Nilsson return r; 25383df57bcfSMattias Nilsson } 25393df57bcfSMattias Nilsson 25403df57bcfSMattias Nilsson static bool read_mailbox_1(void) 25413df57bcfSMattias Nilsson { 25423df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 25433df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 25443df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 25453df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 25463df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 25473df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 25483df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2549c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2550650c2a21SLinus Walleij complete(&mb1_transfer.work); 25513df57bcfSMattias Nilsson return false; 2552650c2a21SLinus Walleij } 2553650c2a21SLinus Walleij 25543df57bcfSMattias Nilsson static bool read_mailbox_2(void) 2555650c2a21SLinus Walleij { 25563df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2557c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 25583df57bcfSMattias Nilsson complete(&mb2_transfer.work); 25593df57bcfSMattias Nilsson return false; 2560650c2a21SLinus Walleij } 2561650c2a21SLinus Walleij 25623df57bcfSMattias Nilsson static bool read_mailbox_3(void) 2563650c2a21SLinus Walleij { 2564c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 25653df57bcfSMattias Nilsson return false; 2566650c2a21SLinus Walleij } 2567650c2a21SLinus Walleij 25683df57bcfSMattias Nilsson static bool read_mailbox_4(void) 2569650c2a21SLinus Walleij { 25703df57bcfSMattias Nilsson u8 header; 25713df57bcfSMattias Nilsson bool do_complete = true; 25723df57bcfSMattias Nilsson 25733df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 25743df57bcfSMattias Nilsson switch (header) { 25753df57bcfSMattias Nilsson case MB4H_MEM_ST: 25763df57bcfSMattias Nilsson case MB4H_HOTDOG: 25773df57bcfSMattias Nilsson case MB4H_HOTMON: 25783df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 2579a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 2580a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 2581a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 2582a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 2583a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 25843df57bcfSMattias Nilsson break; 25853df57bcfSMattias Nilsson default: 25863df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 25873df57bcfSMattias Nilsson do_complete = false; 25883df57bcfSMattias Nilsson break; 2589650c2a21SLinus Walleij } 2590650c2a21SLinus Walleij 2591c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 25923df57bcfSMattias Nilsson 25933df57bcfSMattias Nilsson if (do_complete) 25943df57bcfSMattias Nilsson complete(&mb4_transfer.work); 25953df57bcfSMattias Nilsson 25963df57bcfSMattias Nilsson return false; 25973df57bcfSMattias Nilsson } 25983df57bcfSMattias Nilsson 25993df57bcfSMattias Nilsson static bool read_mailbox_5(void) 2600650c2a21SLinus Walleij { 26013df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 26023df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2603c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2604650c2a21SLinus Walleij complete(&mb5_transfer.work); 26053df57bcfSMattias Nilsson return false; 2606650c2a21SLinus Walleij } 2607650c2a21SLinus Walleij 26083df57bcfSMattias Nilsson static bool read_mailbox_6(void) 2609650c2a21SLinus Walleij { 2610c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 26113df57bcfSMattias Nilsson return false; 2612650c2a21SLinus Walleij } 2613650c2a21SLinus Walleij 26143df57bcfSMattias Nilsson static bool read_mailbox_7(void) 2615650c2a21SLinus Walleij { 2616c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 26173df57bcfSMattias Nilsson return false; 2618650c2a21SLinus Walleij } 2619650c2a21SLinus Walleij 26203df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 2621650c2a21SLinus Walleij read_mailbox_0, 2622650c2a21SLinus Walleij read_mailbox_1, 2623650c2a21SLinus Walleij read_mailbox_2, 2624650c2a21SLinus Walleij read_mailbox_3, 2625650c2a21SLinus Walleij read_mailbox_4, 2626650c2a21SLinus Walleij read_mailbox_5, 2627650c2a21SLinus Walleij read_mailbox_6, 2628650c2a21SLinus Walleij read_mailbox_7 2629650c2a21SLinus Walleij }; 2630650c2a21SLinus Walleij 2631650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2632650c2a21SLinus Walleij { 2633650c2a21SLinus Walleij u32 bits; 2634650c2a21SLinus Walleij u8 n; 26353df57bcfSMattias Nilsson irqreturn_t r; 2636650c2a21SLinus Walleij 2637c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2638650c2a21SLinus Walleij if (unlikely(!bits)) 2639650c2a21SLinus Walleij return IRQ_NONE; 2640650c2a21SLinus Walleij 26413df57bcfSMattias Nilsson r = IRQ_HANDLED; 2642650c2a21SLinus Walleij for (n = 0; bits; n++) { 2643650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2644650c2a21SLinus Walleij bits -= MBOX_BIT(n); 26453df57bcfSMattias Nilsson if (read_mailbox[n]()) 26463df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2647650c2a21SLinus Walleij } 2648650c2a21SLinus Walleij } 26493df57bcfSMattias Nilsson return r; 26503df57bcfSMattias Nilsson } 26513df57bcfSMattias Nilsson 26523df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 26533df57bcfSMattias Nilsson { 26543df57bcfSMattias Nilsson ack_dbb_wakeup(); 2655650c2a21SLinus Walleij return IRQ_HANDLED; 2656650c2a21SLinus Walleij } 2657650c2a21SLinus Walleij 26583df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 26593df57bcfSMattias Nilsson { 26603df57bcfSMattias Nilsson unsigned long flags; 26613df57bcfSMattias Nilsson 26623df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 26633df57bcfSMattias Nilsson 26643df57bcfSMattias Nilsson config_wakeups(); 26653df57bcfSMattias Nilsson 26663df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 26673df57bcfSMattias Nilsson } 26683df57bcfSMattias Nilsson 26693df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 26703df57bcfSMattias Nilsson { 26713df57bcfSMattias Nilsson unsigned long flags; 26723df57bcfSMattias Nilsson 26733df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26743df57bcfSMattias Nilsson 2675f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; 26763df57bcfSMattias Nilsson 26773df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26783df57bcfSMattias Nilsson 26793df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26803df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26813df57bcfSMattias Nilsson } 26823df57bcfSMattias Nilsson 26833df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 26843df57bcfSMattias Nilsson { 26853df57bcfSMattias Nilsson unsigned long flags; 26863df57bcfSMattias Nilsson 26873df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26883df57bcfSMattias Nilsson 2689f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; 26903df57bcfSMattias Nilsson 26913df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26923df57bcfSMattias Nilsson 26933df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26943df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26953df57bcfSMattias Nilsson } 26963df57bcfSMattias Nilsson 26973df57bcfSMattias Nilsson static void noop(struct irq_data *d) 26983df57bcfSMattias Nilsson { 26993df57bcfSMattias Nilsson } 27003df57bcfSMattias Nilsson 27013df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 27023df57bcfSMattias Nilsson .name = "prcmu", 27033df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 27043df57bcfSMattias Nilsson .irq_ack = noop, 27053df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 27063df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 27073df57bcfSMattias Nilsson }; 27083df57bcfSMattias Nilsson 2709b58d12feSMattias Nilsson static char *fw_project_name(u8 project) 2710b58d12feSMattias Nilsson { 2711b58d12feSMattias Nilsson switch (project) { 2712b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500: 2713b58d12feSMattias Nilsson return "U8500"; 2714b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500_C2: 2715b58d12feSMattias Nilsson return "U8500 C2"; 2716b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500: 2717b58d12feSMattias Nilsson return "U9500"; 2718b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500_C2: 2719b58d12feSMattias Nilsson return "U9500 C2"; 27205f96a1a6SBengt Jonsson case PRCMU_FW_PROJECT_U8520: 27215f96a1a6SBengt Jonsson return "U8520"; 27221927ddf6SBengt Jonsson case PRCMU_FW_PROJECT_U8420: 27231927ddf6SBengt Jonsson return "U8420"; 2724b58d12feSMattias Nilsson default: 2725b58d12feSMattias Nilsson return "Unknown"; 2726b58d12feSMattias Nilsson } 2727b58d12feSMattias Nilsson } 2728b58d12feSMattias Nilsson 2729f3f1f0a1SLee Jones static int db8500_irq_map(struct irq_domain *d, unsigned int virq, 2730f3f1f0a1SLee Jones irq_hw_number_t hwirq) 2731f3f1f0a1SLee Jones { 2732f3f1f0a1SLee Jones irq_set_chip_and_handler(virq, &prcmu_irq_chip, 2733f3f1f0a1SLee Jones handle_simple_irq); 2734f3f1f0a1SLee Jones set_irq_flags(virq, IRQF_VALID); 2735f3f1f0a1SLee Jones 2736f3f1f0a1SLee Jones return 0; 2737f3f1f0a1SLee Jones } 2738f3f1f0a1SLee Jones 2739f3f1f0a1SLee Jones static struct irq_domain_ops db8500_irq_ops = { 2740f3f1f0a1SLee Jones .map = db8500_irq_map, 2741f3f1f0a1SLee Jones .xlate = irq_domain_xlate_twocell, 2742f3f1f0a1SLee Jones }; 2743f3f1f0a1SLee Jones 2744f3f1f0a1SLee Jones static int db8500_irq_init(struct device_node *np) 2745f3f1f0a1SLee Jones { 2746a7238e43SLinus Walleij int irq_base = -1; 2747a7238e43SLinus Walleij 2748a7238e43SLinus Walleij /* In the device tree case, just take some IRQs */ 2749a7238e43SLinus Walleij if (!np) 2750a7238e43SLinus Walleij irq_base = IRQ_PRCMU_BASE; 2751a7238e43SLinus Walleij 2752a7238e43SLinus Walleij db8500_irq_domain = irq_domain_add_simple( 2753a7238e43SLinus Walleij np, NUM_PRCMU_WAKEUPS, irq_base, 2754a7238e43SLinus Walleij &db8500_irq_ops, NULL); 2755f3f1f0a1SLee Jones 2756f3f1f0a1SLee Jones if (!db8500_irq_domain) { 2757f3f1f0a1SLee Jones pr_err("Failed to create irqdomain\n"); 2758f3f1f0a1SLee Jones return -ENOSYS; 2759f3f1f0a1SLee Jones } 2760f3f1f0a1SLee Jones 2761f3f1f0a1SLee Jones return 0; 2762f3f1f0a1SLee Jones } 2763f3f1f0a1SLee Jones 276473180f85SMattias Nilsson void __init db8500_prcmu_early_init(void) 2765650c2a21SLinus Walleij { 2766b851c06cSLee Jones if (cpu_is_u8500v2() || cpu_is_u9540()) { 27673df57bcfSMattias Nilsson void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); 27683df57bcfSMattias Nilsson 27693df57bcfSMattias Nilsson if (tcpm_base != NULL) { 27703e2762c8SLinus Walleij u32 version; 27713df57bcfSMattias Nilsson version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); 2772b58d12feSMattias Nilsson fw_info.version.project = version & 0xFF; 2773b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF; 2774b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF; 2775b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF; 2776b58d12feSMattias Nilsson fw_info.valid = true; 2777b58d12feSMattias Nilsson pr_info("PRCMU firmware: %s, version %d.%d.%d\n", 2778b58d12feSMattias Nilsson fw_project_name(fw_info.version.project), 27793df57bcfSMattias Nilsson (version >> 8) & 0xFF, (version >> 16) & 0xFF, 27803df57bcfSMattias Nilsson (version >> 24) & 0xFF); 27813df57bcfSMattias Nilsson iounmap(tcpm_base); 27823df57bcfSMattias Nilsson } 27833df57bcfSMattias Nilsson 2784b851c06cSLee Jones if (cpu_is_u9540()) 2785b851c06cSLee Jones tcdm_base = ioremap_nocache(U8500_PRCMU_TCDM_BASE, 2786b851c06cSLee Jones SZ_4K + SZ_8K) + SZ_8K; 2787b851c06cSLee Jones else 2788650c2a21SLinus Walleij tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); 2789650c2a21SLinus Walleij } else { 2790650c2a21SLinus Walleij pr_err("prcmu: Unsupported chip version\n"); 2791650c2a21SLinus Walleij BUG(); 2792650c2a21SLinus Walleij } 2793650c2a21SLinus Walleij 27943df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 27953df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 27963df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 27973df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2798650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2799650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 28004d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE; 28013df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 28023df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 28033df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 28043df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 28053df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 28063df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 28073df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 28083df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2809650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2810650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2811650c2a21SLinus Walleij 28123df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2813650c2a21SLinus Walleij } 2814650c2a21SLinus Walleij 28150508901cSMattias Nilsson static void __init init_prcm_registers(void) 2816d65e12d7SMattias Nilsson { 2817d65e12d7SMattias Nilsson u32 val; 2818d65e12d7SMattias Nilsson 2819d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2820d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2821d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2822d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2823d65e12d7SMattias Nilsson } 2824d65e12d7SMattias Nilsson 28251032fbfdSBengt Jonsson /* 28261032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 28271032fbfdSBengt Jonsson */ 28281032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 28291032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 28301032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 28311032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 28321032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 28331032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 2834ae840635SLee Jones REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), 28351032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 28361032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 28371032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 28381032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 28391032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 28401032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 28411032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 28421032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 28431032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 28441032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 28451032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 28461032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 28471032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2848992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 2849bc367481SLee Jones REGULATOR_SUPPLY("vddvario", "smsc911x.0"), 28501032fbfdSBengt Jonsson }; 28511032fbfdSBengt Jonsson 28521032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 28531032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 28541032fbfdSBengt Jonsson /* AV8100 regulator */ 28551032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 28561032fbfdSBengt Jonsson }; 28571032fbfdSBengt Jonsson 28581032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2859992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2860624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2861624e87c2SBengt Jonsson }; 2862624e87c2SBengt Jonsson 2863624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2864624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2865624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2866624e87c2SBengt Jonsson }; 2867624e87c2SBengt Jonsson 2868624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2869624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2870624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2871624e87c2SBengt Jonsson }; 2872624e87c2SBengt Jonsson 2873624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2874624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2875624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2876624e87c2SBengt Jonsson }; 2877624e87c2SBengt Jonsson 2878624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2879624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2880624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2881624e87c2SBengt Jonsson }; 2882624e87c2SBengt Jonsson 2883624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2884624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2885624e87c2SBengt Jonsson }; 2886624e87c2SBengt Jonsson 2887624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2888624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2889624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2890624e87c2SBengt Jonsson }; 2891624e87c2SBengt Jonsson 2892624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2893624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2894624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2895624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 2896992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 28971032fbfdSBengt Jonsson }; 28981032fbfdSBengt Jonsson 28991032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 29001032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 29011032fbfdSBengt Jonsson .constraints = { 29021032fbfdSBengt Jonsson .name = "db8500-vape", 29031032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29041e45860fSMark Brown .always_on = true, 29051032fbfdSBengt Jonsson }, 29061032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 29071032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 29081032fbfdSBengt Jonsson }, 29091032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 29101032fbfdSBengt Jonsson .constraints = { 29111032fbfdSBengt Jonsson .name = "db8500-varm", 29121032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29131032fbfdSBengt Jonsson }, 29141032fbfdSBengt Jonsson }, 29151032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 29161032fbfdSBengt Jonsson .constraints = { 29171032fbfdSBengt Jonsson .name = "db8500-vmodem", 29181032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29191032fbfdSBengt Jonsson }, 29201032fbfdSBengt Jonsson }, 29211032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 29221032fbfdSBengt Jonsson .constraints = { 29231032fbfdSBengt Jonsson .name = "db8500-vpll", 29241032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29251032fbfdSBengt Jonsson }, 29261032fbfdSBengt Jonsson }, 29271032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 29281032fbfdSBengt Jonsson .constraints = { 29291032fbfdSBengt Jonsson .name = "db8500-vsmps1", 29301032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29311032fbfdSBengt Jonsson }, 29321032fbfdSBengt Jonsson }, 29331032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 29341032fbfdSBengt Jonsson .constraints = { 29351032fbfdSBengt Jonsson .name = "db8500-vsmps2", 29361032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29371032fbfdSBengt Jonsson }, 29381032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 29391032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 29401032fbfdSBengt Jonsson }, 29411032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 29421032fbfdSBengt Jonsson .constraints = { 29431032fbfdSBengt Jonsson .name = "db8500-vsmps3", 29441032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29451032fbfdSBengt Jonsson }, 29461032fbfdSBengt Jonsson }, 29471032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 29481032fbfdSBengt Jonsson .constraints = { 29491032fbfdSBengt Jonsson .name = "db8500-vrf1", 29501032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29511032fbfdSBengt Jonsson }, 29521032fbfdSBengt Jonsson }, 29531032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2954992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29551032fbfdSBengt Jonsson .constraints = { 29561032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 29571032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29581032fbfdSBengt Jonsson }, 2959624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2960624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 29611032fbfdSBengt Jonsson }, 29621032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 29631032fbfdSBengt Jonsson .constraints = { 29641032fbfdSBengt Jonsson /* "ret" means "retention" */ 29651032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 29661032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29671032fbfdSBengt Jonsson }, 29681032fbfdSBengt Jonsson }, 29691032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2970992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29711032fbfdSBengt Jonsson .constraints = { 29721032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 29731032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29741032fbfdSBengt Jonsson }, 2975624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2976624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 29771032fbfdSBengt Jonsson }, 29781032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2979992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29801032fbfdSBengt Jonsson .constraints = { 29811032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 29821032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29831032fbfdSBengt Jonsson }, 2984624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2985624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 29861032fbfdSBengt Jonsson }, 29871032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 29881032fbfdSBengt Jonsson .constraints = { 29891032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 29901032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29911032fbfdSBengt Jonsson }, 29921032fbfdSBengt Jonsson }, 29931032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2994992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29951032fbfdSBengt Jonsson .constraints = { 29961032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 29971032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29981032fbfdSBengt Jonsson }, 2999624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 3000624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 30011032fbfdSBengt Jonsson }, 30021032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 30031032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 30041032fbfdSBengt Jonsson .constraints = { 30051032fbfdSBengt Jonsson .name = "db8500-sga", 30061032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30071032fbfdSBengt Jonsson }, 3008624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 3009624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 3010624e87c2SBengt Jonsson 30111032fbfdSBengt Jonsson }, 30121032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 30131032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 30141032fbfdSBengt Jonsson .constraints = { 30151032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 30161032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30171032fbfdSBengt Jonsson }, 30181032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 30191032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 30201032fbfdSBengt Jonsson }, 30211032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 3022992b133aSBengt Jonsson /* 3023992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off, 3024992b133aSBengt Jonsson * no need to hold Vape 3025992b133aSBengt Jonsson */ 30261032fbfdSBengt Jonsson .constraints = { 30271032fbfdSBengt Jonsson .name = "db8500-esram12", 30281032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30291032fbfdSBengt Jonsson }, 3030624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 3031624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 30321032fbfdSBengt Jonsson }, 30331032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 30341032fbfdSBengt Jonsson .constraints = { 30351032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 30361032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30371032fbfdSBengt Jonsson }, 30381032fbfdSBengt Jonsson }, 30391032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 3040992b133aSBengt Jonsson /* 3041992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off, 3042992b133aSBengt Jonsson * no need to hold Vape 3043992b133aSBengt Jonsson */ 30441032fbfdSBengt Jonsson .constraints = { 30451032fbfdSBengt Jonsson .name = "db8500-esram34", 30461032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30471032fbfdSBengt Jonsson }, 3048624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 3049624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 30501032fbfdSBengt Jonsson }, 30511032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 30521032fbfdSBengt Jonsson .constraints = { 30531032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 30541032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30551032fbfdSBengt Jonsson }, 30561032fbfdSBengt Jonsson }, 30571032fbfdSBengt Jonsson }; 30581032fbfdSBengt Jonsson 30596d11d135SLee Jones static struct resource ab8500_resources[] = { 30606d11d135SLee Jones [0] = { 30616d11d135SLee Jones .start = IRQ_DB8500_AB8500, 30626d11d135SLee Jones .end = IRQ_DB8500_AB8500, 30636d11d135SLee Jones .flags = IORESOURCE_IRQ 30646d11d135SLee Jones } 30656d11d135SLee Jones }; 30666d11d135SLee Jones 30673df57bcfSMattias Nilsson static struct mfd_cell db8500_prcmu_devs[] = { 30683df57bcfSMattias Nilsson { 30693df57bcfSMattias Nilsson .name = "db8500-prcmu-regulators", 30705d90322bSLee Jones .of_compatible = "stericsson,db8500-prcmu-regulator", 30711ed7891fSMattias Wallin .platform_data = &db8500_regulators, 30721ed7891fSMattias Wallin .pdata_size = sizeof(db8500_regulators), 30733df57bcfSMattias Nilsson }, 30743df57bcfSMattias Nilsson { 307584c7c20fSLee Jones .name = "cpufreq-ux500", 307684c7c20fSLee Jones .of_compatible = "stericsson,cpufreq-ux500", 3077c280f45fSUlf Hansson .platform_data = &db8500_cpufreq_table, 3078c280f45fSUlf Hansson .pdata_size = sizeof(db8500_cpufreq_table), 30793df57bcfSMattias Nilsson }, 30806d11d135SLee Jones { 30816d11d135SLee Jones .name = "ab8500-core", 30826d11d135SLee Jones .of_compatible = "stericsson,ab8500", 30836d11d135SLee Jones .num_resources = ARRAY_SIZE(ab8500_resources), 30846d11d135SLee Jones .resources = ab8500_resources, 30856d11d135SLee Jones .id = AB8500_VERSION_AB8500, 30866d11d135SLee Jones }, 30873df57bcfSMattias Nilsson }; 30883df57bcfSMattias Nilsson 3089c280f45fSUlf Hansson static void db8500_prcmu_update_cpufreq(void) 3090c280f45fSUlf Hansson { 3091c280f45fSUlf Hansson if (prcmu_has_arm_maxopp()) { 3092c280f45fSUlf Hansson db8500_cpufreq_table[3].frequency = 1000000; 3093c280f45fSUlf Hansson db8500_cpufreq_table[3].index = ARM_MAX_OPP; 3094c280f45fSUlf Hansson } 3095c280f45fSUlf Hansson } 3096c280f45fSUlf Hansson 30973df57bcfSMattias Nilsson /** 30983df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 30993df57bcfSMattias Nilsson * 31003df57bcfSMattias Nilsson */ 3101f791be49SBill Pemberton static int db8500_prcmu_probe(struct platform_device *pdev) 31023df57bcfSMattias Nilsson { 31033a8e39c9SLee Jones struct ab8500_platform_data *ab8500_platdata = pdev->dev.platform_data; 3104ca7edd16SLee Jones struct device_node *np = pdev->dev.of_node; 31053a8e39c9SLee Jones int irq = 0, err = 0, i; 31063df57bcfSMattias Nilsson 31073df57bcfSMattias Nilsson if (ux500_is_svp()) 31083df57bcfSMattias Nilsson return -ENODEV; 31093df57bcfSMattias Nilsson 31100508901cSMattias Nilsson init_prcm_registers(); 3111d65e12d7SMattias Nilsson 31123df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 3113c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 31143df57bcfSMattias Nilsson 3115ca7edd16SLee Jones if (np) 3116ca7edd16SLee Jones irq = platform_get_irq(pdev, 0); 3117ca7edd16SLee Jones 3118ca7edd16SLee Jones if (!np || irq <= 0) 3119ca7edd16SLee Jones irq = IRQ_DB8500_PRCMU1; 3120ca7edd16SLee Jones 3121ca7edd16SLee Jones err = request_threaded_irq(irq, prcmu_irq_handler, 31223df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 31233df57bcfSMattias Nilsson if (err < 0) { 31243df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 31253df57bcfSMattias Nilsson err = -EBUSY; 31263df57bcfSMattias Nilsson goto no_irq_return; 31273df57bcfSMattias Nilsson } 31283df57bcfSMattias Nilsson 3129f3f1f0a1SLee Jones db8500_irq_init(np); 3130f3f1f0a1SLee Jones 31313a8e39c9SLee Jones for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) { 31323a8e39c9SLee Jones if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) { 31333a8e39c9SLee Jones db8500_prcmu_devs[i].platform_data = ab8500_platdata; 31343c1534c7SLee Jones db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data); 31353a8e39c9SLee Jones } 31363a8e39c9SLee Jones } 31373a8e39c9SLee Jones 31383df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later()) 31393df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 31403df57bcfSMattias Nilsson 3141c280f45fSUlf Hansson db8500_prcmu_update_cpufreq(); 3142c280f45fSUlf Hansson 31433df57bcfSMattias Nilsson err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 31440848c94fSMark Brown ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL); 3145ca7edd16SLee Jones if (err) { 31463df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 3147ca7edd16SLee Jones return err; 3148ca7edd16SLee Jones } 3149ca7edd16SLee Jones 31503df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 31513df57bcfSMattias Nilsson 31523df57bcfSMattias Nilsson no_irq_return: 31533df57bcfSMattias Nilsson return err; 31543df57bcfSMattias Nilsson } 31553c144762SLee Jones static const struct of_device_id db8500_prcmu_match[] = { 31563c144762SLee Jones { .compatible = "stericsson,db8500-prcmu"}, 31573c144762SLee Jones { }, 31583c144762SLee Jones }; 31593df57bcfSMattias Nilsson 31603df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 31613df57bcfSMattias Nilsson .driver = { 31623df57bcfSMattias Nilsson .name = "db8500-prcmu", 31633df57bcfSMattias Nilsson .owner = THIS_MODULE, 31643c144762SLee Jones .of_match_table = db8500_prcmu_match, 31653df57bcfSMattias Nilsson }, 31669fc63f67SLee Jones .probe = db8500_prcmu_probe, 31673df57bcfSMattias Nilsson }; 31683df57bcfSMattias Nilsson 31693df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 31703df57bcfSMattias Nilsson { 31719fc63f67SLee Jones return platform_driver_register(&db8500_prcmu_driver); 31723df57bcfSMattias Nilsson } 31733df57bcfSMattias Nilsson 3174a661aca4SLee Jones core_initcall(db8500_prcmu_init); 31753df57bcfSMattias Nilsson 31763df57bcfSMattias Nilsson MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 31773df57bcfSMattias Nilsson MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 31783df57bcfSMattias Nilsson MODULE_LICENSE("GPL v2"); 3179