1650c2a21SLinus Walleij /* 2650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 3650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 4650c2a21SLinus Walleij * 5650c2a21SLinus Walleij * License Terms: GNU General Public License v2 6650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9650c2a21SLinus Walleij * 10650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij */ 13650c2a21SLinus Walleij #include <linux/module.h> 143df57bcfSMattias Nilsson #include <linux/kernel.h> 153df57bcfSMattias Nilsson #include <linux/delay.h> 16650c2a21SLinus Walleij #include <linux/errno.h> 17650c2a21SLinus Walleij #include <linux/err.h> 183df57bcfSMattias Nilsson #include <linux/spinlock.h> 19650c2a21SLinus Walleij #include <linux/io.h> 203df57bcfSMattias Nilsson #include <linux/slab.h> 21650c2a21SLinus Walleij #include <linux/mutex.h> 22650c2a21SLinus Walleij #include <linux/completion.h> 233df57bcfSMattias Nilsson #include <linux/irq.h> 24650c2a21SLinus Walleij #include <linux/jiffies.h> 25650c2a21SLinus Walleij #include <linux/bitops.h> 263df57bcfSMattias Nilsson #include <linux/fs.h> 273df57bcfSMattias Nilsson #include <linux/platform_device.h> 283df57bcfSMattias Nilsson #include <linux/uaccess.h> 293df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3073180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 311032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 321032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 33650c2a21SLinus Walleij #include <mach/hardware.h> 343df57bcfSMattias Nilsson #include <mach/irqs.h> 353df57bcfSMattias Nilsson #include <mach/db8500-regs.h> 363df57bcfSMattias Nilsson #include <mach/id.h> 3773180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 38650c2a21SLinus Walleij 393df57bcfSMattias Nilsson /* Offset for the firmware version within the TCPM */ 403df57bcfSMattias Nilsson #define PRCMU_FW_VERSION_OFFSET 0xA4 41650c2a21SLinus Walleij 423df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 433df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 443df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 453df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 463df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 473df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 483df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 493df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 503df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 513df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 523df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 533df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 543df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 553df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 563df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 57650c2a21SLinus Walleij 583df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 593df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 603df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 613df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 62650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 63650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 64650c2a21SLinus Walleij 653df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 663df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 673df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 683df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 69650c2a21SLinus Walleij 703df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 713df57bcfSMattias Nilsson 723df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 733df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 743df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 753df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 793df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 803df57bcfSMattias Nilsson 813df57bcfSMattias Nilsson /* Req Mailboxes */ 823df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 833df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 843df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 853df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 863df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 873df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 883df57bcfSMattias Nilsson 893df57bcfSMattias Nilsson /* Ack Mailboxes */ 903df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 913df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 923df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 933df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 943df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 953df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 963df57bcfSMattias Nilsson 973df57bcfSMattias Nilsson /* Mailbox 0 headers */ 983df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 993df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 1003df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 1013df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1023df57bcfSMattias Nilsson 1033df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1043df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1053df57bcfSMattias Nilsson 1063df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1073df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1083df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1093df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1113df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1123df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1133df57bcfSMattias Nilsson 1143df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1153df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1163df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1173df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1213df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1223df57bcfSMattias Nilsson 1233df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1243df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1253df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1263df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1273df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1283df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 129a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1303df57bcfSMattias Nilsson 1313df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1323df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1333df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 134a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 1356b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1 1366b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2 137a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 138a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1393df57bcfSMattias Nilsson 1403df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1413df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1423df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1433df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1443df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1453df57bcfSMattias Nilsson 1463df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1473df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1483df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1493df57bcfSMattias Nilsson 1503df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1513df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1523df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1533df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1603df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1613df57bcfSMattias Nilsson 1623df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1633df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1643df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1653df57bcfSMattias Nilsson 1663df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1673df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1683df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1693df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1703df57bcfSMattias Nilsson 1713df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1723df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1733df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1743df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1783df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1793df57bcfSMattias Nilsson 1803df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1813df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1823df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1833df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1843df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1853df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 186a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 187a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 188a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 190a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1913df57bcfSMattias Nilsson 1923df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1933df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1943df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1953df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 2003df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 2013df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2023df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 203a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 204a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 205a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 206a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 207a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 208a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 209a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2103df57bcfSMattias Nilsson 2113df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2123df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2133df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2143df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2153df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2163df57bcfSMattias Nilsson #define PRCMU_I2C_WRITE(slave) \ 2173df57bcfSMattias Nilsson (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2183df57bcfSMattias Nilsson #define PRCMU_I2C_READ(slave) \ 2193df57bcfSMattias Nilsson (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2203df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2213df57bcfSMattias Nilsson 2223df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2233df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2243df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2253df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2263df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2273df57bcfSMattias Nilsson 2283df57bcfSMattias Nilsson #define NUM_MB 8 2293df57bcfSMattias Nilsson #define MBOX_BIT BIT 2303df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2313df57bcfSMattias Nilsson 2323df57bcfSMattias Nilsson /* 2333df57bcfSMattias Nilsson * Wakeups/IRQs 2343df57bcfSMattias Nilsson */ 2353df57bcfSMattias Nilsson 2363df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2373df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2383df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2623df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2633df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2643df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2653df57bcfSMattias Nilsson 266b58d12feSMattias Nilsson static struct { 267b58d12feSMattias Nilsson bool valid; 268b58d12feSMattias Nilsson struct prcmu_fw_version version; 269b58d12feSMattias Nilsson } fw_info; 270b58d12feSMattias Nilsson 2713df57bcfSMattias Nilsson /* 2723df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2733df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2743df57bcfSMattias Nilsson * 2753df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2763df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2773df57bcfSMattias Nilsson * around, to further complicate matters.) 2783df57bcfSMattias Nilsson */ 2793df57bcfSMattias Nilsson #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) 2803df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 2813df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 2823df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 2833df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 2843df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 2853df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 2863df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 2873df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 2883df57bcfSMattias Nilsson IRQ_ENTRY(USB), 2893df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 2903df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 2913df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 2923df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 2933df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 2943df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 2953df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 2963df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 2973df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 2983df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 2993df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 3003df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 3013df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3023df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3033df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3043df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 305650c2a21SLinus Walleij }; 306650c2a21SLinus Walleij 3073df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3083df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3093df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3103df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3113df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3123df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3133df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3143df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3153df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3163df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3173df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3183df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3193df57bcfSMattias Nilsson }; 3203df57bcfSMattias Nilsson 3213df57bcfSMattias Nilsson /* 3223df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3233df57bcfSMattias Nilsson * @lock: The transaction lock. 3243df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3253df57bcfSMattias Nilsson * the request data. 3263df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3273df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3283df57bcfSMattias Nilsson */ 3293df57bcfSMattias Nilsson static struct { 3303df57bcfSMattias Nilsson spinlock_t lock; 3313df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3323df57bcfSMattias Nilsson struct work_struct mask_work; 3333df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3343df57bcfSMattias Nilsson struct completion ac_wake_work; 3353df57bcfSMattias Nilsson struct { 3363df57bcfSMattias Nilsson u32 dbb_irqs; 3373df57bcfSMattias Nilsson u32 dbb_wakeups; 3383df57bcfSMattias Nilsson u32 abb_events; 3393df57bcfSMattias Nilsson } req; 3403df57bcfSMattias Nilsson } mb0_transfer; 3413df57bcfSMattias Nilsson 3423df57bcfSMattias Nilsson /* 3433df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3443df57bcfSMattias Nilsson * @lock: The transaction lock. 3453df57bcfSMattias Nilsson * @work: The transaction completion structure. 3464d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP. 3473df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3483df57bcfSMattias Nilsson */ 349650c2a21SLinus Walleij static struct { 350650c2a21SLinus Walleij struct mutex lock; 351650c2a21SLinus Walleij struct completion work; 3524d64d2e3SMattias Nilsson u8 ape_opp; 353650c2a21SLinus Walleij struct { 3543df57bcfSMattias Nilsson u8 header; 355650c2a21SLinus Walleij u8 arm_opp; 356650c2a21SLinus Walleij u8 ape_opp; 3573df57bcfSMattias Nilsson u8 ape_voltage_status; 358650c2a21SLinus Walleij } ack; 359650c2a21SLinus Walleij } mb1_transfer; 360650c2a21SLinus Walleij 3613df57bcfSMattias Nilsson /* 3623df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3633df57bcfSMattias Nilsson * @lock: The transaction lock. 3643df57bcfSMattias Nilsson * @work: The transaction completion structure. 3653df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3663df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3673df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3683df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3693df57bcfSMattias Nilsson */ 370650c2a21SLinus Walleij static struct { 371650c2a21SLinus Walleij struct mutex lock; 372650c2a21SLinus Walleij struct completion work; 3733df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 3743df57bcfSMattias Nilsson bool auto_pm_enabled; 3753df57bcfSMattias Nilsson struct { 3763df57bcfSMattias Nilsson u8 status; 3773df57bcfSMattias Nilsson } ack; 3783df57bcfSMattias Nilsson } mb2_transfer; 3793df57bcfSMattias Nilsson 3803df57bcfSMattias Nilsson /* 3813df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 3823df57bcfSMattias Nilsson * @lock: The request lock. 3833df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 3843df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 3853df57bcfSMattias Nilsson */ 3863df57bcfSMattias Nilsson static struct { 3873df57bcfSMattias Nilsson spinlock_t lock; 3883df57bcfSMattias Nilsson struct mutex sysclk_lock; 3893df57bcfSMattias Nilsson struct completion sysclk_work; 3903df57bcfSMattias Nilsson } mb3_transfer; 3913df57bcfSMattias Nilsson 3923df57bcfSMattias Nilsson /* 3933df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 3943df57bcfSMattias Nilsson * @lock: The transaction lock. 3953df57bcfSMattias Nilsson * @work: The transaction completion structure. 3963df57bcfSMattias Nilsson */ 3973df57bcfSMattias Nilsson static struct { 3983df57bcfSMattias Nilsson struct mutex lock; 3993df57bcfSMattias Nilsson struct completion work; 4003df57bcfSMattias Nilsson } mb4_transfer; 4013df57bcfSMattias Nilsson 4023df57bcfSMattias Nilsson /* 4033df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4043df57bcfSMattias Nilsson * @lock: The transaction lock. 4053df57bcfSMattias Nilsson * @work: The transaction completion structure. 4063df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4073df57bcfSMattias Nilsson */ 4083df57bcfSMattias Nilsson static struct { 4093df57bcfSMattias Nilsson struct mutex lock; 4103df57bcfSMattias Nilsson struct completion work; 411650c2a21SLinus Walleij struct { 412650c2a21SLinus Walleij u8 status; 413650c2a21SLinus Walleij u8 value; 414650c2a21SLinus Walleij } ack; 415650c2a21SLinus Walleij } mb5_transfer; 416650c2a21SLinus Walleij 4173df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4183df57bcfSMattias Nilsson 4193df57bcfSMattias Nilsson /* Spinlocks */ 420b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock); 4213df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4223df57bcfSMattias Nilsson 4233df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4243df57bcfSMattias Nilsson static __iomem void *tcdm_base; 4253df57bcfSMattias Nilsson 4263df57bcfSMattias Nilsson struct clk_mgt { 4276b6fae2bSMattias Nilsson void __iomem *reg; 4283df57bcfSMattias Nilsson u32 pllsw; 4296b6fae2bSMattias Nilsson int branch; 4306b6fae2bSMattias Nilsson bool clk38div; 4316b6fae2bSMattias Nilsson }; 4326b6fae2bSMattias Nilsson 4336b6fae2bSMattias Nilsson enum { 4346b6fae2bSMattias Nilsson PLL_RAW, 4356b6fae2bSMattias Nilsson PLL_FIX, 4366b6fae2bSMattias Nilsson PLL_DIV 4373df57bcfSMattias Nilsson }; 4383df57bcfSMattias Nilsson 4393df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4403df57bcfSMattias Nilsson 4416b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 4426b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 4433df57bcfSMattias Nilsson struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4446b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 4456b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 4466b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 4476b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 4486b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 4496b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 4506b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 4516b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 4526b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 4536b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 4546b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 4556b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 4566b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 4576b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 4586b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 4596b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 4606b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 4616b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 4626b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 4636b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 4646b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 4656b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 4666b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 4676b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 4686b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 4696b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 4706b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 4736b6fae2bSMattias Nilsson }; 4746b6fae2bSMattias Nilsson 4756b6fae2bSMattias Nilsson struct dsiclk { 4766b6fae2bSMattias Nilsson u32 divsel_mask; 4776b6fae2bSMattias Nilsson u32 divsel_shift; 4786b6fae2bSMattias Nilsson u32 divsel; 4796b6fae2bSMattias Nilsson }; 4806b6fae2bSMattias Nilsson 4816b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = { 4826b6fae2bSMattias Nilsson { 4836b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 4846b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 4856b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4866b6fae2bSMattias Nilsson }, 4876b6fae2bSMattias Nilsson { 4886b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 4896b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 4906b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4916b6fae2bSMattias Nilsson } 4926b6fae2bSMattias Nilsson }; 4936b6fae2bSMattias Nilsson 4946b6fae2bSMattias Nilsson struct dsiescclk { 4956b6fae2bSMattias Nilsson u32 en; 4966b6fae2bSMattias Nilsson u32 div_mask; 4976b6fae2bSMattias Nilsson u32 div_shift; 4986b6fae2bSMattias Nilsson }; 4996b6fae2bSMattias Nilsson 5006b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = { 5016b6fae2bSMattias Nilsson { 5026b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 5036b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 5046b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 5056b6fae2bSMattias Nilsson }, 5066b6fae2bSMattias Nilsson { 5076b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 5086b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 5096b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 5106b6fae2bSMattias Nilsson }, 5116b6fae2bSMattias Nilsson { 5126b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 5136b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 5146b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 5156b6fae2bSMattias Nilsson } 5163df57bcfSMattias Nilsson }; 5173df57bcfSMattias Nilsson 5180837bb72SMattias Nilsson static struct regulator *hwacc_regulator[NUM_HW_ACC]; 5190837bb72SMattias Nilsson static struct regulator *hwacc_ret_regulator[NUM_HW_ACC]; 5200837bb72SMattias Nilsson 5210837bb72SMattias Nilsson static bool hwacc_enabled[NUM_HW_ACC]; 5220837bb72SMattias Nilsson static bool hwacc_ret_enabled[NUM_HW_ACC]; 5230837bb72SMattias Nilsson 5240837bb72SMattias Nilsson static const char *hwacc_regulator_name[NUM_HW_ACC] = { 5250837bb72SMattias Nilsson [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp", 5260837bb72SMattias Nilsson [HW_ACC_SVAPIPE] = "hwacc-sva-pipe", 5270837bb72SMattias Nilsson [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp", 5280837bb72SMattias Nilsson [HW_ACC_SIAPIPE] = "hwacc-sia-pipe", 5290837bb72SMattias Nilsson [HW_ACC_SGA] = "hwacc-sga", 5300837bb72SMattias Nilsson [HW_ACC_B2R2] = "hwacc-b2r2", 5310837bb72SMattias Nilsson [HW_ACC_MCDE] = "hwacc-mcde", 5320837bb72SMattias Nilsson [HW_ACC_ESRAM1] = "hwacc-esram1", 5330837bb72SMattias Nilsson [HW_ACC_ESRAM2] = "hwacc-esram2", 5340837bb72SMattias Nilsson [HW_ACC_ESRAM3] = "hwacc-esram3", 5350837bb72SMattias Nilsson [HW_ACC_ESRAM4] = "hwacc-esram4", 5360837bb72SMattias Nilsson }; 5370837bb72SMattias Nilsson 5380837bb72SMattias Nilsson static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { 5390837bb72SMattias Nilsson [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp-ret", 5400837bb72SMattias Nilsson [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp-ret", 5410837bb72SMattias Nilsson [HW_ACC_ESRAM1] = "hwacc-esram1-ret", 5420837bb72SMattias Nilsson [HW_ACC_ESRAM2] = "hwacc-esram2-ret", 5430837bb72SMattias Nilsson [HW_ACC_ESRAM3] = "hwacc-esram3-ret", 5440837bb72SMattias Nilsson [HW_ACC_ESRAM4] = "hwacc-esram4-ret", 5450837bb72SMattias Nilsson }; 5460837bb72SMattias Nilsson 5473df57bcfSMattias Nilsson /* 5483df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 5493df57bcfSMattias Nilsson */ 5503df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 5513df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 5523df57bcfSMattias Nilsson 5533df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 5543df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 5553df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5563df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5573df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5583df57bcfSMattias Nilsson 5593df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5603df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5613df57bcfSMattias Nilsson 5623df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5633df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5643df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5653df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5663df57bcfSMattias Nilsson 5673df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5683df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5693df57bcfSMattias Nilsson 5703df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5713df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5723df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5733df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5743df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5753df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5763df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5773df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5783df57bcfSMattias Nilsson 5793df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5803df57bcfSMattias Nilsson 58173180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5823df57bcfSMattias Nilsson { 5833df57bcfSMattias Nilsson int i; 5843df57bcfSMattias Nilsson 5853df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 586c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5873df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 588c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5893df57bcfSMattias Nilsson 5903df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 591c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 592c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5933df57bcfSMattias Nilsson /* Enable Escape clocks */ 594c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5953df57bcfSMattias Nilsson 5963df57bcfSMattias Nilsson /* Start DSI PLL */ 597c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5983df57bcfSMattias Nilsson /* Reset DSI PLL */ 599c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 6003df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 601c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 6023df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 6033df57bcfSMattias Nilsson break; 6043df57bcfSMattias Nilsson udelay(100); 6053df57bcfSMattias Nilsson } 6063df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 607c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 6083df57bcfSMattias Nilsson return 0; 6093df57bcfSMattias Nilsson } 6103df57bcfSMattias Nilsson 61173180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 6123df57bcfSMattias Nilsson { 6133df57bcfSMattias Nilsson /* Disable dsi pll */ 614c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 6153df57bcfSMattias Nilsson /* Disable escapeclock */ 616c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 6173df57bcfSMattias Nilsson return 0; 6183df57bcfSMattias Nilsson } 6193df57bcfSMattias Nilsson 62073180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 6213df57bcfSMattias Nilsson { 6223df57bcfSMattias Nilsson unsigned long flags; 6233df57bcfSMattias Nilsson 6243df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 6253df57bcfSMattias Nilsson 6263df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 627c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 6283df57bcfSMattias Nilsson cpu_relax(); 6293df57bcfSMattias Nilsson 630c72fe851SDaniel Willerud writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); 631c553b3caSMattias Nilsson writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); 632c553b3caSMattias Nilsson writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); 6333df57bcfSMattias Nilsson 6343df57bcfSMattias Nilsson /* Release the HW semaphore. */ 635c553b3caSMattias Nilsson writel(0, PRCM_SEM); 6363df57bcfSMattias Nilsson 6373df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 6383df57bcfSMattias Nilsson 6393df57bcfSMattias Nilsson return 0; 6403df57bcfSMattias Nilsson } 6413df57bcfSMattias Nilsson 642b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg) 6433df57bcfSMattias Nilsson { 644b4a6dbd5SMattias Nilsson return readl(_PRCMU_BASE + reg); 6453df57bcfSMattias Nilsson } 6463df57bcfSMattias Nilsson 647b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value) 6483df57bcfSMattias Nilsson { 6493df57bcfSMattias Nilsson unsigned long flags; 6503df57bcfSMattias Nilsson 651b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 652b4a6dbd5SMattias Nilsson writel(value, (_PRCMU_BASE + reg)); 653b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 654b4a6dbd5SMattias Nilsson } 655b4a6dbd5SMattias Nilsson 656b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 657b4a6dbd5SMattias Nilsson { 658b4a6dbd5SMattias Nilsson u32 val; 659b4a6dbd5SMattias Nilsson unsigned long flags; 660b4a6dbd5SMattias Nilsson 661b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 662b4a6dbd5SMattias Nilsson val = readl(_PRCMU_BASE + reg); 663b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask)); 664b4a6dbd5SMattias Nilsson writel(val, (_PRCMU_BASE + reg)); 665b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 6663df57bcfSMattias Nilsson } 6673df57bcfSMattias Nilsson 668b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void) 669b58d12feSMattias Nilsson { 670b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL; 671b58d12feSMattias Nilsson } 672b58d12feSMattias Nilsson 6733df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6743df57bcfSMattias Nilsson { 6753df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6763df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6773df57bcfSMattias Nilsson } 6783df57bcfSMattias Nilsson 6793df57bcfSMattias Nilsson /** 6803df57bcfSMattias Nilsson * prcmu_get_boot_status - PRCMU boot status checking 6813df57bcfSMattias Nilsson * Returns: the current PRCMU boot status 6823df57bcfSMattias Nilsson */ 6833df57bcfSMattias Nilsson int prcmu_get_boot_status(void) 6843df57bcfSMattias Nilsson { 6853df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_BOOT_STATUS); 6863df57bcfSMattias Nilsson } 6873df57bcfSMattias Nilsson 6883df57bcfSMattias Nilsson /** 6893df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6903df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6913df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6923df57bcfSMattias Nilsson * 6933df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6943df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6953df57bcfSMattias Nilsson */ 6963df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6973df57bcfSMattias Nilsson { 6983df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 6993df57bcfSMattias Nilsson return -EINVAL; 7003df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 7013df57bcfSMattias Nilsson return 0; 7023df57bcfSMattias Nilsson } 7033df57bcfSMattias Nilsson 7043df57bcfSMattias Nilsson /** 7053df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 7063df57bcfSMattias Nilsson * Returns: the power transition that has last happened 7073df57bcfSMattias Nilsson * 7083df57bcfSMattias Nilsson * This function can return the following transitions- 7093df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 7103df57bcfSMattias Nilsson */ 7113df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 7123df57bcfSMattias Nilsson { 7133df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 7143df57bcfSMattias Nilsson } 7153df57bcfSMattias Nilsson 7163df57bcfSMattias Nilsson /** 7173df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 7183df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 7193df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 7203df57bcfSMattias Nilsson */ 7213df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 7223df57bcfSMattias Nilsson { 7233df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 7243df57bcfSMattias Nilsson } 7253df57bcfSMattias Nilsson 7263df57bcfSMattias Nilsson /** 7273df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 7283df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 7293df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 7303df57bcfSMattias Nilsson * @div: The divider to be applied. 7313df57bcfSMattias Nilsson * 7323df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 7333df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 7343df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 7353df57bcfSMattias Nilsson */ 7363df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 7373df57bcfSMattias Nilsson { 7383df57bcfSMattias Nilsson static int requests[2]; 7393df57bcfSMattias Nilsson int r = 0; 7403df57bcfSMattias Nilsson unsigned long flags; 7413df57bcfSMattias Nilsson u32 val; 7423df57bcfSMattias Nilsson u32 bits; 7433df57bcfSMattias Nilsson u32 mask; 7443df57bcfSMattias Nilsson u32 div_mask; 7453df57bcfSMattias Nilsson 7463df57bcfSMattias Nilsson BUG_ON(clkout > 1); 7473df57bcfSMattias Nilsson BUG_ON(div > 63); 7483df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 7493df57bcfSMattias Nilsson 7503df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7513df57bcfSMattias Nilsson return -EINVAL; 7523df57bcfSMattias Nilsson 7533df57bcfSMattias Nilsson switch (clkout) { 7543df57bcfSMattias Nilsson case 0: 7553df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7563df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7573df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7583df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 7593df57bcfSMattias Nilsson break; 7603df57bcfSMattias Nilsson case 1: 7613df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7623df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7633df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7643df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7653df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7663df57bcfSMattias Nilsson break; 7673df57bcfSMattias Nilsson } 7683df57bcfSMattias Nilsson bits &= mask; 7693df57bcfSMattias Nilsson 7703df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7713df57bcfSMattias Nilsson 772c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7733df57bcfSMattias Nilsson if (val & div_mask) { 7743df57bcfSMattias Nilsson if (div) { 7753df57bcfSMattias Nilsson if ((val & mask) != bits) { 7763df57bcfSMattias Nilsson r = -EBUSY; 7773df57bcfSMattias Nilsson goto unlock_and_return; 7783df57bcfSMattias Nilsson } 7793df57bcfSMattias Nilsson } else { 7803df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7813df57bcfSMattias Nilsson r = -EINVAL; 7823df57bcfSMattias Nilsson goto unlock_and_return; 7833df57bcfSMattias Nilsson } 7843df57bcfSMattias Nilsson } 7853df57bcfSMattias Nilsson } 786c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7873df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7883df57bcfSMattias Nilsson 7893df57bcfSMattias Nilsson unlock_and_return: 7903df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7913df57bcfSMattias Nilsson 7923df57bcfSMattias Nilsson return r; 7933df57bcfSMattias Nilsson } 7943df57bcfSMattias Nilsson 79573180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7963df57bcfSMattias Nilsson { 7973df57bcfSMattias Nilsson unsigned long flags; 7983df57bcfSMattias Nilsson 7993df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 8003df57bcfSMattias Nilsson 8013df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8023df57bcfSMattias Nilsson 803c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 8043df57bcfSMattias Nilsson cpu_relax(); 8053df57bcfSMattias Nilsson 8063df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 8073df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 8083df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 8093df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 8103df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 8113df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 812c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8133df57bcfSMattias Nilsson 8143df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8153df57bcfSMattias Nilsson 8163df57bcfSMattias Nilsson return 0; 8173df57bcfSMattias Nilsson } 8183df57bcfSMattias Nilsson 8194d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void) 8204d64d2e3SMattias Nilsson { 8214d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 8224d64d2e3SMattias Nilsson } 8234d64d2e3SMattias Nilsson 824485540dcSDaniel Lezcano /* This function decouple the gic from the prcmu */ 825485540dcSDaniel Lezcano int db8500_prcmu_gic_decouple(void) 826485540dcSDaniel Lezcano { 827801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 828485540dcSDaniel Lezcano 829485540dcSDaniel Lezcano /* Set bit 0 register value to 1 */ 830801448e0SDaniel Lezcano writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, 831801448e0SDaniel Lezcano PRCM_A9_MASK_REQ); 832485540dcSDaniel Lezcano 833485540dcSDaniel Lezcano /* Make sure the register is updated */ 834801448e0SDaniel Lezcano readl(PRCM_A9_MASK_REQ); 835485540dcSDaniel Lezcano 836485540dcSDaniel Lezcano /* Wait a few cycles for the gic mask completion */ 837801448e0SDaniel Lezcano udelay(1); 838485540dcSDaniel Lezcano 839485540dcSDaniel Lezcano return 0; 840485540dcSDaniel Lezcano } 841485540dcSDaniel Lezcano 842485540dcSDaniel Lezcano /* This function recouple the gic with the prcmu */ 843485540dcSDaniel Lezcano int db8500_prcmu_gic_recouple(void) 844485540dcSDaniel Lezcano { 845801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 846485540dcSDaniel Lezcano 847485540dcSDaniel Lezcano /* Set bit 0 register value to 0 */ 848801448e0SDaniel Lezcano writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); 849485540dcSDaniel Lezcano 850485540dcSDaniel Lezcano return 0; 851485540dcSDaniel Lezcano } 852485540dcSDaniel Lezcano 8533df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 8543df57bcfSMattias Nilsson static void config_wakeups(void) 8553df57bcfSMattias Nilsson { 8563df57bcfSMattias Nilsson const u8 header[2] = { 8573df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 8583df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 8593df57bcfSMattias Nilsson }; 8603df57bcfSMattias Nilsson static u32 last_dbb_events; 8613df57bcfSMattias Nilsson static u32 last_abb_events; 8623df57bcfSMattias Nilsson u32 dbb_events; 8633df57bcfSMattias Nilsson u32 abb_events; 8643df57bcfSMattias Nilsson unsigned int i; 8653df57bcfSMattias Nilsson 8663df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 8673df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 8683df57bcfSMattias Nilsson 8693df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 8703df57bcfSMattias Nilsson 8713df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 8723df57bcfSMattias Nilsson return; 8733df57bcfSMattias Nilsson 8743df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 875c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 8763df57bcfSMattias Nilsson cpu_relax(); 8773df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 8783df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 8793df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 880c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8813df57bcfSMattias Nilsson } 8823df57bcfSMattias Nilsson last_dbb_events = dbb_events; 8833df57bcfSMattias Nilsson last_abb_events = abb_events; 8843df57bcfSMattias Nilsson } 8853df57bcfSMattias Nilsson 88673180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 8873df57bcfSMattias Nilsson { 8883df57bcfSMattias Nilsson unsigned long flags; 8893df57bcfSMattias Nilsson u32 bits; 8903df57bcfSMattias Nilsson int i; 8913df57bcfSMattias Nilsson 8923df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 8933df57bcfSMattias Nilsson 8943df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 8953df57bcfSMattias Nilsson if (wakeups & BIT(i)) 8963df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 8973df57bcfSMattias Nilsson } 8983df57bcfSMattias Nilsson 8993df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9003df57bcfSMattias Nilsson 9013df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 9023df57bcfSMattias Nilsson config_wakeups(); 9033df57bcfSMattias Nilsson 9043df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9053df57bcfSMattias Nilsson } 9063df57bcfSMattias Nilsson 90773180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 9083df57bcfSMattias Nilsson { 9093df57bcfSMattias Nilsson unsigned long flags; 9103df57bcfSMattias Nilsson 9113df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9123df57bcfSMattias Nilsson 9133df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 9143df57bcfSMattias Nilsson config_wakeups(); 9153df57bcfSMattias Nilsson 9163df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9173df57bcfSMattias Nilsson } 9183df57bcfSMattias Nilsson 91973180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 9203df57bcfSMattias Nilsson { 9213df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 9223df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 9233df57bcfSMattias Nilsson else 9243df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 9253df57bcfSMattias Nilsson } 9263df57bcfSMattias Nilsson 9273df57bcfSMattias Nilsson /** 92873180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 9293df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 9303df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9313df57bcfSMattias Nilsson * 9323df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 9333df57bcfSMattias Nilsson */ 93473180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 9353df57bcfSMattias Nilsson { 9363df57bcfSMattias Nilsson int r; 9373df57bcfSMattias Nilsson 9383df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 9393df57bcfSMattias Nilsson return -EINVAL; 9403df57bcfSMattias Nilsson 9413df57bcfSMattias Nilsson r = 0; 9423df57bcfSMattias Nilsson 9433df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 9443df57bcfSMattias Nilsson 945c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 9463df57bcfSMattias Nilsson cpu_relax(); 9473df57bcfSMattias Nilsson 9483df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 9493df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 9503df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 9513df57bcfSMattias Nilsson 952c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 9533df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 9543df57bcfSMattias Nilsson 9553df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 9563df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 9573df57bcfSMattias Nilsson r = -EIO; 9583df57bcfSMattias Nilsson 9593df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 9603df57bcfSMattias Nilsson 9613df57bcfSMattias Nilsson return r; 9623df57bcfSMattias Nilsson } 9633df57bcfSMattias Nilsson 9643df57bcfSMattias Nilsson /** 96573180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 9663df57bcfSMattias Nilsson * 9673df57bcfSMattias Nilsson * Returns: the current ARM OPP 9683df57bcfSMattias Nilsson */ 96973180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 9703df57bcfSMattias Nilsson { 9713df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 9723df57bcfSMattias Nilsson } 9733df57bcfSMattias Nilsson 9743df57bcfSMattias Nilsson /** 9750508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP 9763df57bcfSMattias Nilsson * 9773df57bcfSMattias Nilsson * Returns: the current DDR OPP 9783df57bcfSMattias Nilsson */ 9790508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void) 9803df57bcfSMattias Nilsson { 981c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 9823df57bcfSMattias Nilsson } 9833df57bcfSMattias Nilsson 9843df57bcfSMattias Nilsson /** 9850508901cSMattias Nilsson * db8500_set_ddr_opp - set the appropriate DDR OPP 9863df57bcfSMattias Nilsson * @opp: The new DDR operating point to which transition is to be made 9873df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9883df57bcfSMattias Nilsson * 9893df57bcfSMattias Nilsson * This function sets the operating point of the DDR. 9903df57bcfSMattias Nilsson */ 9910508901cSMattias Nilsson int db8500_prcmu_set_ddr_opp(u8 opp) 9923df57bcfSMattias Nilsson { 9933df57bcfSMattias Nilsson if (opp < DDR_100_OPP || opp > DDR_25_OPP) 9943df57bcfSMattias Nilsson return -EINVAL; 9953df57bcfSMattias Nilsson /* Changing the DDR OPP can hang the hardware pre-v21 */ 9963df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) 997c553b3caSMattias Nilsson writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 9983df57bcfSMattias Nilsson 9993df57bcfSMattias Nilsson return 0; 10003df57bcfSMattias Nilsson } 10016b6fae2bSMattias Nilsson 10024d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 10034d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable) 10044d64d2e3SMattias Nilsson { 10054d64d2e3SMattias Nilsson void __iomem *clock_reg[] = { 10064d64d2e3SMattias Nilsson PRCM_ACLK_MGT, 10074d64d2e3SMattias Nilsson PRCM_DMACLK_MGT 10084d64d2e3SMattias Nilsson }; 10094d64d2e3SMattias Nilsson unsigned long flags; 10104d64d2e3SMattias Nilsson unsigned int i; 10114d64d2e3SMattias Nilsson 10124d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 10134d64d2e3SMattias Nilsson 10144d64d2e3SMattias Nilsson /* Grab the HW semaphore. */ 10154d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 10164d64d2e3SMattias Nilsson cpu_relax(); 10174d64d2e3SMattias Nilsson 10184d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 10194d64d2e3SMattias Nilsson u32 val; 10204d64d2e3SMattias Nilsson u32 div; 10214d64d2e3SMattias Nilsson 10224d64d2e3SMattias Nilsson val = readl(clock_reg[i]); 10234d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 10244d64d2e3SMattias Nilsson if (enable) { 10254d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) { 10264d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n", 10274d64d2e3SMattias Nilsson div, __func__); 10284d64d2e3SMattias Nilsson goto unlock_and_return; 10294d64d2e3SMattias Nilsson } 10304d64d2e3SMattias Nilsson div <<= 1; 10314d64d2e3SMattias Nilsson } else { 10324d64d2e3SMattias Nilsson if (div <= 2) 10334d64d2e3SMattias Nilsson goto unlock_and_return; 10344d64d2e3SMattias Nilsson div >>= 1; 10354d64d2e3SMattias Nilsson } 10364d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 10374d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 10384d64d2e3SMattias Nilsson writel(val, clock_reg[i]); 10394d64d2e3SMattias Nilsson } 10404d64d2e3SMattias Nilsson 10414d64d2e3SMattias Nilsson unlock_and_return: 10424d64d2e3SMattias Nilsson /* Release the HW semaphore. */ 10434d64d2e3SMattias Nilsson writel(0, PRCM_SEM); 10444d64d2e3SMattias Nilsson 10454d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 10464d64d2e3SMattias Nilsson } 10474d64d2e3SMattias Nilsson 10483df57bcfSMattias Nilsson /** 10490508901cSMattias Nilsson * db8500_set_ape_opp - set the appropriate APE OPP 10503df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 10513df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10523df57bcfSMattias Nilsson * 10533df57bcfSMattias Nilsson * This function sets the operating point of the APE. 10543df57bcfSMattias Nilsson */ 10550508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp) 10563df57bcfSMattias Nilsson { 10573df57bcfSMattias Nilsson int r = 0; 10583df57bcfSMattias Nilsson 10594d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp) 10604d64d2e3SMattias Nilsson return 0; 10614d64d2e3SMattias Nilsson 10623df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10633df57bcfSMattias Nilsson 10644d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 10654d64d2e3SMattias Nilsson request_even_slower_clocks(false); 10664d64d2e3SMattias Nilsson 10674d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 10684d64d2e3SMattias Nilsson goto skip_message; 10694d64d2e3SMattias Nilsson 1070c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10713df57bcfSMattias Nilsson cpu_relax(); 10723df57bcfSMattias Nilsson 10733df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10743df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 10754d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 10764d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 10773df57bcfSMattias Nilsson 1078c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10793df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10803df57bcfSMattias Nilsson 10813df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 10823df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 10833df57bcfSMattias Nilsson r = -EIO; 10843df57bcfSMattias Nilsson 10854d64d2e3SMattias Nilsson skip_message: 10864d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 10874d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 10884d64d2e3SMattias Nilsson request_even_slower_clocks(true); 10894d64d2e3SMattias Nilsson if (!r) 10904d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp; 10914d64d2e3SMattias Nilsson 10923df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10933df57bcfSMattias Nilsson 10943df57bcfSMattias Nilsson return r; 10953df57bcfSMattias Nilsson } 10963df57bcfSMattias Nilsson 10973df57bcfSMattias Nilsson /** 10980508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP 10993df57bcfSMattias Nilsson * 11003df57bcfSMattias Nilsson * Returns: the current APE OPP 11013df57bcfSMattias Nilsson */ 11020508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void) 11033df57bcfSMattias Nilsson { 11043df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 11053df57bcfSMattias Nilsson } 11063df57bcfSMattias Nilsson 11073df57bcfSMattias Nilsson /** 11083df57bcfSMattias Nilsson * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 11093df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 11103df57bcfSMattias Nilsson * 11113df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 11123df57bcfSMattias Nilsson */ 11133df57bcfSMattias Nilsson int prcmu_request_ape_opp_100_voltage(bool enable) 11143df57bcfSMattias Nilsson { 11153df57bcfSMattias Nilsson int r = 0; 11163df57bcfSMattias Nilsson u8 header; 11173df57bcfSMattias Nilsson static unsigned int requests; 11183df57bcfSMattias Nilsson 11193df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11203df57bcfSMattias Nilsson 11213df57bcfSMattias Nilsson if (enable) { 11223df57bcfSMattias Nilsson if (0 != requests++) 11233df57bcfSMattias Nilsson goto unlock_and_return; 11243df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 11253df57bcfSMattias Nilsson } else { 11263df57bcfSMattias Nilsson if (requests == 0) { 11273df57bcfSMattias Nilsson r = -EIO; 11283df57bcfSMattias Nilsson goto unlock_and_return; 11293df57bcfSMattias Nilsson } else if (1 != requests--) { 11303df57bcfSMattias Nilsson goto unlock_and_return; 11313df57bcfSMattias Nilsson } 11323df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 11333df57bcfSMattias Nilsson } 11343df57bcfSMattias Nilsson 1135c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11363df57bcfSMattias Nilsson cpu_relax(); 11373df57bcfSMattias Nilsson 11383df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11393df57bcfSMattias Nilsson 1140c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11413df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11423df57bcfSMattias Nilsson 11433df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 11443df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 11453df57bcfSMattias Nilsson r = -EIO; 11463df57bcfSMattias Nilsson 11473df57bcfSMattias Nilsson unlock_and_return: 11483df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11493df57bcfSMattias Nilsson 11503df57bcfSMattias Nilsson return r; 11513df57bcfSMattias Nilsson } 11523df57bcfSMattias Nilsson 11533df57bcfSMattias Nilsson /** 11543df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 11553df57bcfSMattias Nilsson * 11563df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 11573df57bcfSMattias Nilsson */ 11583df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 11593df57bcfSMattias Nilsson { 11603df57bcfSMattias Nilsson int r = 0; 11613df57bcfSMattias Nilsson 11623df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11633df57bcfSMattias Nilsson 1164c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11653df57bcfSMattias Nilsson cpu_relax(); 11663df57bcfSMattias Nilsson 11673df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 11683df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11693df57bcfSMattias Nilsson 1170c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11713df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11723df57bcfSMattias Nilsson 11733df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 11743df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 11753df57bcfSMattias Nilsson r = -EIO; 11763df57bcfSMattias Nilsson 11773df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11783df57bcfSMattias Nilsson 11793df57bcfSMattias Nilsson return r; 11803df57bcfSMattias Nilsson } 11813df57bcfSMattias Nilsson 11820837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 11830837bb72SMattias Nilsson { 11840837bb72SMattias Nilsson int r = 0; 11850837bb72SMattias Nilsson 11866b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0) 11876b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 11886b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 11890837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 11900837bb72SMattias Nilsson else 11910837bb72SMattias Nilsson return -EINVAL; 11920837bb72SMattias Nilsson 11930837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 11940837bb72SMattias Nilsson 11950837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11960837bb72SMattias Nilsson cpu_relax(); 11970837bb72SMattias Nilsson 11980837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11990837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 12000837bb72SMattias Nilsson 12010837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12020837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 12030837bb72SMattias Nilsson 12040837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 12050837bb72SMattias Nilsson r = -EIO; 12060837bb72SMattias Nilsson 12070837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12080837bb72SMattias Nilsson 12090837bb72SMattias Nilsson return r; 12100837bb72SMattias Nilsson } 12110837bb72SMattias Nilsson 12123df57bcfSMattias Nilsson /** 12130b9199e3SBengt Jonsson * prcmu_set_hwacc - set the power state of a h/w accelerator 12140b9199e3SBengt Jonsson * @hwacc_dev: The hardware accelerator (enum hw_acc_dev). 12150b9199e3SBengt Jonsson * @state: The new power state (enum hw_acc_state). 12160b9199e3SBengt Jonsson * 12170b9199e3SBengt Jonsson * This function sets the power state of a hardware accelerator. 12180b9199e3SBengt Jonsson * This function should not be called from interrupt context. 12190b9199e3SBengt Jonsson * 12200b9199e3SBengt Jonsson * NOTE! Deprecated, to be removed when all users switched over to use the 12210b9199e3SBengt Jonsson * regulator framework API. 12220b9199e3SBengt Jonsson */ 12230b9199e3SBengt Jonsson int prcmu_set_hwacc(u16 hwacc_dev, u8 state) 12240b9199e3SBengt Jonsson { 12250b9199e3SBengt Jonsson int r = 0; 12260b9199e3SBengt Jonsson bool ram_retention = false; 12270b9199e3SBengt Jonsson bool enable, enable_ret; 12280b9199e3SBengt Jonsson 12290b9199e3SBengt Jonsson /* check argument */ 12300b9199e3SBengt Jonsson BUG_ON(hwacc_dev >= NUM_HW_ACC); 12310b9199e3SBengt Jonsson 12320b9199e3SBengt Jonsson /* get state of switches */ 12330b9199e3SBengt Jonsson enable = hwacc_enabled[hwacc_dev]; 12340b9199e3SBengt Jonsson enable_ret = hwacc_ret_enabled[hwacc_dev]; 12350b9199e3SBengt Jonsson 12360b9199e3SBengt Jonsson /* set flag if retention is possible */ 12370b9199e3SBengt Jonsson switch (hwacc_dev) { 12380b9199e3SBengt Jonsson case HW_ACC_SVAMMDSP: 12390b9199e3SBengt Jonsson case HW_ACC_SIAMMDSP: 12400b9199e3SBengt Jonsson case HW_ACC_ESRAM1: 12410b9199e3SBengt Jonsson case HW_ACC_ESRAM2: 12420b9199e3SBengt Jonsson case HW_ACC_ESRAM3: 12430b9199e3SBengt Jonsson case HW_ACC_ESRAM4: 12440b9199e3SBengt Jonsson ram_retention = true; 12450b9199e3SBengt Jonsson break; 12460b9199e3SBengt Jonsson } 12470b9199e3SBengt Jonsson 12480b9199e3SBengt Jonsson /* check argument */ 12490b9199e3SBengt Jonsson BUG_ON(state > HW_ON); 12500b9199e3SBengt Jonsson BUG_ON(state == HW_OFF_RAMRET && !ram_retention); 12510b9199e3SBengt Jonsson 12520b9199e3SBengt Jonsson /* modify enable flags */ 12530b9199e3SBengt Jonsson switch (state) { 12540b9199e3SBengt Jonsson case HW_OFF: 12550b9199e3SBengt Jonsson enable_ret = false; 12560b9199e3SBengt Jonsson enable = false; 12570b9199e3SBengt Jonsson break; 12580b9199e3SBengt Jonsson case HW_ON: 12590b9199e3SBengt Jonsson enable = true; 12600b9199e3SBengt Jonsson break; 12610b9199e3SBengt Jonsson case HW_OFF_RAMRET: 12620b9199e3SBengt Jonsson enable_ret = true; 12630b9199e3SBengt Jonsson enable = false; 12640b9199e3SBengt Jonsson break; 12650b9199e3SBengt Jonsson } 12660b9199e3SBengt Jonsson 12670b9199e3SBengt Jonsson /* get regulator (lazy) */ 12680b9199e3SBengt Jonsson if (hwacc_regulator[hwacc_dev] == NULL) { 12690b9199e3SBengt Jonsson hwacc_regulator[hwacc_dev] = regulator_get(NULL, 12700b9199e3SBengt Jonsson hwacc_regulator_name[hwacc_dev]); 12710b9199e3SBengt Jonsson if (IS_ERR(hwacc_regulator[hwacc_dev])) { 12720b9199e3SBengt Jonsson pr_err("prcmu: failed to get supply %s\n", 12730b9199e3SBengt Jonsson hwacc_regulator_name[hwacc_dev]); 12740b9199e3SBengt Jonsson r = PTR_ERR(hwacc_regulator[hwacc_dev]); 12750b9199e3SBengt Jonsson goto out; 12760b9199e3SBengt Jonsson } 12770b9199e3SBengt Jonsson } 12780b9199e3SBengt Jonsson 12790b9199e3SBengt Jonsson if (ram_retention) { 12800b9199e3SBengt Jonsson if (hwacc_ret_regulator[hwacc_dev] == NULL) { 12810b9199e3SBengt Jonsson hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL, 12820b9199e3SBengt Jonsson hwacc_ret_regulator_name[hwacc_dev]); 12830b9199e3SBengt Jonsson if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) { 12840b9199e3SBengt Jonsson pr_err("prcmu: failed to get supply %s\n", 12850b9199e3SBengt Jonsson hwacc_ret_regulator_name[hwacc_dev]); 12860b9199e3SBengt Jonsson r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]); 12870b9199e3SBengt Jonsson goto out; 12880b9199e3SBengt Jonsson } 12890b9199e3SBengt Jonsson } 12900b9199e3SBengt Jonsson } 12910b9199e3SBengt Jonsson 12920b9199e3SBengt Jonsson /* set regulators */ 12930b9199e3SBengt Jonsson if (ram_retention) { 12940b9199e3SBengt Jonsson if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) { 12950b9199e3SBengt Jonsson r = regulator_enable(hwacc_ret_regulator[hwacc_dev]); 12960b9199e3SBengt Jonsson if (r < 0) { 12970b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: ret enable failed\n"); 12980b9199e3SBengt Jonsson goto out; 12990b9199e3SBengt Jonsson } 13000b9199e3SBengt Jonsson hwacc_ret_enabled[hwacc_dev] = true; 13010b9199e3SBengt Jonsson } 13020b9199e3SBengt Jonsson } 13030b9199e3SBengt Jonsson 13040b9199e3SBengt Jonsson if (enable && !hwacc_enabled[hwacc_dev]) { 13050b9199e3SBengt Jonsson r = regulator_enable(hwacc_regulator[hwacc_dev]); 13060b9199e3SBengt Jonsson if (r < 0) { 13070b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: enable failed\n"); 13080b9199e3SBengt Jonsson goto out; 13090b9199e3SBengt Jonsson } 13100b9199e3SBengt Jonsson hwacc_enabled[hwacc_dev] = true; 13110b9199e3SBengt Jonsson } 13120b9199e3SBengt Jonsson 13130b9199e3SBengt Jonsson if (!enable && hwacc_enabled[hwacc_dev]) { 13140b9199e3SBengt Jonsson r = regulator_disable(hwacc_regulator[hwacc_dev]); 13150b9199e3SBengt Jonsson if (r < 0) { 13160b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: disable failed\n"); 13170b9199e3SBengt Jonsson goto out; 13180b9199e3SBengt Jonsson } 13190b9199e3SBengt Jonsson hwacc_enabled[hwacc_dev] = false; 13200b9199e3SBengt Jonsson } 13210b9199e3SBengt Jonsson 13220b9199e3SBengt Jonsson if (ram_retention) { 13230b9199e3SBengt Jonsson if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) { 13240b9199e3SBengt Jonsson r = regulator_disable(hwacc_ret_regulator[hwacc_dev]); 13250b9199e3SBengt Jonsson if (r < 0) { 13260b9199e3SBengt Jonsson pr_err("prcmu_set_hwacc: ret disable failed\n"); 13270b9199e3SBengt Jonsson goto out; 13280b9199e3SBengt Jonsson } 13290b9199e3SBengt Jonsson hwacc_ret_enabled[hwacc_dev] = false; 13300b9199e3SBengt Jonsson } 13310b9199e3SBengt Jonsson } 13320b9199e3SBengt Jonsson 13330b9199e3SBengt Jonsson out: 13340b9199e3SBengt Jonsson return r; 13350b9199e3SBengt Jonsson } 13360b9199e3SBengt Jonsson EXPORT_SYMBOL(prcmu_set_hwacc); 13370b9199e3SBengt Jonsson 13380b9199e3SBengt Jonsson /** 133973180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 13403df57bcfSMattias Nilsson * @epod_id: The EPOD to set 13413df57bcfSMattias Nilsson * @epod_state: The new EPOD state 13423df57bcfSMattias Nilsson * 13433df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 13443df57bcfSMattias Nilsson * from interrupt context. 13453df57bcfSMattias Nilsson */ 134673180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 13473df57bcfSMattias Nilsson { 13483df57bcfSMattias Nilsson int r = 0; 13493df57bcfSMattias Nilsson bool ram_retention = false; 13503df57bcfSMattias Nilsson int i; 13513df57bcfSMattias Nilsson 13523df57bcfSMattias Nilsson /* check argument */ 13533df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 13543df57bcfSMattias Nilsson 13553df57bcfSMattias Nilsson /* set flag if retention is possible */ 13563df57bcfSMattias Nilsson switch (epod_id) { 13573df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 13583df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 13593df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 13603df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 13613df57bcfSMattias Nilsson ram_retention = true; 13623df57bcfSMattias Nilsson break; 13633df57bcfSMattias Nilsson } 13643df57bcfSMattias Nilsson 13653df57bcfSMattias Nilsson /* check argument */ 13663df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 13673df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 13683df57bcfSMattias Nilsson 13693df57bcfSMattias Nilsson /* get lock */ 13703df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 13713df57bcfSMattias Nilsson 13723df57bcfSMattias Nilsson /* wait for mailbox */ 1373c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 13743df57bcfSMattias Nilsson cpu_relax(); 13753df57bcfSMattias Nilsson 13763df57bcfSMattias Nilsson /* fill in mailbox */ 13773df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 13783df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 13793df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 13803df57bcfSMattias Nilsson 13813df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 13823df57bcfSMattias Nilsson 1383c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 13843df57bcfSMattias Nilsson 13853df57bcfSMattias Nilsson /* 13863df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 13873df57bcfSMattias Nilsson * and we cannot recover if there is an error. 13883df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 13893df57bcfSMattias Nilsson */ 13903df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 13913df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 13923df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 13933df57bcfSMattias Nilsson __func__); 13943df57bcfSMattias Nilsson r = -EIO; 13953df57bcfSMattias Nilsson goto unlock_and_return; 13963df57bcfSMattias Nilsson } 13973df57bcfSMattias Nilsson 13983df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 13993df57bcfSMattias Nilsson r = -EIO; 14003df57bcfSMattias Nilsson 14013df57bcfSMattias Nilsson unlock_and_return: 14023df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 14033df57bcfSMattias Nilsson return r; 14043df57bcfSMattias Nilsson } 14053df57bcfSMattias Nilsson 14063df57bcfSMattias Nilsson /** 14073df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 14083df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 14093df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 14103df57bcfSMattias Nilsson */ 14113df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 14123df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 14133df57bcfSMattias Nilsson { 14143df57bcfSMattias Nilsson u32 sleep_cfg; 14153df57bcfSMattias Nilsson u32 idle_cfg; 14163df57bcfSMattias Nilsson unsigned long flags; 14173df57bcfSMattias Nilsson 14183df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 14193df57bcfSMattias Nilsson 14203df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 14213df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 14223df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 14233df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 14243df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 14253df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 14263df57bcfSMattias Nilsson 14273df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 14283df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 14293df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 14303df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 14313df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 14323df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 14333df57bcfSMattias Nilsson 14343df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 14353df57bcfSMattias Nilsson 14363df57bcfSMattias Nilsson /* 14373df57bcfSMattias Nilsson * The autonomous power management configuration is done through 14383df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 14393df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 14403df57bcfSMattias Nilsson */ 14413df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 14423df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 14433df57bcfSMattias Nilsson 14443df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 14453df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 14463df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 14473df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 14483df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 14493df57bcfSMattias Nilsson 14503df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 14513df57bcfSMattias Nilsson } 14523df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 14533df57bcfSMattias Nilsson 14543df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 14553df57bcfSMattias Nilsson { 14563df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 14573df57bcfSMattias Nilsson } 14583df57bcfSMattias Nilsson 14593df57bcfSMattias Nilsson static int request_sysclk(bool enable) 14603df57bcfSMattias Nilsson { 14613df57bcfSMattias Nilsson int r; 14623df57bcfSMattias Nilsson unsigned long flags; 14633df57bcfSMattias Nilsson 14643df57bcfSMattias Nilsson r = 0; 14653df57bcfSMattias Nilsson 14663df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 14673df57bcfSMattias Nilsson 14683df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 14693df57bcfSMattias Nilsson 1470c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 14713df57bcfSMattias Nilsson cpu_relax(); 14723df57bcfSMattias Nilsson 14733df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 14743df57bcfSMattias Nilsson 14753df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1476c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 14773df57bcfSMattias Nilsson 14783df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 14793df57bcfSMattias Nilsson 14803df57bcfSMattias Nilsson /* 14813df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 14823df57bcfSMattias Nilsson * SysClk, and it succeeds. 14833df57bcfSMattias Nilsson */ 14843df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 14853df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 14863df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 14873df57bcfSMattias Nilsson __func__); 14883df57bcfSMattias Nilsson r = -EIO; 14893df57bcfSMattias Nilsson } 14903df57bcfSMattias Nilsson 14913df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 14923df57bcfSMattias Nilsson 14933df57bcfSMattias Nilsson return r; 14943df57bcfSMattias Nilsson } 14953df57bcfSMattias Nilsson 14963df57bcfSMattias Nilsson static int request_timclk(bool enable) 14973df57bcfSMattias Nilsson { 14983df57bcfSMattias Nilsson u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 14993df57bcfSMattias Nilsson 15003df57bcfSMattias Nilsson if (!enable) 15013df57bcfSMattias Nilsson val |= PRCM_TCR_STOP_TIMERS; 1502c553b3caSMattias Nilsson writel(val, PRCM_TCR); 15033df57bcfSMattias Nilsson 15043df57bcfSMattias Nilsson return 0; 15053df57bcfSMattias Nilsson } 15063df57bcfSMattias Nilsson 15076b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable) 15083df57bcfSMattias Nilsson { 15093df57bcfSMattias Nilsson u32 val; 15103df57bcfSMattias Nilsson unsigned long flags; 15113df57bcfSMattias Nilsson 15123df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 15133df57bcfSMattias Nilsson 15143df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1515c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 15163df57bcfSMattias Nilsson cpu_relax(); 15173df57bcfSMattias Nilsson 15186b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 15193df57bcfSMattias Nilsson if (enable) { 15203df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 15213df57bcfSMattias Nilsson } else { 15223df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 15233df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 15243df57bcfSMattias Nilsson } 15256b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 15263df57bcfSMattias Nilsson 15273df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1528c553b3caSMattias Nilsson writel(0, PRCM_SEM); 15293df57bcfSMattias Nilsson 15303df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 15313df57bcfSMattias Nilsson 15323df57bcfSMattias Nilsson return 0; 15333df57bcfSMattias Nilsson } 15343df57bcfSMattias Nilsson 15350837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 15360837bb72SMattias Nilsson { 15370837bb72SMattias Nilsson u32 val; 15380837bb72SMattias Nilsson int ret; 15390837bb72SMattias Nilsson 15400837bb72SMattias Nilsson if (enable) { 15410837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 15420837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 15430837bb72SMattias Nilsson } 15440837bb72SMattias Nilsson 15456b6fae2bSMattias Nilsson ret = request_clock(clock, enable); 15460837bb72SMattias Nilsson 15470837bb72SMattias Nilsson if (!ret && !enable) { 15480837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 15490837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 15500837bb72SMattias Nilsson } 15510837bb72SMattias Nilsson 15520837bb72SMattias Nilsson return ret; 15530837bb72SMattias Nilsson } 15540837bb72SMattias Nilsson 15556b6fae2bSMattias Nilsson static inline bool plldsi_locked(void) 15566b6fae2bSMattias Nilsson { 15576b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) & 15586b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 15596b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 15606b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 15616b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 15626b6fae2bSMattias Nilsson } 15636b6fae2bSMattias Nilsson 15646b6fae2bSMattias Nilsson static int request_plldsi(bool enable) 15656b6fae2bSMattias Nilsson { 15666b6fae2bSMattias Nilsson int r = 0; 15676b6fae2bSMattias Nilsson u32 val; 15686b6fae2bSMattias Nilsson 15696b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 15706b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 15716b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 15726b6fae2bSMattias Nilsson 15736b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE); 15746b6fae2bSMattias Nilsson if (enable) 15756b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15766b6fae2bSMattias Nilsson else 15776b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15786b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 15796b6fae2bSMattias Nilsson 15806b6fae2bSMattias Nilsson if (enable) { 15816b6fae2bSMattias Nilsson unsigned int i; 15826b6fae2bSMattias Nilsson bool locked = plldsi_locked(); 15836b6fae2bSMattias Nilsson 15846b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) { 15856b6fae2bSMattias Nilsson udelay(100); 15866b6fae2bSMattias Nilsson locked = plldsi_locked(); 15876b6fae2bSMattias Nilsson } 15886b6fae2bSMattias Nilsson if (locked) { 15896b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, 15906b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET); 15916b6fae2bSMattias Nilsson } else { 15926b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 15936b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 15946b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET); 15956b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15966b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 15976b6fae2bSMattias Nilsson r = -EAGAIN; 15986b6fae2bSMattias Nilsson } 15996b6fae2bSMattias Nilsson } else { 16006b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 16016b6fae2bSMattias Nilsson } 16026b6fae2bSMattias Nilsson return r; 16036b6fae2bSMattias Nilsson } 16046b6fae2bSMattias Nilsson 16056b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable) 16066b6fae2bSMattias Nilsson { 16076b6fae2bSMattias Nilsson u32 val; 16086b6fae2bSMattias Nilsson 16096b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 16106b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 16116b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 16126b6fae2bSMattias Nilsson dsiclk[n].divsel_shift); 16136b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 16146b6fae2bSMattias Nilsson return 0; 16156b6fae2bSMattias Nilsson } 16166b6fae2bSMattias Nilsson 16176b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable) 16186b6fae2bSMattias Nilsson { 16196b6fae2bSMattias Nilsson u32 val; 16206b6fae2bSMattias Nilsson 16216b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 16226b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 16236b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 16246b6fae2bSMattias Nilsson return 0; 16256b6fae2bSMattias Nilsson } 16266b6fae2bSMattias Nilsson 16273df57bcfSMattias Nilsson /** 162873180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 16293df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 16303df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 16313df57bcfSMattias Nilsson * 16323df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 16333df57bcfSMattias Nilsson * Do not use it from any other place! 16343df57bcfSMattias Nilsson */ 163573180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 16363df57bcfSMattias Nilsson { 16376b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK) 16380837bb72SMattias Nilsson return request_sga_clock(clock, enable); 16396b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS) 16406b6fae2bSMattias Nilsson return request_clock(clock, enable); 16416b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 16423df57bcfSMattias Nilsson return request_timclk(enable); 16436b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 16446b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 16456b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 16466b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 16476b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 16486b6fae2bSMattias Nilsson return request_plldsi(enable); 16496b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 16503df57bcfSMattias Nilsson return request_sysclk(enable); 16516b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 16520837bb72SMattias Nilsson return request_pll(clock, enable); 16536b6fae2bSMattias Nilsson else 16546b6fae2bSMattias Nilsson return -EINVAL; 16556b6fae2bSMattias Nilsson } 16566b6fae2bSMattias Nilsson 16576b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 16586b6fae2bSMattias Nilsson int branch) 16596b6fae2bSMattias Nilsson { 16606b6fae2bSMattias Nilsson u64 rate; 16616b6fae2bSMattias Nilsson u32 val; 16626b6fae2bSMattias Nilsson u32 d; 16636b6fae2bSMattias Nilsson u32 div = 1; 16646b6fae2bSMattias Nilsson 16656b6fae2bSMattias Nilsson val = readl(reg); 16666b6fae2bSMattias Nilsson 16676b6fae2bSMattias Nilsson rate = src_rate; 16686b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 16696b6fae2bSMattias Nilsson 16706b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 16716b6fae2bSMattias Nilsson if (d > 1) 16726b6fae2bSMattias Nilsson div *= d; 16736b6fae2bSMattias Nilsson 16746b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 16756b6fae2bSMattias Nilsson if (d > 1) 16766b6fae2bSMattias Nilsson div *= d; 16776b6fae2bSMattias Nilsson 16786b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2) 16796b6fae2bSMattias Nilsson div *= 2; 16806b6fae2bSMattias Nilsson 16816b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 16826b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) && 16836b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) || 16846b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ)))) 16856b6fae2bSMattias Nilsson div *= 2; 16866b6fae2bSMattias Nilsson 16876b6fae2bSMattias Nilsson (void)do_div(rate, div); 16886b6fae2bSMattias Nilsson 16896b6fae2bSMattias Nilsson return (unsigned long)rate; 16906b6fae2bSMattias Nilsson } 16916b6fae2bSMattias Nilsson 16926b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000 16936b6fae2bSMattias Nilsson 16946b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock) 16956b6fae2bSMattias Nilsson { 16966b6fae2bSMattias Nilsson u32 val; 16976b6fae2bSMattias Nilsson u32 pllsw; 16986b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE; 16996b6fae2bSMattias Nilsson 17006b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 17016b6fae2bSMattias Nilsson 17026b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 17036b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 17046b6fae2bSMattias Nilsson rate /= 2; 17056b6fae2bSMattias Nilsson return rate; 17066b6fae2bSMattias Nilsson } 17076b6fae2bSMattias Nilsson 17086b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw; 17096b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 17106b6fae2bSMattias Nilsson 17116b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 17126b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 17136b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 17146b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 17156b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 17166b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 17176b6fae2bSMattias Nilsson else 17186b6fae2bSMattias Nilsson return 0; 17196b6fae2bSMattias Nilsson 17206b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) && 17216b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 17226b6fae2bSMattias Nilsson u64 r = (rate * 10); 17236b6fae2bSMattias Nilsson 17246b6fae2bSMattias Nilsson (void)do_div(r, 25); 17256b6fae2bSMattias Nilsson return (unsigned long)r; 17266b6fae2bSMattias Nilsson } 17276b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 17286b6fae2bSMattias Nilsson if (val) 17296b6fae2bSMattias Nilsson return rate / val; 17306b6fae2bSMattias Nilsson else 17316b6fae2bSMattias Nilsson return 0; 17326b6fae2bSMattias Nilsson } 17336b6fae2bSMattias Nilsson 17346b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n) 17356b6fae2bSMattias Nilsson { 17366b6fae2bSMattias Nilsson u32 divsel; 17376b6fae2bSMattias Nilsson u32 div = 1; 17386b6fae2bSMattias Nilsson 17396b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL); 17406b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 17416b6fae2bSMattias Nilsson 17426b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 17436b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel; 17446b6fae2bSMattias Nilsson 17456b6fae2bSMattias Nilsson switch (divsel) { 17466b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4: 17476b6fae2bSMattias Nilsson div *= 2; 17486b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2: 17496b6fae2bSMattias Nilsson div *= 2; 17506b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI: 17516b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 17526b6fae2bSMattias Nilsson PLL_RAW) / div; 1753e62ccf3aSLinus Walleij default: 17546b6fae2bSMattias Nilsson return 0; 17556b6fae2bSMattias Nilsson } 17566b6fae2bSMattias Nilsson } 17576b6fae2bSMattias Nilsson 17586b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n) 17596b6fae2bSMattias Nilsson { 17606b6fae2bSMattias Nilsson u32 div; 17616b6fae2bSMattias Nilsson 17626b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV); 17636b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 17646b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 17656b6fae2bSMattias Nilsson } 17666b6fae2bSMattias Nilsson 17676b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock) 17686b6fae2bSMattias Nilsson { 17696b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 17706b6fae2bSMattias Nilsson return clock_rate(clock); 17716b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 17726b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE / 16; 17736b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 17746b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 17756b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0) 17766b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17776b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 17786b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17796b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR) 17806b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17816b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 17826b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 17836b6fae2bSMattias Nilsson PLL_RAW); 17846b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 17856b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK); 17866b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 17876b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 17886b6fae2bSMattias Nilsson else 17896b6fae2bSMattias Nilsson return 0; 17906b6fae2bSMattias Nilsson } 17916b6fae2bSMattias Nilsson 17926b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 17936b6fae2bSMattias Nilsson { 17946b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 17956b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 17966b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 17976b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 17986b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 17996b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 18006b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 18016b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 18026b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 18036b6fae2bSMattias Nilsson else 18046b6fae2bSMattias Nilsson return 0; 18056b6fae2bSMattias Nilsson } 18066b6fae2bSMattias Nilsson 18076b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate) 18086b6fae2bSMattias Nilsson { 18096b6fae2bSMattias Nilsson u32 div; 18106b6fae2bSMattias Nilsson 18116b6fae2bSMattias Nilsson div = (src_rate / rate); 18126b6fae2bSMattias Nilsson if (div == 0) 18136b6fae2bSMattias Nilsson return 1; 18146b6fae2bSMattias Nilsson if (rate < (src_rate / div)) 18156b6fae2bSMattias Nilsson div++; 18166b6fae2bSMattias Nilsson return div; 18176b6fae2bSMattias Nilsson } 18186b6fae2bSMattias Nilsson 18196b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate) 18206b6fae2bSMattias Nilsson { 18216b6fae2bSMattias Nilsson u32 val; 18226b6fae2bSMattias Nilsson u32 div; 18236b6fae2bSMattias Nilsson unsigned long src_rate; 18246b6fae2bSMattias Nilsson long rounded_rate; 18256b6fae2bSMattias Nilsson 18266b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 18276b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 18286b6fae2bSMattias Nilsson clk_mgt[clock].branch); 18296b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18306b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 18316b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 18326b6fae2bSMattias Nilsson if (div > 2) 18336b6fae2bSMattias Nilsson div = 2; 18346b6fae2bSMattias Nilsson } else { 18356b6fae2bSMattias Nilsson div = 1; 18366b6fae2bSMattias Nilsson } 18376b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 18386b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 18396b6fae2bSMattias Nilsson 18406b6fae2bSMattias Nilsson (void)do_div(r, 25); 18416b6fae2bSMattias Nilsson if (r <= rate) 18426b6fae2bSMattias Nilsson return (unsigned long)r; 18436b6fae2bSMattias Nilsson } 18446b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31)); 18456b6fae2bSMattias Nilsson 18466b6fae2bSMattias Nilsson return rounded_rate; 18476b6fae2bSMattias Nilsson } 18486b6fae2bSMattias Nilsson 18496b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL 18506b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL 18516b6fae2bSMattias Nilsson 18526b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate) 18536b6fae2bSMattias Nilsson { 18546b6fae2bSMattias Nilsson long rounded_rate = 0; 18556b6fae2bSMattias Nilsson unsigned long src_rate; 18566b6fae2bSMattias Nilsson unsigned long rem; 18576b6fae2bSMattias Nilsson u32 r; 18586b6fae2bSMattias Nilsson 18596b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 18606b6fae2bSMattias Nilsson rem = rate; 18616b6fae2bSMattias Nilsson 18626b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 18636b6fae2bSMattias Nilsson u64 d; 18646b6fae2bSMattias Nilsson 18656b6fae2bSMattias Nilsson d = (r * rate); 18666b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 18676b6fae2bSMattias Nilsson if (d < 6) 18686b6fae2bSMattias Nilsson d = 6; 18696b6fae2bSMattias Nilsson else if (d > 255) 18706b6fae2bSMattias Nilsson d = 255; 18716b6fae2bSMattias Nilsson d *= src_rate; 18726b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 18736b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d))) 18746b6fae2bSMattias Nilsson continue; 18756b6fae2bSMattias Nilsson (void)do_div(d, r); 18766b6fae2bSMattias Nilsson if (rate < d) { 18776b6fae2bSMattias Nilsson if (rounded_rate == 0) 18786b6fae2bSMattias Nilsson rounded_rate = (long)d; 1879e62ccf3aSLinus Walleij break; 1880e62ccf3aSLinus Walleij } 18816b6fae2bSMattias Nilsson if ((rate - d) < rem) { 18826b6fae2bSMattias Nilsson rem = (rate - d); 18836b6fae2bSMattias Nilsson rounded_rate = (long)d; 18846b6fae2bSMattias Nilsson } 18856b6fae2bSMattias Nilsson } 18866b6fae2bSMattias Nilsson return rounded_rate; 18876b6fae2bSMattias Nilsson } 18886b6fae2bSMattias Nilsson 18896b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate) 18906b6fae2bSMattias Nilsson { 18916b6fae2bSMattias Nilsson u32 div; 18926b6fae2bSMattias Nilsson unsigned long src_rate; 18936b6fae2bSMattias Nilsson long rounded_rate; 18946b6fae2bSMattias Nilsson 18956b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 18966b6fae2bSMattias Nilsson PLL_RAW); 18976b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18986b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 18996b6fae2bSMattias Nilsson 19006b6fae2bSMattias Nilsson return rounded_rate; 19016b6fae2bSMattias Nilsson } 19026b6fae2bSMattias Nilsson 19036b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate) 19046b6fae2bSMattias Nilsson { 19056b6fae2bSMattias Nilsson u32 div; 19066b6fae2bSMattias Nilsson unsigned long src_rate; 19076b6fae2bSMattias Nilsson long rounded_rate; 19086b6fae2bSMattias Nilsson 19096b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK); 19106b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 19116b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255)); 19126b6fae2bSMattias Nilsson 19136b6fae2bSMattias Nilsson return rounded_rate; 19146b6fae2bSMattias Nilsson } 19156b6fae2bSMattias Nilsson 19166b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate) 19176b6fae2bSMattias Nilsson { 1918e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 19196b6fae2bSMattias Nilsson return round_clock_rate(clock, rate); 19206b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 19216b6fae2bSMattias Nilsson return round_plldsi_rate(rate); 19226b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 19236b6fae2bSMattias Nilsson return round_dsiclk_rate(rate); 19246b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 19256b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate); 19266b6fae2bSMattias Nilsson else 19276b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock); 19286b6fae2bSMattias Nilsson } 19296b6fae2bSMattias Nilsson 19306b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate) 19316b6fae2bSMattias Nilsson { 19326b6fae2bSMattias Nilsson u32 val; 19336b6fae2bSMattias Nilsson u32 div; 19346b6fae2bSMattias Nilsson unsigned long src_rate; 19356b6fae2bSMattias Nilsson unsigned long flags; 19366b6fae2bSMattias Nilsson 19376b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 19386b6fae2bSMattias Nilsson 19396b6fae2bSMattias Nilsson /* Grab the HW semaphore. */ 19406b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 19416b6fae2bSMattias Nilsson cpu_relax(); 19426b6fae2bSMattias Nilsson 19436b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 19446b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 19456b6fae2bSMattias Nilsson clk_mgt[clock].branch); 19466b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 19476b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 19486b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 19496b6fae2bSMattias Nilsson if (div > 1) 19506b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV; 19516b6fae2bSMattias Nilsson else 19526b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV; 19536b6fae2bSMattias Nilsson } 19546b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) { 19556b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 19566b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 19576b6fae2bSMattias Nilsson if (div == 3) { 19586b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 19596b6fae2bSMattias Nilsson 19606b6fae2bSMattias Nilsson (void)do_div(r, 25); 19616b6fae2bSMattias Nilsson if (r <= rate) { 19626b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 19636b6fae2bSMattias Nilsson div = 0; 19646b6fae2bSMattias Nilsson } 19656b6fae2bSMattias Nilsson } 19666b6fae2bSMattias Nilsson val |= min(div, (u32)31); 19676b6fae2bSMattias Nilsson } else { 19686b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 19696b6fae2bSMattias Nilsson val |= min(div, (u32)31); 19706b6fae2bSMattias Nilsson } 19716b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 19726b6fae2bSMattias Nilsson 19736b6fae2bSMattias Nilsson /* Release the HW semaphore. */ 19746b6fae2bSMattias Nilsson writel(0, PRCM_SEM); 19756b6fae2bSMattias Nilsson 19766b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 19776b6fae2bSMattias Nilsson } 19786b6fae2bSMattias Nilsson 19796b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate) 19806b6fae2bSMattias Nilsson { 19816b6fae2bSMattias Nilsson unsigned long src_rate; 19826b6fae2bSMattias Nilsson unsigned long rem; 19836b6fae2bSMattias Nilsson u32 pll_freq = 0; 19846b6fae2bSMattias Nilsson u32 r; 19856b6fae2bSMattias Nilsson 19866b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 19876b6fae2bSMattias Nilsson rem = rate; 19886b6fae2bSMattias Nilsson 19896b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 19906b6fae2bSMattias Nilsson u64 d; 19916b6fae2bSMattias Nilsson u64 hwrate; 19926b6fae2bSMattias Nilsson 19936b6fae2bSMattias Nilsson d = (r * rate); 19946b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 19956b6fae2bSMattias Nilsson if (d < 6) 19966b6fae2bSMattias Nilsson d = 6; 19976b6fae2bSMattias Nilsson else if (d > 255) 19986b6fae2bSMattias Nilsson d = 255; 19996b6fae2bSMattias Nilsson hwrate = (d * src_rate); 20006b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 20016b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 20026b6fae2bSMattias Nilsson continue; 20036b6fae2bSMattias Nilsson (void)do_div(hwrate, r); 20046b6fae2bSMattias Nilsson if (rate < hwrate) { 20056b6fae2bSMattias Nilsson if (pll_freq == 0) 20066b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 20076b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 20086b6fae2bSMattias Nilsson break; 20096b6fae2bSMattias Nilsson } 20106b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) { 20116b6fae2bSMattias Nilsson rem = (rate - hwrate); 20126b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 20136b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 20146b6fae2bSMattias Nilsson } 20156b6fae2bSMattias Nilsson } 20166b6fae2bSMattias Nilsson if (pll_freq == 0) 20173df57bcfSMattias Nilsson return -EINVAL; 20186b6fae2bSMattias Nilsson 20196b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 20206b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ); 20216b6fae2bSMattias Nilsson 20226b6fae2bSMattias Nilsson return 0; 20236b6fae2bSMattias Nilsson } 20246b6fae2bSMattias Nilsson 20256b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate) 20266b6fae2bSMattias Nilsson { 20276b6fae2bSMattias Nilsson u32 val; 20286b6fae2bSMattias Nilsson u32 div; 20296b6fae2bSMattias Nilsson 20306b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 20316b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 20326b6fae2bSMattias Nilsson 20336b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 20346b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 20356b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 20366b6fae2bSMattias Nilsson 20376b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 20386b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 20396b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 20406b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 20416b6fae2bSMattias Nilsson } 20426b6fae2bSMattias Nilsson 20436b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate) 20446b6fae2bSMattias Nilsson { 20456b6fae2bSMattias Nilsson u32 val; 20466b6fae2bSMattias Nilsson u32 div; 20476b6fae2bSMattias Nilsson 20486b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 20496b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 20506b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask; 20516b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 20526b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 20536b6fae2bSMattias Nilsson } 20546b6fae2bSMattias Nilsson 20556b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate) 20566b6fae2bSMattias Nilsson { 20576b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 20586b6fae2bSMattias Nilsson set_clock_rate(clock, rate); 20596b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 20606b6fae2bSMattias Nilsson return set_plldsi_rate(rate); 20616b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 20626b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 20636b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 20646b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 20656b6fae2bSMattias Nilsson return 0; 20663df57bcfSMattias Nilsson } 20673df57bcfSMattias Nilsson 206873180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 20693df57bcfSMattias Nilsson { 20703df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 20713df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 20723df57bcfSMattias Nilsson return -EINVAL; 20733df57bcfSMattias Nilsson 20743df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20753df57bcfSMattias Nilsson 2076c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20773df57bcfSMattias Nilsson cpu_relax(); 20783df57bcfSMattias Nilsson 20793df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20803df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 20813df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 20823df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 20833df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 20843df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 20853df57bcfSMattias Nilsson 2086c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20873df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20883df57bcfSMattias Nilsson 20893df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20903df57bcfSMattias Nilsson 20913df57bcfSMattias Nilsson return 0; 20923df57bcfSMattias Nilsson } 20933df57bcfSMattias Nilsson 20940508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold) 20953df57bcfSMattias Nilsson { 20963df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20973df57bcfSMattias Nilsson 2098c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20993df57bcfSMattias Nilsson cpu_relax(); 21003df57bcfSMattias Nilsson 21013df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 21023df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21033df57bcfSMattias Nilsson 2104c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21053df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21063df57bcfSMattias Nilsson 21073df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21083df57bcfSMattias Nilsson 21093df57bcfSMattias Nilsson return 0; 21103df57bcfSMattias Nilsson } 21113df57bcfSMattias Nilsson 21120508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high) 21133df57bcfSMattias Nilsson { 21143df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21153df57bcfSMattias Nilsson 2116c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21173df57bcfSMattias Nilsson cpu_relax(); 21183df57bcfSMattias Nilsson 21193df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 21203df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 21213df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 21223df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 21233df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21243df57bcfSMattias Nilsson 2125c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21263df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21273df57bcfSMattias Nilsson 21283df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21293df57bcfSMattias Nilsson 21303df57bcfSMattias Nilsson return 0; 21313df57bcfSMattias Nilsson } 21323df57bcfSMattias Nilsson 21333df57bcfSMattias Nilsson static int config_hot_period(u16 val) 21343df57bcfSMattias Nilsson { 21353df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 21363df57bcfSMattias Nilsson 2137c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 21383df57bcfSMattias Nilsson cpu_relax(); 21393df57bcfSMattias Nilsson 21403df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 21413df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 21423df57bcfSMattias Nilsson 2143c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 21443df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 21453df57bcfSMattias Nilsson 21463df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 21473df57bcfSMattias Nilsson 21483df57bcfSMattias Nilsson return 0; 21493df57bcfSMattias Nilsson } 21503df57bcfSMattias Nilsson 21510508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k) 21523df57bcfSMattias Nilsson { 21533df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 21543df57bcfSMattias Nilsson return -EINVAL; 21553df57bcfSMattias Nilsson 21563df57bcfSMattias Nilsson return config_hot_period(cycles32k); 21573df57bcfSMattias Nilsson } 21583df57bcfSMattias Nilsson 21590508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void) 21603df57bcfSMattias Nilsson { 21613df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 21623df57bcfSMattias Nilsson } 21633df57bcfSMattias Nilsson 216484165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 216584165b80SJonas Aberg { 216684165b80SJonas Aberg 216784165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 216884165b80SJonas Aberg 216984165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 217084165b80SJonas Aberg cpu_relax(); 217184165b80SJonas Aberg 217284165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 217384165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 217484165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 217584165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 217684165b80SJonas Aberg 217784165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 217884165b80SJonas Aberg 217984165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 218084165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 218184165b80SJonas Aberg 218284165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 218384165b80SJonas Aberg 218484165b80SJonas Aberg return 0; 218584165b80SJonas Aberg 218684165b80SJonas Aberg } 218784165b80SJonas Aberg 21880508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 218984165b80SJonas Aberg { 219084165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 219184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 219284165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 219384165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 219484165b80SJonas Aberg } 219584165b80SJonas Aberg 21960508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id) 219784165b80SJonas Aberg { 219884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 219984165b80SJonas Aberg } 220084165b80SJonas Aberg 22010508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id) 220284165b80SJonas Aberg { 220384165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 220484165b80SJonas Aberg } 220584165b80SJonas Aberg 22060508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id) 220784165b80SJonas Aberg { 220884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 220984165b80SJonas Aberg } 221084165b80SJonas Aberg 221184165b80SJonas Aberg /* 221284165b80SJonas Aberg * timeout is 28 bit, in ms. 221384165b80SJonas Aberg */ 22140508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 221584165b80SJonas Aberg { 221684165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 221784165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 221884165b80SJonas Aberg /* 221984165b80SJonas Aberg * Put the lowest 28 bits of timeout at 222084165b80SJonas Aberg * offset 4. Four first bits are used for id. 222184165b80SJonas Aberg */ 222284165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 222384165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 222484165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 222584165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 222684165b80SJonas Aberg } 222784165b80SJonas Aberg 22283df57bcfSMattias Nilsson /** 2229650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 2230650c2a21SLinus Walleij * @slave: The I2C slave address. 2231650c2a21SLinus Walleij * @reg: The (start) register address. 2232650c2a21SLinus Walleij * @value: The read out value(s). 2233650c2a21SLinus Walleij * @size: The number of registers to read. 2234650c2a21SLinus Walleij * 2235650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2236650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2237650c2a21SLinus Walleij */ 2238650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2239650c2a21SLinus Walleij { 2240650c2a21SLinus Walleij int r; 2241650c2a21SLinus Walleij 2242650c2a21SLinus Walleij if (size != 1) 2243650c2a21SLinus Walleij return -EINVAL; 2244650c2a21SLinus Walleij 22453df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2246650c2a21SLinus Walleij 2247c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2248650c2a21SLinus Walleij cpu_relax(); 2249650c2a21SLinus Walleij 22503df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22513df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22523df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22533df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2254650c2a21SLinus Walleij 2255c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 22563df57bcfSMattias Nilsson 2257650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 22583df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 22593df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 22603df57bcfSMattias Nilsson __func__); 2261650c2a21SLinus Walleij r = -EIO; 22623df57bcfSMattias Nilsson } else { 2263650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 22643df57bcfSMattias Nilsson } 22653df57bcfSMattias Nilsson 2266650c2a21SLinus Walleij if (!r) 2267650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 2268650c2a21SLinus Walleij 2269650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 22703df57bcfSMattias Nilsson 2271650c2a21SLinus Walleij return r; 2272650c2a21SLinus Walleij } 2273650c2a21SLinus Walleij 2274650c2a21SLinus Walleij /** 2275650c2a21SLinus Walleij * prcmu_abb_write() - Write register value(s) to the ABB. 2276650c2a21SLinus Walleij * @slave: The I2C slave address. 2277650c2a21SLinus Walleij * @reg: The (start) register address. 2278650c2a21SLinus Walleij * @value: The value(s) to write. 2279650c2a21SLinus Walleij * @size: The number of registers to write. 2280650c2a21SLinus Walleij * 2281650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2282650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2283650c2a21SLinus Walleij */ 2284650c2a21SLinus Walleij int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 2285650c2a21SLinus Walleij { 2286650c2a21SLinus Walleij int r; 2287650c2a21SLinus Walleij 2288650c2a21SLinus Walleij if (size != 1) 2289650c2a21SLinus Walleij return -EINVAL; 2290650c2a21SLinus Walleij 22913df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2292650c2a21SLinus Walleij 2293c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2294650c2a21SLinus Walleij cpu_relax(); 2295650c2a21SLinus Walleij 22963df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22973df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22983df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22993df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2300650c2a21SLinus Walleij 2301c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 23023df57bcfSMattias Nilsson 2303650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 23043df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 23053df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 23063df57bcfSMattias Nilsson __func__); 2307650c2a21SLinus Walleij r = -EIO; 23083df57bcfSMattias Nilsson } else { 2309650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 23103df57bcfSMattias Nilsson } 23113df57bcfSMattias Nilsson 23123df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 23133df57bcfSMattias Nilsson 23143df57bcfSMattias Nilsson return r; 23153df57bcfSMattias Nilsson } 23163df57bcfSMattias Nilsson 23173df57bcfSMattias Nilsson /** 23183df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 23193df57bcfSMattias Nilsson */ 23203df57bcfSMattias Nilsson void prcmu_ac_wake_req(void) 23213df57bcfSMattias Nilsson { 23223df57bcfSMattias Nilsson u32 val; 2323d6e3002eSMattias Nilsson u32 status; 23243df57bcfSMattias Nilsson 23253df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 23263df57bcfSMattias Nilsson 2327c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23283df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 23293df57bcfSMattias Nilsson goto unlock_and_return; 23303df57bcfSMattias Nilsson 23313df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 23323df57bcfSMattias Nilsson 2333d6e3002eSMattias Nilsson retry: 2334c553b3caSMattias Nilsson writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); 23353df57bcfSMattias Nilsson 23363df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2337d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 233857265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2339d6e3002eSMattias Nilsson __func__); 2340d6e3002eSMattias Nilsson goto unlock_and_return; 2341d6e3002eSMattias Nilsson } 2342d6e3002eSMattias Nilsson 2343d6e3002eSMattias Nilsson /* 2344d6e3002eSMattias Nilsson * The modem can generate an AC_WAKE_ACK, and then still go to sleep. 2345d6e3002eSMattias Nilsson * As a workaround, we wait, and then check that the modem is indeed 2346d6e3002eSMattias Nilsson * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS 2347d6e3002eSMattias Nilsson * register, which may not be the whole truth). 2348d6e3002eSMattias Nilsson */ 2349d6e3002eSMattias Nilsson udelay(400); 2350d6e3002eSMattias Nilsson status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2)); 2351d6e3002eSMattias Nilsson if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE | 2352d6e3002eSMattias Nilsson PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) { 2353d6e3002eSMattias Nilsson pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n", 2354d6e3002eSMattias Nilsson __func__, status); 2355d6e3002eSMattias Nilsson udelay(1200); 2356d6e3002eSMattias Nilsson writel(val, PRCM_HOSTACCESS_REQ); 2357d6e3002eSMattias Nilsson if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2358d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) 2359d6e3002eSMattias Nilsson goto retry; 236057265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n", 23613df57bcfSMattias Nilsson __func__); 23623df57bcfSMattias Nilsson } 2363650c2a21SLinus Walleij 2364650c2a21SLinus Walleij unlock_and_return: 23653df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 2366650c2a21SLinus Walleij } 2367650c2a21SLinus Walleij 23683df57bcfSMattias Nilsson /** 23693df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 23703df57bcfSMattias Nilsson */ 23713df57bcfSMattias Nilsson void prcmu_ac_sleep_req() 2372650c2a21SLinus Walleij { 23733df57bcfSMattias Nilsson u32 val; 2374650c2a21SLinus Walleij 23753df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 2376650c2a21SLinus Walleij 2377c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23783df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 23793df57bcfSMattias Nilsson goto unlock_and_return; 23803df57bcfSMattias Nilsson 23813df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2382c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 23833df57bcfSMattias Nilsson 23843df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2385d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 238657265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 23873df57bcfSMattias Nilsson __func__); 23883df57bcfSMattias Nilsson } 23893df57bcfSMattias Nilsson 23903df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 23913df57bcfSMattias Nilsson 23923df57bcfSMattias Nilsson unlock_and_return: 23933df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23943df57bcfSMattias Nilsson } 23953df57bcfSMattias Nilsson 239673180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 23973df57bcfSMattias Nilsson { 23983df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 23993df57bcfSMattias Nilsson } 24003df57bcfSMattias Nilsson 24013df57bcfSMattias Nilsson /** 240273180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 24033df57bcfSMattias Nilsson * 240473180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 24053df57bcfSMattias Nilsson * fires interrupt to fw 24063df57bcfSMattias Nilsson */ 240773180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 24083df57bcfSMattias Nilsson { 24093df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2410c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 24113df57bcfSMattias Nilsson } 24123df57bcfSMattias Nilsson 24133df57bcfSMattias Nilsson /** 2414597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2415597045deSSebastian Rasmussen * 2416597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 2417597045deSSebastian Rasmussen * last restart. 2418597045deSSebastian Rasmussen */ 2419597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 2420597045deSSebastian Rasmussen { 2421597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 2422597045deSSebastian Rasmussen } 2423597045deSSebastian Rasmussen 2424597045deSSebastian Rasmussen /** 24250508901cSMattias Nilsson * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 24263df57bcfSMattias Nilsson */ 24270508901cSMattias Nilsson void db8500_prcmu_modem_reset(void) 24283df57bcfSMattias Nilsson { 2429650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 2430650c2a21SLinus Walleij 2431c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2432650c2a21SLinus Walleij cpu_relax(); 2433650c2a21SLinus Walleij 24343df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2435c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2436650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 24373df57bcfSMattias Nilsson 24383df57bcfSMattias Nilsson /* 24393df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 24403df57bcfSMattias Nilsson * This state is already managed by upper layer 24413df57bcfSMattias Nilsson */ 2442650c2a21SLinus Walleij 2443650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 2444650c2a21SLinus Walleij } 2445650c2a21SLinus Walleij 24463df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 2447650c2a21SLinus Walleij { 24483df57bcfSMattias Nilsson unsigned long flags; 2449650c2a21SLinus Walleij 24503df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 2451650c2a21SLinus Walleij 2452c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 24533df57bcfSMattias Nilsson cpu_relax(); 2454650c2a21SLinus Walleij 24553df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2456c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2457650c2a21SLinus Walleij 24583df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2459650c2a21SLinus Walleij } 2460650c2a21SLinus Walleij 24613df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 2462650c2a21SLinus Walleij { 24633df57bcfSMattias Nilsson pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 24643df57bcfSMattias Nilsson header, n); 2465650c2a21SLinus Walleij } 2466650c2a21SLinus Walleij 24673df57bcfSMattias Nilsson static bool read_mailbox_0(void) 2468650c2a21SLinus Walleij { 24693df57bcfSMattias Nilsson bool r; 24703df57bcfSMattias Nilsson u32 ev; 24713df57bcfSMattias Nilsson unsigned int n; 24723df57bcfSMattias Nilsson u8 header; 24733df57bcfSMattias Nilsson 24743df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 24753df57bcfSMattias Nilsson switch (header) { 24763df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 24773df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 24783df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 24793df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 24803df57bcfSMattias Nilsson else 24813df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 24823df57bcfSMattias Nilsson 24833df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 24843df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 24853df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 24863df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 24873df57bcfSMattias Nilsson 24883df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 24893df57bcfSMattias Nilsson 24903df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 24913df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 24923df57bcfSMattias Nilsson generic_handle_irq(IRQ_PRCMU_BASE + n); 24933df57bcfSMattias Nilsson } 24943df57bcfSMattias Nilsson r = true; 24953df57bcfSMattias Nilsson break; 24963df57bcfSMattias Nilsson default: 24973df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 24983df57bcfSMattias Nilsson r = false; 24993df57bcfSMattias Nilsson break; 25003df57bcfSMattias Nilsson } 2501c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 25023df57bcfSMattias Nilsson return r; 25033df57bcfSMattias Nilsson } 25043df57bcfSMattias Nilsson 25053df57bcfSMattias Nilsson static bool read_mailbox_1(void) 25063df57bcfSMattias Nilsson { 25073df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 25083df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 25093df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 25103df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 25113df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 25123df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 25133df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2514c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2515650c2a21SLinus Walleij complete(&mb1_transfer.work); 25163df57bcfSMattias Nilsson return false; 2517650c2a21SLinus Walleij } 2518650c2a21SLinus Walleij 25193df57bcfSMattias Nilsson static bool read_mailbox_2(void) 2520650c2a21SLinus Walleij { 25213df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2522c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 25233df57bcfSMattias Nilsson complete(&mb2_transfer.work); 25243df57bcfSMattias Nilsson return false; 2525650c2a21SLinus Walleij } 2526650c2a21SLinus Walleij 25273df57bcfSMattias Nilsson static bool read_mailbox_3(void) 2528650c2a21SLinus Walleij { 2529c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 25303df57bcfSMattias Nilsson return false; 2531650c2a21SLinus Walleij } 2532650c2a21SLinus Walleij 25333df57bcfSMattias Nilsson static bool read_mailbox_4(void) 2534650c2a21SLinus Walleij { 25353df57bcfSMattias Nilsson u8 header; 25363df57bcfSMattias Nilsson bool do_complete = true; 25373df57bcfSMattias Nilsson 25383df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 25393df57bcfSMattias Nilsson switch (header) { 25403df57bcfSMattias Nilsson case MB4H_MEM_ST: 25413df57bcfSMattias Nilsson case MB4H_HOTDOG: 25423df57bcfSMattias Nilsson case MB4H_HOTMON: 25433df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 2544a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 2545a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 2546a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 2547a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 2548a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 25493df57bcfSMattias Nilsson break; 25503df57bcfSMattias Nilsson default: 25513df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 25523df57bcfSMattias Nilsson do_complete = false; 25533df57bcfSMattias Nilsson break; 2554650c2a21SLinus Walleij } 2555650c2a21SLinus Walleij 2556c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 25573df57bcfSMattias Nilsson 25583df57bcfSMattias Nilsson if (do_complete) 25593df57bcfSMattias Nilsson complete(&mb4_transfer.work); 25603df57bcfSMattias Nilsson 25613df57bcfSMattias Nilsson return false; 25623df57bcfSMattias Nilsson } 25633df57bcfSMattias Nilsson 25643df57bcfSMattias Nilsson static bool read_mailbox_5(void) 2565650c2a21SLinus Walleij { 25663df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 25673df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2568c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2569650c2a21SLinus Walleij complete(&mb5_transfer.work); 25703df57bcfSMattias Nilsson return false; 2571650c2a21SLinus Walleij } 2572650c2a21SLinus Walleij 25733df57bcfSMattias Nilsson static bool read_mailbox_6(void) 2574650c2a21SLinus Walleij { 2575c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 25763df57bcfSMattias Nilsson return false; 2577650c2a21SLinus Walleij } 2578650c2a21SLinus Walleij 25793df57bcfSMattias Nilsson static bool read_mailbox_7(void) 2580650c2a21SLinus Walleij { 2581c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 25823df57bcfSMattias Nilsson return false; 2583650c2a21SLinus Walleij } 2584650c2a21SLinus Walleij 25853df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 2586650c2a21SLinus Walleij read_mailbox_0, 2587650c2a21SLinus Walleij read_mailbox_1, 2588650c2a21SLinus Walleij read_mailbox_2, 2589650c2a21SLinus Walleij read_mailbox_3, 2590650c2a21SLinus Walleij read_mailbox_4, 2591650c2a21SLinus Walleij read_mailbox_5, 2592650c2a21SLinus Walleij read_mailbox_6, 2593650c2a21SLinus Walleij read_mailbox_7 2594650c2a21SLinus Walleij }; 2595650c2a21SLinus Walleij 2596650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2597650c2a21SLinus Walleij { 2598650c2a21SLinus Walleij u32 bits; 2599650c2a21SLinus Walleij u8 n; 26003df57bcfSMattias Nilsson irqreturn_t r; 2601650c2a21SLinus Walleij 2602c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2603650c2a21SLinus Walleij if (unlikely(!bits)) 2604650c2a21SLinus Walleij return IRQ_NONE; 2605650c2a21SLinus Walleij 26063df57bcfSMattias Nilsson r = IRQ_HANDLED; 2607650c2a21SLinus Walleij for (n = 0; bits; n++) { 2608650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2609650c2a21SLinus Walleij bits -= MBOX_BIT(n); 26103df57bcfSMattias Nilsson if (read_mailbox[n]()) 26113df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2612650c2a21SLinus Walleij } 2613650c2a21SLinus Walleij } 26143df57bcfSMattias Nilsson return r; 26153df57bcfSMattias Nilsson } 26163df57bcfSMattias Nilsson 26173df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 26183df57bcfSMattias Nilsson { 26193df57bcfSMattias Nilsson ack_dbb_wakeup(); 2620650c2a21SLinus Walleij return IRQ_HANDLED; 2621650c2a21SLinus Walleij } 2622650c2a21SLinus Walleij 26233df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 26243df57bcfSMattias Nilsson { 26253df57bcfSMattias Nilsson unsigned long flags; 26263df57bcfSMattias Nilsson 26273df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 26283df57bcfSMattias Nilsson 26293df57bcfSMattias Nilsson config_wakeups(); 26303df57bcfSMattias Nilsson 26313df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 26323df57bcfSMattias Nilsson } 26333df57bcfSMattias Nilsson 26343df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 26353df57bcfSMattias Nilsson { 26363df57bcfSMattias Nilsson unsigned long flags; 26373df57bcfSMattias Nilsson 26383df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26393df57bcfSMattias Nilsson 26403df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 26413df57bcfSMattias Nilsson 26423df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26433df57bcfSMattias Nilsson 26443df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26453df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26463df57bcfSMattias Nilsson } 26473df57bcfSMattias Nilsson 26483df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 26493df57bcfSMattias Nilsson { 26503df57bcfSMattias Nilsson unsigned long flags; 26513df57bcfSMattias Nilsson 26523df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26533df57bcfSMattias Nilsson 26543df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 26553df57bcfSMattias Nilsson 26563df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26573df57bcfSMattias Nilsson 26583df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26593df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26603df57bcfSMattias Nilsson } 26613df57bcfSMattias Nilsson 26623df57bcfSMattias Nilsson static void noop(struct irq_data *d) 26633df57bcfSMattias Nilsson { 26643df57bcfSMattias Nilsson } 26653df57bcfSMattias Nilsson 26663df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 26673df57bcfSMattias Nilsson .name = "prcmu", 26683df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 26693df57bcfSMattias Nilsson .irq_ack = noop, 26703df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 26713df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 26723df57bcfSMattias Nilsson }; 26733df57bcfSMattias Nilsson 2674b58d12feSMattias Nilsson static char *fw_project_name(u8 project) 2675b58d12feSMattias Nilsson { 2676b58d12feSMattias Nilsson switch (project) { 2677b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500: 2678b58d12feSMattias Nilsson return "U8500"; 2679b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500_C2: 2680b58d12feSMattias Nilsson return "U8500 C2"; 2681b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500: 2682b58d12feSMattias Nilsson return "U9500"; 2683b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500_C2: 2684b58d12feSMattias Nilsson return "U9500 C2"; 2685b58d12feSMattias Nilsson default: 2686b58d12feSMattias Nilsson return "Unknown"; 2687b58d12feSMattias Nilsson } 2688b58d12feSMattias Nilsson } 2689b58d12feSMattias Nilsson 269073180f85SMattias Nilsson void __init db8500_prcmu_early_init(void) 2691650c2a21SLinus Walleij { 26923df57bcfSMattias Nilsson unsigned int i; 26933e2762c8SLinus Walleij if (cpu_is_u8500v2()) { 26943df57bcfSMattias Nilsson void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); 26953df57bcfSMattias Nilsson 26963df57bcfSMattias Nilsson if (tcpm_base != NULL) { 26973e2762c8SLinus Walleij u32 version; 26983df57bcfSMattias Nilsson version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); 2699b58d12feSMattias Nilsson fw_info.version.project = version & 0xFF; 2700b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF; 2701b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF; 2702b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF; 2703b58d12feSMattias Nilsson fw_info.valid = true; 2704b58d12feSMattias Nilsson pr_info("PRCMU firmware: %s, version %d.%d.%d\n", 2705b58d12feSMattias Nilsson fw_project_name(fw_info.version.project), 27063df57bcfSMattias Nilsson (version >> 8) & 0xFF, (version >> 16) & 0xFF, 27073df57bcfSMattias Nilsson (version >> 24) & 0xFF); 27083df57bcfSMattias Nilsson iounmap(tcpm_base); 27093df57bcfSMattias Nilsson } 27103df57bcfSMattias Nilsson 2711650c2a21SLinus Walleij tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); 2712650c2a21SLinus Walleij } else { 2713650c2a21SLinus Walleij pr_err("prcmu: Unsupported chip version\n"); 2714650c2a21SLinus Walleij BUG(); 2715650c2a21SLinus Walleij } 2716650c2a21SLinus Walleij 27173df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 27183df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 27193df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 27203df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2721650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2722650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 27234d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE; 27243df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 27253df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 27263df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 27273df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 27283df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 27293df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 27303df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 27313df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2732650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2733650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2734650c2a21SLinus Walleij 27353df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2736650c2a21SLinus Walleij 27373df57bcfSMattias Nilsson /* Initalize irqs. */ 27383df57bcfSMattias Nilsson for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { 27393df57bcfSMattias Nilsson unsigned int irq; 27403df57bcfSMattias Nilsson 27413df57bcfSMattias Nilsson irq = IRQ_PRCMU_BASE + i; 27423df57bcfSMattias Nilsson irq_set_chip_and_handler(irq, &prcmu_irq_chip, 27433df57bcfSMattias Nilsson handle_simple_irq); 27443df57bcfSMattias Nilsson set_irq_flags(irq, IRQF_VALID); 27453df57bcfSMattias Nilsson } 2746650c2a21SLinus Walleij } 2747650c2a21SLinus Walleij 27480508901cSMattias Nilsson static void __init init_prcm_registers(void) 2749d65e12d7SMattias Nilsson { 2750d65e12d7SMattias Nilsson u32 val; 2751d65e12d7SMattias Nilsson 2752d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2753d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2754d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2755d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2756d65e12d7SMattias Nilsson } 2757d65e12d7SMattias Nilsson 27581032fbfdSBengt Jonsson /* 27591032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 27601032fbfdSBengt Jonsson */ 27611032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 27621032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 27631032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 27641032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 27651032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 27661032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 27671032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 27681032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 27691032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 27701032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 27711032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 27721032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 27731032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 27741032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 27751032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 27761032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 27771032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 27781032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 27791032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2780992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 27811032fbfdSBengt Jonsson }; 27821032fbfdSBengt Jonsson 27831032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 27841032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 27851032fbfdSBengt Jonsson /* AV8100 regulator */ 27861032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 27871032fbfdSBengt Jonsson }; 27881032fbfdSBengt Jonsson 27891032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2790992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2791624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2792624e87c2SBengt Jonsson }; 2793624e87c2SBengt Jonsson 2794624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2795624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2796624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2797624e87c2SBengt Jonsson }; 2798624e87c2SBengt Jonsson 2799624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2800624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2801624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2802624e87c2SBengt Jonsson }; 2803624e87c2SBengt Jonsson 2804624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2805624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2806624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2807624e87c2SBengt Jonsson }; 2808624e87c2SBengt Jonsson 2809624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2810624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2811624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2812624e87c2SBengt Jonsson }; 2813624e87c2SBengt Jonsson 2814624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2815624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2816624e87c2SBengt Jonsson }; 2817624e87c2SBengt Jonsson 2818624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2819624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2820624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2821624e87c2SBengt Jonsson }; 2822624e87c2SBengt Jonsson 2823624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2824624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2825624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2826624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 2827992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 28281032fbfdSBengt Jonsson }; 28291032fbfdSBengt Jonsson 28301032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 28311032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 28321032fbfdSBengt Jonsson .constraints = { 28331032fbfdSBengt Jonsson .name = "db8500-vape", 28341032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28351032fbfdSBengt Jonsson }, 28361032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 28371032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 28381032fbfdSBengt Jonsson }, 28391032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 28401032fbfdSBengt Jonsson .constraints = { 28411032fbfdSBengt Jonsson .name = "db8500-varm", 28421032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28431032fbfdSBengt Jonsson }, 28441032fbfdSBengt Jonsson }, 28451032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 28461032fbfdSBengt Jonsson .constraints = { 28471032fbfdSBengt Jonsson .name = "db8500-vmodem", 28481032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28491032fbfdSBengt Jonsson }, 28501032fbfdSBengt Jonsson }, 28511032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 28521032fbfdSBengt Jonsson .constraints = { 28531032fbfdSBengt Jonsson .name = "db8500-vpll", 28541032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28551032fbfdSBengt Jonsson }, 28561032fbfdSBengt Jonsson }, 28571032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 28581032fbfdSBengt Jonsson .constraints = { 28591032fbfdSBengt Jonsson .name = "db8500-vsmps1", 28601032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28611032fbfdSBengt Jonsson }, 28621032fbfdSBengt Jonsson }, 28631032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 28641032fbfdSBengt Jonsson .constraints = { 28651032fbfdSBengt Jonsson .name = "db8500-vsmps2", 28661032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28671032fbfdSBengt Jonsson }, 28681032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 28691032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 28701032fbfdSBengt Jonsson }, 28711032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 28721032fbfdSBengt Jonsson .constraints = { 28731032fbfdSBengt Jonsson .name = "db8500-vsmps3", 28741032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28751032fbfdSBengt Jonsson }, 28761032fbfdSBengt Jonsson }, 28771032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 28781032fbfdSBengt Jonsson .constraints = { 28791032fbfdSBengt Jonsson .name = "db8500-vrf1", 28801032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28811032fbfdSBengt Jonsson }, 28821032fbfdSBengt Jonsson }, 28831032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2884992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 28851032fbfdSBengt Jonsson .constraints = { 28861032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 28871032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28881032fbfdSBengt Jonsson }, 2889624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2890624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 28911032fbfdSBengt Jonsson }, 28921032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 28931032fbfdSBengt Jonsson .constraints = { 28941032fbfdSBengt Jonsson /* "ret" means "retention" */ 28951032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 28961032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28971032fbfdSBengt Jonsson }, 28981032fbfdSBengt Jonsson }, 28991032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2900992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29011032fbfdSBengt Jonsson .constraints = { 29021032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 29031032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29041032fbfdSBengt Jonsson }, 2905624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2906624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 29071032fbfdSBengt Jonsson }, 29081032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2909992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29101032fbfdSBengt Jonsson .constraints = { 29111032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 29121032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29131032fbfdSBengt Jonsson }, 2914624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2915624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 29161032fbfdSBengt Jonsson }, 29171032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 29181032fbfdSBengt Jonsson .constraints = { 29191032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 29201032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29211032fbfdSBengt Jonsson }, 29221032fbfdSBengt Jonsson }, 29231032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2924992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29251032fbfdSBengt Jonsson .constraints = { 29261032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 29271032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29281032fbfdSBengt Jonsson }, 2929624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 2930624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 29311032fbfdSBengt Jonsson }, 29321032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 29331032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29341032fbfdSBengt Jonsson .constraints = { 29351032fbfdSBengt Jonsson .name = "db8500-sga", 29361032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29371032fbfdSBengt Jonsson }, 2938624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 2939624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2940624e87c2SBengt Jonsson 29411032fbfdSBengt Jonsson }, 29421032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 29431032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29441032fbfdSBengt Jonsson .constraints = { 29451032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 29461032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29471032fbfdSBengt Jonsson }, 29481032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 29491032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 29501032fbfdSBengt Jonsson }, 29511032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 2952992b133aSBengt Jonsson /* 2953992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off, 2954992b133aSBengt Jonsson * no need to hold Vape 2955992b133aSBengt Jonsson */ 29561032fbfdSBengt Jonsson .constraints = { 29571032fbfdSBengt Jonsson .name = "db8500-esram12", 29581032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29591032fbfdSBengt Jonsson }, 2960624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 2961624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 29621032fbfdSBengt Jonsson }, 29631032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 29641032fbfdSBengt Jonsson .constraints = { 29651032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 29661032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29671032fbfdSBengt Jonsson }, 29681032fbfdSBengt Jonsson }, 29691032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 2970992b133aSBengt Jonsson /* 2971992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off, 2972992b133aSBengt Jonsson * no need to hold Vape 2973992b133aSBengt Jonsson */ 29741032fbfdSBengt Jonsson .constraints = { 29751032fbfdSBengt Jonsson .name = "db8500-esram34", 29761032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29771032fbfdSBengt Jonsson }, 2978624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 2979624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 29801032fbfdSBengt Jonsson }, 29811032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 29821032fbfdSBengt Jonsson .constraints = { 29831032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 29841032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29851032fbfdSBengt Jonsson }, 29861032fbfdSBengt Jonsson }, 29871032fbfdSBengt Jonsson }; 29881032fbfdSBengt Jonsson 29893df57bcfSMattias Nilsson static struct mfd_cell db8500_prcmu_devs[] = { 29903df57bcfSMattias Nilsson { 29913df57bcfSMattias Nilsson .name = "db8500-prcmu-regulators", 29921ed7891fSMattias Wallin .platform_data = &db8500_regulators, 29931ed7891fSMattias Wallin .pdata_size = sizeof(db8500_regulators), 29943df57bcfSMattias Nilsson }, 29953df57bcfSMattias Nilsson { 29963df57bcfSMattias Nilsson .name = "cpufreq-u8500", 29973df57bcfSMattias Nilsson }, 29983df57bcfSMattias Nilsson }; 29993df57bcfSMattias Nilsson 30003df57bcfSMattias Nilsson /** 30013df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 30023df57bcfSMattias Nilsson * 30033df57bcfSMattias Nilsson */ 30043df57bcfSMattias Nilsson static int __init db8500_prcmu_probe(struct platform_device *pdev) 30053df57bcfSMattias Nilsson { 30063df57bcfSMattias Nilsson int err = 0; 30073df57bcfSMattias Nilsson 30083df57bcfSMattias Nilsson if (ux500_is_svp()) 30093df57bcfSMattias Nilsson return -ENODEV; 30103df57bcfSMattias Nilsson 30110508901cSMattias Nilsson init_prcm_registers(); 3012d65e12d7SMattias Nilsson 30133df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 3014c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 30153df57bcfSMattias Nilsson 30163df57bcfSMattias Nilsson err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 30173df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 30183df57bcfSMattias Nilsson if (err < 0) { 30193df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 30203df57bcfSMattias Nilsson err = -EBUSY; 30213df57bcfSMattias Nilsson goto no_irq_return; 30223df57bcfSMattias Nilsson } 30233df57bcfSMattias Nilsson 30243df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later()) 30253df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 30263df57bcfSMattias Nilsson 30273df57bcfSMattias Nilsson err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 30283df57bcfSMattias Nilsson ARRAY_SIZE(db8500_prcmu_devs), NULL, 30293df57bcfSMattias Nilsson 0); 30303df57bcfSMattias Nilsson 30313df57bcfSMattias Nilsson if (err) 30323df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 30333df57bcfSMattias Nilsson else 30343df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 30353df57bcfSMattias Nilsson 30363df57bcfSMattias Nilsson no_irq_return: 30373df57bcfSMattias Nilsson return err; 30383df57bcfSMattias Nilsson } 30393df57bcfSMattias Nilsson 30403df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 30413df57bcfSMattias Nilsson .driver = { 30423df57bcfSMattias Nilsson .name = "db8500-prcmu", 30433df57bcfSMattias Nilsson .owner = THIS_MODULE, 30443df57bcfSMattias Nilsson }, 30453df57bcfSMattias Nilsson }; 30463df57bcfSMattias Nilsson 30473df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 30483df57bcfSMattias Nilsson { 30493df57bcfSMattias Nilsson return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe); 30503df57bcfSMattias Nilsson } 30513df57bcfSMattias Nilsson 30523df57bcfSMattias Nilsson arch_initcall(db8500_prcmu_init); 30533df57bcfSMattias Nilsson 30543df57bcfSMattias Nilsson MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 30553df57bcfSMattias Nilsson MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 30563df57bcfSMattias Nilsson MODULE_LICENSE("GPL v2"); 3057