1650c2a21SLinus Walleij /* 2650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 3650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 4650c2a21SLinus Walleij * 5650c2a21SLinus Walleij * License Terms: GNU General Public License v2 6650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9650c2a21SLinus Walleij * 10650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij */ 13650c2a21SLinus Walleij #include <linux/module.h> 143df57bcfSMattias Nilsson #include <linux/kernel.h> 153df57bcfSMattias Nilsson #include <linux/delay.h> 16650c2a21SLinus Walleij #include <linux/errno.h> 17650c2a21SLinus Walleij #include <linux/err.h> 183df57bcfSMattias Nilsson #include <linux/spinlock.h> 19650c2a21SLinus Walleij #include <linux/io.h> 203df57bcfSMattias Nilsson #include <linux/slab.h> 21650c2a21SLinus Walleij #include <linux/mutex.h> 22650c2a21SLinus Walleij #include <linux/completion.h> 233df57bcfSMattias Nilsson #include <linux/irq.h> 24650c2a21SLinus Walleij #include <linux/jiffies.h> 25650c2a21SLinus Walleij #include <linux/bitops.h> 263df57bcfSMattias Nilsson #include <linux/fs.h> 273df57bcfSMattias Nilsson #include <linux/platform_device.h> 283df57bcfSMattias Nilsson #include <linux/uaccess.h> 293df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3073180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 311032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 321032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 33cc9a0f68SDaniel Lezcano #include <asm/hardware/gic.h> 34650c2a21SLinus Walleij #include <mach/hardware.h> 353df57bcfSMattias Nilsson #include <mach/irqs.h> 363df57bcfSMattias Nilsson #include <mach/db8500-regs.h> 373df57bcfSMattias Nilsson #include <mach/id.h> 3873180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 39650c2a21SLinus Walleij 403df57bcfSMattias Nilsson /* Offset for the firmware version within the TCPM */ 413df57bcfSMattias Nilsson #define PRCMU_FW_VERSION_OFFSET 0xA4 42650c2a21SLinus Walleij 433df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 443df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 453df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 463df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 473df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 483df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 493df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 503df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 513df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 523df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 533df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 543df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 553df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 563df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 573df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 58650c2a21SLinus Walleij 593df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 603df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 613df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 623df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 63650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 64650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 65650c2a21SLinus Walleij 663df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 673df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 683df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 693df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 70650c2a21SLinus Walleij 713df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 723df57bcfSMattias Nilsson 733df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 743df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 753df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 793df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 803df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 813df57bcfSMattias Nilsson 823df57bcfSMattias Nilsson /* Req Mailboxes */ 833df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 843df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 853df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 863df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 873df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 883df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 893df57bcfSMattias Nilsson 903df57bcfSMattias Nilsson /* Ack Mailboxes */ 913df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 923df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 933df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 943df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 953df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 963df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 973df57bcfSMattias Nilsson 983df57bcfSMattias Nilsson /* Mailbox 0 headers */ 993df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 1003df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 1013df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 1023df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1033df57bcfSMattias Nilsson 1043df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1053df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1063df57bcfSMattias Nilsson 1073df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1083df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1093df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1113df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1123df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1133df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1143df57bcfSMattias Nilsson 1153df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1163df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1173df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1213df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1223df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1233df57bcfSMattias Nilsson 1243df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1253df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1263df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1273df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1283df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1293df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 130a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1313df57bcfSMattias Nilsson 1323df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1333df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1343df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 135a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 1366b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1 1376b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2 138a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 139a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1403df57bcfSMattias Nilsson 1413df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1423df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1433df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1443df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1453df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1463df57bcfSMattias Nilsson 1473df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1483df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1493df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1503df57bcfSMattias Nilsson 1513df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1523df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1533df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1603df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1613df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1623df57bcfSMattias Nilsson 1633df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1643df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1653df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1663df57bcfSMattias Nilsson 1673df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1683df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1693df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1703df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1713df57bcfSMattias Nilsson 1723df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1733df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1743df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1783df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1793df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1803df57bcfSMattias Nilsson 1813df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1823df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1833df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1843df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1853df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1863df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 187a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 188a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 190a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 191a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1923df57bcfSMattias Nilsson 1933df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1943df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1953df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 2003df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 2013df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 2023df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2033df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 204a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 205a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 206a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 207a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 208a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 209a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 210a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2113df57bcfSMattias Nilsson 2123df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2133df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2143df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2153df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2163df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2173df57bcfSMattias Nilsson #define PRCMU_I2C_WRITE(slave) \ 2183df57bcfSMattias Nilsson (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2193df57bcfSMattias Nilsson #define PRCMU_I2C_READ(slave) \ 2203df57bcfSMattias Nilsson (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) 2213df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2223df57bcfSMattias Nilsson 2233df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2243df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2253df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2263df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2273df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2283df57bcfSMattias Nilsson 2293df57bcfSMattias Nilsson #define NUM_MB 8 2303df57bcfSMattias Nilsson #define MBOX_BIT BIT 2313df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2323df57bcfSMattias Nilsson 2333df57bcfSMattias Nilsson /* 2343df57bcfSMattias Nilsson * Wakeups/IRQs 2353df57bcfSMattias Nilsson */ 2363df57bcfSMattias Nilsson 2373df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2383df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2623df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2633df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2643df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2653df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2663df57bcfSMattias Nilsson 267b58d12feSMattias Nilsson static struct { 268b58d12feSMattias Nilsson bool valid; 269b58d12feSMattias Nilsson struct prcmu_fw_version version; 270b58d12feSMattias Nilsson } fw_info; 271b58d12feSMattias Nilsson 2723df57bcfSMattias Nilsson /* 2733df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2743df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2753df57bcfSMattias Nilsson * 2763df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2773df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2783df57bcfSMattias Nilsson * around, to further complicate matters.) 2793df57bcfSMattias Nilsson */ 2803df57bcfSMattias Nilsson #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) 2813df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 2823df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 2833df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 2843df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 2853df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 2863df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 2873df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 2883df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 2893df57bcfSMattias Nilsson IRQ_ENTRY(USB), 2903df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 2913df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 2923df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 2933df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 2943df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 2953df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 2963df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 2973df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 2983df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 2993df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 3003df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 3013df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 3023df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3033df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3043df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3053df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 306650c2a21SLinus Walleij }; 307650c2a21SLinus Walleij 3083df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3093df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3103df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3113df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3123df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3133df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3143df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3153df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3163df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3173df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3183df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3193df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3203df57bcfSMattias Nilsson }; 3213df57bcfSMattias Nilsson 3223df57bcfSMattias Nilsson /* 3233df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3243df57bcfSMattias Nilsson * @lock: The transaction lock. 3253df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3263df57bcfSMattias Nilsson * the request data. 3273df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3283df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3293df57bcfSMattias Nilsson */ 3303df57bcfSMattias Nilsson static struct { 3313df57bcfSMattias Nilsson spinlock_t lock; 3323df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3333df57bcfSMattias Nilsson struct work_struct mask_work; 3343df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3353df57bcfSMattias Nilsson struct completion ac_wake_work; 3363df57bcfSMattias Nilsson struct { 3373df57bcfSMattias Nilsson u32 dbb_irqs; 3383df57bcfSMattias Nilsson u32 dbb_wakeups; 3393df57bcfSMattias Nilsson u32 abb_events; 3403df57bcfSMattias Nilsson } req; 3413df57bcfSMattias Nilsson } mb0_transfer; 3423df57bcfSMattias Nilsson 3433df57bcfSMattias Nilsson /* 3443df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3453df57bcfSMattias Nilsson * @lock: The transaction lock. 3463df57bcfSMattias Nilsson * @work: The transaction completion structure. 3474d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP. 3483df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3493df57bcfSMattias Nilsson */ 350650c2a21SLinus Walleij static struct { 351650c2a21SLinus Walleij struct mutex lock; 352650c2a21SLinus Walleij struct completion work; 3534d64d2e3SMattias Nilsson u8 ape_opp; 354650c2a21SLinus Walleij struct { 3553df57bcfSMattias Nilsson u8 header; 356650c2a21SLinus Walleij u8 arm_opp; 357650c2a21SLinus Walleij u8 ape_opp; 3583df57bcfSMattias Nilsson u8 ape_voltage_status; 359650c2a21SLinus Walleij } ack; 360650c2a21SLinus Walleij } mb1_transfer; 361650c2a21SLinus Walleij 3623df57bcfSMattias Nilsson /* 3633df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3643df57bcfSMattias Nilsson * @lock: The transaction lock. 3653df57bcfSMattias Nilsson * @work: The transaction completion structure. 3663df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3673df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3683df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3693df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3703df57bcfSMattias Nilsson */ 371650c2a21SLinus Walleij static struct { 372650c2a21SLinus Walleij struct mutex lock; 373650c2a21SLinus Walleij struct completion work; 3743df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 3753df57bcfSMattias Nilsson bool auto_pm_enabled; 3763df57bcfSMattias Nilsson struct { 3773df57bcfSMattias Nilsson u8 status; 3783df57bcfSMattias Nilsson } ack; 3793df57bcfSMattias Nilsson } mb2_transfer; 3803df57bcfSMattias Nilsson 3813df57bcfSMattias Nilsson /* 3823df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 3833df57bcfSMattias Nilsson * @lock: The request lock. 3843df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 3853df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 3863df57bcfSMattias Nilsson */ 3873df57bcfSMattias Nilsson static struct { 3883df57bcfSMattias Nilsson spinlock_t lock; 3893df57bcfSMattias Nilsson struct mutex sysclk_lock; 3903df57bcfSMattias Nilsson struct completion sysclk_work; 3913df57bcfSMattias Nilsson } mb3_transfer; 3923df57bcfSMattias Nilsson 3933df57bcfSMattias Nilsson /* 3943df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 3953df57bcfSMattias Nilsson * @lock: The transaction lock. 3963df57bcfSMattias Nilsson * @work: The transaction completion structure. 3973df57bcfSMattias Nilsson */ 3983df57bcfSMattias Nilsson static struct { 3993df57bcfSMattias Nilsson struct mutex lock; 4003df57bcfSMattias Nilsson struct completion work; 4013df57bcfSMattias Nilsson } mb4_transfer; 4023df57bcfSMattias Nilsson 4033df57bcfSMattias Nilsson /* 4043df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4053df57bcfSMattias Nilsson * @lock: The transaction lock. 4063df57bcfSMattias Nilsson * @work: The transaction completion structure. 4073df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4083df57bcfSMattias Nilsson */ 4093df57bcfSMattias Nilsson static struct { 4103df57bcfSMattias Nilsson struct mutex lock; 4113df57bcfSMattias Nilsson struct completion work; 412650c2a21SLinus Walleij struct { 413650c2a21SLinus Walleij u8 status; 414650c2a21SLinus Walleij u8 value; 415650c2a21SLinus Walleij } ack; 416650c2a21SLinus Walleij } mb5_transfer; 417650c2a21SLinus Walleij 4183df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4193df57bcfSMattias Nilsson 4203df57bcfSMattias Nilsson /* Spinlocks */ 421b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock); 4223df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4233df57bcfSMattias Nilsson 4243df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4253df57bcfSMattias Nilsson static __iomem void *tcdm_base; 4263df57bcfSMattias Nilsson 4273df57bcfSMattias Nilsson struct clk_mgt { 4286b6fae2bSMattias Nilsson void __iomem *reg; 4293df57bcfSMattias Nilsson u32 pllsw; 4306b6fae2bSMattias Nilsson int branch; 4316b6fae2bSMattias Nilsson bool clk38div; 4326b6fae2bSMattias Nilsson }; 4336b6fae2bSMattias Nilsson 4346b6fae2bSMattias Nilsson enum { 4356b6fae2bSMattias Nilsson PLL_RAW, 4366b6fae2bSMattias Nilsson PLL_FIX, 4376b6fae2bSMattias Nilsson PLL_DIV 4383df57bcfSMattias Nilsson }; 4393df57bcfSMattias Nilsson 4403df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4413df57bcfSMattias Nilsson 4426b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 4436b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 4443df57bcfSMattias Nilsson struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4456b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 4466b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 4476b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 4486b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 4496b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 4506b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 4516b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 4526b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 4536b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 4546b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 4556b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 4566b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 4576b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 4586b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 4596b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 4606b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 4616b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 4626b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 4636b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 4646b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 4656b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 4666b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 4676b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 4686b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 4696b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 4706b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 4736b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 4746b6fae2bSMattias Nilsson }; 4756b6fae2bSMattias Nilsson 4766b6fae2bSMattias Nilsson struct dsiclk { 4776b6fae2bSMattias Nilsson u32 divsel_mask; 4786b6fae2bSMattias Nilsson u32 divsel_shift; 4796b6fae2bSMattias Nilsson u32 divsel; 4806b6fae2bSMattias Nilsson }; 4816b6fae2bSMattias Nilsson 4826b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = { 4836b6fae2bSMattias Nilsson { 4846b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 4856b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 4866b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4876b6fae2bSMattias Nilsson }, 4886b6fae2bSMattias Nilsson { 4896b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 4906b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 4916b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 4926b6fae2bSMattias Nilsson } 4936b6fae2bSMattias Nilsson }; 4946b6fae2bSMattias Nilsson 4956b6fae2bSMattias Nilsson struct dsiescclk { 4966b6fae2bSMattias Nilsson u32 en; 4976b6fae2bSMattias Nilsson u32 div_mask; 4986b6fae2bSMattias Nilsson u32 div_shift; 4996b6fae2bSMattias Nilsson }; 5006b6fae2bSMattias Nilsson 5016b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = { 5026b6fae2bSMattias Nilsson { 5036b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 5046b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 5056b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 5066b6fae2bSMattias Nilsson }, 5076b6fae2bSMattias Nilsson { 5086b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 5096b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 5106b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 5116b6fae2bSMattias Nilsson }, 5126b6fae2bSMattias Nilsson { 5136b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 5146b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 5156b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 5166b6fae2bSMattias Nilsson } 5173df57bcfSMattias Nilsson }; 5183df57bcfSMattias Nilsson 5193df57bcfSMattias Nilsson /* 5203df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 5213df57bcfSMattias Nilsson */ 5223df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 5233df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 5243df57bcfSMattias Nilsson 5253df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 5263df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 5273df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5283df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5293df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5303df57bcfSMattias Nilsson 5313df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5323df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5333df57bcfSMattias Nilsson 5343df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5353df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5363df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5373df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5383df57bcfSMattias Nilsson 5393df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5403df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5413df57bcfSMattias Nilsson 5423df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5433df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5443df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5453df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5463df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5473df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5483df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5493df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5503df57bcfSMattias Nilsson 5513df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5523df57bcfSMattias Nilsson 55373180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5543df57bcfSMattias Nilsson { 5553df57bcfSMattias Nilsson int i; 5563df57bcfSMattias Nilsson 5573df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 558c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5593df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 560c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5613df57bcfSMattias Nilsson 5623df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 563c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 564c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5653df57bcfSMattias Nilsson /* Enable Escape clocks */ 566c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5673df57bcfSMattias Nilsson 5683df57bcfSMattias Nilsson /* Start DSI PLL */ 569c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5703df57bcfSMattias Nilsson /* Reset DSI PLL */ 571c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 5723df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 573c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 5743df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 5753df57bcfSMattias Nilsson break; 5763df57bcfSMattias Nilsson udelay(100); 5773df57bcfSMattias Nilsson } 5783df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 579c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 5803df57bcfSMattias Nilsson return 0; 5813df57bcfSMattias Nilsson } 5823df57bcfSMattias Nilsson 58373180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 5843df57bcfSMattias Nilsson { 5853df57bcfSMattias Nilsson /* Disable dsi pll */ 586c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5873df57bcfSMattias Nilsson /* Disable escapeclock */ 588c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5893df57bcfSMattias Nilsson return 0; 5903df57bcfSMattias Nilsson } 5913df57bcfSMattias Nilsson 59273180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 5933df57bcfSMattias Nilsson { 5943df57bcfSMattias Nilsson unsigned long flags; 5953df57bcfSMattias Nilsson 5963df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 5973df57bcfSMattias Nilsson 5983df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 599c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 6003df57bcfSMattias Nilsson cpu_relax(); 6013df57bcfSMattias Nilsson 602c72fe851SDaniel Willerud writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); 603c553b3caSMattias Nilsson writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); 604c553b3caSMattias Nilsson writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); 6053df57bcfSMattias Nilsson 6063df57bcfSMattias Nilsson /* Release the HW semaphore. */ 607c553b3caSMattias Nilsson writel(0, PRCM_SEM); 6083df57bcfSMattias Nilsson 6093df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 6103df57bcfSMattias Nilsson 6113df57bcfSMattias Nilsson return 0; 6123df57bcfSMattias Nilsson } 6133df57bcfSMattias Nilsson 614b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg) 6153df57bcfSMattias Nilsson { 616b4a6dbd5SMattias Nilsson return readl(_PRCMU_BASE + reg); 6173df57bcfSMattias Nilsson } 6183df57bcfSMattias Nilsson 619b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value) 6203df57bcfSMattias Nilsson { 6213df57bcfSMattias Nilsson unsigned long flags; 6223df57bcfSMattias Nilsson 623b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 624b4a6dbd5SMattias Nilsson writel(value, (_PRCMU_BASE + reg)); 625b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 626b4a6dbd5SMattias Nilsson } 627b4a6dbd5SMattias Nilsson 628b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 629b4a6dbd5SMattias Nilsson { 630b4a6dbd5SMattias Nilsson u32 val; 631b4a6dbd5SMattias Nilsson unsigned long flags; 632b4a6dbd5SMattias Nilsson 633b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 634b4a6dbd5SMattias Nilsson val = readl(_PRCMU_BASE + reg); 635b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask)); 636b4a6dbd5SMattias Nilsson writel(val, (_PRCMU_BASE + reg)); 637b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 6383df57bcfSMattias Nilsson } 6393df57bcfSMattias Nilsson 640b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void) 641b58d12feSMattias Nilsson { 642b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL; 643b58d12feSMattias Nilsson } 644b58d12feSMattias Nilsson 6453df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6463df57bcfSMattias Nilsson { 6473df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6483df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6493df57bcfSMattias Nilsson } 6503df57bcfSMattias Nilsson 6513df57bcfSMattias Nilsson /** 6523df57bcfSMattias Nilsson * prcmu_get_boot_status - PRCMU boot status checking 6533df57bcfSMattias Nilsson * Returns: the current PRCMU boot status 6543df57bcfSMattias Nilsson */ 6553df57bcfSMattias Nilsson int prcmu_get_boot_status(void) 6563df57bcfSMattias Nilsson { 6573df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_BOOT_STATUS); 6583df57bcfSMattias Nilsson } 6593df57bcfSMattias Nilsson 6603df57bcfSMattias Nilsson /** 6613df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6623df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6633df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6643df57bcfSMattias Nilsson * 6653df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6663df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6673df57bcfSMattias Nilsson */ 6683df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6693df57bcfSMattias Nilsson { 6703df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 6713df57bcfSMattias Nilsson return -EINVAL; 6723df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 6733df57bcfSMattias Nilsson return 0; 6743df57bcfSMattias Nilsson } 6753df57bcfSMattias Nilsson 6763df57bcfSMattias Nilsson /** 6773df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 6783df57bcfSMattias Nilsson * Returns: the power transition that has last happened 6793df57bcfSMattias Nilsson * 6803df57bcfSMattias Nilsson * This function can return the following transitions- 6813df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6823df57bcfSMattias Nilsson */ 6833df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 6843df57bcfSMattias Nilsson { 6853df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 6863df57bcfSMattias Nilsson } 6873df57bcfSMattias Nilsson 6883df57bcfSMattias Nilsson /** 6893df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 6903df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 6913df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 6923df57bcfSMattias Nilsson */ 6933df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 6943df57bcfSMattias Nilsson { 6953df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 6963df57bcfSMattias Nilsson } 6973df57bcfSMattias Nilsson 6983df57bcfSMattias Nilsson /** 6993df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 7003df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 7013df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 7023df57bcfSMattias Nilsson * @div: The divider to be applied. 7033df57bcfSMattias Nilsson * 7043df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 7053df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 7063df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 7073df57bcfSMattias Nilsson */ 7083df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 7093df57bcfSMattias Nilsson { 7103df57bcfSMattias Nilsson static int requests[2]; 7113df57bcfSMattias Nilsson int r = 0; 7123df57bcfSMattias Nilsson unsigned long flags; 7133df57bcfSMattias Nilsson u32 val; 7143df57bcfSMattias Nilsson u32 bits; 7153df57bcfSMattias Nilsson u32 mask; 7163df57bcfSMattias Nilsson u32 div_mask; 7173df57bcfSMattias Nilsson 7183df57bcfSMattias Nilsson BUG_ON(clkout > 1); 7193df57bcfSMattias Nilsson BUG_ON(div > 63); 7203df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 7213df57bcfSMattias Nilsson 7223df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7233df57bcfSMattias Nilsson return -EINVAL; 7243df57bcfSMattias Nilsson 7253df57bcfSMattias Nilsson switch (clkout) { 7263df57bcfSMattias Nilsson case 0: 7273df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7283df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7293df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7303df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 7313df57bcfSMattias Nilsson break; 7323df57bcfSMattias Nilsson case 1: 7333df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7343df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7353df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7363df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7373df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7383df57bcfSMattias Nilsson break; 7393df57bcfSMattias Nilsson } 7403df57bcfSMattias Nilsson bits &= mask; 7413df57bcfSMattias Nilsson 7423df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7433df57bcfSMattias Nilsson 744c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7453df57bcfSMattias Nilsson if (val & div_mask) { 7463df57bcfSMattias Nilsson if (div) { 7473df57bcfSMattias Nilsson if ((val & mask) != bits) { 7483df57bcfSMattias Nilsson r = -EBUSY; 7493df57bcfSMattias Nilsson goto unlock_and_return; 7503df57bcfSMattias Nilsson } 7513df57bcfSMattias Nilsson } else { 7523df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7533df57bcfSMattias Nilsson r = -EINVAL; 7543df57bcfSMattias Nilsson goto unlock_and_return; 7553df57bcfSMattias Nilsson } 7563df57bcfSMattias Nilsson } 7573df57bcfSMattias Nilsson } 758c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7593df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7603df57bcfSMattias Nilsson 7613df57bcfSMattias Nilsson unlock_and_return: 7623df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7633df57bcfSMattias Nilsson 7643df57bcfSMattias Nilsson return r; 7653df57bcfSMattias Nilsson } 7663df57bcfSMattias Nilsson 76773180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7683df57bcfSMattias Nilsson { 7693df57bcfSMattias Nilsson unsigned long flags; 7703df57bcfSMattias Nilsson 7713df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 7723df57bcfSMattias Nilsson 7733df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 7743df57bcfSMattias Nilsson 775c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 7763df57bcfSMattias Nilsson cpu_relax(); 7773df57bcfSMattias Nilsson 7783df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 7793df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 7803df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 7813df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 7823df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 7833df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 784c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 7853df57bcfSMattias Nilsson 7863df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 7873df57bcfSMattias Nilsson 7883df57bcfSMattias Nilsson return 0; 7893df57bcfSMattias Nilsson } 7903df57bcfSMattias Nilsson 7914d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void) 7924d64d2e3SMattias Nilsson { 7934d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 7944d64d2e3SMattias Nilsson } 7954d64d2e3SMattias Nilsson 796485540dcSDaniel Lezcano /* This function decouple the gic from the prcmu */ 797485540dcSDaniel Lezcano int db8500_prcmu_gic_decouple(void) 798485540dcSDaniel Lezcano { 799801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 800485540dcSDaniel Lezcano 801485540dcSDaniel Lezcano /* Set bit 0 register value to 1 */ 802801448e0SDaniel Lezcano writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, 803801448e0SDaniel Lezcano PRCM_A9_MASK_REQ); 804485540dcSDaniel Lezcano 805485540dcSDaniel Lezcano /* Make sure the register is updated */ 806801448e0SDaniel Lezcano readl(PRCM_A9_MASK_REQ); 807485540dcSDaniel Lezcano 808485540dcSDaniel Lezcano /* Wait a few cycles for the gic mask completion */ 809801448e0SDaniel Lezcano udelay(1); 810485540dcSDaniel Lezcano 811485540dcSDaniel Lezcano return 0; 812485540dcSDaniel Lezcano } 813485540dcSDaniel Lezcano 814485540dcSDaniel Lezcano /* This function recouple the gic with the prcmu */ 815485540dcSDaniel Lezcano int db8500_prcmu_gic_recouple(void) 816485540dcSDaniel Lezcano { 817801448e0SDaniel Lezcano u32 val = readl(PRCM_A9_MASK_REQ); 818485540dcSDaniel Lezcano 819485540dcSDaniel Lezcano /* Set bit 0 register value to 0 */ 820801448e0SDaniel Lezcano writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); 821485540dcSDaniel Lezcano 822485540dcSDaniel Lezcano return 0; 823485540dcSDaniel Lezcano } 824485540dcSDaniel Lezcano 825cc9a0f68SDaniel Lezcano #define PRCMU_GIC_NUMBER_REGS 5 826cc9a0f68SDaniel Lezcano 827cc9a0f68SDaniel Lezcano /* 828cc9a0f68SDaniel Lezcano * This function checks if there are pending irq on the gic. It only 829cc9a0f68SDaniel Lezcano * makes sense if the gic has been decoupled before with the 830cc9a0f68SDaniel Lezcano * db8500_prcmu_gic_decouple function. Disabling an interrupt only 831cc9a0f68SDaniel Lezcano * disables the forwarding of the interrupt to any CPU interface. It 832cc9a0f68SDaniel Lezcano * does not prevent the interrupt from changing state, for example 833cc9a0f68SDaniel Lezcano * becoming pending, or active and pending if it is already 834cc9a0f68SDaniel Lezcano * active. Hence, we have to check the interrupt is pending *and* is 835cc9a0f68SDaniel Lezcano * active. 836cc9a0f68SDaniel Lezcano */ 837cc9a0f68SDaniel Lezcano bool db8500_prcmu_gic_pending_irq(void) 838cc9a0f68SDaniel Lezcano { 839cc9a0f68SDaniel Lezcano u32 pr; /* Pending register */ 840cc9a0f68SDaniel Lezcano u32 er; /* Enable register */ 841cc9a0f68SDaniel Lezcano void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 842cc9a0f68SDaniel Lezcano int i; 843cc9a0f68SDaniel Lezcano 844cc9a0f68SDaniel Lezcano /* 5 registers. STI & PPI not skipped */ 845cc9a0f68SDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { 846cc9a0f68SDaniel Lezcano 847cc9a0f68SDaniel Lezcano pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); 848cc9a0f68SDaniel Lezcano er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 849cc9a0f68SDaniel Lezcano 850cc9a0f68SDaniel Lezcano if (pr & er) 851cc9a0f68SDaniel Lezcano return true; /* There is a pending interrupt */ 852cc9a0f68SDaniel Lezcano } 853cc9a0f68SDaniel Lezcano 854cc9a0f68SDaniel Lezcano return false; 855cc9a0f68SDaniel Lezcano } 856cc9a0f68SDaniel Lezcano 8579f60d33eSDaniel Lezcano /* 8589ab492e1SDaniel Lezcano * This function checks if there are pending interrupt on the 8599ab492e1SDaniel Lezcano * prcmu which has been delegated to monitor the irqs with the 8609ab492e1SDaniel Lezcano * db8500_prcmu_copy_gic_settings function. 8619ab492e1SDaniel Lezcano */ 8629ab492e1SDaniel Lezcano bool db8500_prcmu_pending_irq(void) 8639ab492e1SDaniel Lezcano { 8649ab492e1SDaniel Lezcano u32 it, im; 8659ab492e1SDaniel Lezcano int i; 8669ab492e1SDaniel Lezcano 8679ab492e1SDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 8689ab492e1SDaniel Lezcano it = readl(PRCM_ARMITVAL31TO0 + i * 4); 8699ab492e1SDaniel Lezcano im = readl(PRCM_ARMITMSK31TO0 + i * 4); 8709ab492e1SDaniel Lezcano if (it & im) 8719ab492e1SDaniel Lezcano return true; /* There is a pending interrupt */ 8729ab492e1SDaniel Lezcano } 8739ab492e1SDaniel Lezcano 8749ab492e1SDaniel Lezcano return false; 8759ab492e1SDaniel Lezcano } 8769ab492e1SDaniel Lezcano 8779ab492e1SDaniel Lezcano /* 87834fe6f10SDaniel Lezcano * This function checks if the specified cpu is in in WFI. It's usage 87934fe6f10SDaniel Lezcano * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple 88034fe6f10SDaniel Lezcano * function. Of course passing smp_processor_id() to this function will 88134fe6f10SDaniel Lezcano * always return false... 88234fe6f10SDaniel Lezcano */ 88334fe6f10SDaniel Lezcano bool db8500_prcmu_is_cpu_in_wfi(int cpu) 88434fe6f10SDaniel Lezcano { 88534fe6f10SDaniel Lezcano return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : 88634fe6f10SDaniel Lezcano PRCM_ARM_WFI_STANDBY_WFI0; 88734fe6f10SDaniel Lezcano } 88834fe6f10SDaniel Lezcano 88934fe6f10SDaniel Lezcano /* 8909f60d33eSDaniel Lezcano * This function copies the gic SPI settings to the prcmu in order to 8919f60d33eSDaniel Lezcano * monitor them and abort/finish the retention/off sequence or state. 8929f60d33eSDaniel Lezcano */ 8939f60d33eSDaniel Lezcano int db8500_prcmu_copy_gic_settings(void) 8949f60d33eSDaniel Lezcano { 8959f60d33eSDaniel Lezcano u32 er; /* Enable register */ 8969f60d33eSDaniel Lezcano void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 8979f60d33eSDaniel Lezcano int i; 8989f60d33eSDaniel Lezcano 8999f60d33eSDaniel Lezcano /* We skip the STI and PPI */ 9009f60d33eSDaniel Lezcano for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 9019f60d33eSDaniel Lezcano er = readl_relaxed(dist_base + 9029f60d33eSDaniel Lezcano GIC_DIST_ENABLE_SET + (i + 1) * 4); 9039f60d33eSDaniel Lezcano writel(er, PRCM_ARMITMSK31TO0 + i * 4); 9049f60d33eSDaniel Lezcano } 9059f60d33eSDaniel Lezcano 9069f60d33eSDaniel Lezcano return 0; 9079f60d33eSDaniel Lezcano } 9089f60d33eSDaniel Lezcano 9093df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 9103df57bcfSMattias Nilsson static void config_wakeups(void) 9113df57bcfSMattias Nilsson { 9123df57bcfSMattias Nilsson const u8 header[2] = { 9133df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 9143df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 9153df57bcfSMattias Nilsson }; 9163df57bcfSMattias Nilsson static u32 last_dbb_events; 9173df57bcfSMattias Nilsson static u32 last_abb_events; 9183df57bcfSMattias Nilsson u32 dbb_events; 9193df57bcfSMattias Nilsson u32 abb_events; 9203df57bcfSMattias Nilsson unsigned int i; 9213df57bcfSMattias Nilsson 9223df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 9233df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 9243df57bcfSMattias Nilsson 9253df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 9263df57bcfSMattias Nilsson 9273df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 9283df57bcfSMattias Nilsson return; 9293df57bcfSMattias Nilsson 9303df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 931c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 9323df57bcfSMattias Nilsson cpu_relax(); 9333df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 9343df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 9353df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 936c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 9373df57bcfSMattias Nilsson } 9383df57bcfSMattias Nilsson last_dbb_events = dbb_events; 9393df57bcfSMattias Nilsson last_abb_events = abb_events; 9403df57bcfSMattias Nilsson } 9413df57bcfSMattias Nilsson 94273180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 9433df57bcfSMattias Nilsson { 9443df57bcfSMattias Nilsson unsigned long flags; 9453df57bcfSMattias Nilsson u32 bits; 9463df57bcfSMattias Nilsson int i; 9473df57bcfSMattias Nilsson 9483df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 9493df57bcfSMattias Nilsson 9503df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 9513df57bcfSMattias Nilsson if (wakeups & BIT(i)) 9523df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 9533df57bcfSMattias Nilsson } 9543df57bcfSMattias Nilsson 9553df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9563df57bcfSMattias Nilsson 9573df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 9583df57bcfSMattias Nilsson config_wakeups(); 9593df57bcfSMattias Nilsson 9603df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9613df57bcfSMattias Nilsson } 9623df57bcfSMattias Nilsson 96373180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 9643df57bcfSMattias Nilsson { 9653df57bcfSMattias Nilsson unsigned long flags; 9663df57bcfSMattias Nilsson 9673df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 9683df57bcfSMattias Nilsson 9693df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 9703df57bcfSMattias Nilsson config_wakeups(); 9713df57bcfSMattias Nilsson 9723df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 9733df57bcfSMattias Nilsson } 9743df57bcfSMattias Nilsson 97573180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 9763df57bcfSMattias Nilsson { 9773df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 9783df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 9793df57bcfSMattias Nilsson else 9803df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 9813df57bcfSMattias Nilsson } 9823df57bcfSMattias Nilsson 9833df57bcfSMattias Nilsson /** 98473180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 9853df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 9863df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9873df57bcfSMattias Nilsson * 9883df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 9893df57bcfSMattias Nilsson */ 99073180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 9913df57bcfSMattias Nilsson { 9923df57bcfSMattias Nilsson int r; 9933df57bcfSMattias Nilsson 9943df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 9953df57bcfSMattias Nilsson return -EINVAL; 9963df57bcfSMattias Nilsson 9973df57bcfSMattias Nilsson r = 0; 9983df57bcfSMattias Nilsson 9993df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10003df57bcfSMattias Nilsson 1001c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10023df57bcfSMattias Nilsson cpu_relax(); 10033df57bcfSMattias Nilsson 10043df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10053df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 10063df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 10073df57bcfSMattias Nilsson 1008c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10093df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10103df57bcfSMattias Nilsson 10113df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 10123df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 10133df57bcfSMattias Nilsson r = -EIO; 10143df57bcfSMattias Nilsson 10153df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10163df57bcfSMattias Nilsson 10173df57bcfSMattias Nilsson return r; 10183df57bcfSMattias Nilsson } 10193df57bcfSMattias Nilsson 10203df57bcfSMattias Nilsson /** 102173180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 10223df57bcfSMattias Nilsson * 10233df57bcfSMattias Nilsson * Returns: the current ARM OPP 10243df57bcfSMattias Nilsson */ 102573180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 10263df57bcfSMattias Nilsson { 10273df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 10283df57bcfSMattias Nilsson } 10293df57bcfSMattias Nilsson 10303df57bcfSMattias Nilsson /** 10310508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP 10323df57bcfSMattias Nilsson * 10333df57bcfSMattias Nilsson * Returns: the current DDR OPP 10343df57bcfSMattias Nilsson */ 10350508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void) 10363df57bcfSMattias Nilsson { 1037c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 10383df57bcfSMattias Nilsson } 10393df57bcfSMattias Nilsson 10403df57bcfSMattias Nilsson /** 10410508901cSMattias Nilsson * db8500_set_ddr_opp - set the appropriate DDR OPP 10423df57bcfSMattias Nilsson * @opp: The new DDR operating point to which transition is to be made 10433df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10443df57bcfSMattias Nilsson * 10453df57bcfSMattias Nilsson * This function sets the operating point of the DDR. 10463df57bcfSMattias Nilsson */ 10470508901cSMattias Nilsson int db8500_prcmu_set_ddr_opp(u8 opp) 10483df57bcfSMattias Nilsson { 10493df57bcfSMattias Nilsson if (opp < DDR_100_OPP || opp > DDR_25_OPP) 10503df57bcfSMattias Nilsson return -EINVAL; 10513df57bcfSMattias Nilsson /* Changing the DDR OPP can hang the hardware pre-v21 */ 10523df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) 1053c553b3caSMattias Nilsson writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 10543df57bcfSMattias Nilsson 10553df57bcfSMattias Nilsson return 0; 10563df57bcfSMattias Nilsson } 10576b6fae2bSMattias Nilsson 10584d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 10594d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable) 10604d64d2e3SMattias Nilsson { 10614d64d2e3SMattias Nilsson void __iomem *clock_reg[] = { 10624d64d2e3SMattias Nilsson PRCM_ACLK_MGT, 10634d64d2e3SMattias Nilsson PRCM_DMACLK_MGT 10644d64d2e3SMattias Nilsson }; 10654d64d2e3SMattias Nilsson unsigned long flags; 10664d64d2e3SMattias Nilsson unsigned int i; 10674d64d2e3SMattias Nilsson 10684d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 10694d64d2e3SMattias Nilsson 10704d64d2e3SMattias Nilsson /* Grab the HW semaphore. */ 10714d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 10724d64d2e3SMattias Nilsson cpu_relax(); 10734d64d2e3SMattias Nilsson 10744d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 10754d64d2e3SMattias Nilsson u32 val; 10764d64d2e3SMattias Nilsson u32 div; 10774d64d2e3SMattias Nilsson 10784d64d2e3SMattias Nilsson val = readl(clock_reg[i]); 10794d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 10804d64d2e3SMattias Nilsson if (enable) { 10814d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) { 10824d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n", 10834d64d2e3SMattias Nilsson div, __func__); 10844d64d2e3SMattias Nilsson goto unlock_and_return; 10854d64d2e3SMattias Nilsson } 10864d64d2e3SMattias Nilsson div <<= 1; 10874d64d2e3SMattias Nilsson } else { 10884d64d2e3SMattias Nilsson if (div <= 2) 10894d64d2e3SMattias Nilsson goto unlock_and_return; 10904d64d2e3SMattias Nilsson div >>= 1; 10914d64d2e3SMattias Nilsson } 10924d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 10934d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 10944d64d2e3SMattias Nilsson writel(val, clock_reg[i]); 10954d64d2e3SMattias Nilsson } 10964d64d2e3SMattias Nilsson 10974d64d2e3SMattias Nilsson unlock_and_return: 10984d64d2e3SMattias Nilsson /* Release the HW semaphore. */ 10994d64d2e3SMattias Nilsson writel(0, PRCM_SEM); 11004d64d2e3SMattias Nilsson 11014d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 11024d64d2e3SMattias Nilsson } 11034d64d2e3SMattias Nilsson 11043df57bcfSMattias Nilsson /** 11050508901cSMattias Nilsson * db8500_set_ape_opp - set the appropriate APE OPP 11063df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 11073df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 11083df57bcfSMattias Nilsson * 11093df57bcfSMattias Nilsson * This function sets the operating point of the APE. 11103df57bcfSMattias Nilsson */ 11110508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp) 11123df57bcfSMattias Nilsson { 11133df57bcfSMattias Nilsson int r = 0; 11143df57bcfSMattias Nilsson 11154d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp) 11164d64d2e3SMattias Nilsson return 0; 11174d64d2e3SMattias Nilsson 11183df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11193df57bcfSMattias Nilsson 11204d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 11214d64d2e3SMattias Nilsson request_even_slower_clocks(false); 11224d64d2e3SMattias Nilsson 11234d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 11244d64d2e3SMattias Nilsson goto skip_message; 11254d64d2e3SMattias Nilsson 1126c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11273df57bcfSMattias Nilsson cpu_relax(); 11283df57bcfSMattias Nilsson 11293df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11303df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 11314d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 11324d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 11333df57bcfSMattias Nilsson 1134c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11353df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11363df57bcfSMattias Nilsson 11373df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 11383df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 11393df57bcfSMattias Nilsson r = -EIO; 11403df57bcfSMattias Nilsson 11414d64d2e3SMattias Nilsson skip_message: 11424d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 11434d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 11444d64d2e3SMattias Nilsson request_even_slower_clocks(true); 11454d64d2e3SMattias Nilsson if (!r) 11464d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp; 11474d64d2e3SMattias Nilsson 11483df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11493df57bcfSMattias Nilsson 11503df57bcfSMattias Nilsson return r; 11513df57bcfSMattias Nilsson } 11523df57bcfSMattias Nilsson 11533df57bcfSMattias Nilsson /** 11540508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP 11553df57bcfSMattias Nilsson * 11563df57bcfSMattias Nilsson * Returns: the current APE OPP 11573df57bcfSMattias Nilsson */ 11580508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void) 11593df57bcfSMattias Nilsson { 11603df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 11613df57bcfSMattias Nilsson } 11623df57bcfSMattias Nilsson 11633df57bcfSMattias Nilsson /** 11643df57bcfSMattias Nilsson * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 11653df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 11663df57bcfSMattias Nilsson * 11673df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 11683df57bcfSMattias Nilsson */ 11693df57bcfSMattias Nilsson int prcmu_request_ape_opp_100_voltage(bool enable) 11703df57bcfSMattias Nilsson { 11713df57bcfSMattias Nilsson int r = 0; 11723df57bcfSMattias Nilsson u8 header; 11733df57bcfSMattias Nilsson static unsigned int requests; 11743df57bcfSMattias Nilsson 11753df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11763df57bcfSMattias Nilsson 11773df57bcfSMattias Nilsson if (enable) { 11783df57bcfSMattias Nilsson if (0 != requests++) 11793df57bcfSMattias Nilsson goto unlock_and_return; 11803df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 11813df57bcfSMattias Nilsson } else { 11823df57bcfSMattias Nilsson if (requests == 0) { 11833df57bcfSMattias Nilsson r = -EIO; 11843df57bcfSMattias Nilsson goto unlock_and_return; 11853df57bcfSMattias Nilsson } else if (1 != requests--) { 11863df57bcfSMattias Nilsson goto unlock_and_return; 11873df57bcfSMattias Nilsson } 11883df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 11893df57bcfSMattias Nilsson } 11903df57bcfSMattias Nilsson 1191c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11923df57bcfSMattias Nilsson cpu_relax(); 11933df57bcfSMattias Nilsson 11943df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11953df57bcfSMattias Nilsson 1196c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11973df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11983df57bcfSMattias Nilsson 11993df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 12003df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 12013df57bcfSMattias Nilsson r = -EIO; 12023df57bcfSMattias Nilsson 12033df57bcfSMattias Nilsson unlock_and_return: 12043df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12053df57bcfSMattias Nilsson 12063df57bcfSMattias Nilsson return r; 12073df57bcfSMattias Nilsson } 12083df57bcfSMattias Nilsson 12093df57bcfSMattias Nilsson /** 12103df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 12113df57bcfSMattias Nilsson * 12123df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 12133df57bcfSMattias Nilsson */ 12143df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 12153df57bcfSMattias Nilsson { 12163df57bcfSMattias Nilsson int r = 0; 12173df57bcfSMattias Nilsson 12183df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 12193df57bcfSMattias Nilsson 1220c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 12213df57bcfSMattias Nilsson cpu_relax(); 12223df57bcfSMattias Nilsson 12233df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 12243df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12253df57bcfSMattias Nilsson 1226c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12273df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 12283df57bcfSMattias Nilsson 12293df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 12303df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 12313df57bcfSMattias Nilsson r = -EIO; 12323df57bcfSMattias Nilsson 12333df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12343df57bcfSMattias Nilsson 12353df57bcfSMattias Nilsson return r; 12363df57bcfSMattias Nilsson } 12373df57bcfSMattias Nilsson 12380837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 12390837bb72SMattias Nilsson { 12400837bb72SMattias Nilsson int r = 0; 12410837bb72SMattias Nilsson 12426b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0) 12436b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 12446b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 12450837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 12460837bb72SMattias Nilsson else 12470837bb72SMattias Nilsson return -EINVAL; 12480837bb72SMattias Nilsson 12490837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 12500837bb72SMattias Nilsson 12510837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 12520837bb72SMattias Nilsson cpu_relax(); 12530837bb72SMattias Nilsson 12540837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 12550837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 12560837bb72SMattias Nilsson 12570837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 12580837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 12590837bb72SMattias Nilsson 12600837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 12610837bb72SMattias Nilsson r = -EIO; 12620837bb72SMattias Nilsson 12630837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 12640837bb72SMattias Nilsson 12650837bb72SMattias Nilsson return r; 12660837bb72SMattias Nilsson } 12670837bb72SMattias Nilsson 12683df57bcfSMattias Nilsson /** 126973180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 12703df57bcfSMattias Nilsson * @epod_id: The EPOD to set 12713df57bcfSMattias Nilsson * @epod_state: The new EPOD state 12723df57bcfSMattias Nilsson * 12733df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 12743df57bcfSMattias Nilsson * from interrupt context. 12753df57bcfSMattias Nilsson */ 127673180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 12773df57bcfSMattias Nilsson { 12783df57bcfSMattias Nilsson int r = 0; 12793df57bcfSMattias Nilsson bool ram_retention = false; 12803df57bcfSMattias Nilsson int i; 12813df57bcfSMattias Nilsson 12823df57bcfSMattias Nilsson /* check argument */ 12833df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 12843df57bcfSMattias Nilsson 12853df57bcfSMattias Nilsson /* set flag if retention is possible */ 12863df57bcfSMattias Nilsson switch (epod_id) { 12873df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 12883df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 12893df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 12903df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 12913df57bcfSMattias Nilsson ram_retention = true; 12923df57bcfSMattias Nilsson break; 12933df57bcfSMattias Nilsson } 12943df57bcfSMattias Nilsson 12953df57bcfSMattias Nilsson /* check argument */ 12963df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 12973df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 12983df57bcfSMattias Nilsson 12993df57bcfSMattias Nilsson /* get lock */ 13003df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 13013df57bcfSMattias Nilsson 13023df57bcfSMattias Nilsson /* wait for mailbox */ 1303c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 13043df57bcfSMattias Nilsson cpu_relax(); 13053df57bcfSMattias Nilsson 13063df57bcfSMattias Nilsson /* fill in mailbox */ 13073df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 13083df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 13093df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 13103df57bcfSMattias Nilsson 13113df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 13123df57bcfSMattias Nilsson 1313c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 13143df57bcfSMattias Nilsson 13153df57bcfSMattias Nilsson /* 13163df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 13173df57bcfSMattias Nilsson * and we cannot recover if there is an error. 13183df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 13193df57bcfSMattias Nilsson */ 13203df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 13213df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 13223df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 13233df57bcfSMattias Nilsson __func__); 13243df57bcfSMattias Nilsson r = -EIO; 13253df57bcfSMattias Nilsson goto unlock_and_return; 13263df57bcfSMattias Nilsson } 13273df57bcfSMattias Nilsson 13283df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 13293df57bcfSMattias Nilsson r = -EIO; 13303df57bcfSMattias Nilsson 13313df57bcfSMattias Nilsson unlock_and_return: 13323df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 13333df57bcfSMattias Nilsson return r; 13343df57bcfSMattias Nilsson } 13353df57bcfSMattias Nilsson 13363df57bcfSMattias Nilsson /** 13373df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 13383df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 13393df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 13403df57bcfSMattias Nilsson */ 13413df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 13423df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 13433df57bcfSMattias Nilsson { 13443df57bcfSMattias Nilsson u32 sleep_cfg; 13453df57bcfSMattias Nilsson u32 idle_cfg; 13463df57bcfSMattias Nilsson unsigned long flags; 13473df57bcfSMattias Nilsson 13483df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 13493df57bcfSMattias Nilsson 13503df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 13513df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 13523df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 13533df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 13543df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 13553df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 13563df57bcfSMattias Nilsson 13573df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 13583df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 13593df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 13603df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 13613df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 13623df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 13633df57bcfSMattias Nilsson 13643df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 13653df57bcfSMattias Nilsson 13663df57bcfSMattias Nilsson /* 13673df57bcfSMattias Nilsson * The autonomous power management configuration is done through 13683df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 13693df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 13703df57bcfSMattias Nilsson */ 13713df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 13723df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 13733df57bcfSMattias Nilsson 13743df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 13753df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 13763df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 13773df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 13783df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 13793df57bcfSMattias Nilsson 13803df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 13813df57bcfSMattias Nilsson } 13823df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 13833df57bcfSMattias Nilsson 13843df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 13853df57bcfSMattias Nilsson { 13863df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 13873df57bcfSMattias Nilsson } 13883df57bcfSMattias Nilsson 13893df57bcfSMattias Nilsson static int request_sysclk(bool enable) 13903df57bcfSMattias Nilsson { 13913df57bcfSMattias Nilsson int r; 13923df57bcfSMattias Nilsson unsigned long flags; 13933df57bcfSMattias Nilsson 13943df57bcfSMattias Nilsson r = 0; 13953df57bcfSMattias Nilsson 13963df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 13973df57bcfSMattias Nilsson 13983df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 13993df57bcfSMattias Nilsson 1400c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 14013df57bcfSMattias Nilsson cpu_relax(); 14023df57bcfSMattias Nilsson 14033df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 14043df57bcfSMattias Nilsson 14053df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1406c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 14073df57bcfSMattias Nilsson 14083df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 14093df57bcfSMattias Nilsson 14103df57bcfSMattias Nilsson /* 14113df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 14123df57bcfSMattias Nilsson * SysClk, and it succeeds. 14133df57bcfSMattias Nilsson */ 14143df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 14153df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 14163df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 14173df57bcfSMattias Nilsson __func__); 14183df57bcfSMattias Nilsson r = -EIO; 14193df57bcfSMattias Nilsson } 14203df57bcfSMattias Nilsson 14213df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 14223df57bcfSMattias Nilsson 14233df57bcfSMattias Nilsson return r; 14243df57bcfSMattias Nilsson } 14253df57bcfSMattias Nilsson 14263df57bcfSMattias Nilsson static int request_timclk(bool enable) 14273df57bcfSMattias Nilsson { 14283df57bcfSMattias Nilsson u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 14293df57bcfSMattias Nilsson 14303df57bcfSMattias Nilsson if (!enable) 14313df57bcfSMattias Nilsson val |= PRCM_TCR_STOP_TIMERS; 1432c553b3caSMattias Nilsson writel(val, PRCM_TCR); 14333df57bcfSMattias Nilsson 14343df57bcfSMattias Nilsson return 0; 14353df57bcfSMattias Nilsson } 14363df57bcfSMattias Nilsson 14376b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable) 14383df57bcfSMattias Nilsson { 14393df57bcfSMattias Nilsson u32 val; 14403df57bcfSMattias Nilsson unsigned long flags; 14413df57bcfSMattias Nilsson 14423df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 14433df57bcfSMattias Nilsson 14443df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1445c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 14463df57bcfSMattias Nilsson cpu_relax(); 14473df57bcfSMattias Nilsson 14486b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 14493df57bcfSMattias Nilsson if (enable) { 14503df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 14513df57bcfSMattias Nilsson } else { 14523df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 14533df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 14543df57bcfSMattias Nilsson } 14556b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 14563df57bcfSMattias Nilsson 14573df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1458c553b3caSMattias Nilsson writel(0, PRCM_SEM); 14593df57bcfSMattias Nilsson 14603df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 14613df57bcfSMattias Nilsson 14623df57bcfSMattias Nilsson return 0; 14633df57bcfSMattias Nilsson } 14643df57bcfSMattias Nilsson 14650837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 14660837bb72SMattias Nilsson { 14670837bb72SMattias Nilsson u32 val; 14680837bb72SMattias Nilsson int ret; 14690837bb72SMattias Nilsson 14700837bb72SMattias Nilsson if (enable) { 14710837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 14720837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 14730837bb72SMattias Nilsson } 14740837bb72SMattias Nilsson 14756b6fae2bSMattias Nilsson ret = request_clock(clock, enable); 14760837bb72SMattias Nilsson 14770837bb72SMattias Nilsson if (!ret && !enable) { 14780837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 14790837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 14800837bb72SMattias Nilsson } 14810837bb72SMattias Nilsson 14820837bb72SMattias Nilsson return ret; 14830837bb72SMattias Nilsson } 14840837bb72SMattias Nilsson 14856b6fae2bSMattias Nilsson static inline bool plldsi_locked(void) 14866b6fae2bSMattias Nilsson { 14876b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) & 14886b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 14896b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 14906b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 14916b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 14926b6fae2bSMattias Nilsson } 14936b6fae2bSMattias Nilsson 14946b6fae2bSMattias Nilsson static int request_plldsi(bool enable) 14956b6fae2bSMattias Nilsson { 14966b6fae2bSMattias Nilsson int r = 0; 14976b6fae2bSMattias Nilsson u32 val; 14986b6fae2bSMattias Nilsson 14996b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 15006b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 15016b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 15026b6fae2bSMattias Nilsson 15036b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE); 15046b6fae2bSMattias Nilsson if (enable) 15056b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15066b6fae2bSMattias Nilsson else 15076b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15086b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 15096b6fae2bSMattias Nilsson 15106b6fae2bSMattias Nilsson if (enable) { 15116b6fae2bSMattias Nilsson unsigned int i; 15126b6fae2bSMattias Nilsson bool locked = plldsi_locked(); 15136b6fae2bSMattias Nilsson 15146b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) { 15156b6fae2bSMattias Nilsson udelay(100); 15166b6fae2bSMattias Nilsson locked = plldsi_locked(); 15176b6fae2bSMattias Nilsson } 15186b6fae2bSMattias Nilsson if (locked) { 15196b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, 15206b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET); 15216b6fae2bSMattias Nilsson } else { 15226b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 15236b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 15246b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET); 15256b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 15266b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 15276b6fae2bSMattias Nilsson r = -EAGAIN; 15286b6fae2bSMattias Nilsson } 15296b6fae2bSMattias Nilsson } else { 15306b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 15316b6fae2bSMattias Nilsson } 15326b6fae2bSMattias Nilsson return r; 15336b6fae2bSMattias Nilsson } 15346b6fae2bSMattias Nilsson 15356b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable) 15366b6fae2bSMattias Nilsson { 15376b6fae2bSMattias Nilsson u32 val; 15386b6fae2bSMattias Nilsson 15396b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 15406b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 15416b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 15426b6fae2bSMattias Nilsson dsiclk[n].divsel_shift); 15436b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 15446b6fae2bSMattias Nilsson return 0; 15456b6fae2bSMattias Nilsson } 15466b6fae2bSMattias Nilsson 15476b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable) 15486b6fae2bSMattias Nilsson { 15496b6fae2bSMattias Nilsson u32 val; 15506b6fae2bSMattias Nilsson 15516b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 15526b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 15536b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 15546b6fae2bSMattias Nilsson return 0; 15556b6fae2bSMattias Nilsson } 15566b6fae2bSMattias Nilsson 15573df57bcfSMattias Nilsson /** 155873180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 15593df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 15603df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 15613df57bcfSMattias Nilsson * 15623df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 15633df57bcfSMattias Nilsson * Do not use it from any other place! 15643df57bcfSMattias Nilsson */ 156573180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 15663df57bcfSMattias Nilsson { 15676b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK) 15680837bb72SMattias Nilsson return request_sga_clock(clock, enable); 15696b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS) 15706b6fae2bSMattias Nilsson return request_clock(clock, enable); 15716b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 15723df57bcfSMattias Nilsson return request_timclk(enable); 15736b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 15746b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 15756b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 15766b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 15776b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 15786b6fae2bSMattias Nilsson return request_plldsi(enable); 15796b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 15803df57bcfSMattias Nilsson return request_sysclk(enable); 15816b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 15820837bb72SMattias Nilsson return request_pll(clock, enable); 15836b6fae2bSMattias Nilsson else 15846b6fae2bSMattias Nilsson return -EINVAL; 15856b6fae2bSMattias Nilsson } 15866b6fae2bSMattias Nilsson 15876b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 15886b6fae2bSMattias Nilsson int branch) 15896b6fae2bSMattias Nilsson { 15906b6fae2bSMattias Nilsson u64 rate; 15916b6fae2bSMattias Nilsson u32 val; 15926b6fae2bSMattias Nilsson u32 d; 15936b6fae2bSMattias Nilsson u32 div = 1; 15946b6fae2bSMattias Nilsson 15956b6fae2bSMattias Nilsson val = readl(reg); 15966b6fae2bSMattias Nilsson 15976b6fae2bSMattias Nilsson rate = src_rate; 15986b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 15996b6fae2bSMattias Nilsson 16006b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 16016b6fae2bSMattias Nilsson if (d > 1) 16026b6fae2bSMattias Nilsson div *= d; 16036b6fae2bSMattias Nilsson 16046b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 16056b6fae2bSMattias Nilsson if (d > 1) 16066b6fae2bSMattias Nilsson div *= d; 16076b6fae2bSMattias Nilsson 16086b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2) 16096b6fae2bSMattias Nilsson div *= 2; 16106b6fae2bSMattias Nilsson 16116b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 16126b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) && 16136b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) || 16146b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ)))) 16156b6fae2bSMattias Nilsson div *= 2; 16166b6fae2bSMattias Nilsson 16176b6fae2bSMattias Nilsson (void)do_div(rate, div); 16186b6fae2bSMattias Nilsson 16196b6fae2bSMattias Nilsson return (unsigned long)rate; 16206b6fae2bSMattias Nilsson } 16216b6fae2bSMattias Nilsson 16226b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000 16236b6fae2bSMattias Nilsson 16246b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock) 16256b6fae2bSMattias Nilsson { 16266b6fae2bSMattias Nilsson u32 val; 16276b6fae2bSMattias Nilsson u32 pllsw; 16286b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE; 16296b6fae2bSMattias Nilsson 16306b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 16316b6fae2bSMattias Nilsson 16326b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 16336b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 16346b6fae2bSMattias Nilsson rate /= 2; 16356b6fae2bSMattias Nilsson return rate; 16366b6fae2bSMattias Nilsson } 16376b6fae2bSMattias Nilsson 16386b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw; 16396b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 16406b6fae2bSMattias Nilsson 16416b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 16426b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 16436b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 16446b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 16456b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 16466b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 16476b6fae2bSMattias Nilsson else 16486b6fae2bSMattias Nilsson return 0; 16496b6fae2bSMattias Nilsson 16506b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) && 16516b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 16526b6fae2bSMattias Nilsson u64 r = (rate * 10); 16536b6fae2bSMattias Nilsson 16546b6fae2bSMattias Nilsson (void)do_div(r, 25); 16556b6fae2bSMattias Nilsson return (unsigned long)r; 16566b6fae2bSMattias Nilsson } 16576b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 16586b6fae2bSMattias Nilsson if (val) 16596b6fae2bSMattias Nilsson return rate / val; 16606b6fae2bSMattias Nilsson else 16616b6fae2bSMattias Nilsson return 0; 16626b6fae2bSMattias Nilsson } 16636b6fae2bSMattias Nilsson 16646b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n) 16656b6fae2bSMattias Nilsson { 16666b6fae2bSMattias Nilsson u32 divsel; 16676b6fae2bSMattias Nilsson u32 div = 1; 16686b6fae2bSMattias Nilsson 16696b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL); 16706b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 16716b6fae2bSMattias Nilsson 16726b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 16736b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel; 16746b6fae2bSMattias Nilsson 16756b6fae2bSMattias Nilsson switch (divsel) { 16766b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4: 16776b6fae2bSMattias Nilsson div *= 2; 16786b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2: 16796b6fae2bSMattias Nilsson div *= 2; 16806b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI: 16816b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 16826b6fae2bSMattias Nilsson PLL_RAW) / div; 1683e62ccf3aSLinus Walleij default: 16846b6fae2bSMattias Nilsson return 0; 16856b6fae2bSMattias Nilsson } 16866b6fae2bSMattias Nilsson } 16876b6fae2bSMattias Nilsson 16886b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n) 16896b6fae2bSMattias Nilsson { 16906b6fae2bSMattias Nilsson u32 div; 16916b6fae2bSMattias Nilsson 16926b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV); 16936b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 16946b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 16956b6fae2bSMattias Nilsson } 16966b6fae2bSMattias Nilsson 16976b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock) 16986b6fae2bSMattias Nilsson { 16996b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 17006b6fae2bSMattias Nilsson return clock_rate(clock); 17016b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 17026b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE / 16; 17036b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 17046b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 17056b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0) 17066b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17076b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 17086b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17096b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR) 17106b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 17116b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 17126b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 17136b6fae2bSMattias Nilsson PLL_RAW); 17146b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 17156b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK); 17166b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 17176b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 17186b6fae2bSMattias Nilsson else 17196b6fae2bSMattias Nilsson return 0; 17206b6fae2bSMattias Nilsson } 17216b6fae2bSMattias Nilsson 17226b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 17236b6fae2bSMattias Nilsson { 17246b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 17256b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 17266b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 17276b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 17286b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 17296b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 17306b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 17316b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 17326b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 17336b6fae2bSMattias Nilsson else 17346b6fae2bSMattias Nilsson return 0; 17356b6fae2bSMattias Nilsson } 17366b6fae2bSMattias Nilsson 17376b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate) 17386b6fae2bSMattias Nilsson { 17396b6fae2bSMattias Nilsson u32 div; 17406b6fae2bSMattias Nilsson 17416b6fae2bSMattias Nilsson div = (src_rate / rate); 17426b6fae2bSMattias Nilsson if (div == 0) 17436b6fae2bSMattias Nilsson return 1; 17446b6fae2bSMattias Nilsson if (rate < (src_rate / div)) 17456b6fae2bSMattias Nilsson div++; 17466b6fae2bSMattias Nilsson return div; 17476b6fae2bSMattias Nilsson } 17486b6fae2bSMattias Nilsson 17496b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate) 17506b6fae2bSMattias Nilsson { 17516b6fae2bSMattias Nilsson u32 val; 17526b6fae2bSMattias Nilsson u32 div; 17536b6fae2bSMattias Nilsson unsigned long src_rate; 17546b6fae2bSMattias Nilsson long rounded_rate; 17556b6fae2bSMattias Nilsson 17566b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 17576b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 17586b6fae2bSMattias Nilsson clk_mgt[clock].branch); 17596b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 17606b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 17616b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 17626b6fae2bSMattias Nilsson if (div > 2) 17636b6fae2bSMattias Nilsson div = 2; 17646b6fae2bSMattias Nilsson } else { 17656b6fae2bSMattias Nilsson div = 1; 17666b6fae2bSMattias Nilsson } 17676b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 17686b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 17696b6fae2bSMattias Nilsson 17706b6fae2bSMattias Nilsson (void)do_div(r, 25); 17716b6fae2bSMattias Nilsson if (r <= rate) 17726b6fae2bSMattias Nilsson return (unsigned long)r; 17736b6fae2bSMattias Nilsson } 17746b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31)); 17756b6fae2bSMattias Nilsson 17766b6fae2bSMattias Nilsson return rounded_rate; 17776b6fae2bSMattias Nilsson } 17786b6fae2bSMattias Nilsson 17796b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL 17806b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL 17816b6fae2bSMattias Nilsson 17826b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate) 17836b6fae2bSMattias Nilsson { 17846b6fae2bSMattias Nilsson long rounded_rate = 0; 17856b6fae2bSMattias Nilsson unsigned long src_rate; 17866b6fae2bSMattias Nilsson unsigned long rem; 17876b6fae2bSMattias Nilsson u32 r; 17886b6fae2bSMattias Nilsson 17896b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 17906b6fae2bSMattias Nilsson rem = rate; 17916b6fae2bSMattias Nilsson 17926b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 17936b6fae2bSMattias Nilsson u64 d; 17946b6fae2bSMattias Nilsson 17956b6fae2bSMattias Nilsson d = (r * rate); 17966b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 17976b6fae2bSMattias Nilsson if (d < 6) 17986b6fae2bSMattias Nilsson d = 6; 17996b6fae2bSMattias Nilsson else if (d > 255) 18006b6fae2bSMattias Nilsson d = 255; 18016b6fae2bSMattias Nilsson d *= src_rate; 18026b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 18036b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d))) 18046b6fae2bSMattias Nilsson continue; 18056b6fae2bSMattias Nilsson (void)do_div(d, r); 18066b6fae2bSMattias Nilsson if (rate < d) { 18076b6fae2bSMattias Nilsson if (rounded_rate == 0) 18086b6fae2bSMattias Nilsson rounded_rate = (long)d; 1809e62ccf3aSLinus Walleij break; 1810e62ccf3aSLinus Walleij } 18116b6fae2bSMattias Nilsson if ((rate - d) < rem) { 18126b6fae2bSMattias Nilsson rem = (rate - d); 18136b6fae2bSMattias Nilsson rounded_rate = (long)d; 18146b6fae2bSMattias Nilsson } 18156b6fae2bSMattias Nilsson } 18166b6fae2bSMattias Nilsson return rounded_rate; 18176b6fae2bSMattias Nilsson } 18186b6fae2bSMattias Nilsson 18196b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate) 18206b6fae2bSMattias Nilsson { 18216b6fae2bSMattias Nilsson u32 div; 18226b6fae2bSMattias Nilsson unsigned long src_rate; 18236b6fae2bSMattias Nilsson long rounded_rate; 18246b6fae2bSMattias Nilsson 18256b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 18266b6fae2bSMattias Nilsson PLL_RAW); 18276b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18286b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 18296b6fae2bSMattias Nilsson 18306b6fae2bSMattias Nilsson return rounded_rate; 18316b6fae2bSMattias Nilsson } 18326b6fae2bSMattias Nilsson 18336b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate) 18346b6fae2bSMattias Nilsson { 18356b6fae2bSMattias Nilsson u32 div; 18366b6fae2bSMattias Nilsson unsigned long src_rate; 18376b6fae2bSMattias Nilsson long rounded_rate; 18386b6fae2bSMattias Nilsson 18396b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK); 18406b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18416b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255)); 18426b6fae2bSMattias Nilsson 18436b6fae2bSMattias Nilsson return rounded_rate; 18446b6fae2bSMattias Nilsson } 18456b6fae2bSMattias Nilsson 18466b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate) 18476b6fae2bSMattias Nilsson { 1848e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 18496b6fae2bSMattias Nilsson return round_clock_rate(clock, rate); 18506b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 18516b6fae2bSMattias Nilsson return round_plldsi_rate(rate); 18526b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 18536b6fae2bSMattias Nilsson return round_dsiclk_rate(rate); 18546b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 18556b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate); 18566b6fae2bSMattias Nilsson else 18576b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock); 18586b6fae2bSMattias Nilsson } 18596b6fae2bSMattias Nilsson 18606b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate) 18616b6fae2bSMattias Nilsson { 18626b6fae2bSMattias Nilsson u32 val; 18636b6fae2bSMattias Nilsson u32 div; 18646b6fae2bSMattias Nilsson unsigned long src_rate; 18656b6fae2bSMattias Nilsson unsigned long flags; 18666b6fae2bSMattias Nilsson 18676b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 18686b6fae2bSMattias Nilsson 18696b6fae2bSMattias Nilsson /* Grab the HW semaphore. */ 18706b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 18716b6fae2bSMattias Nilsson cpu_relax(); 18726b6fae2bSMattias Nilsson 18736b6fae2bSMattias Nilsson val = readl(clk_mgt[clock].reg); 18746b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 18756b6fae2bSMattias Nilsson clk_mgt[clock].branch); 18766b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18776b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 18786b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 18796b6fae2bSMattias Nilsson if (div > 1) 18806b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV; 18816b6fae2bSMattias Nilsson else 18826b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV; 18836b6fae2bSMattias Nilsson } 18846b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) { 18856b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 18866b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 18876b6fae2bSMattias Nilsson if (div == 3) { 18886b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 18896b6fae2bSMattias Nilsson 18906b6fae2bSMattias Nilsson (void)do_div(r, 25); 18916b6fae2bSMattias Nilsson if (r <= rate) { 18926b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 18936b6fae2bSMattias Nilsson div = 0; 18946b6fae2bSMattias Nilsson } 18956b6fae2bSMattias Nilsson } 18966b6fae2bSMattias Nilsson val |= min(div, (u32)31); 18976b6fae2bSMattias Nilsson } else { 18986b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 18996b6fae2bSMattias Nilsson val |= min(div, (u32)31); 19006b6fae2bSMattias Nilsson } 19016b6fae2bSMattias Nilsson writel(val, clk_mgt[clock].reg); 19026b6fae2bSMattias Nilsson 19036b6fae2bSMattias Nilsson /* Release the HW semaphore. */ 19046b6fae2bSMattias Nilsson writel(0, PRCM_SEM); 19056b6fae2bSMattias Nilsson 19066b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 19076b6fae2bSMattias Nilsson } 19086b6fae2bSMattias Nilsson 19096b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate) 19106b6fae2bSMattias Nilsson { 19116b6fae2bSMattias Nilsson unsigned long src_rate; 19126b6fae2bSMattias Nilsson unsigned long rem; 19136b6fae2bSMattias Nilsson u32 pll_freq = 0; 19146b6fae2bSMattias Nilsson u32 r; 19156b6fae2bSMattias Nilsson 19166b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 19176b6fae2bSMattias Nilsson rem = rate; 19186b6fae2bSMattias Nilsson 19196b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 19206b6fae2bSMattias Nilsson u64 d; 19216b6fae2bSMattias Nilsson u64 hwrate; 19226b6fae2bSMattias Nilsson 19236b6fae2bSMattias Nilsson d = (r * rate); 19246b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 19256b6fae2bSMattias Nilsson if (d < 6) 19266b6fae2bSMattias Nilsson d = 6; 19276b6fae2bSMattias Nilsson else if (d > 255) 19286b6fae2bSMattias Nilsson d = 255; 19296b6fae2bSMattias Nilsson hwrate = (d * src_rate); 19306b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 19316b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 19326b6fae2bSMattias Nilsson continue; 19336b6fae2bSMattias Nilsson (void)do_div(hwrate, r); 19346b6fae2bSMattias Nilsson if (rate < hwrate) { 19356b6fae2bSMattias Nilsson if (pll_freq == 0) 19366b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19376b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19386b6fae2bSMattias Nilsson break; 19396b6fae2bSMattias Nilsson } 19406b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) { 19416b6fae2bSMattias Nilsson rem = (rate - hwrate); 19426b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19436b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19446b6fae2bSMattias Nilsson } 19456b6fae2bSMattias Nilsson } 19466b6fae2bSMattias Nilsson if (pll_freq == 0) 19473df57bcfSMattias Nilsson return -EINVAL; 19486b6fae2bSMattias Nilsson 19496b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 19506b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ); 19516b6fae2bSMattias Nilsson 19526b6fae2bSMattias Nilsson return 0; 19536b6fae2bSMattias Nilsson } 19546b6fae2bSMattias Nilsson 19556b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate) 19566b6fae2bSMattias Nilsson { 19576b6fae2bSMattias Nilsson u32 val; 19586b6fae2bSMattias Nilsson u32 div; 19596b6fae2bSMattias Nilsson 19606b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 19616b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 19626b6fae2bSMattias Nilsson 19636b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 19646b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 19656b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 19666b6fae2bSMattias Nilsson 19676b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 19686b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 19696b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 19706b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 19716b6fae2bSMattias Nilsson } 19726b6fae2bSMattias Nilsson 19736b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate) 19746b6fae2bSMattias Nilsson { 19756b6fae2bSMattias Nilsson u32 val; 19766b6fae2bSMattias Nilsson u32 div; 19776b6fae2bSMattias Nilsson 19786b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 19796b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 19806b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask; 19816b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 19826b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 19836b6fae2bSMattias Nilsson } 19846b6fae2bSMattias Nilsson 19856b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate) 19866b6fae2bSMattias Nilsson { 19876b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 19886b6fae2bSMattias Nilsson set_clock_rate(clock, rate); 19896b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 19906b6fae2bSMattias Nilsson return set_plldsi_rate(rate); 19916b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 19926b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 19936b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 19946b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 19956b6fae2bSMattias Nilsson return 0; 19963df57bcfSMattias Nilsson } 19973df57bcfSMattias Nilsson 199873180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 19993df57bcfSMattias Nilsson { 20003df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 20013df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 20023df57bcfSMattias Nilsson return -EINVAL; 20033df57bcfSMattias Nilsson 20043df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20053df57bcfSMattias Nilsson 2006c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20073df57bcfSMattias Nilsson cpu_relax(); 20083df57bcfSMattias Nilsson 20093df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20103df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 20113df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 20123df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 20133df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 20143df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 20153df57bcfSMattias Nilsson 2016c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20173df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20183df57bcfSMattias Nilsson 20193df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20203df57bcfSMattias Nilsson 20213df57bcfSMattias Nilsson return 0; 20223df57bcfSMattias Nilsson } 20233df57bcfSMattias Nilsson 20240508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold) 20253df57bcfSMattias Nilsson { 20263df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20273df57bcfSMattias Nilsson 2028c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20293df57bcfSMattias Nilsson cpu_relax(); 20303df57bcfSMattias Nilsson 20313df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 20323df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20333df57bcfSMattias Nilsson 2034c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20353df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20363df57bcfSMattias Nilsson 20373df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20383df57bcfSMattias Nilsson 20393df57bcfSMattias Nilsson return 0; 20403df57bcfSMattias Nilsson } 20413df57bcfSMattias Nilsson 20420508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high) 20433df57bcfSMattias Nilsson { 20443df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20453df57bcfSMattias Nilsson 2046c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20473df57bcfSMattias Nilsson cpu_relax(); 20483df57bcfSMattias Nilsson 20493df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 20503df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 20513df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 20523df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 20533df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20543df57bcfSMattias Nilsson 2055c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20563df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20573df57bcfSMattias Nilsson 20583df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20593df57bcfSMattias Nilsson 20603df57bcfSMattias Nilsson return 0; 20613df57bcfSMattias Nilsson } 20623df57bcfSMattias Nilsson 20633df57bcfSMattias Nilsson static int config_hot_period(u16 val) 20643df57bcfSMattias Nilsson { 20653df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20663df57bcfSMattias Nilsson 2067c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20683df57bcfSMattias Nilsson cpu_relax(); 20693df57bcfSMattias Nilsson 20703df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 20713df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20723df57bcfSMattias Nilsson 2073c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20743df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20753df57bcfSMattias Nilsson 20763df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20773df57bcfSMattias Nilsson 20783df57bcfSMattias Nilsson return 0; 20793df57bcfSMattias Nilsson } 20803df57bcfSMattias Nilsson 20810508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k) 20823df57bcfSMattias Nilsson { 20833df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 20843df57bcfSMattias Nilsson return -EINVAL; 20853df57bcfSMattias Nilsson 20863df57bcfSMattias Nilsson return config_hot_period(cycles32k); 20873df57bcfSMattias Nilsson } 20883df57bcfSMattias Nilsson 20890508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void) 20903df57bcfSMattias Nilsson { 20913df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 20923df57bcfSMattias Nilsson } 20933df57bcfSMattias Nilsson 209484165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 209584165b80SJonas Aberg { 209684165b80SJonas Aberg 209784165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 209884165b80SJonas Aberg 209984165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 210084165b80SJonas Aberg cpu_relax(); 210184165b80SJonas Aberg 210284165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 210384165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 210484165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 210584165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 210684165b80SJonas Aberg 210784165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 210884165b80SJonas Aberg 210984165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 211084165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 211184165b80SJonas Aberg 211284165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 211384165b80SJonas Aberg 211484165b80SJonas Aberg return 0; 211584165b80SJonas Aberg 211684165b80SJonas Aberg } 211784165b80SJonas Aberg 21180508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 211984165b80SJonas Aberg { 212084165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 212184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 212284165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 212384165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 212484165b80SJonas Aberg } 212584165b80SJonas Aberg 21260508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id) 212784165b80SJonas Aberg { 212884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 212984165b80SJonas Aberg } 213084165b80SJonas Aberg 21310508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id) 213284165b80SJonas Aberg { 213384165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 213484165b80SJonas Aberg } 213584165b80SJonas Aberg 21360508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id) 213784165b80SJonas Aberg { 213884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 213984165b80SJonas Aberg } 214084165b80SJonas Aberg 214184165b80SJonas Aberg /* 214284165b80SJonas Aberg * timeout is 28 bit, in ms. 214384165b80SJonas Aberg */ 21440508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 214584165b80SJonas Aberg { 214684165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 214784165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 214884165b80SJonas Aberg /* 214984165b80SJonas Aberg * Put the lowest 28 bits of timeout at 215084165b80SJonas Aberg * offset 4. Four first bits are used for id. 215184165b80SJonas Aberg */ 215284165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 215384165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 215484165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 215584165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 215684165b80SJonas Aberg } 215784165b80SJonas Aberg 21583df57bcfSMattias Nilsson /** 2159650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 2160650c2a21SLinus Walleij * @slave: The I2C slave address. 2161650c2a21SLinus Walleij * @reg: The (start) register address. 2162650c2a21SLinus Walleij * @value: The read out value(s). 2163650c2a21SLinus Walleij * @size: The number of registers to read. 2164650c2a21SLinus Walleij * 2165650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2166650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2167650c2a21SLinus Walleij */ 2168650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2169650c2a21SLinus Walleij { 2170650c2a21SLinus Walleij int r; 2171650c2a21SLinus Walleij 2172650c2a21SLinus Walleij if (size != 1) 2173650c2a21SLinus Walleij return -EINVAL; 2174650c2a21SLinus Walleij 21753df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2176650c2a21SLinus Walleij 2177c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2178650c2a21SLinus Walleij cpu_relax(); 2179650c2a21SLinus Walleij 21803c3e4898SMattias Nilsson writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 21813df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 21823df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 21833df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 21843df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2185650c2a21SLinus Walleij 2186c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 21873df57bcfSMattias Nilsson 2188650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 21893df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 21903df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 21913df57bcfSMattias Nilsson __func__); 2192650c2a21SLinus Walleij r = -EIO; 21933df57bcfSMattias Nilsson } else { 2194650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 21953df57bcfSMattias Nilsson } 21963df57bcfSMattias Nilsson 2197650c2a21SLinus Walleij if (!r) 2198650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 2199650c2a21SLinus Walleij 2200650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 22013df57bcfSMattias Nilsson 2202650c2a21SLinus Walleij return r; 2203650c2a21SLinus Walleij } 2204650c2a21SLinus Walleij 2205650c2a21SLinus Walleij /** 22063c3e4898SMattias Nilsson * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. 2207650c2a21SLinus Walleij * @slave: The I2C slave address. 2208650c2a21SLinus Walleij * @reg: The (start) register address. 2209650c2a21SLinus Walleij * @value: The value(s) to write. 22103c3e4898SMattias Nilsson * @mask: The mask(s) to use. 2211650c2a21SLinus Walleij * @size: The number of registers to write. 2212650c2a21SLinus Walleij * 22133c3e4898SMattias Nilsson * Writes masked register value(s) to the ABB. 22143c3e4898SMattias Nilsson * For each @value, only the bits set to 1 in the corresponding @mask 22153c3e4898SMattias Nilsson * will be written. The other bits are not changed. 2216650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2217650c2a21SLinus Walleij */ 22183c3e4898SMattias Nilsson int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) 2219650c2a21SLinus Walleij { 2220650c2a21SLinus Walleij int r; 2221650c2a21SLinus Walleij 2222650c2a21SLinus Walleij if (size != 1) 2223650c2a21SLinus Walleij return -EINVAL; 2224650c2a21SLinus Walleij 22253df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2226650c2a21SLinus Walleij 2227c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2228650c2a21SLinus Walleij cpu_relax(); 2229650c2a21SLinus Walleij 22303c3e4898SMattias Nilsson writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 22313df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22323df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22333df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22343df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2235650c2a21SLinus Walleij 2236c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 22373df57bcfSMattias Nilsson 2238650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 22393df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 22403df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 22413df57bcfSMattias Nilsson __func__); 2242650c2a21SLinus Walleij r = -EIO; 22433df57bcfSMattias Nilsson } else { 2244650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 22453df57bcfSMattias Nilsson } 22463df57bcfSMattias Nilsson 22473df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 22483df57bcfSMattias Nilsson 22493df57bcfSMattias Nilsson return r; 22503df57bcfSMattias Nilsson } 22513df57bcfSMattias Nilsson 22523df57bcfSMattias Nilsson /** 22533c3e4898SMattias Nilsson * prcmu_abb_write() - Write register value(s) to the ABB. 22543c3e4898SMattias Nilsson * @slave: The I2C slave address. 22553c3e4898SMattias Nilsson * @reg: The (start) register address. 22563c3e4898SMattias Nilsson * @value: The value(s) to write. 22573c3e4898SMattias Nilsson * @size: The number of registers to write. 22583c3e4898SMattias Nilsson * 22593c3e4898SMattias Nilsson * Writes register value(s) to the ABB. 22603c3e4898SMattias Nilsson * @size has to be 1 for the current firmware version. 22613c3e4898SMattias Nilsson */ 22623c3e4898SMattias Nilsson int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 22633c3e4898SMattias Nilsson { 22643c3e4898SMattias Nilsson u8 mask = ~0; 22653c3e4898SMattias Nilsson 22663c3e4898SMattias Nilsson return prcmu_abb_write_masked(slave, reg, value, &mask, size); 22673c3e4898SMattias Nilsson } 22683c3e4898SMattias Nilsson 22693c3e4898SMattias Nilsson /** 22703df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 22713df57bcfSMattias Nilsson */ 22723df57bcfSMattias Nilsson void prcmu_ac_wake_req(void) 22733df57bcfSMattias Nilsson { 22743df57bcfSMattias Nilsson u32 val; 2275d6e3002eSMattias Nilsson u32 status; 22763df57bcfSMattias Nilsson 22773df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 22783df57bcfSMattias Nilsson 2279c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 22803df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 22813df57bcfSMattias Nilsson goto unlock_and_return; 22823df57bcfSMattias Nilsson 22833df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 22843df57bcfSMattias Nilsson 2285d6e3002eSMattias Nilsson retry: 2286c553b3caSMattias Nilsson writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); 22873df57bcfSMattias Nilsson 22883df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2289d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 229057265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2291d6e3002eSMattias Nilsson __func__); 2292d6e3002eSMattias Nilsson goto unlock_and_return; 2293d6e3002eSMattias Nilsson } 2294d6e3002eSMattias Nilsson 2295d6e3002eSMattias Nilsson /* 2296d6e3002eSMattias Nilsson * The modem can generate an AC_WAKE_ACK, and then still go to sleep. 2297d6e3002eSMattias Nilsson * As a workaround, we wait, and then check that the modem is indeed 2298d6e3002eSMattias Nilsson * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS 2299d6e3002eSMattias Nilsson * register, which may not be the whole truth). 2300d6e3002eSMattias Nilsson */ 2301d6e3002eSMattias Nilsson udelay(400); 2302d6e3002eSMattias Nilsson status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2)); 2303d6e3002eSMattias Nilsson if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE | 2304d6e3002eSMattias Nilsson PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) { 2305d6e3002eSMattias Nilsson pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n", 2306d6e3002eSMattias Nilsson __func__, status); 2307d6e3002eSMattias Nilsson udelay(1200); 2308d6e3002eSMattias Nilsson writel(val, PRCM_HOSTACCESS_REQ); 2309d6e3002eSMattias Nilsson if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2310d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) 2311d6e3002eSMattias Nilsson goto retry; 231257265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n", 23133df57bcfSMattias Nilsson __func__); 23143df57bcfSMattias Nilsson } 2315650c2a21SLinus Walleij 2316650c2a21SLinus Walleij unlock_and_return: 23173df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 2318650c2a21SLinus Walleij } 2319650c2a21SLinus Walleij 23203df57bcfSMattias Nilsson /** 23213df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 23223df57bcfSMattias Nilsson */ 23233df57bcfSMattias Nilsson void prcmu_ac_sleep_req() 2324650c2a21SLinus Walleij { 23253df57bcfSMattias Nilsson u32 val; 2326650c2a21SLinus Walleij 23273df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 2328650c2a21SLinus Walleij 2329c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23303df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 23313df57bcfSMattias Nilsson goto unlock_and_return; 23323df57bcfSMattias Nilsson 23333df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2334c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 23353df57bcfSMattias Nilsson 23363df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2337d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 233857265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 23393df57bcfSMattias Nilsson __func__); 23403df57bcfSMattias Nilsson } 23413df57bcfSMattias Nilsson 23423df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 23433df57bcfSMattias Nilsson 23443df57bcfSMattias Nilsson unlock_and_return: 23453df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23463df57bcfSMattias Nilsson } 23473df57bcfSMattias Nilsson 234873180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 23493df57bcfSMattias Nilsson { 23503df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 23513df57bcfSMattias Nilsson } 23523df57bcfSMattias Nilsson 23533df57bcfSMattias Nilsson /** 235473180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 23553df57bcfSMattias Nilsson * 235673180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 23573df57bcfSMattias Nilsson * fires interrupt to fw 23583df57bcfSMattias Nilsson */ 235973180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 23603df57bcfSMattias Nilsson { 23613df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2362c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 23633df57bcfSMattias Nilsson } 23643df57bcfSMattias Nilsson 23653df57bcfSMattias Nilsson /** 2366597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2367597045deSSebastian Rasmussen * 2368597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 2369597045deSSebastian Rasmussen * last restart. 2370597045deSSebastian Rasmussen */ 2371597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 2372597045deSSebastian Rasmussen { 2373597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 2374597045deSSebastian Rasmussen } 2375597045deSSebastian Rasmussen 2376597045deSSebastian Rasmussen /** 23770508901cSMattias Nilsson * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 23783df57bcfSMattias Nilsson */ 23790508901cSMattias Nilsson void db8500_prcmu_modem_reset(void) 23803df57bcfSMattias Nilsson { 2381650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 2382650c2a21SLinus Walleij 2383c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2384650c2a21SLinus Walleij cpu_relax(); 2385650c2a21SLinus Walleij 23863df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2387c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2388650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 23893df57bcfSMattias Nilsson 23903df57bcfSMattias Nilsson /* 23913df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 23923df57bcfSMattias Nilsson * This state is already managed by upper layer 23933df57bcfSMattias Nilsson */ 2394650c2a21SLinus Walleij 2395650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 2396650c2a21SLinus Walleij } 2397650c2a21SLinus Walleij 23983df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 2399650c2a21SLinus Walleij { 24003df57bcfSMattias Nilsson unsigned long flags; 2401650c2a21SLinus Walleij 24023df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 2403650c2a21SLinus Walleij 2404c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 24053df57bcfSMattias Nilsson cpu_relax(); 2406650c2a21SLinus Walleij 24073df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2408c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2409650c2a21SLinus Walleij 24103df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2411650c2a21SLinus Walleij } 2412650c2a21SLinus Walleij 24133df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 2414650c2a21SLinus Walleij { 24153df57bcfSMattias Nilsson pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 24163df57bcfSMattias Nilsson header, n); 2417650c2a21SLinus Walleij } 2418650c2a21SLinus Walleij 24193df57bcfSMattias Nilsson static bool read_mailbox_0(void) 2420650c2a21SLinus Walleij { 24213df57bcfSMattias Nilsson bool r; 24223df57bcfSMattias Nilsson u32 ev; 24233df57bcfSMattias Nilsson unsigned int n; 24243df57bcfSMattias Nilsson u8 header; 24253df57bcfSMattias Nilsson 24263df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 24273df57bcfSMattias Nilsson switch (header) { 24283df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 24293df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 24303df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 24313df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 24323df57bcfSMattias Nilsson else 24333df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 24343df57bcfSMattias Nilsson 24353df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 24363df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 24373df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 24383df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 24393df57bcfSMattias Nilsson 24403df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 24413df57bcfSMattias Nilsson 24423df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 24433df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 24443df57bcfSMattias Nilsson generic_handle_irq(IRQ_PRCMU_BASE + n); 24453df57bcfSMattias Nilsson } 24463df57bcfSMattias Nilsson r = true; 24473df57bcfSMattias Nilsson break; 24483df57bcfSMattias Nilsson default: 24493df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 24503df57bcfSMattias Nilsson r = false; 24513df57bcfSMattias Nilsson break; 24523df57bcfSMattias Nilsson } 2453c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 24543df57bcfSMattias Nilsson return r; 24553df57bcfSMattias Nilsson } 24563df57bcfSMattias Nilsson 24573df57bcfSMattias Nilsson static bool read_mailbox_1(void) 24583df57bcfSMattias Nilsson { 24593df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 24603df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 24613df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 24623df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 24633df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 24643df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 24653df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2466c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2467650c2a21SLinus Walleij complete(&mb1_transfer.work); 24683df57bcfSMattias Nilsson return false; 2469650c2a21SLinus Walleij } 2470650c2a21SLinus Walleij 24713df57bcfSMattias Nilsson static bool read_mailbox_2(void) 2472650c2a21SLinus Walleij { 24733df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2474c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 24753df57bcfSMattias Nilsson complete(&mb2_transfer.work); 24763df57bcfSMattias Nilsson return false; 2477650c2a21SLinus Walleij } 2478650c2a21SLinus Walleij 24793df57bcfSMattias Nilsson static bool read_mailbox_3(void) 2480650c2a21SLinus Walleij { 2481c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 24823df57bcfSMattias Nilsson return false; 2483650c2a21SLinus Walleij } 2484650c2a21SLinus Walleij 24853df57bcfSMattias Nilsson static bool read_mailbox_4(void) 2486650c2a21SLinus Walleij { 24873df57bcfSMattias Nilsson u8 header; 24883df57bcfSMattias Nilsson bool do_complete = true; 24893df57bcfSMattias Nilsson 24903df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 24913df57bcfSMattias Nilsson switch (header) { 24923df57bcfSMattias Nilsson case MB4H_MEM_ST: 24933df57bcfSMattias Nilsson case MB4H_HOTDOG: 24943df57bcfSMattias Nilsson case MB4H_HOTMON: 24953df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 2496a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 2497a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 2498a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 2499a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 2500a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 25013df57bcfSMattias Nilsson break; 25023df57bcfSMattias Nilsson default: 25033df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 25043df57bcfSMattias Nilsson do_complete = false; 25053df57bcfSMattias Nilsson break; 2506650c2a21SLinus Walleij } 2507650c2a21SLinus Walleij 2508c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 25093df57bcfSMattias Nilsson 25103df57bcfSMattias Nilsson if (do_complete) 25113df57bcfSMattias Nilsson complete(&mb4_transfer.work); 25123df57bcfSMattias Nilsson 25133df57bcfSMattias Nilsson return false; 25143df57bcfSMattias Nilsson } 25153df57bcfSMattias Nilsson 25163df57bcfSMattias Nilsson static bool read_mailbox_5(void) 2517650c2a21SLinus Walleij { 25183df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 25193df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2520c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2521650c2a21SLinus Walleij complete(&mb5_transfer.work); 25223df57bcfSMattias Nilsson return false; 2523650c2a21SLinus Walleij } 2524650c2a21SLinus Walleij 25253df57bcfSMattias Nilsson static bool read_mailbox_6(void) 2526650c2a21SLinus Walleij { 2527c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 25283df57bcfSMattias Nilsson return false; 2529650c2a21SLinus Walleij } 2530650c2a21SLinus Walleij 25313df57bcfSMattias Nilsson static bool read_mailbox_7(void) 2532650c2a21SLinus Walleij { 2533c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 25343df57bcfSMattias Nilsson return false; 2535650c2a21SLinus Walleij } 2536650c2a21SLinus Walleij 25373df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 2538650c2a21SLinus Walleij read_mailbox_0, 2539650c2a21SLinus Walleij read_mailbox_1, 2540650c2a21SLinus Walleij read_mailbox_2, 2541650c2a21SLinus Walleij read_mailbox_3, 2542650c2a21SLinus Walleij read_mailbox_4, 2543650c2a21SLinus Walleij read_mailbox_5, 2544650c2a21SLinus Walleij read_mailbox_6, 2545650c2a21SLinus Walleij read_mailbox_7 2546650c2a21SLinus Walleij }; 2547650c2a21SLinus Walleij 2548650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2549650c2a21SLinus Walleij { 2550650c2a21SLinus Walleij u32 bits; 2551650c2a21SLinus Walleij u8 n; 25523df57bcfSMattias Nilsson irqreturn_t r; 2553650c2a21SLinus Walleij 2554c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2555650c2a21SLinus Walleij if (unlikely(!bits)) 2556650c2a21SLinus Walleij return IRQ_NONE; 2557650c2a21SLinus Walleij 25583df57bcfSMattias Nilsson r = IRQ_HANDLED; 2559650c2a21SLinus Walleij for (n = 0; bits; n++) { 2560650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2561650c2a21SLinus Walleij bits -= MBOX_BIT(n); 25623df57bcfSMattias Nilsson if (read_mailbox[n]()) 25633df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2564650c2a21SLinus Walleij } 2565650c2a21SLinus Walleij } 25663df57bcfSMattias Nilsson return r; 25673df57bcfSMattias Nilsson } 25683df57bcfSMattias Nilsson 25693df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 25703df57bcfSMattias Nilsson { 25713df57bcfSMattias Nilsson ack_dbb_wakeup(); 2572650c2a21SLinus Walleij return IRQ_HANDLED; 2573650c2a21SLinus Walleij } 2574650c2a21SLinus Walleij 25753df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 25763df57bcfSMattias Nilsson { 25773df57bcfSMattias Nilsson unsigned long flags; 25783df57bcfSMattias Nilsson 25793df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 25803df57bcfSMattias Nilsson 25813df57bcfSMattias Nilsson config_wakeups(); 25823df57bcfSMattias Nilsson 25833df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 25843df57bcfSMattias Nilsson } 25853df57bcfSMattias Nilsson 25863df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 25873df57bcfSMattias Nilsson { 25883df57bcfSMattias Nilsson unsigned long flags; 25893df57bcfSMattias Nilsson 25903df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 25913df57bcfSMattias Nilsson 25923df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 25933df57bcfSMattias Nilsson 25943df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 25953df57bcfSMattias Nilsson 25963df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 25973df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 25983df57bcfSMattias Nilsson } 25993df57bcfSMattias Nilsson 26003df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 26013df57bcfSMattias Nilsson { 26023df57bcfSMattias Nilsson unsigned long flags; 26033df57bcfSMattias Nilsson 26043df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26053df57bcfSMattias Nilsson 26063df57bcfSMattias Nilsson mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; 26073df57bcfSMattias Nilsson 26083df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26093df57bcfSMattias Nilsson 26103df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26113df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26123df57bcfSMattias Nilsson } 26133df57bcfSMattias Nilsson 26143df57bcfSMattias Nilsson static void noop(struct irq_data *d) 26153df57bcfSMattias Nilsson { 26163df57bcfSMattias Nilsson } 26173df57bcfSMattias Nilsson 26183df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 26193df57bcfSMattias Nilsson .name = "prcmu", 26203df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 26213df57bcfSMattias Nilsson .irq_ack = noop, 26223df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 26233df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 26243df57bcfSMattias Nilsson }; 26253df57bcfSMattias Nilsson 2626b58d12feSMattias Nilsson static char *fw_project_name(u8 project) 2627b58d12feSMattias Nilsson { 2628b58d12feSMattias Nilsson switch (project) { 2629b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500: 2630b58d12feSMattias Nilsson return "U8500"; 2631b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500_C2: 2632b58d12feSMattias Nilsson return "U8500 C2"; 2633b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500: 2634b58d12feSMattias Nilsson return "U9500"; 2635b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500_C2: 2636b58d12feSMattias Nilsson return "U9500 C2"; 26375f96a1a6SBengt Jonsson case PRCMU_FW_PROJECT_U8520: 26385f96a1a6SBengt Jonsson return "U8520"; 26391927ddf6SBengt Jonsson case PRCMU_FW_PROJECT_U8420: 26401927ddf6SBengt Jonsson return "U8420"; 2641b58d12feSMattias Nilsson default: 2642b58d12feSMattias Nilsson return "Unknown"; 2643b58d12feSMattias Nilsson } 2644b58d12feSMattias Nilsson } 2645b58d12feSMattias Nilsson 264673180f85SMattias Nilsson void __init db8500_prcmu_early_init(void) 2647650c2a21SLinus Walleij { 26483df57bcfSMattias Nilsson unsigned int i; 26493e2762c8SLinus Walleij if (cpu_is_u8500v2()) { 26503df57bcfSMattias Nilsson void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); 26513df57bcfSMattias Nilsson 26523df57bcfSMattias Nilsson if (tcpm_base != NULL) { 26533e2762c8SLinus Walleij u32 version; 26543df57bcfSMattias Nilsson version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); 2655b58d12feSMattias Nilsson fw_info.version.project = version & 0xFF; 2656b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF; 2657b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF; 2658b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF; 2659b58d12feSMattias Nilsson fw_info.valid = true; 2660b58d12feSMattias Nilsson pr_info("PRCMU firmware: %s, version %d.%d.%d\n", 2661b58d12feSMattias Nilsson fw_project_name(fw_info.version.project), 26623df57bcfSMattias Nilsson (version >> 8) & 0xFF, (version >> 16) & 0xFF, 26633df57bcfSMattias Nilsson (version >> 24) & 0xFF); 26643df57bcfSMattias Nilsson iounmap(tcpm_base); 26653df57bcfSMattias Nilsson } 26663df57bcfSMattias Nilsson 2667650c2a21SLinus Walleij tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); 2668650c2a21SLinus Walleij } else { 2669650c2a21SLinus Walleij pr_err("prcmu: Unsupported chip version\n"); 2670650c2a21SLinus Walleij BUG(); 2671650c2a21SLinus Walleij } 2672650c2a21SLinus Walleij 26733df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 26743df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 26753df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 26763df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2677650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2678650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 26794d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE; 26803df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 26813df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 26823df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 26833df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 26843df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 26853df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 26863df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 26873df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2688650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2689650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2690650c2a21SLinus Walleij 26913df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2692650c2a21SLinus Walleij 26933df57bcfSMattias Nilsson /* Initalize irqs. */ 26943df57bcfSMattias Nilsson for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { 26953df57bcfSMattias Nilsson unsigned int irq; 26963df57bcfSMattias Nilsson 26973df57bcfSMattias Nilsson irq = IRQ_PRCMU_BASE + i; 26983df57bcfSMattias Nilsson irq_set_chip_and_handler(irq, &prcmu_irq_chip, 26993df57bcfSMattias Nilsson handle_simple_irq); 27003df57bcfSMattias Nilsson set_irq_flags(irq, IRQF_VALID); 27013df57bcfSMattias Nilsson } 2702650c2a21SLinus Walleij } 2703650c2a21SLinus Walleij 27040508901cSMattias Nilsson static void __init init_prcm_registers(void) 2705d65e12d7SMattias Nilsson { 2706d65e12d7SMattias Nilsson u32 val; 2707d65e12d7SMattias Nilsson 2708d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2709d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2710d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2711d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2712d65e12d7SMattias Nilsson } 2713d65e12d7SMattias Nilsson 27141032fbfdSBengt Jonsson /* 27151032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 27161032fbfdSBengt Jonsson */ 27171032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 27181032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 27191032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 27201032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 27211032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 27221032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 2723ae840635SLee Jones REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), 27241032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 27251032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 27261032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 27271032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 27281032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 27291032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 27301032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 27311032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 27321032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 27331032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 27341032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 27351032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 27361032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2737992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 2738bc367481SLee Jones REGULATOR_SUPPLY("vddvario", "smsc911x.0"), 27391032fbfdSBengt Jonsson }; 27401032fbfdSBengt Jonsson 27411032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 27421032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 27431032fbfdSBengt Jonsson /* AV8100 regulator */ 27441032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 27451032fbfdSBengt Jonsson }; 27461032fbfdSBengt Jonsson 27471032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2748992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2749624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2750624e87c2SBengt Jonsson }; 2751624e87c2SBengt Jonsson 2752624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2753624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2754624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2755624e87c2SBengt Jonsson }; 2756624e87c2SBengt Jonsson 2757624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2758624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2759624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2760624e87c2SBengt Jonsson }; 2761624e87c2SBengt Jonsson 2762624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2763624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2764624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2765624e87c2SBengt Jonsson }; 2766624e87c2SBengt Jonsson 2767624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2768624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2769624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2770624e87c2SBengt Jonsson }; 2771624e87c2SBengt Jonsson 2772624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2773624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2774624e87c2SBengt Jonsson }; 2775624e87c2SBengt Jonsson 2776624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2777624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2778624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2779624e87c2SBengt Jonsson }; 2780624e87c2SBengt Jonsson 2781624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2782624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2783624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2784624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 2785992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 27861032fbfdSBengt Jonsson }; 27871032fbfdSBengt Jonsson 27881032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 27891032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 27901032fbfdSBengt Jonsson .constraints = { 27911032fbfdSBengt Jonsson .name = "db8500-vape", 27921032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 27931e45860fSMark Brown .always_on = true, 27941032fbfdSBengt Jonsson }, 27951032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 27961032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 27971032fbfdSBengt Jonsson }, 27981032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 27991032fbfdSBengt Jonsson .constraints = { 28001032fbfdSBengt Jonsson .name = "db8500-varm", 28011032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28021032fbfdSBengt Jonsson }, 28031032fbfdSBengt Jonsson }, 28041032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 28051032fbfdSBengt Jonsson .constraints = { 28061032fbfdSBengt Jonsson .name = "db8500-vmodem", 28071032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28081032fbfdSBengt Jonsson }, 28091032fbfdSBengt Jonsson }, 28101032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 28111032fbfdSBengt Jonsson .constraints = { 28121032fbfdSBengt Jonsson .name = "db8500-vpll", 28131032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28141032fbfdSBengt Jonsson }, 28151032fbfdSBengt Jonsson }, 28161032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 28171032fbfdSBengt Jonsson .constraints = { 28181032fbfdSBengt Jonsson .name = "db8500-vsmps1", 28191032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28201032fbfdSBengt Jonsson }, 28211032fbfdSBengt Jonsson }, 28221032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 28231032fbfdSBengt Jonsson .constraints = { 28241032fbfdSBengt Jonsson .name = "db8500-vsmps2", 28251032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28261032fbfdSBengt Jonsson }, 28271032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 28281032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 28291032fbfdSBengt Jonsson }, 28301032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 28311032fbfdSBengt Jonsson .constraints = { 28321032fbfdSBengt Jonsson .name = "db8500-vsmps3", 28331032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28341032fbfdSBengt Jonsson }, 28351032fbfdSBengt Jonsson }, 28361032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 28371032fbfdSBengt Jonsson .constraints = { 28381032fbfdSBengt Jonsson .name = "db8500-vrf1", 28391032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28401032fbfdSBengt Jonsson }, 28411032fbfdSBengt Jonsson }, 28421032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2843992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 28441032fbfdSBengt Jonsson .constraints = { 28451032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 28461032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28471032fbfdSBengt Jonsson }, 2848624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2849624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 28501032fbfdSBengt Jonsson }, 28511032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 28521032fbfdSBengt Jonsson .constraints = { 28531032fbfdSBengt Jonsson /* "ret" means "retention" */ 28541032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 28551032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28561032fbfdSBengt Jonsson }, 28571032fbfdSBengt Jonsson }, 28581032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2859992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 28601032fbfdSBengt Jonsson .constraints = { 28611032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 28621032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28631032fbfdSBengt Jonsson }, 2864624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2865624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 28661032fbfdSBengt Jonsson }, 28671032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2868992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 28691032fbfdSBengt Jonsson .constraints = { 28701032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 28711032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28721032fbfdSBengt Jonsson }, 2873624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2874624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 28751032fbfdSBengt Jonsson }, 28761032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 28771032fbfdSBengt Jonsson .constraints = { 28781032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 28791032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28801032fbfdSBengt Jonsson }, 28811032fbfdSBengt Jonsson }, 28821032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2883992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 28841032fbfdSBengt Jonsson .constraints = { 28851032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 28861032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28871032fbfdSBengt Jonsson }, 2888624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 2889624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 28901032fbfdSBengt Jonsson }, 28911032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 28921032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 28931032fbfdSBengt Jonsson .constraints = { 28941032fbfdSBengt Jonsson .name = "db8500-sga", 28951032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28961032fbfdSBengt Jonsson }, 2897624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 2898624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2899624e87c2SBengt Jonsson 29001032fbfdSBengt Jonsson }, 29011032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 29021032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29031032fbfdSBengt Jonsson .constraints = { 29041032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 29051032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29061032fbfdSBengt Jonsson }, 29071032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 29081032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 29091032fbfdSBengt Jonsson }, 29101032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 2911992b133aSBengt Jonsson /* 2912992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off, 2913992b133aSBengt Jonsson * no need to hold Vape 2914992b133aSBengt Jonsson */ 29151032fbfdSBengt Jonsson .constraints = { 29161032fbfdSBengt Jonsson .name = "db8500-esram12", 29171032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29181032fbfdSBengt Jonsson }, 2919624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 2920624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 29211032fbfdSBengt Jonsson }, 29221032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 29231032fbfdSBengt Jonsson .constraints = { 29241032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 29251032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29261032fbfdSBengt Jonsson }, 29271032fbfdSBengt Jonsson }, 29281032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 2929992b133aSBengt Jonsson /* 2930992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off, 2931992b133aSBengt Jonsson * no need to hold Vape 2932992b133aSBengt Jonsson */ 29331032fbfdSBengt Jonsson .constraints = { 29341032fbfdSBengt Jonsson .name = "db8500-esram34", 29351032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29361032fbfdSBengt Jonsson }, 2937624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 2938624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 29391032fbfdSBengt Jonsson }, 29401032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 29411032fbfdSBengt Jonsson .constraints = { 29421032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 29431032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29441032fbfdSBengt Jonsson }, 29451032fbfdSBengt Jonsson }, 29461032fbfdSBengt Jonsson }; 29471032fbfdSBengt Jonsson 29486d11d135SLee Jones static struct resource ab8500_resources[] = { 29496d11d135SLee Jones [0] = { 29506d11d135SLee Jones .start = IRQ_DB8500_AB8500, 29516d11d135SLee Jones .end = IRQ_DB8500_AB8500, 29526d11d135SLee Jones .flags = IORESOURCE_IRQ 29536d11d135SLee Jones } 29546d11d135SLee Jones }; 29556d11d135SLee Jones 29563df57bcfSMattias Nilsson static struct mfd_cell db8500_prcmu_devs[] = { 29573df57bcfSMattias Nilsson { 29583df57bcfSMattias Nilsson .name = "db8500-prcmu-regulators", 29595d90322bSLee Jones .of_compatible = "stericsson,db8500-prcmu-regulator", 29601ed7891fSMattias Wallin .platform_data = &db8500_regulators, 29611ed7891fSMattias Wallin .pdata_size = sizeof(db8500_regulators), 29623df57bcfSMattias Nilsson }, 29633df57bcfSMattias Nilsson { 29643df57bcfSMattias Nilsson .name = "cpufreq-u8500", 29655d90322bSLee Jones .of_compatible = "stericsson,cpufreq-u8500", 29663df57bcfSMattias Nilsson }, 29676d11d135SLee Jones { 29686d11d135SLee Jones .name = "ab8500-core", 29696d11d135SLee Jones .of_compatible = "stericsson,ab8500", 29706d11d135SLee Jones .num_resources = ARRAY_SIZE(ab8500_resources), 29716d11d135SLee Jones .resources = ab8500_resources, 29726d11d135SLee Jones .id = AB8500_VERSION_AB8500, 29736d11d135SLee Jones }, 29743df57bcfSMattias Nilsson }; 29753df57bcfSMattias Nilsson 29763df57bcfSMattias Nilsson /** 29773df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 29783df57bcfSMattias Nilsson * 29793df57bcfSMattias Nilsson */ 29809fc63f67SLee Jones static int __devinit db8500_prcmu_probe(struct platform_device *pdev) 29813df57bcfSMattias Nilsson { 2982ca7edd16SLee Jones struct device_node *np = pdev->dev.of_node; 2983ca7edd16SLee Jones int irq = 0, err = 0; 29843df57bcfSMattias Nilsson 29853df57bcfSMattias Nilsson if (ux500_is_svp()) 29863df57bcfSMattias Nilsson return -ENODEV; 29873df57bcfSMattias Nilsson 29880508901cSMattias Nilsson init_prcm_registers(); 2989d65e12d7SMattias Nilsson 29903df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 2991c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 29923df57bcfSMattias Nilsson 2993ca7edd16SLee Jones if (np) 2994ca7edd16SLee Jones irq = platform_get_irq(pdev, 0); 2995ca7edd16SLee Jones 2996ca7edd16SLee Jones if (!np || irq <= 0) 2997ca7edd16SLee Jones irq = IRQ_DB8500_PRCMU1; 2998ca7edd16SLee Jones 2999ca7edd16SLee Jones err = request_threaded_irq(irq, prcmu_irq_handler, 30003df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 30013df57bcfSMattias Nilsson if (err < 0) { 30023df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 30033df57bcfSMattias Nilsson err = -EBUSY; 30043df57bcfSMattias Nilsson goto no_irq_return; 30053df57bcfSMattias Nilsson } 30063df57bcfSMattias Nilsson 30073df57bcfSMattias Nilsson if (cpu_is_u8500v20_or_later()) 30083df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 30093df57bcfSMattias Nilsson 30103df57bcfSMattias Nilsson err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3011ca7edd16SLee Jones ARRAY_SIZE(db8500_prcmu_devs), NULL, 0); 3012ca7edd16SLee Jones if (err) { 30133df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 3014ca7edd16SLee Jones return err; 3015ca7edd16SLee Jones } 3016ca7edd16SLee Jones 30173df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 30183df57bcfSMattias Nilsson 30193df57bcfSMattias Nilsson no_irq_return: 30203df57bcfSMattias Nilsson return err; 30213df57bcfSMattias Nilsson } 30223c144762SLee Jones static const struct of_device_id db8500_prcmu_match[] = { 30233c144762SLee Jones { .compatible = "stericsson,db8500-prcmu"}, 30243c144762SLee Jones { }, 30253c144762SLee Jones }; 30263df57bcfSMattias Nilsson 30273df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 30283df57bcfSMattias Nilsson .driver = { 30293df57bcfSMattias Nilsson .name = "db8500-prcmu", 30303df57bcfSMattias Nilsson .owner = THIS_MODULE, 30313c144762SLee Jones .of_match_table = db8500_prcmu_match, 30323df57bcfSMattias Nilsson }, 30339fc63f67SLee Jones .probe = db8500_prcmu_probe, 30343df57bcfSMattias Nilsson }; 30353df57bcfSMattias Nilsson 30363df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 30373df57bcfSMattias Nilsson { 30389fc63f67SLee Jones return platform_driver_register(&db8500_prcmu_driver); 30393df57bcfSMattias Nilsson } 30403df57bcfSMattias Nilsson 3041a661aca4SLee Jones core_initcall(db8500_prcmu_init); 30423df57bcfSMattias Nilsson 30433df57bcfSMattias Nilsson MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 30443df57bcfSMattias Nilsson MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 30453df57bcfSMattias Nilsson MODULE_LICENSE("GPL v2"); 3046