1650c2a21SLinus Walleij /* 2650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 3650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 4650c2a21SLinus Walleij * 5650c2a21SLinus Walleij * License Terms: GNU General Public License v2 6650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9650c2a21SLinus Walleij * 10650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij */ 13650c2a21SLinus Walleij #include <linux/module.h> 143df57bcfSMattias Nilsson #include <linux/kernel.h> 153df57bcfSMattias Nilsson #include <linux/delay.h> 16650c2a21SLinus Walleij #include <linux/errno.h> 17650c2a21SLinus Walleij #include <linux/err.h> 183df57bcfSMattias Nilsson #include <linux/spinlock.h> 19650c2a21SLinus Walleij #include <linux/io.h> 203df57bcfSMattias Nilsson #include <linux/slab.h> 21650c2a21SLinus Walleij #include <linux/mutex.h> 22650c2a21SLinus Walleij #include <linux/completion.h> 233df57bcfSMattias Nilsson #include <linux/irq.h> 24650c2a21SLinus Walleij #include <linux/jiffies.h> 25650c2a21SLinus Walleij #include <linux/bitops.h> 263df57bcfSMattias Nilsson #include <linux/fs.h> 27d98a5384SLee Jones #include <linux/of.h> 28f864c46aSLinus Walleij #include <linux/of_irq.h> 293df57bcfSMattias Nilsson #include <linux/platform_device.h> 303df57bcfSMattias Nilsson #include <linux/uaccess.h> 313df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3273180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 333a8e39c9SLee Jones #include <linux/mfd/abx500/ab8500.h> 341032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 351032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 36c280f45fSUlf Hansson #include <linux/cpufreq.h> 37b3aac62bSFabio Baltieri #include <linux/platform_data/ux500_wdt.h> 3855b175d7SArnd Bergmann #include <linux/platform_data/db8500_thermal.h> 3973180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 40650c2a21SLinus Walleij 413df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 423df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 433df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 443df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 453df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 463df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 473df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 483df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 493df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 503df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 513df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 523df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 533df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 543df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 553df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 56650c2a21SLinus Walleij 573df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 583df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 593df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 603df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 61650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 62650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 63650c2a21SLinus Walleij 643df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 653df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 663df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 673df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 68650c2a21SLinus Walleij 693df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 703df57bcfSMattias Nilsson 713df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 723df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 733df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 743df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 753df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 793df57bcfSMattias Nilsson 803df57bcfSMattias Nilsson /* Req Mailboxes */ 813df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 823df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 833df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 843df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 853df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 863df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 873df57bcfSMattias Nilsson 883df57bcfSMattias Nilsson /* Ack Mailboxes */ 893df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 903df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 913df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 923df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 933df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 943df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 953df57bcfSMattias Nilsson 963df57bcfSMattias Nilsson /* Mailbox 0 headers */ 973df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 983df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 993df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 1003df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1013df57bcfSMattias Nilsson 1023df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1033df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1043df57bcfSMattias Nilsson 1053df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1063df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1073df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1083df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1093df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1113df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1123df57bcfSMattias Nilsson 1133df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1143df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1153df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1163df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1173df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1213df57bcfSMattias Nilsson 1223df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1233df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1243df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1253df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1263df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1273df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 128a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1293df57bcfSMattias Nilsson 1303df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1313df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1323df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 133a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 1346b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1 1356b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2 136a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 137a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1383df57bcfSMattias Nilsson 1393df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1403df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1413df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1423df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1433df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1443df57bcfSMattias Nilsson 1453df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1463df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1473df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1483df57bcfSMattias Nilsson 1493df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1503df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1513df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1523df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1533df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1603df57bcfSMattias Nilsson 1613df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1623df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1633df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1643df57bcfSMattias Nilsson 1653df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1663df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1673df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1683df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1693df57bcfSMattias Nilsson 1703df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1713df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1723df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1733df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1743df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1783df57bcfSMattias Nilsson 1793df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1803df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1813df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1823df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1833df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1843df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 185a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 186a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 187a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 188a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1903df57bcfSMattias Nilsson 1913df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1923df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1933df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1943df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1953df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 2003df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2013df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 202a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 203a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 204a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 205a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 206a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 207a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 208a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2093df57bcfSMattias Nilsson 2103df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2113df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2123df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2133df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2143df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2157a4f2609SLinus Walleij #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) 2167a4f2609SLinus Walleij #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) 2173df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2183df57bcfSMattias Nilsson 2193df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2203df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2213df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2223df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2233df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2243df57bcfSMattias Nilsson 2253df57bcfSMattias Nilsson #define NUM_MB 8 2263df57bcfSMattias Nilsson #define MBOX_BIT BIT 2273df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2283df57bcfSMattias Nilsson 2293df57bcfSMattias Nilsson /* 2303df57bcfSMattias Nilsson * Wakeups/IRQs 2313df57bcfSMattias Nilsson */ 2323df57bcfSMattias Nilsson 2333df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2343df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2353df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2363df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2373df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2383df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2623df57bcfSMattias Nilsson 263b58d12feSMattias Nilsson static struct { 264b58d12feSMattias Nilsson bool valid; 265b58d12feSMattias Nilsson struct prcmu_fw_version version; 266b58d12feSMattias Nilsson } fw_info; 267b58d12feSMattias Nilsson 268f3f1f0a1SLee Jones static struct irq_domain *db8500_irq_domain; 269f3f1f0a1SLee Jones 2703df57bcfSMattias Nilsson /* 2713df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2723df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2733df57bcfSMattias Nilsson * 2743df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2753df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2763df57bcfSMattias Nilsson * around, to further complicate matters.) 2773df57bcfSMattias Nilsson */ 27855b175d7SArnd Bergmann #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name)) 2793df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 28055b175d7SArnd Bergmann 28155b175d7SArnd Bergmann #define IRQ_PRCMU_RTC 0 28255b175d7SArnd Bergmann #define IRQ_PRCMU_RTT0 1 28355b175d7SArnd Bergmann #define IRQ_PRCMU_RTT1 2 28455b175d7SArnd Bergmann #define IRQ_PRCMU_HSI0 3 28555b175d7SArnd Bergmann #define IRQ_PRCMU_HSI1 4 28655b175d7SArnd Bergmann #define IRQ_PRCMU_CA_WAKE 5 28755b175d7SArnd Bergmann #define IRQ_PRCMU_USB 6 28855b175d7SArnd Bergmann #define IRQ_PRCMU_ABB 7 28955b175d7SArnd Bergmann #define IRQ_PRCMU_ABB_FIFO 8 29055b175d7SArnd Bergmann #define IRQ_PRCMU_ARM 9 29155b175d7SArnd Bergmann #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10 29255b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO0 11 29355b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO1 12 29455b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO2 13 29555b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO3 14 29655b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO4 15 29755b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO5 16 29855b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO6 17 29955b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO7 18 30055b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO8 19 30155b175d7SArnd Bergmann #define IRQ_PRCMU_CA_SLEEP 20 30255b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_LOW 21 30355b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_HIGH 22 30455b175d7SArnd Bergmann #define NUM_PRCMU_WAKEUPS 23 30555b175d7SArnd Bergmann 3063df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 3073df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 3083df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 3093df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 3103df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 3113df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 3123df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 3133df57bcfSMattias Nilsson IRQ_ENTRY(USB), 3143df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 3153df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 3163df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 3173df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 3183df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 3193df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 3203df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 3213df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 3223df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 3233df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 3243df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 3253df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 3263df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3273df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3283df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3293df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 330650c2a21SLinus Walleij }; 331650c2a21SLinus Walleij 3323df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3333df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3343df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3353df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3363df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3373df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3383df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3393df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3403df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3413df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3423df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3433df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3443df57bcfSMattias Nilsson }; 3453df57bcfSMattias Nilsson 3463df57bcfSMattias Nilsson /* 3473df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3483df57bcfSMattias Nilsson * @lock: The transaction lock. 3493df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3503df57bcfSMattias Nilsson * the request data. 3513df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3523df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3533df57bcfSMattias Nilsson */ 3543df57bcfSMattias Nilsson static struct { 3553df57bcfSMattias Nilsson spinlock_t lock; 3563df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3573df57bcfSMattias Nilsson struct work_struct mask_work; 3583df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3593df57bcfSMattias Nilsson struct completion ac_wake_work; 3603df57bcfSMattias Nilsson struct { 3613df57bcfSMattias Nilsson u32 dbb_irqs; 3623df57bcfSMattias Nilsson u32 dbb_wakeups; 3633df57bcfSMattias Nilsson u32 abb_events; 3643df57bcfSMattias Nilsson } req; 3653df57bcfSMattias Nilsson } mb0_transfer; 3663df57bcfSMattias Nilsson 3673df57bcfSMattias Nilsson /* 3683df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3693df57bcfSMattias Nilsson * @lock: The transaction lock. 3703df57bcfSMattias Nilsson * @work: The transaction completion structure. 3714d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP. 3723df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3733df57bcfSMattias Nilsson */ 374650c2a21SLinus Walleij static struct { 375650c2a21SLinus Walleij struct mutex lock; 376650c2a21SLinus Walleij struct completion work; 3774d64d2e3SMattias Nilsson u8 ape_opp; 378650c2a21SLinus Walleij struct { 3793df57bcfSMattias Nilsson u8 header; 380650c2a21SLinus Walleij u8 arm_opp; 381650c2a21SLinus Walleij u8 ape_opp; 3823df57bcfSMattias Nilsson u8 ape_voltage_status; 383650c2a21SLinus Walleij } ack; 384650c2a21SLinus Walleij } mb1_transfer; 385650c2a21SLinus Walleij 3863df57bcfSMattias Nilsson /* 3873df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3883df57bcfSMattias Nilsson * @lock: The transaction lock. 3893df57bcfSMattias Nilsson * @work: The transaction completion structure. 3903df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3913df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3923df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3933df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3943df57bcfSMattias Nilsson */ 395650c2a21SLinus Walleij static struct { 396650c2a21SLinus Walleij struct mutex lock; 397650c2a21SLinus Walleij struct completion work; 3983df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 3993df57bcfSMattias Nilsson bool auto_pm_enabled; 4003df57bcfSMattias Nilsson struct { 4013df57bcfSMattias Nilsson u8 status; 4023df57bcfSMattias Nilsson } ack; 4033df57bcfSMattias Nilsson } mb2_transfer; 4043df57bcfSMattias Nilsson 4053df57bcfSMattias Nilsson /* 4063df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 4073df57bcfSMattias Nilsson * @lock: The request lock. 4083df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 4093df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 4103df57bcfSMattias Nilsson */ 4113df57bcfSMattias Nilsson static struct { 4123df57bcfSMattias Nilsson spinlock_t lock; 4133df57bcfSMattias Nilsson struct mutex sysclk_lock; 4143df57bcfSMattias Nilsson struct completion sysclk_work; 4153df57bcfSMattias Nilsson } mb3_transfer; 4163df57bcfSMattias Nilsson 4173df57bcfSMattias Nilsson /* 4183df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 4193df57bcfSMattias Nilsson * @lock: The transaction lock. 4203df57bcfSMattias Nilsson * @work: The transaction completion structure. 4213df57bcfSMattias Nilsson */ 4223df57bcfSMattias Nilsson static struct { 4233df57bcfSMattias Nilsson struct mutex lock; 4243df57bcfSMattias Nilsson struct completion work; 4253df57bcfSMattias Nilsson } mb4_transfer; 4263df57bcfSMattias Nilsson 4273df57bcfSMattias Nilsson /* 4283df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4293df57bcfSMattias Nilsson * @lock: The transaction lock. 4303df57bcfSMattias Nilsson * @work: The transaction completion structure. 4313df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4323df57bcfSMattias Nilsson */ 4333df57bcfSMattias Nilsson static struct { 4343df57bcfSMattias Nilsson struct mutex lock; 4353df57bcfSMattias Nilsson struct completion work; 436650c2a21SLinus Walleij struct { 437650c2a21SLinus Walleij u8 status; 438650c2a21SLinus Walleij u8 value; 439650c2a21SLinus Walleij } ack; 440650c2a21SLinus Walleij } mb5_transfer; 441650c2a21SLinus Walleij 4423df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4433df57bcfSMattias Nilsson 4443df57bcfSMattias Nilsson /* Spinlocks */ 445b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock); 4463df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4473df57bcfSMattias Nilsson 4483df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4493df57bcfSMattias Nilsson static __iomem void *tcdm_base; 450b047d981SLinus Walleij static __iomem void *prcmu_base; 4513df57bcfSMattias Nilsson 4523df57bcfSMattias Nilsson struct clk_mgt { 453b047d981SLinus Walleij u32 offset; 4543df57bcfSMattias Nilsson u32 pllsw; 4556b6fae2bSMattias Nilsson int branch; 4566b6fae2bSMattias Nilsson bool clk38div; 4576b6fae2bSMattias Nilsson }; 4586b6fae2bSMattias Nilsson 4596b6fae2bSMattias Nilsson enum { 4606b6fae2bSMattias Nilsson PLL_RAW, 4616b6fae2bSMattias Nilsson PLL_FIX, 4626b6fae2bSMattias Nilsson PLL_DIV 4633df57bcfSMattias Nilsson }; 4643df57bcfSMattias Nilsson 4653df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4663df57bcfSMattias Nilsson 4676b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 4686b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 4696746f232SSachin Kamat static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4706b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 4736b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 4746b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 4756b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 4766b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 4776b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 4786b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 4796b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 4806b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 4816b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 4826b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 4836b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 4846b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 4856b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 4866b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 4876b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 4886b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 4896b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 4906b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 4916b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 4926b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 4936b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 4946b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 4956b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 4966b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 4976b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 4986b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 4996b6fae2bSMattias Nilsson }; 5006b6fae2bSMattias Nilsson 5016b6fae2bSMattias Nilsson struct dsiclk { 5026b6fae2bSMattias Nilsson u32 divsel_mask; 5036b6fae2bSMattias Nilsson u32 divsel_shift; 5046b6fae2bSMattias Nilsson u32 divsel; 5056b6fae2bSMattias Nilsson }; 5066b6fae2bSMattias Nilsson 5076b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = { 5086b6fae2bSMattias Nilsson { 5096b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 5106b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 5116b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 5126b6fae2bSMattias Nilsson }, 5136b6fae2bSMattias Nilsson { 5146b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 5156b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 5166b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 5176b6fae2bSMattias Nilsson } 5186b6fae2bSMattias Nilsson }; 5196b6fae2bSMattias Nilsson 5206b6fae2bSMattias Nilsson struct dsiescclk { 5216b6fae2bSMattias Nilsson u32 en; 5226b6fae2bSMattias Nilsson u32 div_mask; 5236b6fae2bSMattias Nilsson u32 div_shift; 5246b6fae2bSMattias Nilsson }; 5256b6fae2bSMattias Nilsson 5266b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = { 5276b6fae2bSMattias Nilsson { 5286b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 5296b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 5306b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 5316b6fae2bSMattias Nilsson }, 5326b6fae2bSMattias Nilsson { 5336b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 5346b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 5356b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 5366b6fae2bSMattias Nilsson }, 5376b6fae2bSMattias Nilsson { 5386b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 5396b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 5406b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 5416b6fae2bSMattias Nilsson } 5423df57bcfSMattias Nilsson }; 5433df57bcfSMattias Nilsson 54420aee5b6SMichel Jaouen 5453df57bcfSMattias Nilsson /* 5463df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 5473df57bcfSMattias Nilsson */ 5483df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 5493df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 5503df57bcfSMattias Nilsson 5513df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 5523df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 5533df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5543df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5553df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5563df57bcfSMattias Nilsson 5573df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5583df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5593df57bcfSMattias Nilsson 5603df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5613df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5623df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5633df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5643df57bcfSMattias Nilsson 5653df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5663df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5673df57bcfSMattias Nilsson 5683df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5693df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5703df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5713df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5723df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5733df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5743df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5753df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5763df57bcfSMattias Nilsson 5773df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5783df57bcfSMattias Nilsson 57973180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5803df57bcfSMattias Nilsson { 5813df57bcfSMattias Nilsson int i; 5823df57bcfSMattias Nilsson 5833df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 584c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5853df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 586c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5873df57bcfSMattias Nilsson 5883df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 589c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 590c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5913df57bcfSMattias Nilsson /* Enable Escape clocks */ 592c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5933df57bcfSMattias Nilsson 5943df57bcfSMattias Nilsson /* Start DSI PLL */ 595c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5963df57bcfSMattias Nilsson /* Reset DSI PLL */ 597c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 5983df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 599c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 6003df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 6013df57bcfSMattias Nilsson break; 6023df57bcfSMattias Nilsson udelay(100); 6033df57bcfSMattias Nilsson } 6043df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 605c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 6063df57bcfSMattias Nilsson return 0; 6073df57bcfSMattias Nilsson } 6083df57bcfSMattias Nilsson 60973180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 6103df57bcfSMattias Nilsson { 6113df57bcfSMattias Nilsson /* Disable dsi pll */ 612c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 6133df57bcfSMattias Nilsson /* Disable escapeclock */ 614c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 6153df57bcfSMattias Nilsson return 0; 6163df57bcfSMattias Nilsson } 6173df57bcfSMattias Nilsson 61873180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 6193df57bcfSMattias Nilsson { 6203df57bcfSMattias Nilsson unsigned long flags; 6213df57bcfSMattias Nilsson 6223df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 6233df57bcfSMattias Nilsson 6243df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 625c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 6263df57bcfSMattias Nilsson cpu_relax(); 6273df57bcfSMattias Nilsson 628b047d981SLinus Walleij writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); 629b047d981SLinus Walleij writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); 630b047d981SLinus Walleij writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); 6313df57bcfSMattias Nilsson 6323df57bcfSMattias Nilsson /* Release the HW semaphore. */ 633c553b3caSMattias Nilsson writel(0, PRCM_SEM); 6343df57bcfSMattias Nilsson 6353df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 6363df57bcfSMattias Nilsson 6373df57bcfSMattias Nilsson return 0; 6383df57bcfSMattias Nilsson } 6393df57bcfSMattias Nilsson 640b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg) 6413df57bcfSMattias Nilsson { 642b047d981SLinus Walleij return readl(prcmu_base + reg); 6433df57bcfSMattias Nilsson } 6443df57bcfSMattias Nilsson 645b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value) 6463df57bcfSMattias Nilsson { 6473df57bcfSMattias Nilsson unsigned long flags; 6483df57bcfSMattias Nilsson 649b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 650b047d981SLinus Walleij writel(value, (prcmu_base + reg)); 651b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 652b4a6dbd5SMattias Nilsson } 653b4a6dbd5SMattias Nilsson 654b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 655b4a6dbd5SMattias Nilsson { 656b4a6dbd5SMattias Nilsson u32 val; 657b4a6dbd5SMattias Nilsson unsigned long flags; 658b4a6dbd5SMattias Nilsson 659b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 660b047d981SLinus Walleij val = readl(prcmu_base + reg); 661b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask)); 662b047d981SLinus Walleij writel(val, (prcmu_base + reg)); 663b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 6643df57bcfSMattias Nilsson } 6653df57bcfSMattias Nilsson 666b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void) 667b58d12feSMattias Nilsson { 668b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL; 669b58d12feSMattias Nilsson } 670b58d12feSMattias Nilsson 6713df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6723df57bcfSMattias Nilsson { 6733df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6743df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6753df57bcfSMattias Nilsson } 6763df57bcfSMattias Nilsson 6773df57bcfSMattias Nilsson /** 6783df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6793df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6803df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6813df57bcfSMattias Nilsson * 6823df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6833df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6843df57bcfSMattias Nilsson */ 6853df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6863df57bcfSMattias Nilsson { 6873df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 6883df57bcfSMattias Nilsson return -EINVAL; 6893df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 6903df57bcfSMattias Nilsson return 0; 6913df57bcfSMattias Nilsson } 6923df57bcfSMattias Nilsson 6933df57bcfSMattias Nilsson /** 6943df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 6953df57bcfSMattias Nilsson * Returns: the power transition that has last happened 6963df57bcfSMattias Nilsson * 6973df57bcfSMattias Nilsson * This function can return the following transitions- 6983df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6993df57bcfSMattias Nilsson */ 7003df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 7013df57bcfSMattias Nilsson { 7023df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 7033df57bcfSMattias Nilsson } 7043df57bcfSMattias Nilsson 7053df57bcfSMattias Nilsson /** 7063df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 7073df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 7083df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 7093df57bcfSMattias Nilsson */ 7103df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 7113df57bcfSMattias Nilsson { 7123df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 7133df57bcfSMattias Nilsson } 7143df57bcfSMattias Nilsson 7153df57bcfSMattias Nilsson /** 7163df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 7173df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 7183df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 7193df57bcfSMattias Nilsson * @div: The divider to be applied. 7203df57bcfSMattias Nilsson * 7213df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 7223df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 7233df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 7243df57bcfSMattias Nilsson */ 7253df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 7263df57bcfSMattias Nilsson { 7273df57bcfSMattias Nilsson static int requests[2]; 7283df57bcfSMattias Nilsson int r = 0; 7293df57bcfSMattias Nilsson unsigned long flags; 7303df57bcfSMattias Nilsson u32 val; 7313df57bcfSMattias Nilsson u32 bits; 7323df57bcfSMattias Nilsson u32 mask; 7333df57bcfSMattias Nilsson u32 div_mask; 7343df57bcfSMattias Nilsson 7353df57bcfSMattias Nilsson BUG_ON(clkout > 1); 7363df57bcfSMattias Nilsson BUG_ON(div > 63); 7373df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 7383df57bcfSMattias Nilsson 7393df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7403df57bcfSMattias Nilsson return -EINVAL; 7413df57bcfSMattias Nilsson 742a7e46317SArnd Bergmann if (clkout == 0) { 7433df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7443df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7453df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7463df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 747a7e46317SArnd Bergmann } else { 7483df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7493df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7503df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7513df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7523df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7533df57bcfSMattias Nilsson } 7543df57bcfSMattias Nilsson bits &= mask; 7553df57bcfSMattias Nilsson 7563df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7573df57bcfSMattias Nilsson 758c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7593df57bcfSMattias Nilsson if (val & div_mask) { 7603df57bcfSMattias Nilsson if (div) { 7613df57bcfSMattias Nilsson if ((val & mask) != bits) { 7623df57bcfSMattias Nilsson r = -EBUSY; 7633df57bcfSMattias Nilsson goto unlock_and_return; 7643df57bcfSMattias Nilsson } 7653df57bcfSMattias Nilsson } else { 7663df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7673df57bcfSMattias Nilsson r = -EINVAL; 7683df57bcfSMattias Nilsson goto unlock_and_return; 7693df57bcfSMattias Nilsson } 7703df57bcfSMattias Nilsson } 7713df57bcfSMattias Nilsson } 772c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7733df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7743df57bcfSMattias Nilsson 7753df57bcfSMattias Nilsson unlock_and_return: 7763df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7773df57bcfSMattias Nilsson 7783df57bcfSMattias Nilsson return r; 7793df57bcfSMattias Nilsson } 7803df57bcfSMattias Nilsson 78173180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7823df57bcfSMattias Nilsson { 7833df57bcfSMattias Nilsson unsigned long flags; 7843df57bcfSMattias Nilsson 7853df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 7863df57bcfSMattias Nilsson 7873df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 7883df57bcfSMattias Nilsson 789c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 7903df57bcfSMattias Nilsson cpu_relax(); 7913df57bcfSMattias Nilsson 7923df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 7933df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 7943df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 7953df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 7963df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 7973df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 798c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 7993df57bcfSMattias Nilsson 8003df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8013df57bcfSMattias Nilsson 8023df57bcfSMattias Nilsson return 0; 8033df57bcfSMattias Nilsson } 8043df57bcfSMattias Nilsson 8054d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void) 8064d64d2e3SMattias Nilsson { 8074d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 8084d64d2e3SMattias Nilsson } 8094d64d2e3SMattias Nilsson 8103df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 8113df57bcfSMattias Nilsson static void config_wakeups(void) 8123df57bcfSMattias Nilsson { 8133df57bcfSMattias Nilsson const u8 header[2] = { 8143df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 8153df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 8163df57bcfSMattias Nilsson }; 8173df57bcfSMattias Nilsson static u32 last_dbb_events; 8183df57bcfSMattias Nilsson static u32 last_abb_events; 8193df57bcfSMattias Nilsson u32 dbb_events; 8203df57bcfSMattias Nilsson u32 abb_events; 8213df57bcfSMattias Nilsson unsigned int i; 8223df57bcfSMattias Nilsson 8233df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 8243df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 8253df57bcfSMattias Nilsson 8263df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 8273df57bcfSMattias Nilsson 8283df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 8293df57bcfSMattias Nilsson return; 8303df57bcfSMattias Nilsson 8313df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 832c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 8333df57bcfSMattias Nilsson cpu_relax(); 8343df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 8353df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 8363df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 837c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8383df57bcfSMattias Nilsson } 8393df57bcfSMattias Nilsson last_dbb_events = dbb_events; 8403df57bcfSMattias Nilsson last_abb_events = abb_events; 8413df57bcfSMattias Nilsson } 8423df57bcfSMattias Nilsson 84373180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 8443df57bcfSMattias Nilsson { 8453df57bcfSMattias Nilsson unsigned long flags; 8463df57bcfSMattias Nilsson u32 bits; 8473df57bcfSMattias Nilsson int i; 8483df57bcfSMattias Nilsson 8493df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 8503df57bcfSMattias Nilsson 8513df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 8523df57bcfSMattias Nilsson if (wakeups & BIT(i)) 8533df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 8543df57bcfSMattias Nilsson } 8553df57bcfSMattias Nilsson 8563df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8573df57bcfSMattias Nilsson 8583df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 8593df57bcfSMattias Nilsson config_wakeups(); 8603df57bcfSMattias Nilsson 8613df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8623df57bcfSMattias Nilsson } 8633df57bcfSMattias Nilsson 86473180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 8653df57bcfSMattias Nilsson { 8663df57bcfSMattias Nilsson unsigned long flags; 8673df57bcfSMattias Nilsson 8683df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8693df57bcfSMattias Nilsson 8703df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 8713df57bcfSMattias Nilsson config_wakeups(); 8723df57bcfSMattias Nilsson 8733df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8743df57bcfSMattias Nilsson } 8753df57bcfSMattias Nilsson 87673180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 8773df57bcfSMattias Nilsson { 8783df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 8793df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 8803df57bcfSMattias Nilsson else 8813df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 8823df57bcfSMattias Nilsson } 8833df57bcfSMattias Nilsson 8843df57bcfSMattias Nilsson /** 88573180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 8863df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 8873df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 8883df57bcfSMattias Nilsson * 8893df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 8903df57bcfSMattias Nilsson */ 89173180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 8923df57bcfSMattias Nilsson { 8933df57bcfSMattias Nilsson int r; 8943df57bcfSMattias Nilsson 8953df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 8963df57bcfSMattias Nilsson return -EINVAL; 8973df57bcfSMattias Nilsson 8983df57bcfSMattias Nilsson r = 0; 8993df57bcfSMattias Nilsson 9003df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 9013df57bcfSMattias Nilsson 902c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 9033df57bcfSMattias Nilsson cpu_relax(); 9043df57bcfSMattias Nilsson 9053df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 9063df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 9073df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 9083df57bcfSMattias Nilsson 909c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 9103df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 9113df57bcfSMattias Nilsson 9123df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 9133df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 9143df57bcfSMattias Nilsson r = -EIO; 9153df57bcfSMattias Nilsson 9163df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 9173df57bcfSMattias Nilsson 9183df57bcfSMattias Nilsson return r; 9193df57bcfSMattias Nilsson } 9203df57bcfSMattias Nilsson 9213df57bcfSMattias Nilsson /** 92273180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 9233df57bcfSMattias Nilsson * 9243df57bcfSMattias Nilsson * Returns: the current ARM OPP 9253df57bcfSMattias Nilsson */ 92673180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 9273df57bcfSMattias Nilsson { 9283df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 9293df57bcfSMattias Nilsson } 9303df57bcfSMattias Nilsson 9313df57bcfSMattias Nilsson /** 9320508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP 9333df57bcfSMattias Nilsson * 9343df57bcfSMattias Nilsson * Returns: the current DDR OPP 9353df57bcfSMattias Nilsson */ 9360508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void) 9373df57bcfSMattias Nilsson { 938c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 9393df57bcfSMattias Nilsson } 9403df57bcfSMattias Nilsson 9413df57bcfSMattias Nilsson /** 9420508901cSMattias Nilsson * db8500_set_ddr_opp - set the appropriate DDR OPP 9433df57bcfSMattias Nilsson * @opp: The new DDR operating point to which transition is to be made 9443df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 9453df57bcfSMattias Nilsson * 9463df57bcfSMattias Nilsson * This function sets the operating point of the DDR. 9473df57bcfSMattias Nilsson */ 9487a4f2609SLinus Walleij static bool enable_set_ddr_opp; 9490508901cSMattias Nilsson int db8500_prcmu_set_ddr_opp(u8 opp) 9503df57bcfSMattias Nilsson { 9513df57bcfSMattias Nilsson if (opp < DDR_100_OPP || opp > DDR_25_OPP) 9523df57bcfSMattias Nilsson return -EINVAL; 9533df57bcfSMattias Nilsson /* Changing the DDR OPP can hang the hardware pre-v21 */ 9547a4f2609SLinus Walleij if (enable_set_ddr_opp) 955c553b3caSMattias Nilsson writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); 9563df57bcfSMattias Nilsson 9573df57bcfSMattias Nilsson return 0; 9583df57bcfSMattias Nilsson } 9596b6fae2bSMattias Nilsson 9604d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 9614d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable) 9624d64d2e3SMattias Nilsson { 963b047d981SLinus Walleij u32 clock_reg[] = { 9644d64d2e3SMattias Nilsson PRCM_ACLK_MGT, 9654d64d2e3SMattias Nilsson PRCM_DMACLK_MGT 9664d64d2e3SMattias Nilsson }; 9674d64d2e3SMattias Nilsson unsigned long flags; 9684d64d2e3SMattias Nilsson unsigned int i; 9694d64d2e3SMattias Nilsson 9704d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 9714d64d2e3SMattias Nilsson 9724d64d2e3SMattias Nilsson /* Grab the HW semaphore. */ 9734d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 9744d64d2e3SMattias Nilsson cpu_relax(); 9754d64d2e3SMattias Nilsson 9764d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 9774d64d2e3SMattias Nilsson u32 val; 9784d64d2e3SMattias Nilsson u32 div; 9794d64d2e3SMattias Nilsson 980b047d981SLinus Walleij val = readl(prcmu_base + clock_reg[i]); 9814d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 9824d64d2e3SMattias Nilsson if (enable) { 9834d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) { 9844d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n", 9854d64d2e3SMattias Nilsson div, __func__); 9864d64d2e3SMattias Nilsson goto unlock_and_return; 9874d64d2e3SMattias Nilsson } 9884d64d2e3SMattias Nilsson div <<= 1; 9894d64d2e3SMattias Nilsson } else { 9904d64d2e3SMattias Nilsson if (div <= 2) 9914d64d2e3SMattias Nilsson goto unlock_and_return; 9924d64d2e3SMattias Nilsson div >>= 1; 9934d64d2e3SMattias Nilsson } 9944d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 9954d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 996b047d981SLinus Walleij writel(val, prcmu_base + clock_reg[i]); 9974d64d2e3SMattias Nilsson } 9984d64d2e3SMattias Nilsson 9994d64d2e3SMattias Nilsson unlock_and_return: 10004d64d2e3SMattias Nilsson /* Release the HW semaphore. */ 10014d64d2e3SMattias Nilsson writel(0, PRCM_SEM); 10024d64d2e3SMattias Nilsson 10034d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 10044d64d2e3SMattias Nilsson } 10054d64d2e3SMattias Nilsson 10063df57bcfSMattias Nilsson /** 10070508901cSMattias Nilsson * db8500_set_ape_opp - set the appropriate APE OPP 10083df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 10093df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10103df57bcfSMattias Nilsson * 10113df57bcfSMattias Nilsson * This function sets the operating point of the APE. 10123df57bcfSMattias Nilsson */ 10130508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp) 10143df57bcfSMattias Nilsson { 10153df57bcfSMattias Nilsson int r = 0; 10163df57bcfSMattias Nilsson 10174d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp) 10184d64d2e3SMattias Nilsson return 0; 10194d64d2e3SMattias Nilsson 10203df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10213df57bcfSMattias Nilsson 10224d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 10234d64d2e3SMattias Nilsson request_even_slower_clocks(false); 10244d64d2e3SMattias Nilsson 10254d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 10264d64d2e3SMattias Nilsson goto skip_message; 10274d64d2e3SMattias Nilsson 1028c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10293df57bcfSMattias Nilsson cpu_relax(); 10303df57bcfSMattias Nilsson 10313df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10323df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 10334d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 10344d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 10353df57bcfSMattias Nilsson 1036c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10373df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10383df57bcfSMattias Nilsson 10393df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 10403df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 10413df57bcfSMattias Nilsson r = -EIO; 10423df57bcfSMattias Nilsson 10434d64d2e3SMattias Nilsson skip_message: 10444d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 10454d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 10464d64d2e3SMattias Nilsson request_even_slower_clocks(true); 10474d64d2e3SMattias Nilsson if (!r) 10484d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp; 10494d64d2e3SMattias Nilsson 10503df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10513df57bcfSMattias Nilsson 10523df57bcfSMattias Nilsson return r; 10533df57bcfSMattias Nilsson } 10543df57bcfSMattias Nilsson 10553df57bcfSMattias Nilsson /** 10560508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP 10573df57bcfSMattias Nilsson * 10583df57bcfSMattias Nilsson * Returns: the current APE OPP 10593df57bcfSMattias Nilsson */ 10600508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void) 10613df57bcfSMattias Nilsson { 10623df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 10633df57bcfSMattias Nilsson } 10643df57bcfSMattias Nilsson 10653df57bcfSMattias Nilsson /** 1066686f871bSUlf Hansson * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 10673df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 10683df57bcfSMattias Nilsson * 10693df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 10703df57bcfSMattias Nilsson */ 1071686f871bSUlf Hansson int db8500_prcmu_request_ape_opp_100_voltage(bool enable) 10723df57bcfSMattias Nilsson { 10733df57bcfSMattias Nilsson int r = 0; 10743df57bcfSMattias Nilsson u8 header; 10753df57bcfSMattias Nilsson static unsigned int requests; 10763df57bcfSMattias Nilsson 10773df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10783df57bcfSMattias Nilsson 10793df57bcfSMattias Nilsson if (enable) { 10803df57bcfSMattias Nilsson if (0 != requests++) 10813df57bcfSMattias Nilsson goto unlock_and_return; 10823df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 10833df57bcfSMattias Nilsson } else { 10843df57bcfSMattias Nilsson if (requests == 0) { 10853df57bcfSMattias Nilsson r = -EIO; 10863df57bcfSMattias Nilsson goto unlock_and_return; 10873df57bcfSMattias Nilsson } else if (1 != requests--) { 10883df57bcfSMattias Nilsson goto unlock_and_return; 10893df57bcfSMattias Nilsson } 10903df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 10913df57bcfSMattias Nilsson } 10923df57bcfSMattias Nilsson 1093c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10943df57bcfSMattias Nilsson cpu_relax(); 10953df57bcfSMattias Nilsson 10963df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10973df57bcfSMattias Nilsson 1098c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10993df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11003df57bcfSMattias Nilsson 11013df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 11023df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 11033df57bcfSMattias Nilsson r = -EIO; 11043df57bcfSMattias Nilsson 11053df57bcfSMattias Nilsson unlock_and_return: 11063df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11073df57bcfSMattias Nilsson 11083df57bcfSMattias Nilsson return r; 11093df57bcfSMattias Nilsson } 11103df57bcfSMattias Nilsson 11113df57bcfSMattias Nilsson /** 11123df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 11133df57bcfSMattias Nilsson * 11143df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 11153df57bcfSMattias Nilsson */ 11163df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 11173df57bcfSMattias Nilsson { 11183df57bcfSMattias Nilsson int r = 0; 11193df57bcfSMattias Nilsson 11203df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11213df57bcfSMattias Nilsson 1122c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11233df57bcfSMattias Nilsson cpu_relax(); 11243df57bcfSMattias Nilsson 11253df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 11263df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11273df57bcfSMattias Nilsson 1128c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11293df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11303df57bcfSMattias Nilsson 11313df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 11323df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 11333df57bcfSMattias Nilsson r = -EIO; 11343df57bcfSMattias Nilsson 11353df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11363df57bcfSMattias Nilsson 11373df57bcfSMattias Nilsson return r; 11383df57bcfSMattias Nilsson } 11393df57bcfSMattias Nilsson 11400837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 11410837bb72SMattias Nilsson { 11420837bb72SMattias Nilsson int r = 0; 11430837bb72SMattias Nilsson 11446b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0) 11456b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 11466b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 11470837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 11480837bb72SMattias Nilsson else 11490837bb72SMattias Nilsson return -EINVAL; 11500837bb72SMattias Nilsson 11510837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 11520837bb72SMattias Nilsson 11530837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11540837bb72SMattias Nilsson cpu_relax(); 11550837bb72SMattias Nilsson 11560837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11570837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 11580837bb72SMattias Nilsson 11590837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11600837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 11610837bb72SMattias Nilsson 11620837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 11630837bb72SMattias Nilsson r = -EIO; 11640837bb72SMattias Nilsson 11650837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11660837bb72SMattias Nilsson 11670837bb72SMattias Nilsson return r; 11680837bb72SMattias Nilsson } 11690837bb72SMattias Nilsson 11703df57bcfSMattias Nilsson /** 117173180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 11723df57bcfSMattias Nilsson * @epod_id: The EPOD to set 11733df57bcfSMattias Nilsson * @epod_state: The new EPOD state 11743df57bcfSMattias Nilsson * 11753df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 11763df57bcfSMattias Nilsson * from interrupt context. 11773df57bcfSMattias Nilsson */ 117873180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 11793df57bcfSMattias Nilsson { 11803df57bcfSMattias Nilsson int r = 0; 11813df57bcfSMattias Nilsson bool ram_retention = false; 11823df57bcfSMattias Nilsson int i; 11833df57bcfSMattias Nilsson 11843df57bcfSMattias Nilsson /* check argument */ 11853df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 11863df57bcfSMattias Nilsson 11873df57bcfSMattias Nilsson /* set flag if retention is possible */ 11883df57bcfSMattias Nilsson switch (epod_id) { 11893df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 11903df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 11913df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 11923df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 11933df57bcfSMattias Nilsson ram_retention = true; 11943df57bcfSMattias Nilsson break; 11953df57bcfSMattias Nilsson } 11963df57bcfSMattias Nilsson 11973df57bcfSMattias Nilsson /* check argument */ 11983df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 11993df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 12003df57bcfSMattias Nilsson 12013df57bcfSMattias Nilsson /* get lock */ 12023df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 12033df57bcfSMattias Nilsson 12043df57bcfSMattias Nilsson /* wait for mailbox */ 1205c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 12063df57bcfSMattias Nilsson cpu_relax(); 12073df57bcfSMattias Nilsson 12083df57bcfSMattias Nilsson /* fill in mailbox */ 12093df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 12103df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 12113df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 12123df57bcfSMattias Nilsson 12133df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 12143df57bcfSMattias Nilsson 1215c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 12163df57bcfSMattias Nilsson 12173df57bcfSMattias Nilsson /* 12183df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 12193df57bcfSMattias Nilsson * and we cannot recover if there is an error. 12203df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 12213df57bcfSMattias Nilsson */ 12223df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 12233df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 12243df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 12253df57bcfSMattias Nilsson __func__); 12263df57bcfSMattias Nilsson r = -EIO; 12273df57bcfSMattias Nilsson goto unlock_and_return; 12283df57bcfSMattias Nilsson } 12293df57bcfSMattias Nilsson 12303df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 12313df57bcfSMattias Nilsson r = -EIO; 12323df57bcfSMattias Nilsson 12333df57bcfSMattias Nilsson unlock_and_return: 12343df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 12353df57bcfSMattias Nilsson return r; 12363df57bcfSMattias Nilsson } 12373df57bcfSMattias Nilsson 12383df57bcfSMattias Nilsson /** 12393df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 12403df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 12413df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 12423df57bcfSMattias Nilsson */ 12433df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 12443df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 12453df57bcfSMattias Nilsson { 12463df57bcfSMattias Nilsson u32 sleep_cfg; 12473df57bcfSMattias Nilsson u32 idle_cfg; 12483df57bcfSMattias Nilsson unsigned long flags; 12493df57bcfSMattias Nilsson 12503df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 12513df57bcfSMattias Nilsson 12523df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 12533df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 12543df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 12553df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 12563df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 12573df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 12583df57bcfSMattias Nilsson 12593df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 12603df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 12613df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 12623df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 12633df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 12643df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 12653df57bcfSMattias Nilsson 12663df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 12673df57bcfSMattias Nilsson 12683df57bcfSMattias Nilsson /* 12693df57bcfSMattias Nilsson * The autonomous power management configuration is done through 12703df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 12713df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 12723df57bcfSMattias Nilsson */ 12733df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 12743df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 12753df57bcfSMattias Nilsson 12763df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 12773df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12783df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12793df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12803df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 12813df57bcfSMattias Nilsson 12823df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 12833df57bcfSMattias Nilsson } 12843df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 12853df57bcfSMattias Nilsson 12863df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 12873df57bcfSMattias Nilsson { 12883df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 12893df57bcfSMattias Nilsson } 12903df57bcfSMattias Nilsson 12913df57bcfSMattias Nilsson static int request_sysclk(bool enable) 12923df57bcfSMattias Nilsson { 12933df57bcfSMattias Nilsson int r; 12943df57bcfSMattias Nilsson unsigned long flags; 12953df57bcfSMattias Nilsson 12963df57bcfSMattias Nilsson r = 0; 12973df57bcfSMattias Nilsson 12983df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 12993df57bcfSMattias Nilsson 13003df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 13013df57bcfSMattias Nilsson 1302c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 13033df57bcfSMattias Nilsson cpu_relax(); 13043df57bcfSMattias Nilsson 13053df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 13063df57bcfSMattias Nilsson 13073df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1308c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 13093df57bcfSMattias Nilsson 13103df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 13113df57bcfSMattias Nilsson 13123df57bcfSMattias Nilsson /* 13133df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 13143df57bcfSMattias Nilsson * SysClk, and it succeeds. 13153df57bcfSMattias Nilsson */ 13163df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 13173df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 13183df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 13193df57bcfSMattias Nilsson __func__); 13203df57bcfSMattias Nilsson r = -EIO; 13213df57bcfSMattias Nilsson } 13223df57bcfSMattias Nilsson 13233df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 13243df57bcfSMattias Nilsson 13253df57bcfSMattias Nilsson return r; 13263df57bcfSMattias Nilsson } 13273df57bcfSMattias Nilsson 13283df57bcfSMattias Nilsson static int request_timclk(bool enable) 13293df57bcfSMattias Nilsson { 13303df57bcfSMattias Nilsson u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 13313df57bcfSMattias Nilsson 13323df57bcfSMattias Nilsson if (!enable) 13333df57bcfSMattias Nilsson val |= PRCM_TCR_STOP_TIMERS; 1334c553b3caSMattias Nilsson writel(val, PRCM_TCR); 13353df57bcfSMattias Nilsson 13363df57bcfSMattias Nilsson return 0; 13373df57bcfSMattias Nilsson } 13383df57bcfSMattias Nilsson 13396b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable) 13403df57bcfSMattias Nilsson { 13413df57bcfSMattias Nilsson u32 val; 13423df57bcfSMattias Nilsson unsigned long flags; 13433df57bcfSMattias Nilsson 13443df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 13453df57bcfSMattias Nilsson 13463df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1347c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 13483df57bcfSMattias Nilsson cpu_relax(); 13493df57bcfSMattias Nilsson 1350b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 13513df57bcfSMattias Nilsson if (enable) { 13523df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 13533df57bcfSMattias Nilsson } else { 13543df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 13553df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 13563df57bcfSMattias Nilsson } 1357b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset); 13583df57bcfSMattias Nilsson 13593df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1360c553b3caSMattias Nilsson writel(0, PRCM_SEM); 13613df57bcfSMattias Nilsson 13623df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 13633df57bcfSMattias Nilsson 13643df57bcfSMattias Nilsson return 0; 13653df57bcfSMattias Nilsson } 13663df57bcfSMattias Nilsson 13670837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 13680837bb72SMattias Nilsson { 13690837bb72SMattias Nilsson u32 val; 13700837bb72SMattias Nilsson int ret; 13710837bb72SMattias Nilsson 13720837bb72SMattias Nilsson if (enable) { 13730837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13740837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13750837bb72SMattias Nilsson } 13760837bb72SMattias Nilsson 13776b6fae2bSMattias Nilsson ret = request_clock(clock, enable); 13780837bb72SMattias Nilsson 13790837bb72SMattias Nilsson if (!ret && !enable) { 13800837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13810837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13820837bb72SMattias Nilsson } 13830837bb72SMattias Nilsson 13840837bb72SMattias Nilsson return ret; 13850837bb72SMattias Nilsson } 13860837bb72SMattias Nilsson 13876b6fae2bSMattias Nilsson static inline bool plldsi_locked(void) 13886b6fae2bSMattias Nilsson { 13896b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) & 13906b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 13916b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 13926b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 13936b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 13946b6fae2bSMattias Nilsson } 13956b6fae2bSMattias Nilsson 13966b6fae2bSMattias Nilsson static int request_plldsi(bool enable) 13976b6fae2bSMattias Nilsson { 13986b6fae2bSMattias Nilsson int r = 0; 13996b6fae2bSMattias Nilsson u32 val; 14006b6fae2bSMattias Nilsson 14016b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 14026b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 14036b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 14046b6fae2bSMattias Nilsson 14056b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE); 14066b6fae2bSMattias Nilsson if (enable) 14076b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14086b6fae2bSMattias Nilsson else 14096b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14106b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 14116b6fae2bSMattias Nilsson 14126b6fae2bSMattias Nilsson if (enable) { 14136b6fae2bSMattias Nilsson unsigned int i; 14146b6fae2bSMattias Nilsson bool locked = plldsi_locked(); 14156b6fae2bSMattias Nilsson 14166b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) { 14176b6fae2bSMattias Nilsson udelay(100); 14186b6fae2bSMattias Nilsson locked = plldsi_locked(); 14196b6fae2bSMattias Nilsson } 14206b6fae2bSMattias Nilsson if (locked) { 14216b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, 14226b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET); 14236b6fae2bSMattias Nilsson } else { 14246b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 14256b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 14266b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET); 14276b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14286b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 14296b6fae2bSMattias Nilsson r = -EAGAIN; 14306b6fae2bSMattias Nilsson } 14316b6fae2bSMattias Nilsson } else { 14326b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 14336b6fae2bSMattias Nilsson } 14346b6fae2bSMattias Nilsson return r; 14356b6fae2bSMattias Nilsson } 14366b6fae2bSMattias Nilsson 14376b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable) 14386b6fae2bSMattias Nilsson { 14396b6fae2bSMattias Nilsson u32 val; 14406b6fae2bSMattias Nilsson 14416b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 14426b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 14436b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 14446b6fae2bSMattias Nilsson dsiclk[n].divsel_shift); 14456b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 14466b6fae2bSMattias Nilsson return 0; 14476b6fae2bSMattias Nilsson } 14486b6fae2bSMattias Nilsson 14496b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable) 14506b6fae2bSMattias Nilsson { 14516b6fae2bSMattias Nilsson u32 val; 14526b6fae2bSMattias Nilsson 14536b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 14546b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 14556b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 14566b6fae2bSMattias Nilsson return 0; 14576b6fae2bSMattias Nilsson } 14586b6fae2bSMattias Nilsson 14593df57bcfSMattias Nilsson /** 146073180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 14613df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 14623df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 14633df57bcfSMattias Nilsson * 14643df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 14653df57bcfSMattias Nilsson * Do not use it from any other place! 14663df57bcfSMattias Nilsson */ 146773180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 14683df57bcfSMattias Nilsson { 14696b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK) 14700837bb72SMattias Nilsson return request_sga_clock(clock, enable); 14716b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS) 14726b6fae2bSMattias Nilsson return request_clock(clock, enable); 14736b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 14743df57bcfSMattias Nilsson return request_timclk(enable); 14756b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 14766b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 14776b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 14786b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 14796b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 14806b6fae2bSMattias Nilsson return request_plldsi(enable); 14816b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 14823df57bcfSMattias Nilsson return request_sysclk(enable); 14836b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 14840837bb72SMattias Nilsson return request_pll(clock, enable); 14856b6fae2bSMattias Nilsson else 14866b6fae2bSMattias Nilsson return -EINVAL; 14876b6fae2bSMattias Nilsson } 14886b6fae2bSMattias Nilsson 14896b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 14906b6fae2bSMattias Nilsson int branch) 14916b6fae2bSMattias Nilsson { 14926b6fae2bSMattias Nilsson u64 rate; 14936b6fae2bSMattias Nilsson u32 val; 14946b6fae2bSMattias Nilsson u32 d; 14956b6fae2bSMattias Nilsson u32 div = 1; 14966b6fae2bSMattias Nilsson 14976b6fae2bSMattias Nilsson val = readl(reg); 14986b6fae2bSMattias Nilsson 14996b6fae2bSMattias Nilsson rate = src_rate; 15006b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 15016b6fae2bSMattias Nilsson 15026b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 15036b6fae2bSMattias Nilsson if (d > 1) 15046b6fae2bSMattias Nilsson div *= d; 15056b6fae2bSMattias Nilsson 15066b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 15076b6fae2bSMattias Nilsson if (d > 1) 15086b6fae2bSMattias Nilsson div *= d; 15096b6fae2bSMattias Nilsson 15106b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2) 15116b6fae2bSMattias Nilsson div *= 2; 15126b6fae2bSMattias Nilsson 15136b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 15146b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) && 15156b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) || 151620aee5b6SMichel Jaouen (reg == PRCM_PLLARM_FREQ) || 15176b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ)))) 15186b6fae2bSMattias Nilsson div *= 2; 15196b6fae2bSMattias Nilsson 15206b6fae2bSMattias Nilsson (void)do_div(rate, div); 15216b6fae2bSMattias Nilsson 15226b6fae2bSMattias Nilsson return (unsigned long)rate; 15236b6fae2bSMattias Nilsson } 15246b6fae2bSMattias Nilsson 15256b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000 15266b6fae2bSMattias Nilsson 15276b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock) 15286b6fae2bSMattias Nilsson { 15296b6fae2bSMattias Nilsson u32 val; 15306b6fae2bSMattias Nilsson u32 pllsw; 15316b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE; 15326b6fae2bSMattias Nilsson 1533b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 15346b6fae2bSMattias Nilsson 15356b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 15366b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 15376b6fae2bSMattias Nilsson rate /= 2; 15386b6fae2bSMattias Nilsson return rate; 15396b6fae2bSMattias Nilsson } 15406b6fae2bSMattias Nilsson 15416b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw; 15426b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 15436b6fae2bSMattias Nilsson 15446b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 15456b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 15466b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 15476b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 15486b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 15496b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 15506b6fae2bSMattias Nilsson else 15516b6fae2bSMattias Nilsson return 0; 15526b6fae2bSMattias Nilsson 15536b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) && 15546b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 15556b6fae2bSMattias Nilsson u64 r = (rate * 10); 15566b6fae2bSMattias Nilsson 15576b6fae2bSMattias Nilsson (void)do_div(r, 25); 15586b6fae2bSMattias Nilsson return (unsigned long)r; 15596b6fae2bSMattias Nilsson } 15606b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 15616b6fae2bSMattias Nilsson if (val) 15626b6fae2bSMattias Nilsson return rate / val; 15636b6fae2bSMattias Nilsson else 15646b6fae2bSMattias Nilsson return 0; 15656b6fae2bSMattias Nilsson } 156620aee5b6SMichel Jaouen 1567b2302c87SUlf Hansson static unsigned long armss_rate(void) 156820aee5b6SMichel Jaouen { 156920aee5b6SMichel Jaouen u32 r; 157020aee5b6SMichel Jaouen unsigned long rate; 157120aee5b6SMichel Jaouen 157220aee5b6SMichel Jaouen r = readl(PRCM_ARM_CHGCLKREQ); 157320aee5b6SMichel Jaouen 157420aee5b6SMichel Jaouen if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { 157520aee5b6SMichel Jaouen /* External ARMCLKFIX clock */ 157620aee5b6SMichel Jaouen 157720aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); 157820aee5b6SMichel Jaouen 157920aee5b6SMichel Jaouen /* Check PRCM_ARM_CHGCLKREQ divider */ 158020aee5b6SMichel Jaouen if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) 158120aee5b6SMichel Jaouen rate /= 2; 158220aee5b6SMichel Jaouen 158320aee5b6SMichel Jaouen /* Check PRCM_ARMCLKFIX_MGT divider */ 158420aee5b6SMichel Jaouen r = readl(PRCM_ARMCLKFIX_MGT); 158520aee5b6SMichel Jaouen r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 158620aee5b6SMichel Jaouen rate /= r; 158720aee5b6SMichel Jaouen 158820aee5b6SMichel Jaouen } else {/* ARM PLL */ 158920aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); 159020aee5b6SMichel Jaouen } 159120aee5b6SMichel Jaouen 1592b2302c87SUlf Hansson return rate; 159320aee5b6SMichel Jaouen } 15946b6fae2bSMattias Nilsson 15956b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n) 15966b6fae2bSMattias Nilsson { 15976b6fae2bSMattias Nilsson u32 divsel; 15986b6fae2bSMattias Nilsson u32 div = 1; 15996b6fae2bSMattias Nilsson 16006b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL); 16016b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 16026b6fae2bSMattias Nilsson 16036b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 16046b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel; 1605e9d7b4b5SUlf Hansson else 1606e9d7b4b5SUlf Hansson dsiclk[n].divsel = divsel; 16076b6fae2bSMattias Nilsson 16086b6fae2bSMattias Nilsson switch (divsel) { 16096b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4: 16106b6fae2bSMattias Nilsson div *= 2; 16116b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2: 16126b6fae2bSMattias Nilsson div *= 2; 16136b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI: 16146b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 16156b6fae2bSMattias Nilsson PLL_RAW) / div; 1616e62ccf3aSLinus Walleij default: 16176b6fae2bSMattias Nilsson return 0; 16186b6fae2bSMattias Nilsson } 16196b6fae2bSMattias Nilsson } 16206b6fae2bSMattias Nilsson 16216b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n) 16226b6fae2bSMattias Nilsson { 16236b6fae2bSMattias Nilsson u32 div; 16246b6fae2bSMattias Nilsson 16256b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV); 16266b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 16276b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 16286b6fae2bSMattias Nilsson } 16296b6fae2bSMattias Nilsson 16306b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock) 16316b6fae2bSMattias Nilsson { 16326b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 16336b6fae2bSMattias Nilsson return clock_rate(clock); 16346b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 16356b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE / 16; 16366b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 16376b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 16386b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0) 16396b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 16406b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 16416b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 164220aee5b6SMichel Jaouen else if (clock == PRCMU_ARMSS) 164320aee5b6SMichel Jaouen return armss_rate(); 16446b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR) 16456b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 16466b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 16476b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 16486b6fae2bSMattias Nilsson PLL_RAW); 16496b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 16506b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK); 16516b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 16526b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 16536b6fae2bSMattias Nilsson else 16546b6fae2bSMattias Nilsson return 0; 16556b6fae2bSMattias Nilsson } 16566b6fae2bSMattias Nilsson 16576b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 16586b6fae2bSMattias Nilsson { 16596b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 16606b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 16616b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 16626b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 16636b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 16646b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 16656b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 16666b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 16676b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 16686b6fae2bSMattias Nilsson else 16696b6fae2bSMattias Nilsson return 0; 16706b6fae2bSMattias Nilsson } 16716b6fae2bSMattias Nilsson 16726b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate) 16736b6fae2bSMattias Nilsson { 16746b6fae2bSMattias Nilsson u32 div; 16756b6fae2bSMattias Nilsson 16766b6fae2bSMattias Nilsson div = (src_rate / rate); 16776b6fae2bSMattias Nilsson if (div == 0) 16786b6fae2bSMattias Nilsson return 1; 16796b6fae2bSMattias Nilsson if (rate < (src_rate / div)) 16806b6fae2bSMattias Nilsson div++; 16816b6fae2bSMattias Nilsson return div; 16826b6fae2bSMattias Nilsson } 16836b6fae2bSMattias Nilsson 16846b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate) 16856b6fae2bSMattias Nilsson { 16866b6fae2bSMattias Nilsson u32 val; 16876b6fae2bSMattias Nilsson u32 div; 16886b6fae2bSMattias Nilsson unsigned long src_rate; 16896b6fae2bSMattias Nilsson long rounded_rate; 16906b6fae2bSMattias Nilsson 1691b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 16926b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 16936b6fae2bSMattias Nilsson clk_mgt[clock].branch); 16946b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 16956b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 16966b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 16976b6fae2bSMattias Nilsson if (div > 2) 16986b6fae2bSMattias Nilsson div = 2; 16996b6fae2bSMattias Nilsson } else { 17006b6fae2bSMattias Nilsson div = 1; 17016b6fae2bSMattias Nilsson } 17026b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 17036b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 17046b6fae2bSMattias Nilsson 17056b6fae2bSMattias Nilsson (void)do_div(r, 25); 17066b6fae2bSMattias Nilsson if (r <= rate) 17076b6fae2bSMattias Nilsson return (unsigned long)r; 17086b6fae2bSMattias Nilsson } 17096b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31)); 17106b6fae2bSMattias Nilsson 17116b6fae2bSMattias Nilsson return rounded_rate; 17126b6fae2bSMattias Nilsson } 17136b6fae2bSMattias Nilsson 1714b2302c87SUlf Hansson /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ 1715b2302c87SUlf Hansson static struct cpufreq_frequency_table db8500_cpufreq_table[] = { 171650701588SViresh Kumar { .frequency = 200000, .driver_data = ARM_EXTCLK,}, 171750701588SViresh Kumar { .frequency = 400000, .driver_data = ARM_50_OPP,}, 171850701588SViresh Kumar { .frequency = 800000, .driver_data = ARM_100_OPP,}, 1719b2302c87SUlf Hansson { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ 1720b2302c87SUlf Hansson { .frequency = CPUFREQ_TABLE_END,}, 1721b2302c87SUlf Hansson }; 1722b2302c87SUlf Hansson 1723b2302c87SUlf Hansson static long round_armss_rate(unsigned long rate) 1724b2302c87SUlf Hansson { 1725fdb56c45SStratos Karafotis struct cpufreq_frequency_table *pos; 1726b2302c87SUlf Hansson long freq = 0; 1727b2302c87SUlf Hansson 1728b2302c87SUlf Hansson /* cpufreq table frequencies is in KHz. */ 1729b2302c87SUlf Hansson rate = rate / 1000; 1730b2302c87SUlf Hansson 1731b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1732fdb56c45SStratos Karafotis cpufreq_for_each_entry(pos, db8500_cpufreq_table) { 1733fdb56c45SStratos Karafotis freq = pos->frequency; 1734b2302c87SUlf Hansson if (freq == rate) 1735b2302c87SUlf Hansson break; 1736b2302c87SUlf Hansson } 1737b2302c87SUlf Hansson 1738b2302c87SUlf Hansson /* Return the last valid value, even if a match was not found. */ 1739b2302c87SUlf Hansson return freq * 1000; 1740b2302c87SUlf Hansson } 1741b2302c87SUlf Hansson 17426b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL 17436b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL 17446b6fae2bSMattias Nilsson 17456b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate) 17466b6fae2bSMattias Nilsson { 17476b6fae2bSMattias Nilsson long rounded_rate = 0; 17486b6fae2bSMattias Nilsson unsigned long src_rate; 17496b6fae2bSMattias Nilsson unsigned long rem; 17506b6fae2bSMattias Nilsson u32 r; 17516b6fae2bSMattias Nilsson 17526b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 17536b6fae2bSMattias Nilsson rem = rate; 17546b6fae2bSMattias Nilsson 17556b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 17566b6fae2bSMattias Nilsson u64 d; 17576b6fae2bSMattias Nilsson 17586b6fae2bSMattias Nilsson d = (r * rate); 17596b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 17606b6fae2bSMattias Nilsson if (d < 6) 17616b6fae2bSMattias Nilsson d = 6; 17626b6fae2bSMattias Nilsson else if (d > 255) 17636b6fae2bSMattias Nilsson d = 255; 17646b6fae2bSMattias Nilsson d *= src_rate; 17656b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 17666b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d))) 17676b6fae2bSMattias Nilsson continue; 17686b6fae2bSMattias Nilsson (void)do_div(d, r); 17696b6fae2bSMattias Nilsson if (rate < d) { 17706b6fae2bSMattias Nilsson if (rounded_rate == 0) 17716b6fae2bSMattias Nilsson rounded_rate = (long)d; 1772e62ccf3aSLinus Walleij break; 1773e62ccf3aSLinus Walleij } 17746b6fae2bSMattias Nilsson if ((rate - d) < rem) { 17756b6fae2bSMattias Nilsson rem = (rate - d); 17766b6fae2bSMattias Nilsson rounded_rate = (long)d; 17776b6fae2bSMattias Nilsson } 17786b6fae2bSMattias Nilsson } 17796b6fae2bSMattias Nilsson return rounded_rate; 17806b6fae2bSMattias Nilsson } 17816b6fae2bSMattias Nilsson 17826b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate) 17836b6fae2bSMattias Nilsson { 17846b6fae2bSMattias Nilsson u32 div; 17856b6fae2bSMattias Nilsson unsigned long src_rate; 17866b6fae2bSMattias Nilsson long rounded_rate; 17876b6fae2bSMattias Nilsson 17886b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 17896b6fae2bSMattias Nilsson PLL_RAW); 17906b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 17916b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 17926b6fae2bSMattias Nilsson 17936b6fae2bSMattias Nilsson return rounded_rate; 17946b6fae2bSMattias Nilsson } 17956b6fae2bSMattias Nilsson 17966b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate) 17976b6fae2bSMattias Nilsson { 17986b6fae2bSMattias Nilsson u32 div; 17996b6fae2bSMattias Nilsson unsigned long src_rate; 18006b6fae2bSMattias Nilsson long rounded_rate; 18016b6fae2bSMattias Nilsson 18026b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK); 18036b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18046b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255)); 18056b6fae2bSMattias Nilsson 18066b6fae2bSMattias Nilsson return rounded_rate; 18076b6fae2bSMattias Nilsson } 18086b6fae2bSMattias Nilsson 18096b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate) 18106b6fae2bSMattias Nilsson { 1811e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 18126b6fae2bSMattias Nilsson return round_clock_rate(clock, rate); 1813b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 1814b2302c87SUlf Hansson return round_armss_rate(rate); 18156b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 18166b6fae2bSMattias Nilsson return round_plldsi_rate(rate); 18176b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 18186b6fae2bSMattias Nilsson return round_dsiclk_rate(rate); 18196b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 18206b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate); 18216b6fae2bSMattias Nilsson else 18226b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock); 18236b6fae2bSMattias Nilsson } 18246b6fae2bSMattias Nilsson 18256b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate) 18266b6fae2bSMattias Nilsson { 18276b6fae2bSMattias Nilsson u32 val; 18286b6fae2bSMattias Nilsson u32 div; 18296b6fae2bSMattias Nilsson unsigned long src_rate; 18306b6fae2bSMattias Nilsson unsigned long flags; 18316b6fae2bSMattias Nilsson 18326b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 18336b6fae2bSMattias Nilsson 18346b6fae2bSMattias Nilsson /* Grab the HW semaphore. */ 18356b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 18366b6fae2bSMattias Nilsson cpu_relax(); 18376b6fae2bSMattias Nilsson 1838b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 18396b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 18406b6fae2bSMattias Nilsson clk_mgt[clock].branch); 18416b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18426b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 18436b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 18446b6fae2bSMattias Nilsson if (div > 1) 18456b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV; 18466b6fae2bSMattias Nilsson else 18476b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV; 18486b6fae2bSMattias Nilsson } 18496b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) { 18506b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 18516b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 18526b6fae2bSMattias Nilsson if (div == 3) { 18536b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 18546b6fae2bSMattias Nilsson 18556b6fae2bSMattias Nilsson (void)do_div(r, 25); 18566b6fae2bSMattias Nilsson if (r <= rate) { 18576b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 18586b6fae2bSMattias Nilsson div = 0; 18596b6fae2bSMattias Nilsson } 18606b6fae2bSMattias Nilsson } 18616b6fae2bSMattias Nilsson val |= min(div, (u32)31); 18626b6fae2bSMattias Nilsson } else { 18636b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 18646b6fae2bSMattias Nilsson val |= min(div, (u32)31); 18656b6fae2bSMattias Nilsson } 1866b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset); 18676b6fae2bSMattias Nilsson 18686b6fae2bSMattias Nilsson /* Release the HW semaphore. */ 18696b6fae2bSMattias Nilsson writel(0, PRCM_SEM); 18706b6fae2bSMattias Nilsson 18716b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 18726b6fae2bSMattias Nilsson } 18736b6fae2bSMattias Nilsson 1874b2302c87SUlf Hansson static int set_armss_rate(unsigned long rate) 1875b2302c87SUlf Hansson { 1876fdb56c45SStratos Karafotis struct cpufreq_frequency_table *pos; 1877b2302c87SUlf Hansson 1878b2302c87SUlf Hansson /* cpufreq table frequencies is in KHz. */ 1879b2302c87SUlf Hansson rate = rate / 1000; 1880b2302c87SUlf Hansson 1881b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1882fdb56c45SStratos Karafotis cpufreq_for_each_entry(pos, db8500_cpufreq_table) 1883fdb56c45SStratos Karafotis if (pos->frequency == rate) 1884b2302c87SUlf Hansson break; 1885b2302c87SUlf Hansson 1886fdb56c45SStratos Karafotis if (pos->frequency != rate) 1887b2302c87SUlf Hansson return -EINVAL; 1888b2302c87SUlf Hansson 1889b2302c87SUlf Hansson /* Set the new arm opp. */ 1890fdb56c45SStratos Karafotis return db8500_prcmu_set_arm_opp(pos->driver_data); 1891b2302c87SUlf Hansson } 1892b2302c87SUlf Hansson 18936b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate) 18946b6fae2bSMattias Nilsson { 18956b6fae2bSMattias Nilsson unsigned long src_rate; 18966b6fae2bSMattias Nilsson unsigned long rem; 18976b6fae2bSMattias Nilsson u32 pll_freq = 0; 18986b6fae2bSMattias Nilsson u32 r; 18996b6fae2bSMattias Nilsson 19006b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 19016b6fae2bSMattias Nilsson rem = rate; 19026b6fae2bSMattias Nilsson 19036b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 19046b6fae2bSMattias Nilsson u64 d; 19056b6fae2bSMattias Nilsson u64 hwrate; 19066b6fae2bSMattias Nilsson 19076b6fae2bSMattias Nilsson d = (r * rate); 19086b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 19096b6fae2bSMattias Nilsson if (d < 6) 19106b6fae2bSMattias Nilsson d = 6; 19116b6fae2bSMattias Nilsson else if (d > 255) 19126b6fae2bSMattias Nilsson d = 255; 19136b6fae2bSMattias Nilsson hwrate = (d * src_rate); 19146b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 19156b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 19166b6fae2bSMattias Nilsson continue; 19176b6fae2bSMattias Nilsson (void)do_div(hwrate, r); 19186b6fae2bSMattias Nilsson if (rate < hwrate) { 19196b6fae2bSMattias Nilsson if (pll_freq == 0) 19206b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19216b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19226b6fae2bSMattias Nilsson break; 19236b6fae2bSMattias Nilsson } 19246b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) { 19256b6fae2bSMattias Nilsson rem = (rate - hwrate); 19266b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19276b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19286b6fae2bSMattias Nilsson } 19296b6fae2bSMattias Nilsson } 19306b6fae2bSMattias Nilsson if (pll_freq == 0) 19313df57bcfSMattias Nilsson return -EINVAL; 19326b6fae2bSMattias Nilsson 19336b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 19346b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ); 19356b6fae2bSMattias Nilsson 19366b6fae2bSMattias Nilsson return 0; 19376b6fae2bSMattias Nilsson } 19386b6fae2bSMattias Nilsson 19396b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate) 19406b6fae2bSMattias Nilsson { 19416b6fae2bSMattias Nilsson u32 val; 19426b6fae2bSMattias Nilsson u32 div; 19436b6fae2bSMattias Nilsson 19446b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 19456b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 19466b6fae2bSMattias Nilsson 19476b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 19486b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 19496b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 19506b6fae2bSMattias Nilsson 19516b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 19526b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 19536b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 19546b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 19556b6fae2bSMattias Nilsson } 19566b6fae2bSMattias Nilsson 19576b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate) 19586b6fae2bSMattias Nilsson { 19596b6fae2bSMattias Nilsson u32 val; 19606b6fae2bSMattias Nilsson u32 div; 19616b6fae2bSMattias Nilsson 19626b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 19636b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 19646b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask; 19656b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 19666b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 19676b6fae2bSMattias Nilsson } 19686b6fae2bSMattias Nilsson 19696b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate) 19706b6fae2bSMattias Nilsson { 19716b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 19726b6fae2bSMattias Nilsson set_clock_rate(clock, rate); 1973b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 1974b2302c87SUlf Hansson return set_armss_rate(rate); 19756b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 19766b6fae2bSMattias Nilsson return set_plldsi_rate(rate); 19776b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 19786b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 19796b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 19806b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 19816b6fae2bSMattias Nilsson return 0; 19823df57bcfSMattias Nilsson } 19833df57bcfSMattias Nilsson 198473180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 19853df57bcfSMattias Nilsson { 19863df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 19873df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 19883df57bcfSMattias Nilsson return -EINVAL; 19893df57bcfSMattias Nilsson 19903df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 19913df57bcfSMattias Nilsson 1992c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 19933df57bcfSMattias Nilsson cpu_relax(); 19943df57bcfSMattias Nilsson 19953df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 19963df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 19973df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 19983df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 19993df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 20003df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 20013df57bcfSMattias Nilsson 2002c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20033df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20043df57bcfSMattias Nilsson 20053df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20063df57bcfSMattias Nilsson 20073df57bcfSMattias Nilsson return 0; 20083df57bcfSMattias Nilsson } 20093df57bcfSMattias Nilsson 20100508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold) 20113df57bcfSMattias Nilsson { 20123df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20133df57bcfSMattias Nilsson 2014c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20153df57bcfSMattias Nilsson cpu_relax(); 20163df57bcfSMattias Nilsson 20173df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 20183df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20193df57bcfSMattias Nilsson 2020c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20213df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20223df57bcfSMattias Nilsson 20233df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20243df57bcfSMattias Nilsson 20253df57bcfSMattias Nilsson return 0; 20263df57bcfSMattias Nilsson } 20273df57bcfSMattias Nilsson 20280508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high) 20293df57bcfSMattias Nilsson { 20303df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20313df57bcfSMattias Nilsson 2032c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20333df57bcfSMattias Nilsson cpu_relax(); 20343df57bcfSMattias Nilsson 20353df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 20363df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 20373df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 20383df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 20393df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20403df57bcfSMattias Nilsson 2041c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20423df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20433df57bcfSMattias Nilsson 20443df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20453df57bcfSMattias Nilsson 20463df57bcfSMattias Nilsson return 0; 20473df57bcfSMattias Nilsson } 204826716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon); 20493df57bcfSMattias Nilsson 20503df57bcfSMattias Nilsson static int config_hot_period(u16 val) 20513df57bcfSMattias Nilsson { 20523df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20533df57bcfSMattias Nilsson 2054c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20553df57bcfSMattias Nilsson cpu_relax(); 20563df57bcfSMattias Nilsson 20573df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 20583df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20593df57bcfSMattias Nilsson 2060c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20613df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20623df57bcfSMattias Nilsson 20633df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20643df57bcfSMattias Nilsson 20653df57bcfSMattias Nilsson return 0; 20663df57bcfSMattias Nilsson } 20673df57bcfSMattias Nilsson 20680508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k) 20693df57bcfSMattias Nilsson { 20703df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 20713df57bcfSMattias Nilsson return -EINVAL; 20723df57bcfSMattias Nilsson 20733df57bcfSMattias Nilsson return config_hot_period(cycles32k); 20743df57bcfSMattias Nilsson } 207526716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense); 20763df57bcfSMattias Nilsson 20770508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void) 20783df57bcfSMattias Nilsson { 20793df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 20803df57bcfSMattias Nilsson } 208126716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense); 20823df57bcfSMattias Nilsson 208384165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 208484165b80SJonas Aberg { 208584165b80SJonas Aberg 208684165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 208784165b80SJonas Aberg 208884165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 208984165b80SJonas Aberg cpu_relax(); 209084165b80SJonas Aberg 209184165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 209284165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 209384165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 209484165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 209584165b80SJonas Aberg 209684165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 209784165b80SJonas Aberg 209884165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 209984165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 210084165b80SJonas Aberg 210184165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 210284165b80SJonas Aberg 210384165b80SJonas Aberg return 0; 210484165b80SJonas Aberg 210584165b80SJonas Aberg } 210684165b80SJonas Aberg 21070508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 210884165b80SJonas Aberg { 210984165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 211084165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 211184165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 211284165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 211384165b80SJonas Aberg } 21146f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); 211584165b80SJonas Aberg 21160508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id) 211784165b80SJonas Aberg { 211884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 211984165b80SJonas Aberg } 21206f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); 212184165b80SJonas Aberg 21220508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id) 212384165b80SJonas Aberg { 212484165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 212584165b80SJonas Aberg } 21266f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); 212784165b80SJonas Aberg 21280508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id) 212984165b80SJonas Aberg { 213084165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 213184165b80SJonas Aberg } 21326f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); 213384165b80SJonas Aberg 213484165b80SJonas Aberg /* 213584165b80SJonas Aberg * timeout is 28 bit, in ms. 213684165b80SJonas Aberg */ 21370508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 213884165b80SJonas Aberg { 213984165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 214084165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 214184165b80SJonas Aberg /* 214284165b80SJonas Aberg * Put the lowest 28 bits of timeout at 214384165b80SJonas Aberg * offset 4. Four first bits are used for id. 214484165b80SJonas Aberg */ 214584165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 214684165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 214784165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 214884165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 214984165b80SJonas Aberg } 21506f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); 215184165b80SJonas Aberg 21523df57bcfSMattias Nilsson /** 2153650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 2154650c2a21SLinus Walleij * @slave: The I2C slave address. 2155650c2a21SLinus Walleij * @reg: The (start) register address. 2156650c2a21SLinus Walleij * @value: The read out value(s). 2157650c2a21SLinus Walleij * @size: The number of registers to read. 2158650c2a21SLinus Walleij * 2159650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2160650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2161650c2a21SLinus Walleij */ 2162650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2163650c2a21SLinus Walleij { 2164650c2a21SLinus Walleij int r; 2165650c2a21SLinus Walleij 2166650c2a21SLinus Walleij if (size != 1) 2167650c2a21SLinus Walleij return -EINVAL; 2168650c2a21SLinus Walleij 21693df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2170650c2a21SLinus Walleij 2171c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2172650c2a21SLinus Walleij cpu_relax(); 2173650c2a21SLinus Walleij 21743c3e4898SMattias Nilsson writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 21753df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 21763df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 21773df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 21783df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2179650c2a21SLinus Walleij 2180c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 21813df57bcfSMattias Nilsson 2182650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 21833df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 21843df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 21853df57bcfSMattias Nilsson __func__); 2186650c2a21SLinus Walleij r = -EIO; 21873df57bcfSMattias Nilsson } else { 2188650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 21893df57bcfSMattias Nilsson } 21903df57bcfSMattias Nilsson 2191650c2a21SLinus Walleij if (!r) 2192650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 2193650c2a21SLinus Walleij 2194650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 21953df57bcfSMattias Nilsson 2196650c2a21SLinus Walleij return r; 2197650c2a21SLinus Walleij } 2198650c2a21SLinus Walleij 2199650c2a21SLinus Walleij /** 22003c3e4898SMattias Nilsson * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. 2201650c2a21SLinus Walleij * @slave: The I2C slave address. 2202650c2a21SLinus Walleij * @reg: The (start) register address. 2203650c2a21SLinus Walleij * @value: The value(s) to write. 22043c3e4898SMattias Nilsson * @mask: The mask(s) to use. 2205650c2a21SLinus Walleij * @size: The number of registers to write. 2206650c2a21SLinus Walleij * 22073c3e4898SMattias Nilsson * Writes masked register value(s) to the ABB. 22083c3e4898SMattias Nilsson * For each @value, only the bits set to 1 in the corresponding @mask 22093c3e4898SMattias Nilsson * will be written. The other bits are not changed. 2210650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2211650c2a21SLinus Walleij */ 22123c3e4898SMattias Nilsson int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) 2213650c2a21SLinus Walleij { 2214650c2a21SLinus Walleij int r; 2215650c2a21SLinus Walleij 2216650c2a21SLinus Walleij if (size != 1) 2217650c2a21SLinus Walleij return -EINVAL; 2218650c2a21SLinus Walleij 22193df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2220650c2a21SLinus Walleij 2221c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2222650c2a21SLinus Walleij cpu_relax(); 2223650c2a21SLinus Walleij 22243c3e4898SMattias Nilsson writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 22253df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22263df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22273df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22283df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2229650c2a21SLinus Walleij 2230c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 22313df57bcfSMattias Nilsson 2232650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 22333df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 22343df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 22353df57bcfSMattias Nilsson __func__); 2236650c2a21SLinus Walleij r = -EIO; 22373df57bcfSMattias Nilsson } else { 2238650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 22393df57bcfSMattias Nilsson } 22403df57bcfSMattias Nilsson 22413df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 22423df57bcfSMattias Nilsson 22433df57bcfSMattias Nilsson return r; 22443df57bcfSMattias Nilsson } 22453df57bcfSMattias Nilsson 22463df57bcfSMattias Nilsson /** 22473c3e4898SMattias Nilsson * prcmu_abb_write() - Write register value(s) to the ABB. 22483c3e4898SMattias Nilsson * @slave: The I2C slave address. 22493c3e4898SMattias Nilsson * @reg: The (start) register address. 22503c3e4898SMattias Nilsson * @value: The value(s) to write. 22513c3e4898SMattias Nilsson * @size: The number of registers to write. 22523c3e4898SMattias Nilsson * 22533c3e4898SMattias Nilsson * Writes register value(s) to the ABB. 22543c3e4898SMattias Nilsson * @size has to be 1 for the current firmware version. 22553c3e4898SMattias Nilsson */ 22563c3e4898SMattias Nilsson int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 22573c3e4898SMattias Nilsson { 22583c3e4898SMattias Nilsson u8 mask = ~0; 22593c3e4898SMattias Nilsson 22603c3e4898SMattias Nilsson return prcmu_abb_write_masked(slave, reg, value, &mask, size); 22613c3e4898SMattias Nilsson } 22623c3e4898SMattias Nilsson 22633c3e4898SMattias Nilsson /** 22643df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 22653df57bcfSMattias Nilsson */ 22665261e101SArun Murthy int prcmu_ac_wake_req(void) 22673df57bcfSMattias Nilsson { 22683df57bcfSMattias Nilsson u32 val; 22695261e101SArun Murthy int ret = 0; 22703df57bcfSMattias Nilsson 22713df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 22723df57bcfSMattias Nilsson 2273c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 22743df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 22753df57bcfSMattias Nilsson goto unlock_and_return; 22763df57bcfSMattias Nilsson 22773df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 22783df57bcfSMattias Nilsson 22795261e101SArun Murthy /* 22805261e101SArun Murthy * Force Modem Wake-up before hostaccess_req ping-pong. 22815261e101SArun Murthy * It prevents Modem to enter in Sleep while acking the hostaccess 22825261e101SArun Murthy * request. The 31us delay has been calculated by HWI. 22835261e101SArun Murthy */ 22845261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; 22855261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 22865261e101SArun Murthy 22875261e101SArun Murthy udelay(31); 22885261e101SArun Murthy 22895261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; 22905261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 22913df57bcfSMattias Nilsson 22923df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2293d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 229457265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2295d6e3002eSMattias Nilsson __func__); 22965261e101SArun Murthy ret = -EFAULT; 22973df57bcfSMattias Nilsson } 2298650c2a21SLinus Walleij 2299650c2a21SLinus Walleij unlock_and_return: 23003df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23015261e101SArun Murthy return ret; 2302650c2a21SLinus Walleij } 2303650c2a21SLinus Walleij 23043df57bcfSMattias Nilsson /** 23053df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 23063df57bcfSMattias Nilsson */ 2307ffb01160SSachin Kamat void prcmu_ac_sleep_req(void) 2308650c2a21SLinus Walleij { 23093df57bcfSMattias Nilsson u32 val; 2310650c2a21SLinus Walleij 23113df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 2312650c2a21SLinus Walleij 2313c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23143df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 23153df57bcfSMattias Nilsson goto unlock_and_return; 23163df57bcfSMattias Nilsson 23173df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2318c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 23193df57bcfSMattias Nilsson 23203df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2321d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 232257265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 23233df57bcfSMattias Nilsson __func__); 23243df57bcfSMattias Nilsson } 23253df57bcfSMattias Nilsson 23263df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 23273df57bcfSMattias Nilsson 23283df57bcfSMattias Nilsson unlock_and_return: 23293df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23303df57bcfSMattias Nilsson } 23313df57bcfSMattias Nilsson 233273180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 23333df57bcfSMattias Nilsson { 23343df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 23353df57bcfSMattias Nilsson } 23363df57bcfSMattias Nilsson 23373df57bcfSMattias Nilsson /** 233873180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 23393df57bcfSMattias Nilsson * 234073180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 23413df57bcfSMattias Nilsson * fires interrupt to fw 23423df57bcfSMattias Nilsson */ 234373180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 23443df57bcfSMattias Nilsson { 23453df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2346c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 23473df57bcfSMattias Nilsson } 23483df57bcfSMattias Nilsson 23493df57bcfSMattias Nilsson /** 2350597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2351597045deSSebastian Rasmussen * 2352597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 2353597045deSSebastian Rasmussen * last restart. 2354597045deSSebastian Rasmussen */ 2355597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 2356597045deSSebastian Rasmussen { 2357597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 2358597045deSSebastian Rasmussen } 2359597045deSSebastian Rasmussen 2360597045deSSebastian Rasmussen /** 23610508901cSMattias Nilsson * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 23623df57bcfSMattias Nilsson */ 23630508901cSMattias Nilsson void db8500_prcmu_modem_reset(void) 23643df57bcfSMattias Nilsson { 2365650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 2366650c2a21SLinus Walleij 2367c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2368650c2a21SLinus Walleij cpu_relax(); 2369650c2a21SLinus Walleij 23703df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2371c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2372650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 23733df57bcfSMattias Nilsson 23743df57bcfSMattias Nilsson /* 23753df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 23763df57bcfSMattias Nilsson * This state is already managed by upper layer 23773df57bcfSMattias Nilsson */ 2378650c2a21SLinus Walleij 2379650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 2380650c2a21SLinus Walleij } 2381650c2a21SLinus Walleij 23823df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 2383650c2a21SLinus Walleij { 23843df57bcfSMattias Nilsson unsigned long flags; 2385650c2a21SLinus Walleij 23863df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 2387650c2a21SLinus Walleij 2388c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 23893df57bcfSMattias Nilsson cpu_relax(); 2390650c2a21SLinus Walleij 23913df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2392c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2393650c2a21SLinus Walleij 23943df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2395650c2a21SLinus Walleij } 2396650c2a21SLinus Walleij 23973df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 2398650c2a21SLinus Walleij { 23993df57bcfSMattias Nilsson pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", 24003df57bcfSMattias Nilsson header, n); 2401650c2a21SLinus Walleij } 2402650c2a21SLinus Walleij 24033df57bcfSMattias Nilsson static bool read_mailbox_0(void) 2404650c2a21SLinus Walleij { 24053df57bcfSMattias Nilsson bool r; 24063df57bcfSMattias Nilsson u32 ev; 24073df57bcfSMattias Nilsson unsigned int n; 24083df57bcfSMattias Nilsson u8 header; 24093df57bcfSMattias Nilsson 24103df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 24113df57bcfSMattias Nilsson switch (header) { 24123df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 24133df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 24143df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 24153df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 24163df57bcfSMattias Nilsson else 24173df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 24183df57bcfSMattias Nilsson 24193df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 24203df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 24213df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 24223df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 24233df57bcfSMattias Nilsson 24243df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 24253df57bcfSMattias Nilsson 24263df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 24273df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 242889d9b1c9SLinus Walleij generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); 24293df57bcfSMattias Nilsson } 24303df57bcfSMattias Nilsson r = true; 24313df57bcfSMattias Nilsson break; 24323df57bcfSMattias Nilsson default: 24333df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 24343df57bcfSMattias Nilsson r = false; 24353df57bcfSMattias Nilsson break; 24363df57bcfSMattias Nilsson } 2437c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 24383df57bcfSMattias Nilsson return r; 24393df57bcfSMattias Nilsson } 24403df57bcfSMattias Nilsson 24413df57bcfSMattias Nilsson static bool read_mailbox_1(void) 24423df57bcfSMattias Nilsson { 24433df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 24443df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 24453df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 24463df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 24473df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 24483df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 24493df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2450c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2451650c2a21SLinus Walleij complete(&mb1_transfer.work); 24523df57bcfSMattias Nilsson return false; 2453650c2a21SLinus Walleij } 2454650c2a21SLinus Walleij 24553df57bcfSMattias Nilsson static bool read_mailbox_2(void) 2456650c2a21SLinus Walleij { 24573df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2458c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 24593df57bcfSMattias Nilsson complete(&mb2_transfer.work); 24603df57bcfSMattias Nilsson return false; 2461650c2a21SLinus Walleij } 2462650c2a21SLinus Walleij 24633df57bcfSMattias Nilsson static bool read_mailbox_3(void) 2464650c2a21SLinus Walleij { 2465c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 24663df57bcfSMattias Nilsson return false; 2467650c2a21SLinus Walleij } 2468650c2a21SLinus Walleij 24693df57bcfSMattias Nilsson static bool read_mailbox_4(void) 2470650c2a21SLinus Walleij { 24713df57bcfSMattias Nilsson u8 header; 24723df57bcfSMattias Nilsson bool do_complete = true; 24733df57bcfSMattias Nilsson 24743df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 24753df57bcfSMattias Nilsson switch (header) { 24763df57bcfSMattias Nilsson case MB4H_MEM_ST: 24773df57bcfSMattias Nilsson case MB4H_HOTDOG: 24783df57bcfSMattias Nilsson case MB4H_HOTMON: 24793df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 2480a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 2481a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 2482a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 2483a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 2484a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 24853df57bcfSMattias Nilsson break; 24863df57bcfSMattias Nilsson default: 24873df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 24883df57bcfSMattias Nilsson do_complete = false; 24893df57bcfSMattias Nilsson break; 2490650c2a21SLinus Walleij } 2491650c2a21SLinus Walleij 2492c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 24933df57bcfSMattias Nilsson 24943df57bcfSMattias Nilsson if (do_complete) 24953df57bcfSMattias Nilsson complete(&mb4_transfer.work); 24963df57bcfSMattias Nilsson 24973df57bcfSMattias Nilsson return false; 24983df57bcfSMattias Nilsson } 24993df57bcfSMattias Nilsson 25003df57bcfSMattias Nilsson static bool read_mailbox_5(void) 2501650c2a21SLinus Walleij { 25023df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 25033df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2504c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2505650c2a21SLinus Walleij complete(&mb5_transfer.work); 25063df57bcfSMattias Nilsson return false; 2507650c2a21SLinus Walleij } 2508650c2a21SLinus Walleij 25093df57bcfSMattias Nilsson static bool read_mailbox_6(void) 2510650c2a21SLinus Walleij { 2511c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 25123df57bcfSMattias Nilsson return false; 2513650c2a21SLinus Walleij } 2514650c2a21SLinus Walleij 25153df57bcfSMattias Nilsson static bool read_mailbox_7(void) 2516650c2a21SLinus Walleij { 2517c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 25183df57bcfSMattias Nilsson return false; 2519650c2a21SLinus Walleij } 2520650c2a21SLinus Walleij 25213df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 2522650c2a21SLinus Walleij read_mailbox_0, 2523650c2a21SLinus Walleij read_mailbox_1, 2524650c2a21SLinus Walleij read_mailbox_2, 2525650c2a21SLinus Walleij read_mailbox_3, 2526650c2a21SLinus Walleij read_mailbox_4, 2527650c2a21SLinus Walleij read_mailbox_5, 2528650c2a21SLinus Walleij read_mailbox_6, 2529650c2a21SLinus Walleij read_mailbox_7 2530650c2a21SLinus Walleij }; 2531650c2a21SLinus Walleij 2532650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2533650c2a21SLinus Walleij { 2534650c2a21SLinus Walleij u32 bits; 2535650c2a21SLinus Walleij u8 n; 25363df57bcfSMattias Nilsson irqreturn_t r; 2537650c2a21SLinus Walleij 2538c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2539650c2a21SLinus Walleij if (unlikely(!bits)) 2540650c2a21SLinus Walleij return IRQ_NONE; 2541650c2a21SLinus Walleij 25423df57bcfSMattias Nilsson r = IRQ_HANDLED; 2543650c2a21SLinus Walleij for (n = 0; bits; n++) { 2544650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2545650c2a21SLinus Walleij bits -= MBOX_BIT(n); 25463df57bcfSMattias Nilsson if (read_mailbox[n]()) 25473df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2548650c2a21SLinus Walleij } 2549650c2a21SLinus Walleij } 25503df57bcfSMattias Nilsson return r; 25513df57bcfSMattias Nilsson } 25523df57bcfSMattias Nilsson 25533df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 25543df57bcfSMattias Nilsson { 25553df57bcfSMattias Nilsson ack_dbb_wakeup(); 2556650c2a21SLinus Walleij return IRQ_HANDLED; 2557650c2a21SLinus Walleij } 2558650c2a21SLinus Walleij 25593df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 25603df57bcfSMattias Nilsson { 25613df57bcfSMattias Nilsson unsigned long flags; 25623df57bcfSMattias Nilsson 25633df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 25643df57bcfSMattias Nilsson 25653df57bcfSMattias Nilsson config_wakeups(); 25663df57bcfSMattias Nilsson 25673df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 25683df57bcfSMattias Nilsson } 25693df57bcfSMattias Nilsson 25703df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 25713df57bcfSMattias Nilsson { 25723df57bcfSMattias Nilsson unsigned long flags; 25733df57bcfSMattias Nilsson 25743df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 25753df57bcfSMattias Nilsson 2576f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; 25773df57bcfSMattias Nilsson 25783df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 25793df57bcfSMattias Nilsson 25803df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 25813df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 25823df57bcfSMattias Nilsson } 25833df57bcfSMattias Nilsson 25843df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 25853df57bcfSMattias Nilsson { 25863df57bcfSMattias Nilsson unsigned long flags; 25873df57bcfSMattias Nilsson 25883df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 25893df57bcfSMattias Nilsson 2590f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; 25913df57bcfSMattias Nilsson 25923df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 25933df57bcfSMattias Nilsson 25943df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 25953df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 25963df57bcfSMattias Nilsson } 25973df57bcfSMattias Nilsson 25983df57bcfSMattias Nilsson static void noop(struct irq_data *d) 25993df57bcfSMattias Nilsson { 26003df57bcfSMattias Nilsson } 26013df57bcfSMattias Nilsson 26023df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 26033df57bcfSMattias Nilsson .name = "prcmu", 26043df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 26053df57bcfSMattias Nilsson .irq_ack = noop, 26063df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 26073df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 26083df57bcfSMattias Nilsson }; 26093df57bcfSMattias Nilsson 261005ec260eSLinus Walleij static __init char *fw_project_name(u32 project) 2611b58d12feSMattias Nilsson { 2612b58d12feSMattias Nilsson switch (project) { 2613b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500: 2614b58d12feSMattias Nilsson return "U8500"; 261505ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8400: 261605ec260eSLinus Walleij return "U8400"; 2617b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500: 2618b58d12feSMattias Nilsson return "U9500"; 261905ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBB: 262005ec260eSLinus Walleij return "U8500 MBB"; 262105ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C1: 262205ec260eSLinus Walleij return "U8500 C1"; 262305ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C2: 262405ec260eSLinus Walleij return "U8500 C2"; 262505ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C3: 262605ec260eSLinus Walleij return "U8500 C3"; 262705ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C4: 262805ec260eSLinus Walleij return "U8500 C4"; 262905ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9500_MBL: 263005ec260eSLinus Walleij return "U9500 MBL"; 263105ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBL: 263205ec260eSLinus Walleij return "U8500 MBL"; 263305ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBL2: 263405ec260eSLinus Walleij return "U8500 MBL2"; 26355f96a1a6SBengt Jonsson case PRCMU_FW_PROJECT_U8520: 263605ec260eSLinus Walleij return "U8520 MBL"; 26371927ddf6SBengt Jonsson case PRCMU_FW_PROJECT_U8420: 26381927ddf6SBengt Jonsson return "U8420"; 263905ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9540: 264005ec260eSLinus Walleij return "U9540"; 264105ec260eSLinus Walleij case PRCMU_FW_PROJECT_A9420: 264205ec260eSLinus Walleij return "A9420"; 264305ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8540: 264405ec260eSLinus Walleij return "L8540"; 264505ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8580: 264605ec260eSLinus Walleij return "L8580"; 2647b58d12feSMattias Nilsson default: 2648b58d12feSMattias Nilsson return "Unknown"; 2649b58d12feSMattias Nilsson } 2650b58d12feSMattias Nilsson } 2651b58d12feSMattias Nilsson 2652f3f1f0a1SLee Jones static int db8500_irq_map(struct irq_domain *d, unsigned int virq, 2653f3f1f0a1SLee Jones irq_hw_number_t hwirq) 2654f3f1f0a1SLee Jones { 2655f3f1f0a1SLee Jones irq_set_chip_and_handler(virq, &prcmu_irq_chip, 2656f3f1f0a1SLee Jones handle_simple_irq); 2657f3f1f0a1SLee Jones 2658f3f1f0a1SLee Jones return 0; 2659f3f1f0a1SLee Jones } 2660f3f1f0a1SLee Jones 26617ce7b26fSKrzysztof Kozlowski static const struct irq_domain_ops db8500_irq_ops = { 2662f3f1f0a1SLee Jones .map = db8500_irq_map, 2663f3f1f0a1SLee Jones .xlate = irq_domain_xlate_twocell, 2664f3f1f0a1SLee Jones }; 2665f3f1f0a1SLee Jones 2666f864c46aSLinus Walleij static int db8500_irq_init(struct device_node *np) 2667f3f1f0a1SLee Jones { 266889d9b1c9SLinus Walleij int i; 2669a7238e43SLinus Walleij 2670a7238e43SLinus Walleij db8500_irq_domain = irq_domain_add_simple( 2671f864c46aSLinus Walleij np, NUM_PRCMU_WAKEUPS, 0, 2672a7238e43SLinus Walleij &db8500_irq_ops, NULL); 2673f3f1f0a1SLee Jones 2674f3f1f0a1SLee Jones if (!db8500_irq_domain) { 2675f3f1f0a1SLee Jones pr_err("Failed to create irqdomain\n"); 2676f3f1f0a1SLee Jones return -ENOSYS; 2677f3f1f0a1SLee Jones } 2678f3f1f0a1SLee Jones 267989d9b1c9SLinus Walleij /* All wakeups will be used, so create mappings for all */ 268089d9b1c9SLinus Walleij for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) 268189d9b1c9SLinus Walleij irq_create_mapping(db8500_irq_domain, i); 268289d9b1c9SLinus Walleij 2683f3f1f0a1SLee Jones return 0; 2684f3f1f0a1SLee Jones } 2685f3f1f0a1SLee Jones 268605ec260eSLinus Walleij static void dbx500_fw_version_init(struct platform_device *pdev, 268705ec260eSLinus Walleij u32 version_offset) 2688650c2a21SLinus Walleij { 268905ec260eSLinus Walleij struct resource *res; 269005ec260eSLinus Walleij void __iomem *tcpm_base; 2691741cdecfSLee Jones u32 version; 26923df57bcfSMattias Nilsson 269305ec260eSLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 269405ec260eSLinus Walleij "prcmu-tcpm"); 269505ec260eSLinus Walleij if (!res) { 269605ec260eSLinus Walleij dev_err(&pdev->dev, 269705ec260eSLinus Walleij "Error: no prcmu tcpm memory region provided\n"); 269805ec260eSLinus Walleij return; 269905ec260eSLinus Walleij } 270005ec260eSLinus Walleij tcpm_base = ioremap(res->start, resource_size(res)); 2701741cdecfSLee Jones if (!tcpm_base) { 2702741cdecfSLee Jones dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n"); 2703741cdecfSLee Jones return; 2704741cdecfSLee Jones } 270505ec260eSLinus Walleij 270605ec260eSLinus Walleij version = readl(tcpm_base + version_offset); 270705ec260eSLinus Walleij fw_info.version.project = (version & 0xFF); 2708b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF; 2709b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF; 2710b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF; 271105ec260eSLinus Walleij strncpy(fw_info.version.project_name, 2712b58d12feSMattias Nilsson fw_project_name(fw_info.version.project), 271305ec260eSLinus Walleij PRCMU_FW_PROJECT_NAME_LEN); 271405ec260eSLinus Walleij fw_info.valid = true; 271505ec260eSLinus Walleij pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", 271605ec260eSLinus Walleij fw_info.version.project_name, 271705ec260eSLinus Walleij fw_info.version.project, 271805ec260eSLinus Walleij fw_info.version.api_version, 271905ec260eSLinus Walleij fw_info.version.func_version, 272005ec260eSLinus Walleij fw_info.version.errata); 27213df57bcfSMattias Nilsson iounmap(tcpm_base); 27223df57bcfSMattias Nilsson } 2723650c2a21SLinus Walleij 27249a47a8dcSLinus Walleij void __init db8500_prcmu_early_init(u32 phy_base, u32 size) 272505ec260eSLinus Walleij { 27269a47a8dcSLinus Walleij /* 27279a47a8dcSLinus Walleij * This is a temporary remap to bring up the clocks. It is 27289a47a8dcSLinus Walleij * subsequently replaces with a real remap. After the merge of 27299a47a8dcSLinus Walleij * the mailbox subsystem all of this early code goes away, and the 27309a47a8dcSLinus Walleij * clock driver can probe independently. An early initcall will 27319a47a8dcSLinus Walleij * still be needed, but it can be diverted into drivers/clk/ux500. 27329a47a8dcSLinus Walleij */ 27339a47a8dcSLinus Walleij prcmu_base = ioremap(phy_base, size); 27349a47a8dcSLinus Walleij if (!prcmu_base) 27359a47a8dcSLinus Walleij pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); 27369a47a8dcSLinus Walleij 27373df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 27383df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 27393df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 27403df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2741650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2742650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 27434d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE; 27443df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 27453df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 27463df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 27473df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 27483df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 27493df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 27503df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 27513df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2752650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2753650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2754650c2a21SLinus Walleij 27553df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2756650c2a21SLinus Walleij } 2757650c2a21SLinus Walleij 27580508901cSMattias Nilsson static void __init init_prcm_registers(void) 2759d65e12d7SMattias Nilsson { 2760d65e12d7SMattias Nilsson u32 val; 2761d65e12d7SMattias Nilsson 2762d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2763d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2764d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2765d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2766d65e12d7SMattias Nilsson } 2767d65e12d7SMattias Nilsson 27681032fbfdSBengt Jonsson /* 27691032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 27701032fbfdSBengt Jonsson */ 27711032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 27721032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 27731032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 27741032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 27751032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 27761032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 2777ae840635SLee Jones REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), 27781032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 27791032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 27801032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 27811032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 27821032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 27831032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 27841032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 27851032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 27861032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 27871032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 27881032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 27891032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 27901032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2791992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 2792bc367481SLee Jones REGULATOR_SUPPLY("vddvario", "smsc911x.0"), 27931032fbfdSBengt Jonsson }; 27941032fbfdSBengt Jonsson 27951032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 27961032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 27971032fbfdSBengt Jonsson /* AV8100 regulator */ 27981032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 27991032fbfdSBengt Jonsson }; 28001032fbfdSBengt Jonsson 28011032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2802992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2803624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2804624e87c2SBengt Jonsson }; 2805624e87c2SBengt Jonsson 2806624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2807624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2808624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2809624e87c2SBengt Jonsson }; 2810624e87c2SBengt Jonsson 2811624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2812624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2813624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2814624e87c2SBengt Jonsson }; 2815624e87c2SBengt Jonsson 2816624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2817624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2818624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2819624e87c2SBengt Jonsson }; 2820624e87c2SBengt Jonsson 2821624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2822624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2823624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2824624e87c2SBengt Jonsson }; 2825624e87c2SBengt Jonsson 2826624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2827624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2828624e87c2SBengt Jonsson }; 2829624e87c2SBengt Jonsson 2830624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2831624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2832624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2833624e87c2SBengt Jonsson }; 2834624e87c2SBengt Jonsson 2835624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2836624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2837624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2838624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 2839992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 28401032fbfdSBengt Jonsson }; 28411032fbfdSBengt Jonsson 28421032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 28431032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 28441032fbfdSBengt Jonsson .constraints = { 28451032fbfdSBengt Jonsson .name = "db8500-vape", 28461032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28471e45860fSMark Brown .always_on = true, 28481032fbfdSBengt Jonsson }, 28491032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 28501032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 28511032fbfdSBengt Jonsson }, 28521032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 28531032fbfdSBengt Jonsson .constraints = { 28541032fbfdSBengt Jonsson .name = "db8500-varm", 28551032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28561032fbfdSBengt Jonsson }, 28571032fbfdSBengt Jonsson }, 28581032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 28591032fbfdSBengt Jonsson .constraints = { 28601032fbfdSBengt Jonsson .name = "db8500-vmodem", 28611032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28621032fbfdSBengt Jonsson }, 28631032fbfdSBengt Jonsson }, 28641032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 28651032fbfdSBengt Jonsson .constraints = { 28661032fbfdSBengt Jonsson .name = "db8500-vpll", 28671032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28681032fbfdSBengt Jonsson }, 28691032fbfdSBengt Jonsson }, 28701032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 28711032fbfdSBengt Jonsson .constraints = { 28721032fbfdSBengt Jonsson .name = "db8500-vsmps1", 28731032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28741032fbfdSBengt Jonsson }, 28751032fbfdSBengt Jonsson }, 28761032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 28771032fbfdSBengt Jonsson .constraints = { 28781032fbfdSBengt Jonsson .name = "db8500-vsmps2", 28791032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28801032fbfdSBengt Jonsson }, 28811032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 28821032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 28831032fbfdSBengt Jonsson }, 28841032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 28851032fbfdSBengt Jonsson .constraints = { 28861032fbfdSBengt Jonsson .name = "db8500-vsmps3", 28871032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28881032fbfdSBengt Jonsson }, 28891032fbfdSBengt Jonsson }, 28901032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 28911032fbfdSBengt Jonsson .constraints = { 28921032fbfdSBengt Jonsson .name = "db8500-vrf1", 28931032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28941032fbfdSBengt Jonsson }, 28951032fbfdSBengt Jonsson }, 28961032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2897992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 28981032fbfdSBengt Jonsson .constraints = { 28991032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 29001032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29011032fbfdSBengt Jonsson }, 2902624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2903624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 29041032fbfdSBengt Jonsson }, 29051032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 29061032fbfdSBengt Jonsson .constraints = { 29071032fbfdSBengt Jonsson /* "ret" means "retention" */ 29081032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 29091032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29101032fbfdSBengt Jonsson }, 29111032fbfdSBengt Jonsson }, 29121032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2913992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29141032fbfdSBengt Jonsson .constraints = { 29151032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 29161032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29171032fbfdSBengt Jonsson }, 2918624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2919624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 29201032fbfdSBengt Jonsson }, 29211032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2922992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29231032fbfdSBengt Jonsson .constraints = { 29241032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 29251032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29261032fbfdSBengt Jonsson }, 2927624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2928624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 29291032fbfdSBengt Jonsson }, 29301032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 29311032fbfdSBengt Jonsson .constraints = { 29321032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 29331032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29341032fbfdSBengt Jonsson }, 29351032fbfdSBengt Jonsson }, 29361032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2937992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29381032fbfdSBengt Jonsson .constraints = { 29391032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 29401032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29411032fbfdSBengt Jonsson }, 2942624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 2943624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 29441032fbfdSBengt Jonsson }, 29451032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 29461032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29471032fbfdSBengt Jonsson .constraints = { 29481032fbfdSBengt Jonsson .name = "db8500-sga", 29491032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29501032fbfdSBengt Jonsson }, 2951624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 2952624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2953624e87c2SBengt Jonsson 29541032fbfdSBengt Jonsson }, 29551032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 29561032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29571032fbfdSBengt Jonsson .constraints = { 29581032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 29591032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29601032fbfdSBengt Jonsson }, 29611032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 29621032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 29631032fbfdSBengt Jonsson }, 29641032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 2965992b133aSBengt Jonsson /* 2966992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off, 2967992b133aSBengt Jonsson * no need to hold Vape 2968992b133aSBengt Jonsson */ 29691032fbfdSBengt Jonsson .constraints = { 29701032fbfdSBengt Jonsson .name = "db8500-esram12", 29711032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29721032fbfdSBengt Jonsson }, 2973624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 2974624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 29751032fbfdSBengt Jonsson }, 29761032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 29771032fbfdSBengt Jonsson .constraints = { 29781032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 29791032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29801032fbfdSBengt Jonsson }, 29811032fbfdSBengt Jonsson }, 29821032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 2983992b133aSBengt Jonsson /* 2984992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off, 2985992b133aSBengt Jonsson * no need to hold Vape 2986992b133aSBengt Jonsson */ 29871032fbfdSBengt Jonsson .constraints = { 29881032fbfdSBengt Jonsson .name = "db8500-esram34", 29891032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29901032fbfdSBengt Jonsson }, 2991624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 2992624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 29931032fbfdSBengt Jonsson }, 29941032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 29951032fbfdSBengt Jonsson .constraints = { 29961032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 29971032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29981032fbfdSBengt Jonsson }, 29991032fbfdSBengt Jonsson }, 30001032fbfdSBengt Jonsson }; 30011032fbfdSBengt Jonsson 3002b3aac62bSFabio Baltieri static struct ux500_wdt_data db8500_wdt_pdata = { 3003b3aac62bSFabio Baltieri .timeout = 600, /* 10 minutes */ 3004b3aac62bSFabio Baltieri .has_28_bits_resolution = true, 3005b3aac62bSFabio Baltieri }; 300655b175d7SArnd Bergmann /* 300755b175d7SArnd Bergmann * Thermal Sensor 300855b175d7SArnd Bergmann */ 300955b175d7SArnd Bergmann 301055b175d7SArnd Bergmann static struct resource db8500_thsens_resources[] = { 301155b175d7SArnd Bergmann { 301255b175d7SArnd Bergmann .name = "IRQ_HOTMON_LOW", 301355b175d7SArnd Bergmann .start = IRQ_PRCMU_HOTMON_LOW, 301455b175d7SArnd Bergmann .end = IRQ_PRCMU_HOTMON_LOW, 301555b175d7SArnd Bergmann .flags = IORESOURCE_IRQ, 301655b175d7SArnd Bergmann }, 301755b175d7SArnd Bergmann { 301855b175d7SArnd Bergmann .name = "IRQ_HOTMON_HIGH", 301955b175d7SArnd Bergmann .start = IRQ_PRCMU_HOTMON_HIGH, 302055b175d7SArnd Bergmann .end = IRQ_PRCMU_HOTMON_HIGH, 302155b175d7SArnd Bergmann .flags = IORESOURCE_IRQ, 302255b175d7SArnd Bergmann }, 302355b175d7SArnd Bergmann }; 302455b175d7SArnd Bergmann 302555b175d7SArnd Bergmann static struct db8500_thsens_platform_data db8500_thsens_data = { 302655b175d7SArnd Bergmann .trip_points[0] = { 302755b175d7SArnd Bergmann .temp = 70000, 302855b175d7SArnd Bergmann .type = THERMAL_TRIP_ACTIVE, 302955b175d7SArnd Bergmann .cdev_name = { 303055b175d7SArnd Bergmann [0] = "thermal-cpufreq-0", 303155b175d7SArnd Bergmann }, 303255b175d7SArnd Bergmann }, 303355b175d7SArnd Bergmann .trip_points[1] = { 303455b175d7SArnd Bergmann .temp = 75000, 303555b175d7SArnd Bergmann .type = THERMAL_TRIP_ACTIVE, 303655b175d7SArnd Bergmann .cdev_name = { 303755b175d7SArnd Bergmann [0] = "thermal-cpufreq-0", 303855b175d7SArnd Bergmann }, 303955b175d7SArnd Bergmann }, 304055b175d7SArnd Bergmann .trip_points[2] = { 304155b175d7SArnd Bergmann .temp = 80000, 304255b175d7SArnd Bergmann .type = THERMAL_TRIP_ACTIVE, 304355b175d7SArnd Bergmann .cdev_name = { 304455b175d7SArnd Bergmann [0] = "thermal-cpufreq-0", 304555b175d7SArnd Bergmann }, 304655b175d7SArnd Bergmann }, 304755b175d7SArnd Bergmann .trip_points[3] = { 304855b175d7SArnd Bergmann .temp = 85000, 304955b175d7SArnd Bergmann .type = THERMAL_TRIP_CRITICAL, 305055b175d7SArnd Bergmann }, 305155b175d7SArnd Bergmann .num_trips = 4, 305255b175d7SArnd Bergmann }; 3053b3aac62bSFabio Baltieri 30545ac98553SGeert Uytterhoeven static const struct mfd_cell common_prcmu_devs[] = { 3055d98a5384SLee Jones { 3056d98a5384SLee Jones .name = "ux500_wdt", 3057d98a5384SLee Jones .platform_data = &db8500_wdt_pdata, 3058d98a5384SLee Jones .pdata_size = sizeof(db8500_wdt_pdata), 3059d98a5384SLee Jones .id = -1, 3060d98a5384SLee Jones }, 3061d98a5384SLee Jones }; 3062d98a5384SLee Jones 30635ac98553SGeert Uytterhoeven static const struct mfd_cell db8500_prcmu_devs[] = { 30643df57bcfSMattias Nilsson { 30653df57bcfSMattias Nilsson .name = "db8500-prcmu-regulators", 30665d90322bSLee Jones .of_compatible = "stericsson,db8500-prcmu-regulator", 30671ed7891fSMattias Wallin .platform_data = &db8500_regulators, 30681ed7891fSMattias Wallin .pdata_size = sizeof(db8500_regulators), 30693df57bcfSMattias Nilsson }, 30703df57bcfSMattias Nilsson { 307184c7c20fSLee Jones .name = "cpufreq-ux500", 307284c7c20fSLee Jones .of_compatible = "stericsson,cpufreq-ux500", 3073c280f45fSUlf Hansson .platform_data = &db8500_cpufreq_table, 3074c280f45fSUlf Hansson .pdata_size = sizeof(db8500_cpufreq_table), 30753df57bcfSMattias Nilsson }, 30766d11d135SLee Jones { 30778025395fSLinus Walleij .name = "cpuidle-dbx500", 30788025395fSLinus Walleij .of_compatible = "stericsson,cpuidle-dbx500", 30798025395fSLinus Walleij }, 30808025395fSLinus Walleij { 308155b175d7SArnd Bergmann .name = "db8500-thermal", 308255b175d7SArnd Bergmann .num_resources = ARRAY_SIZE(db8500_thsens_resources), 308355b175d7SArnd Bergmann .resources = db8500_thsens_resources, 308455b175d7SArnd Bergmann .platform_data = &db8500_thsens_data, 3085a3ef0debSLee Jones .pdata_size = sizeof(db8500_thsens_data), 30866d11d135SLee Jones }, 30873df57bcfSMattias Nilsson }; 30883df57bcfSMattias Nilsson 3089c280f45fSUlf Hansson static void db8500_prcmu_update_cpufreq(void) 3090c280f45fSUlf Hansson { 3091c280f45fSUlf Hansson if (prcmu_has_arm_maxopp()) { 3092c280f45fSUlf Hansson db8500_cpufreq_table[3].frequency = 1000000; 309350701588SViresh Kumar db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP; 3094c280f45fSUlf Hansson } 3095c280f45fSUlf Hansson } 3096c280f45fSUlf Hansson 30974e657946SArnd Bergmann static int db8500_prcmu_register_ab8500(struct device *parent) 309855b175d7SArnd Bergmann { 3099f864c46aSLinus Walleij struct device_node *np; 3100f864c46aSLinus Walleij struct resource ab8500_resource; 31015785a97eSKrzysztof Kozlowski const struct mfd_cell ab8500_cell = { 310255b175d7SArnd Bergmann .name = "ab8500-core", 310355b175d7SArnd Bergmann .of_compatible = "stericsson,ab8500", 310455b175d7SArnd Bergmann .id = AB8500_VERSION_AB8500, 310555b175d7SArnd Bergmann .resources = &ab8500_resource, 310655b175d7SArnd Bergmann .num_resources = 1, 310755b175d7SArnd Bergmann }; 310855b175d7SArnd Bergmann 3109f864c46aSLinus Walleij if (!parent->of_node) 3110f864c46aSLinus Walleij return -ENODEV; 3111f864c46aSLinus Walleij 3112f864c46aSLinus Walleij /* Look up the device node, sneak the IRQ out of it */ 3113f864c46aSLinus Walleij for_each_child_of_node(parent->of_node, np) { 3114f864c46aSLinus Walleij if (of_device_is_compatible(np, ab8500_cell.of_compatible)) 3115f864c46aSLinus Walleij break; 3116f864c46aSLinus Walleij } 3117f864c46aSLinus Walleij if (!np) { 3118f864c46aSLinus Walleij dev_info(parent, "could not find AB8500 node in the device tree\n"); 3119f864c46aSLinus Walleij return -ENODEV; 3120f864c46aSLinus Walleij } 3121f864c46aSLinus Walleij of_irq_to_resource_table(np, &ab8500_resource, 1); 3122f864c46aSLinus Walleij 312355b175d7SArnd Bergmann return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL); 312455b175d7SArnd Bergmann } 312555b175d7SArnd Bergmann 31263df57bcfSMattias Nilsson /** 31273df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 31283df57bcfSMattias Nilsson * 31293df57bcfSMattias Nilsson */ 3130f791be49SBill Pemberton static int db8500_prcmu_probe(struct platform_device *pdev) 31313df57bcfSMattias Nilsson { 3132ca7edd16SLee Jones struct device_node *np = pdev->dev.of_node; 313355b175d7SArnd Bergmann int irq = 0, err = 0; 313405ec260eSLinus Walleij struct resource *res; 31353df57bcfSMattias Nilsson 3136b047d981SLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); 3137b047d981SLinus Walleij if (!res) { 3138b047d981SLinus Walleij dev_err(&pdev->dev, "no prcmu memory region provided\n"); 31396bdf891aSLee Jones return -EINVAL; 3140b047d981SLinus Walleij } 3141b047d981SLinus Walleij prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 3142b047d981SLinus Walleij if (!prcmu_base) { 3143b047d981SLinus Walleij dev_err(&pdev->dev, 3144b047d981SLinus Walleij "failed to ioremap prcmu register memory\n"); 31456bdf891aSLee Jones return -ENOMEM; 3146b047d981SLinus Walleij } 31470508901cSMattias Nilsson init_prcm_registers(); 31484e657946SArnd Bergmann dbx500_fw_version_init(pdev, DB8500_PRCMU_FW_VERSION_OFFSET); 314905ec260eSLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); 315005ec260eSLinus Walleij if (!res) { 315105ec260eSLinus Walleij dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); 31526bdf891aSLee Jones return -EINVAL; 315305ec260eSLinus Walleij } 315405ec260eSLinus Walleij tcdm_base = devm_ioremap(&pdev->dev, res->start, 315505ec260eSLinus Walleij resource_size(res)); 315651a7e02bSPramod Gurav if (!tcdm_base) { 315751a7e02bSPramod Gurav dev_err(&pdev->dev, 315851a7e02bSPramod Gurav "failed to ioremap prcmu-tcdm register memory\n"); 31596bdf891aSLee Jones return -ENOMEM; 316051a7e02bSPramod Gurav } 316105ec260eSLinus Walleij 31623df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 3163c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 31643df57bcfSMattias Nilsson 3165ca7edd16SLee Jones irq = platform_get_irq(pdev, 0); 316605ec260eSLinus Walleij if (irq <= 0) { 316705ec260eSLinus Walleij dev_err(&pdev->dev, "no prcmu irq provided\n"); 31686bdf891aSLee Jones return irq; 316905ec260eSLinus Walleij } 3170ca7edd16SLee Jones 3171ca7edd16SLee Jones err = request_threaded_irq(irq, prcmu_irq_handler, 31723df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 31733df57bcfSMattias Nilsson if (err < 0) { 31743df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 31756bdf891aSLee Jones return err; 31763df57bcfSMattias Nilsson } 31773df57bcfSMattias Nilsson 3178f864c46aSLinus Walleij db8500_irq_init(np); 31793a8e39c9SLee Jones 31803df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 31813df57bcfSMattias Nilsson 3182c280f45fSUlf Hansson db8500_prcmu_update_cpufreq(); 3183c280f45fSUlf Hansson 3184d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs, 3185d98a5384SLee Jones ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain); 3186ca7edd16SLee Jones if (err) { 31873df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 3188ca7edd16SLee Jones return err; 3189ca7edd16SLee Jones } 3190ca7edd16SLee Jones 3191d98a5384SLee Jones /* TODO: Remove restriction when clk definitions are available. */ 3192d98a5384SLee Jones if (!of_machine_is_compatible("st-ericsson,u8540")) { 3193d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3194d98a5384SLee Jones ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, 3195d98a5384SLee Jones db8500_irq_domain); 3196d98a5384SLee Jones if (err) { 3197d98a5384SLee Jones mfd_remove_devices(&pdev->dev); 3198d98a5384SLee Jones pr_err("prcmu: Failed to add subdevices\n"); 31996bdf891aSLee Jones return err; 3200d98a5384SLee Jones } 3201d98a5384SLee Jones } 3202d98a5384SLee Jones 32034e657946SArnd Bergmann err = db8500_prcmu_register_ab8500(&pdev->dev); 320455b175d7SArnd Bergmann if (err) { 320555b175d7SArnd Bergmann mfd_remove_devices(&pdev->dev); 320655b175d7SArnd Bergmann pr_err("prcmu: Failed to add ab8500 subdevice\n"); 32076bdf891aSLee Jones return err; 320855b175d7SArnd Bergmann } 320955b175d7SArnd Bergmann 32103df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 32113df57bcfSMattias Nilsson return err; 32123df57bcfSMattias Nilsson } 32133c144762SLee Jones static const struct of_device_id db8500_prcmu_match[] = { 32143c144762SLee Jones { .compatible = "stericsson,db8500-prcmu"}, 32153c144762SLee Jones { }, 32163c144762SLee Jones }; 32173df57bcfSMattias Nilsson 32183df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 32193df57bcfSMattias Nilsson .driver = { 32203df57bcfSMattias Nilsson .name = "db8500-prcmu", 32213c144762SLee Jones .of_match_table = db8500_prcmu_match, 32223df57bcfSMattias Nilsson }, 32239fc63f67SLee Jones .probe = db8500_prcmu_probe, 32243df57bcfSMattias Nilsson }; 32253df57bcfSMattias Nilsson 32263df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 32273df57bcfSMattias Nilsson { 32289fc63f67SLee Jones return platform_driver_register(&db8500_prcmu_driver); 32293df57bcfSMattias Nilsson } 32303df57bcfSMattias Nilsson 3231a661aca4SLee Jones core_initcall(db8500_prcmu_init); 32323df57bcfSMattias Nilsson 32333df57bcfSMattias Nilsson MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); 32343df57bcfSMattias Nilsson MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); 32353df57bcfSMattias Nilsson MODULE_LICENSE("GPL v2"); 3236