10376148fSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2650c2a21SLinus Walleij /* 3adef9cf5SPaul Gortmaker * DB8500 PRCM Unit driver 4adef9cf5SPaul Gortmaker * 5650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009 6650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 7650c2a21SLinus Walleij * 8650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 9650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 10650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 11650c2a21SLinus Walleij * 12650c2a21SLinus Walleij * U8500 PRCM Unit interface driver 13650c2a21SLinus Walleij */ 14adef9cf5SPaul Gortmaker #include <linux/init.h> 15adef9cf5SPaul Gortmaker #include <linux/export.h> 163df57bcfSMattias Nilsson #include <linux/kernel.h> 173df57bcfSMattias Nilsson #include <linux/delay.h> 18650c2a21SLinus Walleij #include <linux/errno.h> 19650c2a21SLinus Walleij #include <linux/err.h> 203df57bcfSMattias Nilsson #include <linux/spinlock.h> 21650c2a21SLinus Walleij #include <linux/io.h> 223df57bcfSMattias Nilsson #include <linux/slab.h> 23650c2a21SLinus Walleij #include <linux/mutex.h> 24650c2a21SLinus Walleij #include <linux/completion.h> 253df57bcfSMattias Nilsson #include <linux/irq.h> 26650c2a21SLinus Walleij #include <linux/jiffies.h> 27650c2a21SLinus Walleij #include <linux/bitops.h> 283df57bcfSMattias Nilsson #include <linux/fs.h> 29d98a5384SLee Jones #include <linux/of.h> 3022fb3ad0SLinus Walleij #include <linux/of_address.h> 31f864c46aSLinus Walleij #include <linux/of_irq.h> 323df57bcfSMattias Nilsson #include <linux/platform_device.h> 333df57bcfSMattias Nilsson #include <linux/uaccess.h> 343df57bcfSMattias Nilsson #include <linux/mfd/core.h> 3573180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h> 363a8e39c9SLee Jones #include <linux/mfd/abx500/ab8500.h> 371032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h> 381032fbfdSBengt Jonsson #include <linux/regulator/machine.h> 39b3aac62bSFabio Baltieri #include <linux/platform_data/ux500_wdt.h> 4073180f85SMattias Nilsson #include "dbx500-prcmu-regs.h" 41650c2a21SLinus Walleij 423df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */ 433df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC 443df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) 453df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) 463df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) 473df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) 483df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) 493df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) 503df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) 513df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) 523df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) 533df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) 543df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) 553df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) 563df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) 57650c2a21SLinus Walleij 583df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0 593df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f 603df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6 613df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) 62650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7 63650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) 64650c2a21SLinus Walleij 653df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF 663df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE 673df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD 683df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ 69650c2a21SLinus Walleij 703df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ 713df57bcfSMattias Nilsson 723df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ 733df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) 743df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) 753df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) 763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) 773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) 783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) 793df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) 803df57bcfSMattias Nilsson 813df57bcfSMattias Nilsson /* Req Mailboxes */ 823df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ 833df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ 843df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ 853df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ 863df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ 873df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ 883df57bcfSMattias Nilsson 893df57bcfSMattias Nilsson /* Ack Mailboxes */ 903df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ 913df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ 923df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ 933df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ 943df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ 953df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ 963df57bcfSMattias Nilsson 973df57bcfSMattias Nilsson /* Mailbox 0 headers */ 983df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0 993df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1 1003df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3 1013df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4 1023df57bcfSMattias Nilsson 1033df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2 1043df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5 1053df57bcfSMattias Nilsson 1063df57bcfSMattias Nilsson /* Mailbox 0 REQs */ 1073df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) 1083df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) 1093df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) 1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) 1113df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) 1123df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) 1133df57bcfSMattias Nilsson 1143df57bcfSMattias Nilsson /* Mailbox 0 ACKs */ 1153df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) 1163df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) 1173df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) 1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) 1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) 1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) 1213df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 1223df57bcfSMattias Nilsson 1233df57bcfSMattias Nilsson /* Mailbox 1 headers */ 1243df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0 1253df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2 1263df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 1273df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 1283df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5 129a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6 1303df57bcfSMattias Nilsson 1313df57bcfSMattias Nilsson /* Mailbox 1 Requests */ 1323df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) 1333df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) 134a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) 1356b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1 1366b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2 137a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4 138a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8 1393df57bcfSMattias Nilsson 1403df57bcfSMattias Nilsson /* Mailbox 1 ACKs */ 1413df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) 1423df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) 1433df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) 1443df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) 1453df57bcfSMattias Nilsson 1463df57bcfSMattias Nilsson /* Mailbox 2 headers */ 1473df57bcfSMattias Nilsson #define MB2H_DPS 0x0 1483df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1 1493df57bcfSMattias Nilsson 1503df57bcfSMattias Nilsson /* Mailbox 2 REQs */ 1513df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) 1523df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) 1533df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) 1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) 1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) 1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) 1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) 1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) 1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) 1603df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) 1613df57bcfSMattias Nilsson 1623df57bcfSMattias Nilsson /* Mailbox 2 ACKs */ 1633df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) 1643df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE 1653df57bcfSMattias Nilsson 1663df57bcfSMattias Nilsson /* Mailbox 3 headers */ 1673df57bcfSMattias Nilsson #define MB3H_ANC 0x0 1683df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1 1693df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE 1703df57bcfSMattias Nilsson 1713df57bcfSMattias Nilsson /* Mailbox 3 Requests */ 1723df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) 1733df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) 1743df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) 1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) 1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) 1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) 1783df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) 1793df57bcfSMattias Nilsson 1803df57bcfSMattias Nilsson /* Mailbox 4 headers */ 1813df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0 1823df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1 1833df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12 1843df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13 1853df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14 186a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16 187a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17 188a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18 189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19 190a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20 1913df57bcfSMattias Nilsson 1923df57bcfSMattias Nilsson /* Mailbox 4 Requests */ 1933df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) 1943df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) 1953df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) 1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) 1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) 1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) 1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) 2003df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) 2013df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0) 2023df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1) 203a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) 204a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) 205a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) 206a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) 207a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7) 208a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0 209a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf 2103df57bcfSMattias Nilsson 2113df57bcfSMattias Nilsson /* Mailbox 5 Requests */ 2123df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) 2133df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) 2143df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) 2153df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) 2167a4f2609SLinus Walleij #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) 2177a4f2609SLinus Walleij #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) 2183df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3) 2193df57bcfSMattias Nilsson 2203df57bcfSMattias Nilsson /* Mailbox 5 ACKs */ 2213df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) 2223df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) 2233df57bcfSMattias Nilsson #define I2C_WR_OK 0x1 2243df57bcfSMattias Nilsson #define I2C_RD_OK 0x2 2253df57bcfSMattias Nilsson 2263df57bcfSMattias Nilsson #define NUM_MB 8 2273df57bcfSMattias Nilsson #define MBOX_BIT BIT 2283df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) 2293df57bcfSMattias Nilsson 2303df57bcfSMattias Nilsson /* 2313df57bcfSMattias Nilsson * Wakeups/IRQs 2323df57bcfSMattias Nilsson */ 2333df57bcfSMattias Nilsson 2343df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0) 2353df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1) 2363df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2) 2373df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3) 2383df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4) 2393df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5) 2403df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6) 2413df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7) 2423df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8) 2433df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9) 2443df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10) 2453df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) 2463df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) 2473df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13) 2483df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14) 2493df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) 2503df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17) 2513df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18) 2523df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19) 2533df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) 2543df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23) 2553df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24) 2563df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25) 2573df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26) 2583df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27) 2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28) 2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29) 2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30) 2623df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31) 2633df57bcfSMattias Nilsson 264b58d12feSMattias Nilsson static struct { 265b58d12feSMattias Nilsson bool valid; 266b58d12feSMattias Nilsson struct prcmu_fw_version version; 267b58d12feSMattias Nilsson } fw_info; 268b58d12feSMattias Nilsson 269f3f1f0a1SLee Jones static struct irq_domain *db8500_irq_domain; 270f3f1f0a1SLee Jones 2713df57bcfSMattias Nilsson /* 2723df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in 2733df57bcfSMattias Nilsson * communication with the PRCMU firmware. 2743df57bcfSMattias Nilsson * 2753df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though 2763df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move 2773df57bcfSMattias Nilsson * around, to further complicate matters.) 2783df57bcfSMattias Nilsson */ 27955b175d7SArnd Bergmann #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name)) 2803df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 28155b175d7SArnd Bergmann 28255b175d7SArnd Bergmann #define IRQ_PRCMU_RTC 0 28355b175d7SArnd Bergmann #define IRQ_PRCMU_RTT0 1 28455b175d7SArnd Bergmann #define IRQ_PRCMU_RTT1 2 28555b175d7SArnd Bergmann #define IRQ_PRCMU_HSI0 3 28655b175d7SArnd Bergmann #define IRQ_PRCMU_HSI1 4 28755b175d7SArnd Bergmann #define IRQ_PRCMU_CA_WAKE 5 28855b175d7SArnd Bergmann #define IRQ_PRCMU_USB 6 28955b175d7SArnd Bergmann #define IRQ_PRCMU_ABB 7 29055b175d7SArnd Bergmann #define IRQ_PRCMU_ABB_FIFO 8 29155b175d7SArnd Bergmann #define IRQ_PRCMU_ARM 9 29255b175d7SArnd Bergmann #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10 29355b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO0 11 29455b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO1 12 29555b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO2 13 29655b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO3 14 29755b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO4 15 29855b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO5 16 29955b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO6 17 30055b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO7 18 30155b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO8 19 30255b175d7SArnd Bergmann #define IRQ_PRCMU_CA_SLEEP 20 30355b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_LOW 21 30455b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_HIGH 22 30555b175d7SArnd Bergmann #define NUM_PRCMU_WAKEUPS 23 30655b175d7SArnd Bergmann 3073df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 3083df57bcfSMattias Nilsson IRQ_ENTRY(RTC), 3093df57bcfSMattias Nilsson IRQ_ENTRY(RTT0), 3103df57bcfSMattias Nilsson IRQ_ENTRY(RTT1), 3113df57bcfSMattias Nilsson IRQ_ENTRY(HSI0), 3123df57bcfSMattias Nilsson IRQ_ENTRY(HSI1), 3133df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE), 3143df57bcfSMattias Nilsson IRQ_ENTRY(USB), 3153df57bcfSMattias Nilsson IRQ_ENTRY(ABB), 3163df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO), 3173df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP), 3183df57bcfSMattias Nilsson IRQ_ENTRY(ARM), 3193df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW), 3203df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH), 3213df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ), 3223df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0), 3233df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1), 3243df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2), 3253df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3), 3263df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4), 3273df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5), 3283df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6), 3293df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7), 3303df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8) 331650c2a21SLinus Walleij }; 332650c2a21SLinus Walleij 3333df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) 3343df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) 3353df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { 3363df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC), 3373df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0), 3383df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1), 3393df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0), 3403df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1), 3413df57bcfSMattias Nilsson WAKEUP_ENTRY(USB), 3423df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB), 3433df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO), 3443df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM) 3453df57bcfSMattias Nilsson }; 3463df57bcfSMattias Nilsson 3473df57bcfSMattias Nilsson /* 3483df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication. 3493df57bcfSMattias Nilsson * @lock: The transaction lock. 3503df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of) 3513df57bcfSMattias Nilsson * the request data. 3523df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts. 3533df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3543df57bcfSMattias Nilsson */ 3553df57bcfSMattias Nilsson static struct { 3563df57bcfSMattias Nilsson spinlock_t lock; 3573df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock; 3583df57bcfSMattias Nilsson struct work_struct mask_work; 3593df57bcfSMattias Nilsson struct mutex ac_wake_lock; 3603df57bcfSMattias Nilsson struct completion ac_wake_work; 3613df57bcfSMattias Nilsson struct { 3623df57bcfSMattias Nilsson u32 dbb_irqs; 3633df57bcfSMattias Nilsson u32 dbb_wakeups; 3643df57bcfSMattias Nilsson u32 abb_events; 3653df57bcfSMattias Nilsson } req; 3663df57bcfSMattias Nilsson } mb0_transfer; 3673df57bcfSMattias Nilsson 3683df57bcfSMattias Nilsson /* 3693df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication. 3703df57bcfSMattias Nilsson * @lock: The transaction lock. 3713df57bcfSMattias Nilsson * @work: The transaction completion structure. 3724d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP. 3733df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3743df57bcfSMattias Nilsson */ 375650c2a21SLinus Walleij static struct { 376650c2a21SLinus Walleij struct mutex lock; 377650c2a21SLinus Walleij struct completion work; 3784d64d2e3SMattias Nilsson u8 ape_opp; 379650c2a21SLinus Walleij struct { 3803df57bcfSMattias Nilsson u8 header; 381650c2a21SLinus Walleij u8 arm_opp; 382650c2a21SLinus Walleij u8 ape_opp; 3833df57bcfSMattias Nilsson u8 ape_voltage_status; 384650c2a21SLinus Walleij } ack; 385650c2a21SLinus Walleij } mb1_transfer; 386650c2a21SLinus Walleij 3873df57bcfSMattias Nilsson /* 3883df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication. 3893df57bcfSMattias Nilsson * @lock: The transaction lock. 3903df57bcfSMattias Nilsson * @work: The transaction completion structure. 3913df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock. 3923df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. 3933df57bcfSMattias Nilsson * @req: Request data that need to persist between requests. 3943df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 3953df57bcfSMattias Nilsson */ 396650c2a21SLinus Walleij static struct { 397650c2a21SLinus Walleij struct mutex lock; 398650c2a21SLinus Walleij struct completion work; 3993df57bcfSMattias Nilsson spinlock_t auto_pm_lock; 4003df57bcfSMattias Nilsson bool auto_pm_enabled; 4013df57bcfSMattias Nilsson struct { 4023df57bcfSMattias Nilsson u8 status; 4033df57bcfSMattias Nilsson } ack; 4043df57bcfSMattias Nilsson } mb2_transfer; 4053df57bcfSMattias Nilsson 4063df57bcfSMattias Nilsson /* 4073df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication. 4083df57bcfSMattias Nilsson * @lock: The request lock. 4093df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests. 4103df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests. 4113df57bcfSMattias Nilsson */ 4123df57bcfSMattias Nilsson static struct { 4133df57bcfSMattias Nilsson spinlock_t lock; 4143df57bcfSMattias Nilsson struct mutex sysclk_lock; 4153df57bcfSMattias Nilsson struct completion sysclk_work; 4163df57bcfSMattias Nilsson } mb3_transfer; 4173df57bcfSMattias Nilsson 4183df57bcfSMattias Nilsson /* 4193df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication. 4203df57bcfSMattias Nilsson * @lock: The transaction lock. 4213df57bcfSMattias Nilsson * @work: The transaction completion structure. 4223df57bcfSMattias Nilsson */ 4233df57bcfSMattias Nilsson static struct { 4243df57bcfSMattias Nilsson struct mutex lock; 4253df57bcfSMattias Nilsson struct completion work; 4263df57bcfSMattias Nilsson } mb4_transfer; 4273df57bcfSMattias Nilsson 4283df57bcfSMattias Nilsson /* 4293df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication. 4303df57bcfSMattias Nilsson * @lock: The transaction lock. 4313df57bcfSMattias Nilsson * @work: The transaction completion structure. 4323df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data. 4333df57bcfSMattias Nilsson */ 4343df57bcfSMattias Nilsson static struct { 4353df57bcfSMattias Nilsson struct mutex lock; 4363df57bcfSMattias Nilsson struct completion work; 437650c2a21SLinus Walleij struct { 438650c2a21SLinus Walleij u8 status; 439650c2a21SLinus Walleij u8 value; 440650c2a21SLinus Walleij } ack; 441650c2a21SLinus Walleij } mb5_transfer; 442650c2a21SLinus Walleij 4433df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 4443df57bcfSMattias Nilsson 4453df57bcfSMattias Nilsson /* Spinlocks */ 446b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock); 4473df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock); 4483df57bcfSMattias Nilsson 4493df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */ 4503df57bcfSMattias Nilsson static __iomem void *tcdm_base; 451b047d981SLinus Walleij static __iomem void *prcmu_base; 4523df57bcfSMattias Nilsson 4533df57bcfSMattias Nilsson struct clk_mgt { 454b047d981SLinus Walleij u32 offset; 4553df57bcfSMattias Nilsson u32 pllsw; 4566b6fae2bSMattias Nilsson int branch; 4576b6fae2bSMattias Nilsson bool clk38div; 4586b6fae2bSMattias Nilsson }; 4596b6fae2bSMattias Nilsson 4606b6fae2bSMattias Nilsson enum { 4616b6fae2bSMattias Nilsson PLL_RAW, 4626b6fae2bSMattias Nilsson PLL_FIX, 4636b6fae2bSMattias Nilsson PLL_DIV 4643df57bcfSMattias Nilsson }; 4653df57bcfSMattias Nilsson 4663df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock); 4673df57bcfSMattias Nilsson 4686b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ 4696b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} 4706746f232SSachin Kamat static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { 4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), 4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), 4736b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), 4746b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), 4756b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), 4766b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), 4776b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), 4786b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), 4796b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), 4806b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), 4816b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), 4826b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 4836b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 4846b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 4856b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 4866b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 4876b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 4886b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), 4896b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), 4906b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), 4916b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), 4926b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), 4936b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), 4946b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), 4956b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), 4966b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), 4976b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), 4986b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), 4996b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), 5006b6fae2bSMattias Nilsson }; 5016b6fae2bSMattias Nilsson 5026b6fae2bSMattias Nilsson struct dsiclk { 5036b6fae2bSMattias Nilsson u32 divsel_mask; 5046b6fae2bSMattias Nilsson u32 divsel_shift; 5056b6fae2bSMattias Nilsson u32 divsel; 5066b6fae2bSMattias Nilsson }; 5076b6fae2bSMattias Nilsson 5086b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = { 5096b6fae2bSMattias Nilsson { 5106b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, 5116b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, 5126b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 5136b6fae2bSMattias Nilsson }, 5146b6fae2bSMattias Nilsson { 5156b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, 5166b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, 5176b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI, 5186b6fae2bSMattias Nilsson } 5196b6fae2bSMattias Nilsson }; 5206b6fae2bSMattias Nilsson 5216b6fae2bSMattias Nilsson struct dsiescclk { 5226b6fae2bSMattias Nilsson u32 en; 5236b6fae2bSMattias Nilsson u32 div_mask; 5246b6fae2bSMattias Nilsson u32 div_shift; 5256b6fae2bSMattias Nilsson }; 5266b6fae2bSMattias Nilsson 5276b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = { 5286b6fae2bSMattias Nilsson { 5296b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, 5306b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 5316b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, 5326b6fae2bSMattias Nilsson }, 5336b6fae2bSMattias Nilsson { 5346b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, 5356b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 5366b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, 5376b6fae2bSMattias Nilsson }, 5386b6fae2bSMattias Nilsson { 5396b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, 5406b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 5416b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, 5426b6fae2bSMattias Nilsson } 5433df57bcfSMattias Nilsson }; 5443df57bcfSMattias Nilsson 54520aee5b6SMichel Jaouen 5463df57bcfSMattias Nilsson /* 5473df57bcfSMattias Nilsson * Used by MCDE to setup all necessary PRCMU registers 5483df57bcfSMattias Nilsson */ 5493df57bcfSMattias Nilsson #define PRCMU_RESET_DSIPLL 0x00004000 5503df57bcfSMattias Nilsson #define PRCMU_UNCLAMP_DSIPLL 0x00400800 5513df57bcfSMattias Nilsson 5523df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_DIV_SHIFT 0 5533df57bcfSMattias Nilsson #define PRCMU_CLK_PLL_SW_SHIFT 5 5543df57bcfSMattias Nilsson #define PRCMU_CLK_38 (1 << 9) 5553df57bcfSMattias Nilsson #define PRCMU_CLK_38_SRC (1 << 10) 5563df57bcfSMattias Nilsson #define PRCMU_CLK_38_DIV (1 << 11) 5573df57bcfSMattias Nilsson 5583df57bcfSMattias Nilsson /* PLLDIV=12, PLLSW=4 (PLLDDR) */ 5593df57bcfSMattias Nilsson #define PRCMU_DSI_CLOCK_SETTING 0x0000008C 5603df57bcfSMattias Nilsson 5613df57bcfSMattias Nilsson /* DPI 50000000 Hz */ 5623df57bcfSMattias Nilsson #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ 5633df57bcfSMattias Nilsson (16 << PRCMU_CLK_PLL_DIV_SHIFT)) 5643df57bcfSMattias Nilsson #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 5653df57bcfSMattias Nilsson 5663df57bcfSMattias Nilsson /* D=101, N=1, R=4, SELDIV2=0 */ 5673df57bcfSMattias Nilsson #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 5683df57bcfSMattias Nilsson 5693df57bcfSMattias Nilsson #define PRCMU_ENABLE_PLLDSI 0x00000001 5703df57bcfSMattias Nilsson #define PRCMU_DISABLE_PLLDSI 0x00000000 5713df57bcfSMattias Nilsson #define PRCMU_RELEASE_RESET_DSS 0x0000400C 5723df57bcfSMattias Nilsson #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 5733df57bcfSMattias Nilsson /* ESC clk, div0=1, div1=1, div2=3 */ 5743df57bcfSMattias Nilsson #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 5753df57bcfSMattias Nilsson #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 5763df57bcfSMattias Nilsson #define PRCMU_DSI_RESET_SW 0x00000007 5773df57bcfSMattias Nilsson 5783df57bcfSMattias Nilsson #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 5793df57bcfSMattias Nilsson 58073180f85SMattias Nilsson int db8500_prcmu_enable_dsipll(void) 5813df57bcfSMattias Nilsson { 5823df57bcfSMattias Nilsson int i; 5833df57bcfSMattias Nilsson 5843df57bcfSMattias Nilsson /* Clear DSIPLL_RESETN */ 585c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); 5863df57bcfSMattias Nilsson /* Unclamp DSIPLL in/out */ 587c553b3caSMattias Nilsson writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); 5883df57bcfSMattias Nilsson 5893df57bcfSMattias Nilsson /* Set DSI PLL FREQ */ 590c72fe851SDaniel Willerud writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); 591c553b3caSMattias Nilsson writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); 5923df57bcfSMattias Nilsson /* Enable Escape clocks */ 593c553b3caSMattias Nilsson writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 5943df57bcfSMattias Nilsson 5953df57bcfSMattias Nilsson /* Start DSI PLL */ 596c553b3caSMattias Nilsson writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 5973df57bcfSMattias Nilsson /* Reset DSI PLL */ 598c553b3caSMattias Nilsson writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); 5993df57bcfSMattias Nilsson for (i = 0; i < 10; i++) { 600c553b3caSMattias Nilsson if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) 6013df57bcfSMattias Nilsson == PRCMU_PLLDSI_LOCKP_LOCKED) 6023df57bcfSMattias Nilsson break; 6033df57bcfSMattias Nilsson udelay(100); 6043df57bcfSMattias Nilsson } 6053df57bcfSMattias Nilsson /* Set DSIPLL_RESETN */ 606c553b3caSMattias Nilsson writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); 6073df57bcfSMattias Nilsson return 0; 6083df57bcfSMattias Nilsson } 6093df57bcfSMattias Nilsson 61073180f85SMattias Nilsson int db8500_prcmu_disable_dsipll(void) 6113df57bcfSMattias Nilsson { 6123df57bcfSMattias Nilsson /* Disable dsi pll */ 613c553b3caSMattias Nilsson writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 6143df57bcfSMattias Nilsson /* Disable escapeclock */ 615c553b3caSMattias Nilsson writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); 6163df57bcfSMattias Nilsson return 0; 6173df57bcfSMattias Nilsson } 6183df57bcfSMattias Nilsson 61973180f85SMattias Nilsson int db8500_prcmu_set_display_clocks(void) 6203df57bcfSMattias Nilsson { 6213df57bcfSMattias Nilsson unsigned long flags; 6223df57bcfSMattias Nilsson 6233df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 6243df57bcfSMattias Nilsson 6253df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 626c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 6273df57bcfSMattias Nilsson cpu_relax(); 6283df57bcfSMattias Nilsson 629b047d981SLinus Walleij writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); 630b047d981SLinus Walleij writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); 631b047d981SLinus Walleij writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); 6323df57bcfSMattias Nilsson 6333df57bcfSMattias Nilsson /* Release the HW semaphore. */ 634c553b3caSMattias Nilsson writel(0, PRCM_SEM); 6353df57bcfSMattias Nilsson 6363df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 6373df57bcfSMattias Nilsson 6383df57bcfSMattias Nilsson return 0; 6393df57bcfSMattias Nilsson } 6403df57bcfSMattias Nilsson 641b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg) 6423df57bcfSMattias Nilsson { 643b047d981SLinus Walleij return readl(prcmu_base + reg); 6443df57bcfSMattias Nilsson } 6453df57bcfSMattias Nilsson 646b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value) 6473df57bcfSMattias Nilsson { 6483df57bcfSMattias Nilsson unsigned long flags; 6493df57bcfSMattias Nilsson 650b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 651b047d981SLinus Walleij writel(value, (prcmu_base + reg)); 652b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 653b4a6dbd5SMattias Nilsson } 654b4a6dbd5SMattias Nilsson 655b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 656b4a6dbd5SMattias Nilsson { 657b4a6dbd5SMattias Nilsson u32 val; 658b4a6dbd5SMattias Nilsson unsigned long flags; 659b4a6dbd5SMattias Nilsson 660b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags); 661b047d981SLinus Walleij val = readl(prcmu_base + reg); 662b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask)); 663b047d981SLinus Walleij writel(val, (prcmu_base + reg)); 664b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags); 6653df57bcfSMattias Nilsson } 6663df57bcfSMattias Nilsson 667b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void) 668b58d12feSMattias Nilsson { 669b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL; 670b58d12feSMattias Nilsson } 671b58d12feSMattias Nilsson 67222fb3ad0SLinus Walleij static bool prcmu_is_ulppll_disabled(void) 67322fb3ad0SLinus Walleij { 67422fb3ad0SLinus Walleij struct prcmu_fw_version *ver; 67522fb3ad0SLinus Walleij 67622fb3ad0SLinus Walleij ver = prcmu_get_fw_version(); 67722fb3ad0SLinus Walleij return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK; 67822fb3ad0SLinus Walleij } 67922fb3ad0SLinus Walleij 6803df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void) 6813df57bcfSMattias Nilsson { 6823df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & 6833df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; 6843df57bcfSMattias Nilsson } 6853df57bcfSMattias Nilsson 6863df57bcfSMattias Nilsson /** 6873df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences 6883df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested 6893df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument 6903df57bcfSMattias Nilsson * 6913df57bcfSMattias Nilsson * This function is used to run the following power state sequences - 6923df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 6933df57bcfSMattias Nilsson */ 6943df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val) 6953df57bcfSMattias Nilsson { 6963df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST) 6973df57bcfSMattias Nilsson return -EINVAL; 6983df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); 6993df57bcfSMattias Nilsson return 0; 7003df57bcfSMattias Nilsson } 7013df57bcfSMattias Nilsson 7023df57bcfSMattias Nilsson /** 7033df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences 7043df57bcfSMattias Nilsson * Returns: the power transition that has last happened 7053df57bcfSMattias Nilsson * 7063df57bcfSMattias Nilsson * This function can return the following transitions- 7073df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep 7083df57bcfSMattias Nilsson */ 7093df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void) 7103df57bcfSMattias Nilsson { 7113df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A); 7123df57bcfSMattias Nilsson } 7133df57bcfSMattias Nilsson 7143df57bcfSMattias Nilsson /** 7153df57bcfSMattias Nilsson * prcmu_get_current_mode - Return the current XP70 power mode 7163df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init, 7173df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset 7183df57bcfSMattias Nilsson */ 7193df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void) 7203df57bcfSMattias Nilsson { 7213df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); 7223df57bcfSMattias Nilsson } 7233df57bcfSMattias Nilsson 7243df57bcfSMattias Nilsson /** 7253df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs. 7263df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1). 7273df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*). 7283df57bcfSMattias Nilsson * @div: The divider to be applied. 7293df57bcfSMattias Nilsson * 7303df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs). 7313df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to 7323df57bcfSMattias Nilsson * inform that the configuration is no longer requested. 7333df57bcfSMattias Nilsson */ 7343df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 7353df57bcfSMattias Nilsson { 7363df57bcfSMattias Nilsson static int requests[2]; 7373df57bcfSMattias Nilsson int r = 0; 7383df57bcfSMattias Nilsson unsigned long flags; 7393df57bcfSMattias Nilsson u32 val; 7403df57bcfSMattias Nilsson u32 bits; 7413df57bcfSMattias Nilsson u32 mask; 7423df57bcfSMattias Nilsson u32 div_mask; 7433df57bcfSMattias Nilsson 7443df57bcfSMattias Nilsson BUG_ON(clkout > 1); 7453df57bcfSMattias Nilsson BUG_ON(div > 63); 7463df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); 7473df57bcfSMattias Nilsson 7483df57bcfSMattias Nilsson if (!div && !requests[clkout]) 7493df57bcfSMattias Nilsson return -EINVAL; 7503df57bcfSMattias Nilsson 751a7e46317SArnd Bergmann if (clkout == 0) { 7523df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 7533df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); 7543df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | 7553df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); 756a7e46317SArnd Bergmann } else { 7573df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 7583df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | 7593df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE); 7603df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | 7613df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); 7623df57bcfSMattias Nilsson } 7633df57bcfSMattias Nilsson bits &= mask; 7643df57bcfSMattias Nilsson 7653df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags); 7663df57bcfSMattias Nilsson 767c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR); 7683df57bcfSMattias Nilsson if (val & div_mask) { 7693df57bcfSMattias Nilsson if (div) { 7703df57bcfSMattias Nilsson if ((val & mask) != bits) { 7713df57bcfSMattias Nilsson r = -EBUSY; 7723df57bcfSMattias Nilsson goto unlock_and_return; 7733df57bcfSMattias Nilsson } 7743df57bcfSMattias Nilsson } else { 7753df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) { 7763df57bcfSMattias Nilsson r = -EINVAL; 7773df57bcfSMattias Nilsson goto unlock_and_return; 7783df57bcfSMattias Nilsson } 7793df57bcfSMattias Nilsson } 7803df57bcfSMattias Nilsson } 781c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR); 7823df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1); 7833df57bcfSMattias Nilsson 7843df57bcfSMattias Nilsson unlock_and_return: 7853df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags); 7863df57bcfSMattias Nilsson 7873df57bcfSMattias Nilsson return r; 7883df57bcfSMattias Nilsson } 7893df57bcfSMattias Nilsson 79073180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 7913df57bcfSMattias Nilsson { 7923df57bcfSMattias Nilsson unsigned long flags; 7933df57bcfSMattias Nilsson 7943df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); 7953df57bcfSMattias Nilsson 7963df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 7973df57bcfSMattias Nilsson 798c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 7993df57bcfSMattias Nilsson cpu_relax(); 8003df57bcfSMattias Nilsson 8013df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 8023df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); 8033df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); 8043df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0), 8053df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); 8063df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); 807c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8083df57bcfSMattias Nilsson 8093df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8103df57bcfSMattias Nilsson 8113df57bcfSMattias Nilsson return 0; 8123df57bcfSMattias Nilsson } 8133df57bcfSMattias Nilsson 8144d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void) 8154d64d2e3SMattias Nilsson { 8164d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 8174d64d2e3SMattias Nilsson } 8184d64d2e3SMattias Nilsson 8193df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */ 8203df57bcfSMattias Nilsson static void config_wakeups(void) 8213df57bcfSMattias Nilsson { 8223df57bcfSMattias Nilsson const u8 header[2] = { 8233df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE, 8243df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP 8253df57bcfSMattias Nilsson }; 8263df57bcfSMattias Nilsson static u32 last_dbb_events; 8273df57bcfSMattias Nilsson static u32 last_abb_events; 8283df57bcfSMattias Nilsson u32 dbb_events; 8293df57bcfSMattias Nilsson u32 abb_events; 8303df57bcfSMattias Nilsson unsigned int i; 8313df57bcfSMattias Nilsson 8323df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; 8333df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); 8343df57bcfSMattias Nilsson 8353df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events; 8363df57bcfSMattias Nilsson 8373df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) 8383df57bcfSMattias Nilsson return; 8393df57bcfSMattias Nilsson 8403df57bcfSMattias Nilsson for (i = 0; i < 2; i++) { 841c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 8423df57bcfSMattias Nilsson cpu_relax(); 8433df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); 8443df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); 8453df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 846c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 8473df57bcfSMattias Nilsson } 8483df57bcfSMattias Nilsson last_dbb_events = dbb_events; 8493df57bcfSMattias Nilsson last_abb_events = abb_events; 8503df57bcfSMattias Nilsson } 8513df57bcfSMattias Nilsson 85273180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups) 8533df57bcfSMattias Nilsson { 8543df57bcfSMattias Nilsson unsigned long flags; 8553df57bcfSMattias Nilsson u32 bits; 8563df57bcfSMattias Nilsson int i; 8573df57bcfSMattias Nilsson 8583df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); 8593df57bcfSMattias Nilsson 8603df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { 8613df57bcfSMattias Nilsson if (wakeups & BIT(i)) 8623df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i]; 8633df57bcfSMattias Nilsson } 8643df57bcfSMattias Nilsson 8653df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8663df57bcfSMattias Nilsson 8673df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits; 8683df57bcfSMattias Nilsson config_wakeups(); 8693df57bcfSMattias Nilsson 8703df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8713df57bcfSMattias Nilsson } 8723df57bcfSMattias Nilsson 87373180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events) 8743df57bcfSMattias Nilsson { 8753df57bcfSMattias Nilsson unsigned long flags; 8763df57bcfSMattias Nilsson 8773df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 8783df57bcfSMattias Nilsson 8793df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events; 8803df57bcfSMattias Nilsson config_wakeups(); 8813df57bcfSMattias Nilsson 8823df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 8833df57bcfSMattias Nilsson } 8843df57bcfSMattias Nilsson 88573180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) 8863df57bcfSMattias Nilsson { 8873df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 8883df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 8893df57bcfSMattias Nilsson else 8903df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); 8913df57bcfSMattias Nilsson } 8923df57bcfSMattias Nilsson 8933df57bcfSMattias Nilsson /** 89473180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP 8953df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made 8963df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 8973df57bcfSMattias Nilsson * 8983df57bcfSMattias Nilsson * This function sets the the operating point of the ARM. 8993df57bcfSMattias Nilsson */ 90073180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp) 9013df57bcfSMattias Nilsson { 9023df57bcfSMattias Nilsson int r; 9033df57bcfSMattias Nilsson 9043df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) 9053df57bcfSMattias Nilsson return -EINVAL; 9063df57bcfSMattias Nilsson 9073df57bcfSMattias Nilsson r = 0; 9083df57bcfSMattias Nilsson 9093df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 9103df57bcfSMattias Nilsson 911c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 9123df57bcfSMattias Nilsson cpu_relax(); 9133df57bcfSMattias Nilsson 9143df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 9153df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 9163df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 9173df57bcfSMattias Nilsson 918c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 9193df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 9203df57bcfSMattias Nilsson 9213df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 9223df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp)) 9233df57bcfSMattias Nilsson r = -EIO; 9243df57bcfSMattias Nilsson 9253df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 9263df57bcfSMattias Nilsson 9273df57bcfSMattias Nilsson return r; 9283df57bcfSMattias Nilsson } 9293df57bcfSMattias Nilsson 9303df57bcfSMattias Nilsson /** 93173180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP 9323df57bcfSMattias Nilsson * 9333df57bcfSMattias Nilsson * Returns: the current ARM OPP 9343df57bcfSMattias Nilsson */ 93573180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void) 9363df57bcfSMattias Nilsson { 9373df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 9383df57bcfSMattias Nilsson } 9393df57bcfSMattias Nilsson 9403df57bcfSMattias Nilsson /** 9410508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP 9423df57bcfSMattias Nilsson * 9433df57bcfSMattias Nilsson * Returns: the current DDR OPP 9443df57bcfSMattias Nilsson */ 9450508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void) 9463df57bcfSMattias Nilsson { 947c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW); 9483df57bcfSMattias Nilsson } 9493df57bcfSMattias Nilsson 9504d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 9514d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable) 9524d64d2e3SMattias Nilsson { 953b047d981SLinus Walleij u32 clock_reg[] = { 9544d64d2e3SMattias Nilsson PRCM_ACLK_MGT, 9554d64d2e3SMattias Nilsson PRCM_DMACLK_MGT 9564d64d2e3SMattias Nilsson }; 9574d64d2e3SMattias Nilsson unsigned long flags; 9584d64d2e3SMattias Nilsson unsigned int i; 9594d64d2e3SMattias Nilsson 9604d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 9614d64d2e3SMattias Nilsson 9624d64d2e3SMattias Nilsson /* Grab the HW semaphore. */ 9634d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 9644d64d2e3SMattias Nilsson cpu_relax(); 9654d64d2e3SMattias Nilsson 9664d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { 9674d64d2e3SMattias Nilsson u32 val; 9684d64d2e3SMattias Nilsson u32 div; 9694d64d2e3SMattias Nilsson 970b047d981SLinus Walleij val = readl(prcmu_base + clock_reg[i]); 9714d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 9724d64d2e3SMattias Nilsson if (enable) { 9734d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) { 9744d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n", 9754d64d2e3SMattias Nilsson div, __func__); 9764d64d2e3SMattias Nilsson goto unlock_and_return; 9774d64d2e3SMattias Nilsson } 9784d64d2e3SMattias Nilsson div <<= 1; 9794d64d2e3SMattias Nilsson } else { 9804d64d2e3SMattias Nilsson if (div <= 2) 9814d64d2e3SMattias Nilsson goto unlock_and_return; 9824d64d2e3SMattias Nilsson div >>= 1; 9834d64d2e3SMattias Nilsson } 9844d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 9854d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 986b047d981SLinus Walleij writel(val, prcmu_base + clock_reg[i]); 9874d64d2e3SMattias Nilsson } 9884d64d2e3SMattias Nilsson 9894d64d2e3SMattias Nilsson unlock_and_return: 9904d64d2e3SMattias Nilsson /* Release the HW semaphore. */ 9914d64d2e3SMattias Nilsson writel(0, PRCM_SEM); 9924d64d2e3SMattias Nilsson 9934d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 9944d64d2e3SMattias Nilsson } 9954d64d2e3SMattias Nilsson 9963df57bcfSMattias Nilsson /** 9970508901cSMattias Nilsson * db8500_set_ape_opp - set the appropriate APE OPP 9983df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made 9993df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure 10003df57bcfSMattias Nilsson * 10013df57bcfSMattias Nilsson * This function sets the operating point of the APE. 10023df57bcfSMattias Nilsson */ 10030508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp) 10043df57bcfSMattias Nilsson { 10053df57bcfSMattias Nilsson int r = 0; 10063df57bcfSMattias Nilsson 10074d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp) 10084d64d2e3SMattias Nilsson return 0; 10094d64d2e3SMattias Nilsson 10103df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10113df57bcfSMattias Nilsson 10124d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) 10134d64d2e3SMattias Nilsson request_even_slower_clocks(false); 10144d64d2e3SMattias Nilsson 10154d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) 10164d64d2e3SMattias Nilsson goto skip_message; 10174d64d2e3SMattias Nilsson 1018c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10193df57bcfSMattias Nilsson cpu_relax(); 10203df57bcfSMattias Nilsson 10213df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10223df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); 10234d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), 10244d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP)); 10253df57bcfSMattias Nilsson 1026c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10273df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10283df57bcfSMattias Nilsson 10293df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || 10303df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp)) 10313df57bcfSMattias Nilsson r = -EIO; 10323df57bcfSMattias Nilsson 10334d64d2e3SMattias Nilsson skip_message: 10344d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) || 10354d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) 10364d64d2e3SMattias Nilsson request_even_slower_clocks(true); 10374d64d2e3SMattias Nilsson if (!r) 10384d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp; 10394d64d2e3SMattias Nilsson 10403df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10413df57bcfSMattias Nilsson 10423df57bcfSMattias Nilsson return r; 10433df57bcfSMattias Nilsson } 10443df57bcfSMattias Nilsson 10453df57bcfSMattias Nilsson /** 10460508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP 10473df57bcfSMattias Nilsson * 10483df57bcfSMattias Nilsson * Returns: the current APE OPP 10493df57bcfSMattias Nilsson */ 10500508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void) 10513df57bcfSMattias Nilsson { 10523df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); 10533df57bcfSMattias Nilsson } 10543df57bcfSMattias Nilsson 10553df57bcfSMattias Nilsson /** 1056686f871bSUlf Hansson * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 10573df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request. 10583df57bcfSMattias Nilsson * 10593df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced. 10603df57bcfSMattias Nilsson */ 1061686f871bSUlf Hansson int db8500_prcmu_request_ape_opp_100_voltage(bool enable) 10623df57bcfSMattias Nilsson { 10633df57bcfSMattias Nilsson int r = 0; 10643df57bcfSMattias Nilsson u8 header; 10653df57bcfSMattias Nilsson static unsigned int requests; 10663df57bcfSMattias Nilsson 10673df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 10683df57bcfSMattias Nilsson 10693df57bcfSMattias Nilsson if (enable) { 10703df57bcfSMattias Nilsson if (0 != requests++) 10713df57bcfSMattias Nilsson goto unlock_and_return; 10723df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT; 10733df57bcfSMattias Nilsson } else { 10743df57bcfSMattias Nilsson if (requests == 0) { 10753df57bcfSMattias Nilsson r = -EIO; 10763df57bcfSMattias Nilsson goto unlock_and_return; 10773df57bcfSMattias Nilsson } else if (1 != requests--) { 10783df57bcfSMattias Nilsson goto unlock_and_return; 10793df57bcfSMattias Nilsson } 10803df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT; 10813df57bcfSMattias Nilsson } 10823df57bcfSMattias Nilsson 1083c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 10843df57bcfSMattias Nilsson cpu_relax(); 10853df57bcfSMattias Nilsson 10863df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 10873df57bcfSMattias Nilsson 1088c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 10893df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 10903df57bcfSMattias Nilsson 10913df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) || 10923df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 10933df57bcfSMattias Nilsson r = -EIO; 10943df57bcfSMattias Nilsson 10953df57bcfSMattias Nilsson unlock_and_return: 10963df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 10973df57bcfSMattias Nilsson 10983df57bcfSMattias Nilsson return r; 10993df57bcfSMattias Nilsson } 11003df57bcfSMattias Nilsson 11013df57bcfSMattias Nilsson /** 11023df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup 11033df57bcfSMattias Nilsson * 11043df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup. 11053df57bcfSMattias Nilsson */ 11063df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void) 11073df57bcfSMattias Nilsson { 11083df57bcfSMattias Nilsson int r = 0; 11093df57bcfSMattias Nilsson 11103df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock); 11113df57bcfSMattias Nilsson 1112c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11133df57bcfSMattias Nilsson cpu_relax(); 11143df57bcfSMattias Nilsson 11153df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP, 11163df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11173df57bcfSMattias Nilsson 1118c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11193df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work); 11203df57bcfSMattias Nilsson 11213df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || 11223df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) 11233df57bcfSMattias Nilsson r = -EIO; 11243df57bcfSMattias Nilsson 11253df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11263df57bcfSMattias Nilsson 11273df57bcfSMattias Nilsson return r; 11283df57bcfSMattias Nilsson } 11293df57bcfSMattias Nilsson 11300837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable) 11310837bb72SMattias Nilsson { 11320837bb72SMattias Nilsson int r = 0; 11330837bb72SMattias Nilsson 11346b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0) 11356b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); 11366b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 11370837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); 11380837bb72SMattias Nilsson else 11390837bb72SMattias Nilsson return -EINVAL; 11400837bb72SMattias Nilsson 11410837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock); 11420837bb72SMattias Nilsson 11430837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 11440837bb72SMattias Nilsson cpu_relax(); 11450837bb72SMattias Nilsson 11460837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 11470837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); 11480837bb72SMattias Nilsson 11490837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 11500837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work); 11510837bb72SMattias Nilsson 11520837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) 11530837bb72SMattias Nilsson r = -EIO; 11540837bb72SMattias Nilsson 11550837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock); 11560837bb72SMattias Nilsson 11570837bb72SMattias Nilsson return r; 11580837bb72SMattias Nilsson } 11590837bb72SMattias Nilsson 11603df57bcfSMattias Nilsson /** 116173180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain) 11623df57bcfSMattias Nilsson * @epod_id: The EPOD to set 11633df57bcfSMattias Nilsson * @epod_state: The new EPOD state 11643df57bcfSMattias Nilsson * 11653df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called 11663df57bcfSMattias Nilsson * from interrupt context. 11673df57bcfSMattias Nilsson */ 116873180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) 11693df57bcfSMattias Nilsson { 11703df57bcfSMattias Nilsson int r = 0; 11713df57bcfSMattias Nilsson bool ram_retention = false; 11723df57bcfSMattias Nilsson int i; 11733df57bcfSMattias Nilsson 11743df57bcfSMattias Nilsson /* check argument */ 11753df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID); 11763df57bcfSMattias Nilsson 11773df57bcfSMattias Nilsson /* set flag if retention is possible */ 11783df57bcfSMattias Nilsson switch (epod_id) { 11793df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP: 11803df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP: 11813df57bcfSMattias Nilsson case EPOD_ID_ESRAM12: 11823df57bcfSMattias Nilsson case EPOD_ID_ESRAM34: 11833df57bcfSMattias Nilsson ram_retention = true; 11843df57bcfSMattias Nilsson break; 11853df57bcfSMattias Nilsson } 11863df57bcfSMattias Nilsson 11873df57bcfSMattias Nilsson /* check argument */ 11883df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON); 11893df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); 11903df57bcfSMattias Nilsson 11913df57bcfSMattias Nilsson /* get lock */ 11923df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock); 11933df57bcfSMattias Nilsson 11943df57bcfSMattias Nilsson /* wait for mailbox */ 1195c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) 11963df57bcfSMattias Nilsson cpu_relax(); 11973df57bcfSMattias Nilsson 11983df57bcfSMattias Nilsson /* fill in mailbox */ 11993df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++) 12003df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); 12013df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); 12023df57bcfSMattias Nilsson 12033df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); 12043df57bcfSMattias Nilsson 1205c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); 12063df57bcfSMattias Nilsson 12073df57bcfSMattias Nilsson /* 12083df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly, 12093df57bcfSMattias Nilsson * and we cannot recover if there is an error. 12103df57bcfSMattias Nilsson * This is expected to change when the firmware is updated. 12113df57bcfSMattias Nilsson */ 12123df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work, 12133df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 12143df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 12153df57bcfSMattias Nilsson __func__); 12163df57bcfSMattias Nilsson r = -EIO; 12173df57bcfSMattias Nilsson goto unlock_and_return; 12183df57bcfSMattias Nilsson } 12193df57bcfSMattias Nilsson 12203df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) 12213df57bcfSMattias Nilsson r = -EIO; 12223df57bcfSMattias Nilsson 12233df57bcfSMattias Nilsson unlock_and_return: 12243df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock); 12253df57bcfSMattias Nilsson return r; 12263df57bcfSMattias Nilsson } 12273df57bcfSMattias Nilsson 12283df57bcfSMattias Nilsson /** 12293df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management. 12303df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep. 12313df57bcfSMattias Nilsson * @idle: Configuration for ApIdle. 12323df57bcfSMattias Nilsson */ 12333df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 12343df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle) 12353df57bcfSMattias Nilsson { 12363df57bcfSMattias Nilsson u32 sleep_cfg; 12373df57bcfSMattias Nilsson u32 idle_cfg; 12383df57bcfSMattias Nilsson unsigned long flags; 12393df57bcfSMattias Nilsson 12403df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL)); 12413df57bcfSMattias Nilsson 12423df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); 12433df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); 12443df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); 12453df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); 12463df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); 12473df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); 12483df57bcfSMattias Nilsson 12493df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF); 12503df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); 12513df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); 12523df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); 12533df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); 12543df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); 12553df57bcfSMattias Nilsson 12563df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); 12573df57bcfSMattias Nilsson 12583df57bcfSMattias Nilsson /* 12593df57bcfSMattias Nilsson * The autonomous power management configuration is done through 12603df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared 12613df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message. 12623df57bcfSMattias Nilsson */ 12633df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); 12643df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); 12653df57bcfSMattias Nilsson 12663df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled = 12673df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12683df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12693df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || 12703df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); 12713df57bcfSMattias Nilsson 12723df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); 12733df57bcfSMattias Nilsson } 12743df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm); 12753df57bcfSMattias Nilsson 12763df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void) 12773df57bcfSMattias Nilsson { 12783df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled; 12793df57bcfSMattias Nilsson } 12803df57bcfSMattias Nilsson 12813df57bcfSMattias Nilsson static int request_sysclk(bool enable) 12823df57bcfSMattias Nilsson { 12833df57bcfSMattias Nilsson int r; 12843df57bcfSMattias Nilsson unsigned long flags; 12853df57bcfSMattias Nilsson 12863df57bcfSMattias Nilsson r = 0; 12873df57bcfSMattias Nilsson 12883df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock); 12893df57bcfSMattias Nilsson 12903df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags); 12913df57bcfSMattias Nilsson 1292c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) 12933df57bcfSMattias Nilsson cpu_relax(); 12943df57bcfSMattias Nilsson 12953df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); 12963df57bcfSMattias Nilsson 12973df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); 1298c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); 12993df57bcfSMattias Nilsson 13003df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags); 13013df57bcfSMattias Nilsson 13023df57bcfSMattias Nilsson /* 13033df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the 13043df57bcfSMattias Nilsson * SysClk, and it succeeds. 13053df57bcfSMattias Nilsson */ 13063df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, 13073df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 13083df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 13093df57bcfSMattias Nilsson __func__); 13103df57bcfSMattias Nilsson r = -EIO; 13113df57bcfSMattias Nilsson } 13123df57bcfSMattias Nilsson 13133df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock); 13143df57bcfSMattias Nilsson 13153df57bcfSMattias Nilsson return r; 13163df57bcfSMattias Nilsson } 13173df57bcfSMattias Nilsson 13183df57bcfSMattias Nilsson static int request_timclk(bool enable) 13193df57bcfSMattias Nilsson { 132022fb3ad0SLinus Walleij u32 val; 132122fb3ad0SLinus Walleij 132222fb3ad0SLinus Walleij /* 132322fb3ad0SLinus Walleij * On the U8420_CLKSEL firmware, the ULP (Ultra Low Power) 132422fb3ad0SLinus Walleij * PLL is disabled so we cannot use doze mode, this will 132522fb3ad0SLinus Walleij * stop the clock on this firmware. 132622fb3ad0SLinus Walleij */ 132722fb3ad0SLinus Walleij if (prcmu_is_ulppll_disabled()) 132822fb3ad0SLinus Walleij val = 0; 132922fb3ad0SLinus Walleij else 133022fb3ad0SLinus Walleij val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); 13313df57bcfSMattias Nilsson 13323df57bcfSMattias Nilsson if (!enable) 133322fb3ad0SLinus Walleij val |= PRCM_TCR_STOP_TIMERS | 133422fb3ad0SLinus Walleij PRCM_TCR_DOZE_MODE | 133522fb3ad0SLinus Walleij PRCM_TCR_TENSEL_MASK; 133622fb3ad0SLinus Walleij 1337c553b3caSMattias Nilsson writel(val, PRCM_TCR); 13383df57bcfSMattias Nilsson 13393df57bcfSMattias Nilsson return 0; 13403df57bcfSMattias Nilsson } 13413df57bcfSMattias Nilsson 13426b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable) 13433df57bcfSMattias Nilsson { 13443df57bcfSMattias Nilsson u32 val; 13453df57bcfSMattias Nilsson unsigned long flags; 13463df57bcfSMattias Nilsson 13473df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 13483df57bcfSMattias Nilsson 13493df57bcfSMattias Nilsson /* Grab the HW semaphore. */ 1350c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 13513df57bcfSMattias Nilsson cpu_relax(); 13523df57bcfSMattias Nilsson 1353b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 13543df57bcfSMattias Nilsson if (enable) { 13553df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 13563df57bcfSMattias Nilsson } else { 13573df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 13583df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 13593df57bcfSMattias Nilsson } 1360b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset); 13613df57bcfSMattias Nilsson 13623df57bcfSMattias Nilsson /* Release the HW semaphore. */ 1363c553b3caSMattias Nilsson writel(0, PRCM_SEM); 13643df57bcfSMattias Nilsson 13653df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 13663df57bcfSMattias Nilsson 13673df57bcfSMattias Nilsson return 0; 13683df57bcfSMattias Nilsson } 13693df57bcfSMattias Nilsson 13700837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable) 13710837bb72SMattias Nilsson { 13720837bb72SMattias Nilsson u32 val; 13730837bb72SMattias Nilsson int ret; 13740837bb72SMattias Nilsson 13750837bb72SMattias Nilsson if (enable) { 13760837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13770837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13780837bb72SMattias Nilsson } 13790837bb72SMattias Nilsson 13806b6fae2bSMattias Nilsson ret = request_clock(clock, enable); 13810837bb72SMattias Nilsson 13820837bb72SMattias Nilsson if (!ret && !enable) { 13830837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS); 13840837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); 13850837bb72SMattias Nilsson } 13860837bb72SMattias Nilsson 13870837bb72SMattias Nilsson return ret; 13880837bb72SMattias Nilsson } 13890837bb72SMattias Nilsson 13906b6fae2bSMattias Nilsson static inline bool plldsi_locked(void) 13916b6fae2bSMattias Nilsson { 13926b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) & 13936b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 13946b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == 13956b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | 13966b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); 13976b6fae2bSMattias Nilsson } 13986b6fae2bSMattias Nilsson 13996b6fae2bSMattias Nilsson static int request_plldsi(bool enable) 14006b6fae2bSMattias Nilsson { 14016b6fae2bSMattias Nilsson int r = 0; 14026b6fae2bSMattias Nilsson u32 val; 14036b6fae2bSMattias Nilsson 14046b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 14056b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? 14066b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); 14076b6fae2bSMattias Nilsson 14086b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE); 14096b6fae2bSMattias Nilsson if (enable) 14106b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14116b6fae2bSMattias Nilsson else 14126b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14136b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 14146b6fae2bSMattias Nilsson 14156b6fae2bSMattias Nilsson if (enable) { 14166b6fae2bSMattias Nilsson unsigned int i; 14176b6fae2bSMattias Nilsson bool locked = plldsi_locked(); 14186b6fae2bSMattias Nilsson 14196b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) { 14206b6fae2bSMattias Nilsson udelay(100); 14216b6fae2bSMattias Nilsson locked = plldsi_locked(); 14226b6fae2bSMattias Nilsson } 14236b6fae2bSMattias Nilsson if (locked) { 14246b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, 14256b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET); 14266b6fae2bSMattias Nilsson } else { 14276b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | 14286b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), 14296b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET); 14306b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; 14316b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE); 14326b6fae2bSMattias Nilsson r = -EAGAIN; 14336b6fae2bSMattias Nilsson } 14346b6fae2bSMattias Nilsson } else { 14356b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); 14366b6fae2bSMattias Nilsson } 14376b6fae2bSMattias Nilsson return r; 14386b6fae2bSMattias Nilsson } 14396b6fae2bSMattias Nilsson 14406b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable) 14416b6fae2bSMattias Nilsson { 14426b6fae2bSMattias Nilsson u32 val; 14436b6fae2bSMattias Nilsson 14446b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 14456b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 14466b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << 14476b6fae2bSMattias Nilsson dsiclk[n].divsel_shift); 14486b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 14496b6fae2bSMattias Nilsson return 0; 14506b6fae2bSMattias Nilsson } 14516b6fae2bSMattias Nilsson 14526b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable) 14536b6fae2bSMattias Nilsson { 14546b6fae2bSMattias Nilsson u32 val; 14556b6fae2bSMattias Nilsson 14566b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 14576b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); 14586b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 14596b6fae2bSMattias Nilsson return 0; 14606b6fae2bSMattias Nilsson } 14616b6fae2bSMattias Nilsson 14623df57bcfSMattias Nilsson /** 146373180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. 14643df57bcfSMattias Nilsson * @clock: The clock for which the request is made. 14653df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false). 14663df57bcfSMattias Nilsson * 14673df57bcfSMattias Nilsson * This function should only be used by the clock implementation. 14683df57bcfSMattias Nilsson * Do not use it from any other place! 14693df57bcfSMattias Nilsson */ 147073180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable) 14713df57bcfSMattias Nilsson { 14726b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK) 14730837bb72SMattias Nilsson return request_sga_clock(clock, enable); 14746b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS) 14756b6fae2bSMattias Nilsson return request_clock(clock, enable); 14766b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 14773df57bcfSMattias Nilsson return request_timclk(enable); 14786b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 14796b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable); 14806b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 14816b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); 14826b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 14836b6fae2bSMattias Nilsson return request_plldsi(enable); 14846b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 14853df57bcfSMattias Nilsson return request_sysclk(enable); 14866b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) 14870837bb72SMattias Nilsson return request_pll(clock, enable); 14886b6fae2bSMattias Nilsson else 14896b6fae2bSMattias Nilsson return -EINVAL; 14906b6fae2bSMattias Nilsson } 14916b6fae2bSMattias Nilsson 14926b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, 14936b6fae2bSMattias Nilsson int branch) 14946b6fae2bSMattias Nilsson { 14956b6fae2bSMattias Nilsson u64 rate; 14966b6fae2bSMattias Nilsson u32 val; 14976b6fae2bSMattias Nilsson u32 d; 14986b6fae2bSMattias Nilsson u32 div = 1; 14996b6fae2bSMattias Nilsson 15006b6fae2bSMattias Nilsson val = readl(reg); 15016b6fae2bSMattias Nilsson 15026b6fae2bSMattias Nilsson rate = src_rate; 15036b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); 15046b6fae2bSMattias Nilsson 15056b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); 15066b6fae2bSMattias Nilsson if (d > 1) 15076b6fae2bSMattias Nilsson div *= d; 15086b6fae2bSMattias Nilsson 15096b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); 15106b6fae2bSMattias Nilsson if (d > 1) 15116b6fae2bSMattias Nilsson div *= d; 15126b6fae2bSMattias Nilsson 15136b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2) 15146b6fae2bSMattias Nilsson div *= 2; 15156b6fae2bSMattias Nilsson 15166b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 15176b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) && 15186b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) || 151920aee5b6SMichel Jaouen (reg == PRCM_PLLARM_FREQ) || 15206b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ)))) 15216b6fae2bSMattias Nilsson div *= 2; 15226b6fae2bSMattias Nilsson 15236b6fae2bSMattias Nilsson (void)do_div(rate, div); 15246b6fae2bSMattias Nilsson 15256b6fae2bSMattias Nilsson return (unsigned long)rate; 15266b6fae2bSMattias Nilsson } 15276b6fae2bSMattias Nilsson 15286b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000 15296b6fae2bSMattias Nilsson 15306b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock) 15316b6fae2bSMattias Nilsson { 15326b6fae2bSMattias Nilsson u32 val; 15336b6fae2bSMattias Nilsson u32 pllsw; 15346b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE; 15356b6fae2bSMattias Nilsson 1536b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 15376b6fae2bSMattias Nilsson 15386b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 15396b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 15406b6fae2bSMattias Nilsson rate /= 2; 15416b6fae2bSMattias Nilsson return rate; 15426b6fae2bSMattias Nilsson } 15436b6fae2bSMattias Nilsson 15446b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw; 15456b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 15466b6fae2bSMattias Nilsson 15476b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) 15486b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); 15496b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) 15506b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); 15516b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) 15526b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); 15536b6fae2bSMattias Nilsson else 15546b6fae2bSMattias Nilsson return 0; 15556b6fae2bSMattias Nilsson 15566b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) && 15576b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { 15586b6fae2bSMattias Nilsson u64 r = (rate * 10); 15596b6fae2bSMattias Nilsson 15606b6fae2bSMattias Nilsson (void)do_div(r, 25); 15616b6fae2bSMattias Nilsson return (unsigned long)r; 15626b6fae2bSMattias Nilsson } 15636b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 15646b6fae2bSMattias Nilsson if (val) 15656b6fae2bSMattias Nilsson return rate / val; 15666b6fae2bSMattias Nilsson else 15676b6fae2bSMattias Nilsson return 0; 15686b6fae2bSMattias Nilsson } 156920aee5b6SMichel Jaouen 1570b2302c87SUlf Hansson static unsigned long armss_rate(void) 157120aee5b6SMichel Jaouen { 157220aee5b6SMichel Jaouen u32 r; 157320aee5b6SMichel Jaouen unsigned long rate; 157420aee5b6SMichel Jaouen 157520aee5b6SMichel Jaouen r = readl(PRCM_ARM_CHGCLKREQ); 157620aee5b6SMichel Jaouen 157720aee5b6SMichel Jaouen if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { 157820aee5b6SMichel Jaouen /* External ARMCLKFIX clock */ 157920aee5b6SMichel Jaouen 158020aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); 158120aee5b6SMichel Jaouen 158220aee5b6SMichel Jaouen /* Check PRCM_ARM_CHGCLKREQ divider */ 158320aee5b6SMichel Jaouen if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) 158420aee5b6SMichel Jaouen rate /= 2; 158520aee5b6SMichel Jaouen 158620aee5b6SMichel Jaouen /* Check PRCM_ARMCLKFIX_MGT divider */ 158720aee5b6SMichel Jaouen r = readl(PRCM_ARMCLKFIX_MGT); 158820aee5b6SMichel Jaouen r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; 158920aee5b6SMichel Jaouen rate /= r; 159020aee5b6SMichel Jaouen 159120aee5b6SMichel Jaouen } else {/* ARM PLL */ 159220aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); 159320aee5b6SMichel Jaouen } 159420aee5b6SMichel Jaouen 1595b2302c87SUlf Hansson return rate; 159620aee5b6SMichel Jaouen } 15976b6fae2bSMattias Nilsson 15986b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n) 15996b6fae2bSMattias Nilsson { 16006b6fae2bSMattias Nilsson u32 divsel; 16016b6fae2bSMattias Nilsson u32 div = 1; 16026b6fae2bSMattias Nilsson 16036b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL); 16046b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); 16056b6fae2bSMattias Nilsson 16066b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) 16076b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel; 1608e9d7b4b5SUlf Hansson else 1609e9d7b4b5SUlf Hansson dsiclk[n].divsel = divsel; 16106b6fae2bSMattias Nilsson 16116b6fae2bSMattias Nilsson switch (divsel) { 16126b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4: 16136b6fae2bSMattias Nilsson div *= 2; 1614b620c176SGustavo A. R. Silva /* Fall through */ 16156b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2: 16166b6fae2bSMattias Nilsson div *= 2; 1617b620c176SGustavo A. R. Silva /* Fall through */ 16186b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI: 16196b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 16206b6fae2bSMattias Nilsson PLL_RAW) / div; 1621e62ccf3aSLinus Walleij default: 16226b6fae2bSMattias Nilsson return 0; 16236b6fae2bSMattias Nilsson } 16246b6fae2bSMattias Nilsson } 16256b6fae2bSMattias Nilsson 16266b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n) 16276b6fae2bSMattias Nilsson { 16286b6fae2bSMattias Nilsson u32 div; 16296b6fae2bSMattias Nilsson 16306b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV); 16316b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); 16326b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div); 16336b6fae2bSMattias Nilsson } 16346b6fae2bSMattias Nilsson 16356b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock) 16366b6fae2bSMattias Nilsson { 16376b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 16386b6fae2bSMattias Nilsson return clock_rate(clock); 16396b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK) 164022fb3ad0SLinus Walleij return prcmu_is_ulppll_disabled() ? 164122fb3ad0SLinus Walleij 32768 : ROOT_CLOCK_RATE / 16; 16426b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK) 16436b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 16446b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0) 16456b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 16466b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1) 16476b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 164820aee5b6SMichel Jaouen else if (clock == PRCMU_ARMSS) 164920aee5b6SMichel Jaouen return armss_rate(); 16506b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR) 16516b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 16526b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 16536b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 16546b6fae2bSMattias Nilsson PLL_RAW); 16556b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 16566b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK); 16576b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 16586b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); 16596b6fae2bSMattias Nilsson else 16606b6fae2bSMattias Nilsson return 0; 16616b6fae2bSMattias Nilsson } 16626b6fae2bSMattias Nilsson 16636b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) 16646b6fae2bSMattias Nilsson { 16656b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38) 16666b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE; 16676b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; 16686b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) 16696b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); 16706b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) 16716b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); 16726b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) 16736b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); 16746b6fae2bSMattias Nilsson else 16756b6fae2bSMattias Nilsson return 0; 16766b6fae2bSMattias Nilsson } 16776b6fae2bSMattias Nilsson 16786b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate) 16796b6fae2bSMattias Nilsson { 16806b6fae2bSMattias Nilsson u32 div; 16816b6fae2bSMattias Nilsson 16826b6fae2bSMattias Nilsson div = (src_rate / rate); 16836b6fae2bSMattias Nilsson if (div == 0) 16846b6fae2bSMattias Nilsson return 1; 16856b6fae2bSMattias Nilsson if (rate < (src_rate / div)) 16866b6fae2bSMattias Nilsson div++; 16876b6fae2bSMattias Nilsson return div; 16886b6fae2bSMattias Nilsson } 16896b6fae2bSMattias Nilsson 16906b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate) 16916b6fae2bSMattias Nilsson { 16926b6fae2bSMattias Nilsson u32 val; 16936b6fae2bSMattias Nilsson u32 div; 16946b6fae2bSMattias Nilsson unsigned long src_rate; 16956b6fae2bSMattias Nilsson long rounded_rate; 16966b6fae2bSMattias Nilsson 1697b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 16986b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 16996b6fae2bSMattias Nilsson clk_mgt[clock].branch); 17006b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 17016b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 17026b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 17036b6fae2bSMattias Nilsson if (div > 2) 17046b6fae2bSMattias Nilsson div = 2; 17056b6fae2bSMattias Nilsson } else { 17066b6fae2bSMattias Nilsson div = 1; 17076b6fae2bSMattias Nilsson } 17086b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) { 17096b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 17106b6fae2bSMattias Nilsson 17116b6fae2bSMattias Nilsson (void)do_div(r, 25); 17126b6fae2bSMattias Nilsson if (r <= rate) 17136b6fae2bSMattias Nilsson return (unsigned long)r; 17146b6fae2bSMattias Nilsson } 17156b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31)); 17166b6fae2bSMattias Nilsson 17176b6fae2bSMattias Nilsson return rounded_rate; 17186b6fae2bSMattias Nilsson } 17196b6fae2bSMattias Nilsson 1720fea3ac55SLinus Walleij static const unsigned long db8500_armss_freqs[] = { 1721836a1e25SLinus Walleij 200000000, 1722836a1e25SLinus Walleij 400000000, 1723836a1e25SLinus Walleij 800000000, 1724836a1e25SLinus Walleij 998400000 1725b2302c87SUlf Hansson }; 1726b2302c87SUlf Hansson 1727fea3ac55SLinus Walleij /* The DB8520 has slightly higher ARMSS max frequency */ 1728fea3ac55SLinus Walleij static const unsigned long db8520_armss_freqs[] = { 1729fea3ac55SLinus Walleij 200000000, 1730fea3ac55SLinus Walleij 400000000, 1731fea3ac55SLinus Walleij 800000000, 1732fea3ac55SLinus Walleij 1152000000 1733fea3ac55SLinus Walleij }; 1734fea3ac55SLinus Walleij 1735fea3ac55SLinus Walleij 1736fea3ac55SLinus Walleij 1737b2302c87SUlf Hansson static long round_armss_rate(unsigned long rate) 1738b2302c87SUlf Hansson { 1739836a1e25SLinus Walleij unsigned long freq = 0; 1740fea3ac55SLinus Walleij const unsigned long *freqs; 1741fea3ac55SLinus Walleij int nfreqs; 1742836a1e25SLinus Walleij int i; 1743b2302c87SUlf Hansson 1744fea3ac55SLinus Walleij if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) { 1745fea3ac55SLinus Walleij freqs = db8520_armss_freqs; 1746fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8520_armss_freqs); 1747fea3ac55SLinus Walleij } else { 1748fea3ac55SLinus Walleij freqs = db8500_armss_freqs; 1749fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8500_armss_freqs); 1750fea3ac55SLinus Walleij } 1751fea3ac55SLinus Walleij 1752b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1753fea3ac55SLinus Walleij for (i = 0; i < nfreqs; i++) { 1754fea3ac55SLinus Walleij freq = freqs[i]; 1755836a1e25SLinus Walleij if (rate <= freq) 1756b2302c87SUlf Hansson break; 1757b2302c87SUlf Hansson } 1758b2302c87SUlf Hansson 1759b2302c87SUlf Hansson /* Return the last valid value, even if a match was not found. */ 1760836a1e25SLinus Walleij return freq; 1761b2302c87SUlf Hansson } 1762b2302c87SUlf Hansson 17636b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL 17646b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL 17656b6fae2bSMattias Nilsson 17666b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate) 17676b6fae2bSMattias Nilsson { 17686b6fae2bSMattias Nilsson long rounded_rate = 0; 17696b6fae2bSMattias Nilsson unsigned long src_rate; 17706b6fae2bSMattias Nilsson unsigned long rem; 17716b6fae2bSMattias Nilsson u32 r; 17726b6fae2bSMattias Nilsson 17736b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 17746b6fae2bSMattias Nilsson rem = rate; 17756b6fae2bSMattias Nilsson 17766b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 17776b6fae2bSMattias Nilsson u64 d; 17786b6fae2bSMattias Nilsson 17796b6fae2bSMattias Nilsson d = (r * rate); 17806b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 17816b6fae2bSMattias Nilsson if (d < 6) 17826b6fae2bSMattias Nilsson d = 6; 17836b6fae2bSMattias Nilsson else if (d > 255) 17846b6fae2bSMattias Nilsson d = 255; 17856b6fae2bSMattias Nilsson d *= src_rate; 17866b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || 17876b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d))) 17886b6fae2bSMattias Nilsson continue; 17896b6fae2bSMattias Nilsson (void)do_div(d, r); 17906b6fae2bSMattias Nilsson if (rate < d) { 17916b6fae2bSMattias Nilsson if (rounded_rate == 0) 17926b6fae2bSMattias Nilsson rounded_rate = (long)d; 1793e62ccf3aSLinus Walleij break; 1794e62ccf3aSLinus Walleij } 17956b6fae2bSMattias Nilsson if ((rate - d) < rem) { 17966b6fae2bSMattias Nilsson rem = (rate - d); 17976b6fae2bSMattias Nilsson rounded_rate = (long)d; 17986b6fae2bSMattias Nilsson } 17996b6fae2bSMattias Nilsson } 18006b6fae2bSMattias Nilsson return rounded_rate; 18016b6fae2bSMattias Nilsson } 18026b6fae2bSMattias Nilsson 18036b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate) 18046b6fae2bSMattias Nilsson { 18056b6fae2bSMattias Nilsson u32 div; 18066b6fae2bSMattias Nilsson unsigned long src_rate; 18076b6fae2bSMattias Nilsson long rounded_rate; 18086b6fae2bSMattias Nilsson 18096b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), 18106b6fae2bSMattias Nilsson PLL_RAW); 18116b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18126b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div)); 18136b6fae2bSMattias Nilsson 18146b6fae2bSMattias Nilsson return rounded_rate; 18156b6fae2bSMattias Nilsson } 18166b6fae2bSMattias Nilsson 18176b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate) 18186b6fae2bSMattias Nilsson { 18196b6fae2bSMattias Nilsson u32 div; 18206b6fae2bSMattias Nilsson unsigned long src_rate; 18216b6fae2bSMattias Nilsson long rounded_rate; 18226b6fae2bSMattias Nilsson 18236b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK); 18246b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18256b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255)); 18266b6fae2bSMattias Nilsson 18276b6fae2bSMattias Nilsson return rounded_rate; 18286b6fae2bSMattias Nilsson } 18296b6fae2bSMattias Nilsson 18306b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate) 18316b6fae2bSMattias Nilsson { 1832e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS) 18336b6fae2bSMattias Nilsson return round_clock_rate(clock, rate); 1834b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 1835b2302c87SUlf Hansson return round_armss_rate(rate); 18366b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 18376b6fae2bSMattias Nilsson return round_plldsi_rate(rate); 18386b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 18396b6fae2bSMattias Nilsson return round_dsiclk_rate(rate); 18406b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 18416b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate); 18426b6fae2bSMattias Nilsson else 18436b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock); 18446b6fae2bSMattias Nilsson } 18456b6fae2bSMattias Nilsson 18466b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate) 18476b6fae2bSMattias Nilsson { 18486b6fae2bSMattias Nilsson u32 val; 18496b6fae2bSMattias Nilsson u32 div; 18506b6fae2bSMattias Nilsson unsigned long src_rate; 18516b6fae2bSMattias Nilsson unsigned long flags; 18526b6fae2bSMattias Nilsson 18536b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags); 18546b6fae2bSMattias Nilsson 18556b6fae2bSMattias Nilsson /* Grab the HW semaphore. */ 18566b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 18576b6fae2bSMattias Nilsson cpu_relax(); 18586b6fae2bSMattias Nilsson 1859b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset); 18606b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 18616b6fae2bSMattias Nilsson clk_mgt[clock].branch); 18626b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate); 18636b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) { 18646b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) { 18656b6fae2bSMattias Nilsson if (div > 1) 18666b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV; 18676b6fae2bSMattias Nilsson else 18686b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV; 18696b6fae2bSMattias Nilsson } 18706b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) { 18716b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | 18726b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); 18736b6fae2bSMattias Nilsson if (div == 3) { 18746b6fae2bSMattias Nilsson u64 r = (src_rate * 10); 18756b6fae2bSMattias Nilsson 18766b6fae2bSMattias Nilsson (void)do_div(r, 25); 18776b6fae2bSMattias Nilsson if (r <= rate) { 18786b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; 18796b6fae2bSMattias Nilsson div = 0; 18806b6fae2bSMattias Nilsson } 18816b6fae2bSMattias Nilsson } 18826b6fae2bSMattias Nilsson val |= min(div, (u32)31); 18836b6fae2bSMattias Nilsson } else { 18846b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 18856b6fae2bSMattias Nilsson val |= min(div, (u32)31); 18866b6fae2bSMattias Nilsson } 1887b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset); 18886b6fae2bSMattias Nilsson 18896b6fae2bSMattias Nilsson /* Release the HW semaphore. */ 18906b6fae2bSMattias Nilsson writel(0, PRCM_SEM); 18916b6fae2bSMattias Nilsson 18926b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags); 18936b6fae2bSMattias Nilsson } 18946b6fae2bSMattias Nilsson 1895b2302c87SUlf Hansson static int set_armss_rate(unsigned long rate) 1896b2302c87SUlf Hansson { 1897836a1e25SLinus Walleij unsigned long freq; 1898836a1e25SLinus Walleij u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP }; 1899fea3ac55SLinus Walleij const unsigned long *freqs; 1900fea3ac55SLinus Walleij int nfreqs; 1901836a1e25SLinus Walleij int i; 1902b2302c87SUlf Hansson 1903fea3ac55SLinus Walleij if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) { 1904fea3ac55SLinus Walleij freqs = db8520_armss_freqs; 1905fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8520_armss_freqs); 1906fea3ac55SLinus Walleij } else { 1907fea3ac55SLinus Walleij freqs = db8500_armss_freqs; 1908fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8500_armss_freqs); 1909fea3ac55SLinus Walleij } 1910fea3ac55SLinus Walleij 1911b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */ 1912fea3ac55SLinus Walleij for (i = 0; i < nfreqs; i++) { 1913fea3ac55SLinus Walleij freq = freqs[i]; 1914836a1e25SLinus Walleij if (rate == freq) 1915b2302c87SUlf Hansson break; 1916836a1e25SLinus Walleij } 1917b2302c87SUlf Hansson 1918836a1e25SLinus Walleij if (rate != freq) 1919b2302c87SUlf Hansson return -EINVAL; 1920b2302c87SUlf Hansson 1921b2302c87SUlf Hansson /* Set the new arm opp. */ 1922836a1e25SLinus Walleij pr_debug("SET ARM OPP 0x%02x\n", opps[i]); 1923836a1e25SLinus Walleij return db8500_prcmu_set_arm_opp(opps[i]); 1924b2302c87SUlf Hansson } 1925b2302c87SUlf Hansson 19266b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate) 19276b6fae2bSMattias Nilsson { 19286b6fae2bSMattias Nilsson unsigned long src_rate; 19296b6fae2bSMattias Nilsson unsigned long rem; 19306b6fae2bSMattias Nilsson u32 pll_freq = 0; 19316b6fae2bSMattias Nilsson u32 r; 19326b6fae2bSMattias Nilsson 19336b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK); 19346b6fae2bSMattias Nilsson rem = rate; 19356b6fae2bSMattias Nilsson 19366b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) { 19376b6fae2bSMattias Nilsson u64 d; 19386b6fae2bSMattias Nilsson u64 hwrate; 19396b6fae2bSMattias Nilsson 19406b6fae2bSMattias Nilsson d = (r * rate); 19416b6fae2bSMattias Nilsson (void)do_div(d, src_rate); 19426b6fae2bSMattias Nilsson if (d < 6) 19436b6fae2bSMattias Nilsson d = 6; 19446b6fae2bSMattias Nilsson else if (d > 255) 19456b6fae2bSMattias Nilsson d = 255; 19466b6fae2bSMattias Nilsson hwrate = (d * src_rate); 19476b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || 19486b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) 19496b6fae2bSMattias Nilsson continue; 19506b6fae2bSMattias Nilsson (void)do_div(hwrate, r); 19516b6fae2bSMattias Nilsson if (rate < hwrate) { 19526b6fae2bSMattias Nilsson if (pll_freq == 0) 19536b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19546b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19556b6fae2bSMattias Nilsson break; 19566b6fae2bSMattias Nilsson } 19576b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) { 19586b6fae2bSMattias Nilsson rem = (rate - hwrate); 19596b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | 19606b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT)); 19616b6fae2bSMattias Nilsson } 19626b6fae2bSMattias Nilsson } 19636b6fae2bSMattias Nilsson if (pll_freq == 0) 19643df57bcfSMattias Nilsson return -EINVAL; 19656b6fae2bSMattias Nilsson 19666b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); 19676b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ); 19686b6fae2bSMattias Nilsson 19696b6fae2bSMattias Nilsson return 0; 19706b6fae2bSMattias Nilsson } 19716b6fae2bSMattias Nilsson 19726b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate) 19736b6fae2bSMattias Nilsson { 19746b6fae2bSMattias Nilsson u32 val; 19756b6fae2bSMattias Nilsson u32 div; 19766b6fae2bSMattias Nilsson 19776b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, 19786b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); 19796b6fae2bSMattias Nilsson 19806b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : 19816b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : 19826b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; 19836b6fae2bSMattias Nilsson 19846b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL); 19856b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask; 19866b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); 19876b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL); 19886b6fae2bSMattias Nilsson } 19896b6fae2bSMattias Nilsson 19906b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate) 19916b6fae2bSMattias Nilsson { 19926b6fae2bSMattias Nilsson u32 val; 19936b6fae2bSMattias Nilsson u32 div; 19946b6fae2bSMattias Nilsson 19956b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate); 19966b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV); 19976b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask; 19986b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift); 19996b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV); 20006b6fae2bSMattias Nilsson } 20016b6fae2bSMattias Nilsson 20026b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate) 20036b6fae2bSMattias Nilsson { 20046b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS) 20056b6fae2bSMattias Nilsson set_clock_rate(clock, rate); 2006b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS) 2007b2302c87SUlf Hansson return set_armss_rate(rate); 20086b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI) 20096b6fae2bSMattias Nilsson return set_plldsi_rate(rate); 20106b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 20116b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); 20126b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) 20136b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); 20146b6fae2bSMattias Nilsson return 0; 20153df57bcfSMattias Nilsson } 20163df57bcfSMattias Nilsson 201773180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state) 20183df57bcfSMattias Nilsson { 20193df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 20203df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 20213df57bcfSMattias Nilsson return -EINVAL; 20223df57bcfSMattias Nilsson 20233df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20243df57bcfSMattias Nilsson 2025c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20263df57bcfSMattias Nilsson cpu_relax(); 20273df57bcfSMattias Nilsson 20283df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20293df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), 20303df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); 20313df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON, 20323df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); 20333df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); 20343df57bcfSMattias Nilsson 2035c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20363df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20373df57bcfSMattias Nilsson 20383df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20393df57bcfSMattias Nilsson 20403df57bcfSMattias Nilsson return 0; 20413df57bcfSMattias Nilsson } 20423df57bcfSMattias Nilsson 20430508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold) 20443df57bcfSMattias Nilsson { 20453df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20463df57bcfSMattias Nilsson 2047c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20483df57bcfSMattias Nilsson cpu_relax(); 20493df57bcfSMattias Nilsson 20503df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); 20513df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20523df57bcfSMattias Nilsson 2053c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20543df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20553df57bcfSMattias Nilsson 20563df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20573df57bcfSMattias Nilsson 20583df57bcfSMattias Nilsson return 0; 20593df57bcfSMattias Nilsson } 20603df57bcfSMattias Nilsson 20610508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high) 20623df57bcfSMattias Nilsson { 20633df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20643df57bcfSMattias Nilsson 2065c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20663df57bcfSMattias Nilsson cpu_relax(); 20673df57bcfSMattias Nilsson 20683df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); 20693df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); 20703df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), 20713df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); 20723df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20733df57bcfSMattias Nilsson 2074c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20753df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20763df57bcfSMattias Nilsson 20773df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20783df57bcfSMattias Nilsson 20793df57bcfSMattias Nilsson return 0; 20803df57bcfSMattias Nilsson } 208126716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon); 20823df57bcfSMattias Nilsson 20833df57bcfSMattias Nilsson static int config_hot_period(u16 val) 20843df57bcfSMattias Nilsson { 20853df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock); 20863df57bcfSMattias Nilsson 2087c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 20883df57bcfSMattias Nilsson cpu_relax(); 20893df57bcfSMattias Nilsson 20903df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); 20913df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 20923df57bcfSMattias Nilsson 2093c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 20943df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work); 20953df57bcfSMattias Nilsson 20963df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock); 20973df57bcfSMattias Nilsson 20983df57bcfSMattias Nilsson return 0; 20993df57bcfSMattias Nilsson } 21003df57bcfSMattias Nilsson 21010508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k) 21023df57bcfSMattias Nilsson { 21033df57bcfSMattias Nilsson if (cycles32k == 0xFFFF) 21043df57bcfSMattias Nilsson return -EINVAL; 21053df57bcfSMattias Nilsson 21063df57bcfSMattias Nilsson return config_hot_period(cycles32k); 21073df57bcfSMattias Nilsson } 210826716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense); 21093df57bcfSMattias Nilsson 21100508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void) 21113df57bcfSMattias Nilsson { 21123df57bcfSMattias Nilsson return config_hot_period(0xFFFF); 21133df57bcfSMattias Nilsson } 211426716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense); 21153df57bcfSMattias Nilsson 211684165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) 211784165b80SJonas Aberg { 211884165b80SJonas Aberg 211984165b80SJonas Aberg mutex_lock(&mb4_transfer.lock); 212084165b80SJonas Aberg 212184165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) 212284165b80SJonas Aberg cpu_relax(); 212384165b80SJonas Aberg 212484165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); 212584165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); 212684165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); 212784165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); 212884165b80SJonas Aberg 212984165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); 213084165b80SJonas Aberg 213184165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); 213284165b80SJonas Aberg wait_for_completion(&mb4_transfer.work); 213384165b80SJonas Aberg 213484165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock); 213584165b80SJonas Aberg 213684165b80SJonas Aberg return 0; 213784165b80SJonas Aberg 213884165b80SJonas Aberg } 213984165b80SJonas Aberg 21400508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 214184165b80SJonas Aberg { 214284165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf); 214384165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, 214484165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN : 214584165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS); 214684165b80SJonas Aberg } 21476f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); 214884165b80SJonas Aberg 21490508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id) 215084165b80SJonas Aberg { 215184165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); 215284165b80SJonas Aberg } 21536f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); 215484165b80SJonas Aberg 21550508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id) 215684165b80SJonas Aberg { 215784165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); 215884165b80SJonas Aberg } 21596f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); 216084165b80SJonas Aberg 21610508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id) 216284165b80SJonas Aberg { 216384165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); 216484165b80SJonas Aberg } 21656f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); 216684165b80SJonas Aberg 216784165b80SJonas Aberg /* 216884165b80SJonas Aberg * timeout is 28 bit, in ms. 216984165b80SJonas Aberg */ 21700508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) 217184165b80SJonas Aberg { 217284165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD, 217384165b80SJonas Aberg (id & A9WDOG_ID_MASK) | 217484165b80SJonas Aberg /* 217584165b80SJonas Aberg * Put the lowest 28 bits of timeout at 217684165b80SJonas Aberg * offset 4. Four first bits are used for id. 217784165b80SJonas Aberg */ 217884165b80SJonas Aberg (u8)((timeout << 4) & 0xf0), 217984165b80SJonas Aberg (u8)((timeout >> 4) & 0xff), 218084165b80SJonas Aberg (u8)((timeout >> 12) & 0xff), 218184165b80SJonas Aberg (u8)((timeout >> 20) & 0xff)); 218284165b80SJonas Aberg } 21836f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); 218484165b80SJonas Aberg 21853df57bcfSMattias Nilsson /** 2186650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB. 2187650c2a21SLinus Walleij * @slave: The I2C slave address. 2188650c2a21SLinus Walleij * @reg: The (start) register address. 2189650c2a21SLinus Walleij * @value: The read out value(s). 2190650c2a21SLinus Walleij * @size: The number of registers to read. 2191650c2a21SLinus Walleij * 2192650c2a21SLinus Walleij * Reads register value(s) from the ABB. 2193650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2194650c2a21SLinus Walleij */ 2195650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 2196650c2a21SLinus Walleij { 2197650c2a21SLinus Walleij int r; 2198650c2a21SLinus Walleij 2199650c2a21SLinus Walleij if (size != 1) 2200650c2a21SLinus Walleij return -EINVAL; 2201650c2a21SLinus Walleij 22023df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2203650c2a21SLinus Walleij 2204c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2205650c2a21SLinus Walleij cpu_relax(); 2206650c2a21SLinus Walleij 22073c3e4898SMattias Nilsson writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 22083df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22093df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22103df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22113df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2212650c2a21SLinus Walleij 2213c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 22143df57bcfSMattias Nilsson 2215650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 22163df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 22173df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 22183df57bcfSMattias Nilsson __func__); 2219650c2a21SLinus Walleij r = -EIO; 22203df57bcfSMattias Nilsson } else { 2221650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); 22223df57bcfSMattias Nilsson } 22233df57bcfSMattias Nilsson 2224650c2a21SLinus Walleij if (!r) 2225650c2a21SLinus Walleij *value = mb5_transfer.ack.value; 2226650c2a21SLinus Walleij 2227650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock); 22283df57bcfSMattias Nilsson 2229650c2a21SLinus Walleij return r; 2230650c2a21SLinus Walleij } 2231650c2a21SLinus Walleij 2232650c2a21SLinus Walleij /** 22333c3e4898SMattias Nilsson * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. 2234650c2a21SLinus Walleij * @slave: The I2C slave address. 2235650c2a21SLinus Walleij * @reg: The (start) register address. 2236650c2a21SLinus Walleij * @value: The value(s) to write. 22373c3e4898SMattias Nilsson * @mask: The mask(s) to use. 2238650c2a21SLinus Walleij * @size: The number of registers to write. 2239650c2a21SLinus Walleij * 22403c3e4898SMattias Nilsson * Writes masked register value(s) to the ABB. 22413c3e4898SMattias Nilsson * For each @value, only the bits set to 1 in the corresponding @mask 22423c3e4898SMattias Nilsson * will be written. The other bits are not changed. 2243650c2a21SLinus Walleij * @size has to be 1 for the current firmware version. 2244650c2a21SLinus Walleij */ 22453c3e4898SMattias Nilsson int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) 2246650c2a21SLinus Walleij { 2247650c2a21SLinus Walleij int r; 2248650c2a21SLinus Walleij 2249650c2a21SLinus Walleij if (size != 1) 2250650c2a21SLinus Walleij return -EINVAL; 2251650c2a21SLinus Walleij 22523df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock); 2253650c2a21SLinus Walleij 2254c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) 2255650c2a21SLinus Walleij cpu_relax(); 2256650c2a21SLinus Walleij 22573c3e4898SMattias Nilsson writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); 22583df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); 22593df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); 22603df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); 22613df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); 2262650c2a21SLinus Walleij 2263c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); 22643df57bcfSMattias Nilsson 2265650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work, 22663df57bcfSMattias Nilsson msecs_to_jiffies(20000))) { 22673df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", 22683df57bcfSMattias Nilsson __func__); 2269650c2a21SLinus Walleij r = -EIO; 22703df57bcfSMattias Nilsson } else { 2271650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); 22723df57bcfSMattias Nilsson } 22733df57bcfSMattias Nilsson 22743df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock); 22753df57bcfSMattias Nilsson 22763df57bcfSMattias Nilsson return r; 22773df57bcfSMattias Nilsson } 22783df57bcfSMattias Nilsson 22793df57bcfSMattias Nilsson /** 22803c3e4898SMattias Nilsson * prcmu_abb_write() - Write register value(s) to the ABB. 22813c3e4898SMattias Nilsson * @slave: The I2C slave address. 22823c3e4898SMattias Nilsson * @reg: The (start) register address. 22833c3e4898SMattias Nilsson * @value: The value(s) to write. 22843c3e4898SMattias Nilsson * @size: The number of registers to write. 22853c3e4898SMattias Nilsson * 22863c3e4898SMattias Nilsson * Writes register value(s) to the ABB. 22873c3e4898SMattias Nilsson * @size has to be 1 for the current firmware version. 22883c3e4898SMattias Nilsson */ 22893c3e4898SMattias Nilsson int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 22903c3e4898SMattias Nilsson { 22913c3e4898SMattias Nilsson u8 mask = ~0; 22923c3e4898SMattias Nilsson 22933c3e4898SMattias Nilsson return prcmu_abb_write_masked(slave, reg, value, &mask, size); 22943c3e4898SMattias Nilsson } 22953c3e4898SMattias Nilsson 22963c3e4898SMattias Nilsson /** 22973df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem 22983df57bcfSMattias Nilsson */ 22995261e101SArun Murthy int prcmu_ac_wake_req(void) 23003df57bcfSMattias Nilsson { 23013df57bcfSMattias Nilsson u32 val; 23025261e101SArun Murthy int ret = 0; 23033df57bcfSMattias Nilsson 23043df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 23053df57bcfSMattias Nilsson 2306c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23073df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) 23083df57bcfSMattias Nilsson goto unlock_and_return; 23093df57bcfSMattias Nilsson 23103df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1); 23113df57bcfSMattias Nilsson 23125261e101SArun Murthy /* 23135261e101SArun Murthy * Force Modem Wake-up before hostaccess_req ping-pong. 23145261e101SArun Murthy * It prevents Modem to enter in Sleep while acking the hostaccess 23155261e101SArun Murthy * request. The 31us delay has been calculated by HWI. 23165261e101SArun Murthy */ 23175261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; 23185261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 23195261e101SArun Murthy 23205261e101SArun Murthy udelay(31); 23215261e101SArun Murthy 23225261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; 23235261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ); 23243df57bcfSMattias Nilsson 23253df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2326d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 232757265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 2328d6e3002eSMattias Nilsson __func__); 23295261e101SArun Murthy ret = -EFAULT; 23303df57bcfSMattias Nilsson } 2331650c2a21SLinus Walleij 2332650c2a21SLinus Walleij unlock_and_return: 23333df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23345261e101SArun Murthy return ret; 2335650c2a21SLinus Walleij } 2336650c2a21SLinus Walleij 23373df57bcfSMattias Nilsson /** 23383df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem 23393df57bcfSMattias Nilsson */ 2340ffb01160SSachin Kamat void prcmu_ac_sleep_req(void) 2341650c2a21SLinus Walleij { 23423df57bcfSMattias Nilsson u32 val; 2343650c2a21SLinus Walleij 23443df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock); 2345650c2a21SLinus Walleij 2346c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ); 23473df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) 23483df57bcfSMattias Nilsson goto unlock_and_return; 23493df57bcfSMattias Nilsson 23503df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), 2351c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ); 23523df57bcfSMattias Nilsson 23533df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, 2354d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) { 235557265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", 23563df57bcfSMattias Nilsson __func__); 23573df57bcfSMattias Nilsson } 23583df57bcfSMattias Nilsson 23593df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0); 23603df57bcfSMattias Nilsson 23613df57bcfSMattias Nilsson unlock_and_return: 23623df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock); 23633df57bcfSMattias Nilsson } 23643df57bcfSMattias Nilsson 236573180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void) 23663df57bcfSMattias Nilsson { 23673df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0); 23683df57bcfSMattias Nilsson } 23693df57bcfSMattias Nilsson 23703df57bcfSMattias Nilsson /** 237173180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset 23723df57bcfSMattias Nilsson * 237373180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which 23743df57bcfSMattias Nilsson * fires interrupt to fw 23753df57bcfSMattias Nilsson */ 237673180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code) 23773df57bcfSMattias Nilsson { 23783df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 2379c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST); 23803df57bcfSMattias Nilsson } 23813df57bcfSMattias Nilsson 23823df57bcfSMattias Nilsson /** 2383597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code 2384597045deSSebastian Rasmussen * 2385597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before 2386597045deSSebastian Rasmussen * last restart. 2387597045deSSebastian Rasmussen */ 2388597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void) 2389597045deSSebastian Rasmussen { 2390597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON); 2391597045deSSebastian Rasmussen } 2392597045deSSebastian Rasmussen 2393597045deSSebastian Rasmussen /** 23940508901cSMattias Nilsson * db8500_prcmu_reset_modem - ask the PRCMU to reset modem 23953df57bcfSMattias Nilsson */ 23960508901cSMattias Nilsson void db8500_prcmu_modem_reset(void) 23973df57bcfSMattias Nilsson { 2398650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock); 2399650c2a21SLinus Walleij 2400c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) 2401650c2a21SLinus Walleij cpu_relax(); 2402650c2a21SLinus Walleij 24033df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); 2404c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); 2405650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work); 24063df57bcfSMattias Nilsson 24073df57bcfSMattias Nilsson /* 24083df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state 24093df57bcfSMattias Nilsson * This state is already managed by upper layer 24103df57bcfSMattias Nilsson */ 2411650c2a21SLinus Walleij 2412650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock); 2413650c2a21SLinus Walleij } 2414650c2a21SLinus Walleij 24153df57bcfSMattias Nilsson static void ack_dbb_wakeup(void) 2416650c2a21SLinus Walleij { 24173df57bcfSMattias Nilsson unsigned long flags; 2418650c2a21SLinus Walleij 24193df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 2420650c2a21SLinus Walleij 2421c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) 24223df57bcfSMattias Nilsson cpu_relax(); 2423650c2a21SLinus Walleij 24243df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); 2425c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); 2426650c2a21SLinus Walleij 24273df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 2428650c2a21SLinus Walleij } 2429650c2a21SLinus Walleij 24303df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header) 2431650c2a21SLinus Walleij { 243281d30edaSJoe Perches pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n", 24333df57bcfSMattias Nilsson header, n); 2434650c2a21SLinus Walleij } 2435650c2a21SLinus Walleij 24363df57bcfSMattias Nilsson static bool read_mailbox_0(void) 2437650c2a21SLinus Walleij { 24383df57bcfSMattias Nilsson bool r; 24393df57bcfSMattias Nilsson u32 ev; 24403df57bcfSMattias Nilsson unsigned int n; 24413df57bcfSMattias Nilsson u8 header; 24423df57bcfSMattias Nilsson 24433df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); 24443df57bcfSMattias Nilsson switch (header) { 24453df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE: 24463df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP: 24473df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 24483df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); 24493df57bcfSMattias Nilsson else 24503df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); 24513df57bcfSMattias Nilsson 24523df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) 24533df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work); 24543df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK) 24553df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work); 24563df57bcfSMattias Nilsson 24573df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs; 24583df57bcfSMattias Nilsson 24593df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { 24603df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n]) 246189d9b1c9SLinus Walleij generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); 24623df57bcfSMattias Nilsson } 24633df57bcfSMattias Nilsson r = true; 24643df57bcfSMattias Nilsson break; 24653df57bcfSMattias Nilsson default: 24663df57bcfSMattias Nilsson print_unknown_header_warning(0, header); 24673df57bcfSMattias Nilsson r = false; 24683df57bcfSMattias Nilsson break; 24693df57bcfSMattias Nilsson } 2470c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); 24713df57bcfSMattias Nilsson return r; 24723df57bcfSMattias Nilsson } 24733df57bcfSMattias Nilsson 24743df57bcfSMattias Nilsson static bool read_mailbox_1(void) 24753df57bcfSMattias Nilsson { 24763df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); 24773df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base + 24783df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP); 24793df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base + 24803df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP); 24813df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + 24823df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS); 2483c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); 2484650c2a21SLinus Walleij complete(&mb1_transfer.work); 24853df57bcfSMattias Nilsson return false; 2486650c2a21SLinus Walleij } 2487650c2a21SLinus Walleij 24883df57bcfSMattias Nilsson static bool read_mailbox_2(void) 2489650c2a21SLinus Walleij { 24903df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); 2491c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); 24923df57bcfSMattias Nilsson complete(&mb2_transfer.work); 24933df57bcfSMattias Nilsson return false; 2494650c2a21SLinus Walleij } 2495650c2a21SLinus Walleij 24963df57bcfSMattias Nilsson static bool read_mailbox_3(void) 2497650c2a21SLinus Walleij { 2498c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); 24993df57bcfSMattias Nilsson return false; 2500650c2a21SLinus Walleij } 2501650c2a21SLinus Walleij 25023df57bcfSMattias Nilsson static bool read_mailbox_4(void) 2503650c2a21SLinus Walleij { 25043df57bcfSMattias Nilsson u8 header; 25053df57bcfSMattias Nilsson bool do_complete = true; 25063df57bcfSMattias Nilsson 25073df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); 25083df57bcfSMattias Nilsson switch (header) { 25093df57bcfSMattias Nilsson case MB4H_MEM_ST: 25103df57bcfSMattias Nilsson case MB4H_HOTDOG: 25113df57bcfSMattias Nilsson case MB4H_HOTMON: 25123df57bcfSMattias Nilsson case MB4H_HOT_PERIOD: 2513a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF: 2514a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN: 2515a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS: 2516a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD: 2517a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK: 25183df57bcfSMattias Nilsson break; 25193df57bcfSMattias Nilsson default: 25203df57bcfSMattias Nilsson print_unknown_header_warning(4, header); 25213df57bcfSMattias Nilsson do_complete = false; 25223df57bcfSMattias Nilsson break; 2523650c2a21SLinus Walleij } 2524650c2a21SLinus Walleij 2525c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); 25263df57bcfSMattias Nilsson 25273df57bcfSMattias Nilsson if (do_complete) 25283df57bcfSMattias Nilsson complete(&mb4_transfer.work); 25293df57bcfSMattias Nilsson 25303df57bcfSMattias Nilsson return false; 25313df57bcfSMattias Nilsson } 25323df57bcfSMattias Nilsson 25333df57bcfSMattias Nilsson static bool read_mailbox_5(void) 2534650c2a21SLinus Walleij { 25353df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); 25363df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); 2537c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); 2538650c2a21SLinus Walleij complete(&mb5_transfer.work); 25393df57bcfSMattias Nilsson return false; 2540650c2a21SLinus Walleij } 2541650c2a21SLinus Walleij 25423df57bcfSMattias Nilsson static bool read_mailbox_6(void) 2543650c2a21SLinus Walleij { 2544c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); 25453df57bcfSMattias Nilsson return false; 2546650c2a21SLinus Walleij } 2547650c2a21SLinus Walleij 25483df57bcfSMattias Nilsson static bool read_mailbox_7(void) 2549650c2a21SLinus Walleij { 2550c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); 25513df57bcfSMattias Nilsson return false; 2552650c2a21SLinus Walleij } 2553650c2a21SLinus Walleij 25543df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = { 2555650c2a21SLinus Walleij read_mailbox_0, 2556650c2a21SLinus Walleij read_mailbox_1, 2557650c2a21SLinus Walleij read_mailbox_2, 2558650c2a21SLinus Walleij read_mailbox_3, 2559650c2a21SLinus Walleij read_mailbox_4, 2560650c2a21SLinus Walleij read_mailbox_5, 2561650c2a21SLinus Walleij read_mailbox_6, 2562650c2a21SLinus Walleij read_mailbox_7 2563650c2a21SLinus Walleij }; 2564650c2a21SLinus Walleij 2565650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data) 2566650c2a21SLinus Walleij { 2567650c2a21SLinus Walleij u32 bits; 2568650c2a21SLinus Walleij u8 n; 25693df57bcfSMattias Nilsson irqreturn_t r; 2570650c2a21SLinus Walleij 2571c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); 2572650c2a21SLinus Walleij if (unlikely(!bits)) 2573650c2a21SLinus Walleij return IRQ_NONE; 2574650c2a21SLinus Walleij 25753df57bcfSMattias Nilsson r = IRQ_HANDLED; 2576650c2a21SLinus Walleij for (n = 0; bits; n++) { 2577650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) { 2578650c2a21SLinus Walleij bits -= MBOX_BIT(n); 25793df57bcfSMattias Nilsson if (read_mailbox[n]()) 25803df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD; 2581650c2a21SLinus Walleij } 2582650c2a21SLinus Walleij } 25833df57bcfSMattias Nilsson return r; 25843df57bcfSMattias Nilsson } 25853df57bcfSMattias Nilsson 25863df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) 25873df57bcfSMattias Nilsson { 25883df57bcfSMattias Nilsson ack_dbb_wakeup(); 2589650c2a21SLinus Walleij return IRQ_HANDLED; 2590650c2a21SLinus Walleij } 2591650c2a21SLinus Walleij 25923df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work) 25933df57bcfSMattias Nilsson { 25943df57bcfSMattias Nilsson unsigned long flags; 25953df57bcfSMattias Nilsson 25963df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags); 25973df57bcfSMattias Nilsson 25983df57bcfSMattias Nilsson config_wakeups(); 25993df57bcfSMattias Nilsson 26003df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags); 26013df57bcfSMattias Nilsson } 26023df57bcfSMattias Nilsson 26033df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d) 26043df57bcfSMattias Nilsson { 26053df57bcfSMattias Nilsson unsigned long flags; 26063df57bcfSMattias Nilsson 26073df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26083df57bcfSMattias Nilsson 2609f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; 26103df57bcfSMattias Nilsson 26113df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26123df57bcfSMattias Nilsson 26133df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26143df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26153df57bcfSMattias Nilsson } 26163df57bcfSMattias Nilsson 26173df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d) 26183df57bcfSMattias Nilsson { 26193df57bcfSMattias Nilsson unsigned long flags; 26203df57bcfSMattias Nilsson 26213df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); 26223df57bcfSMattias Nilsson 2623f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; 26243df57bcfSMattias Nilsson 26253df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); 26263df57bcfSMattias Nilsson 26273df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP) 26283df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work); 26293df57bcfSMattias Nilsson } 26303df57bcfSMattias Nilsson 26313df57bcfSMattias Nilsson static void noop(struct irq_data *d) 26323df57bcfSMattias Nilsson { 26333df57bcfSMattias Nilsson } 26343df57bcfSMattias Nilsson 26353df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = { 26363df57bcfSMattias Nilsson .name = "prcmu", 26373df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask, 26383df57bcfSMattias Nilsson .irq_ack = noop, 26393df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask, 26403df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask, 26413df57bcfSMattias Nilsson }; 26423df57bcfSMattias Nilsson 2643a3888f62SNathan Chancellor static char *fw_project_name(u32 project) 2644b58d12feSMattias Nilsson { 2645b58d12feSMattias Nilsson switch (project) { 2646b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500: 2647b58d12feSMattias Nilsson return "U8500"; 264805ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8400: 264905ec260eSLinus Walleij return "U8400"; 2650b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500: 2651b58d12feSMattias Nilsson return "U9500"; 265205ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBB: 265305ec260eSLinus Walleij return "U8500 MBB"; 265405ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C1: 265505ec260eSLinus Walleij return "U8500 C1"; 265605ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C2: 265705ec260eSLinus Walleij return "U8500 C2"; 265805ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C3: 265905ec260eSLinus Walleij return "U8500 C3"; 266005ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C4: 266105ec260eSLinus Walleij return "U8500 C4"; 266205ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9500_MBL: 266305ec260eSLinus Walleij return "U9500 MBL"; 266405ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBL: 266505ec260eSLinus Walleij return "U8500 MBL"; 266605ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBL2: 266705ec260eSLinus Walleij return "U8500 MBL2"; 26685f96a1a6SBengt Jonsson case PRCMU_FW_PROJECT_U8520: 266905ec260eSLinus Walleij return "U8520 MBL"; 26701927ddf6SBengt Jonsson case PRCMU_FW_PROJECT_U8420: 26711927ddf6SBengt Jonsson return "U8420"; 267222fb3ad0SLinus Walleij case PRCMU_FW_PROJECT_U8420_SYSCLK: 267322fb3ad0SLinus Walleij return "U8420-sysclk"; 267405ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9540: 267505ec260eSLinus Walleij return "U9540"; 267605ec260eSLinus Walleij case PRCMU_FW_PROJECT_A9420: 267705ec260eSLinus Walleij return "A9420"; 267805ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8540: 267905ec260eSLinus Walleij return "L8540"; 268005ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8580: 268105ec260eSLinus Walleij return "L8580"; 2682b58d12feSMattias Nilsson default: 2683b58d12feSMattias Nilsson return "Unknown"; 2684b58d12feSMattias Nilsson } 2685b58d12feSMattias Nilsson } 2686b58d12feSMattias Nilsson 2687f3f1f0a1SLee Jones static int db8500_irq_map(struct irq_domain *d, unsigned int virq, 2688f3f1f0a1SLee Jones irq_hw_number_t hwirq) 2689f3f1f0a1SLee Jones { 2690f3f1f0a1SLee Jones irq_set_chip_and_handler(virq, &prcmu_irq_chip, 2691f3f1f0a1SLee Jones handle_simple_irq); 2692f3f1f0a1SLee Jones 2693f3f1f0a1SLee Jones return 0; 2694f3f1f0a1SLee Jones } 2695f3f1f0a1SLee Jones 26967ce7b26fSKrzysztof Kozlowski static const struct irq_domain_ops db8500_irq_ops = { 2697f3f1f0a1SLee Jones .map = db8500_irq_map, 2698f3f1f0a1SLee Jones .xlate = irq_domain_xlate_twocell, 2699f3f1f0a1SLee Jones }; 2700f3f1f0a1SLee Jones 2701f864c46aSLinus Walleij static int db8500_irq_init(struct device_node *np) 2702f3f1f0a1SLee Jones { 270389d9b1c9SLinus Walleij int i; 2704a7238e43SLinus Walleij 2705a7238e43SLinus Walleij db8500_irq_domain = irq_domain_add_simple( 2706f864c46aSLinus Walleij np, NUM_PRCMU_WAKEUPS, 0, 2707a7238e43SLinus Walleij &db8500_irq_ops, NULL); 2708f3f1f0a1SLee Jones 2709f3f1f0a1SLee Jones if (!db8500_irq_domain) { 2710f3f1f0a1SLee Jones pr_err("Failed to create irqdomain\n"); 2711f3f1f0a1SLee Jones return -ENOSYS; 2712f3f1f0a1SLee Jones } 2713f3f1f0a1SLee Jones 271489d9b1c9SLinus Walleij /* All wakeups will be used, so create mappings for all */ 271589d9b1c9SLinus Walleij for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) 271689d9b1c9SLinus Walleij irq_create_mapping(db8500_irq_domain, i); 271789d9b1c9SLinus Walleij 2718f3f1f0a1SLee Jones return 0; 2719f3f1f0a1SLee Jones } 2720f3f1f0a1SLee Jones 272122fb3ad0SLinus Walleij static void dbx500_fw_version_init(struct device_node *np) 2722650c2a21SLinus Walleij { 272305ec260eSLinus Walleij void __iomem *tcpm_base; 2724741cdecfSLee Jones u32 version; 27253df57bcfSMattias Nilsson 272622fb3ad0SLinus Walleij tcpm_base = of_iomap(np, 1); 2727741cdecfSLee Jones if (!tcpm_base) { 272822fb3ad0SLinus Walleij pr_err("no prcmu tcpm mem region provided\n"); 2729741cdecfSLee Jones return; 2730741cdecfSLee Jones } 273105ec260eSLinus Walleij 273222fb3ad0SLinus Walleij version = readl(tcpm_base + DB8500_PRCMU_FW_VERSION_OFFSET); 273305ec260eSLinus Walleij fw_info.version.project = (version & 0xFF); 2734b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF; 2735b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF; 2736b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF; 273705ec260eSLinus Walleij strncpy(fw_info.version.project_name, 2738b58d12feSMattias Nilsson fw_project_name(fw_info.version.project), 273905ec260eSLinus Walleij PRCMU_FW_PROJECT_NAME_LEN); 274005ec260eSLinus Walleij fw_info.valid = true; 274105ec260eSLinus Walleij pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", 274205ec260eSLinus Walleij fw_info.version.project_name, 274305ec260eSLinus Walleij fw_info.version.project, 274405ec260eSLinus Walleij fw_info.version.api_version, 274505ec260eSLinus Walleij fw_info.version.func_version, 274605ec260eSLinus Walleij fw_info.version.errata); 27473df57bcfSMattias Nilsson iounmap(tcpm_base); 27483df57bcfSMattias Nilsson } 2749650c2a21SLinus Walleij 275022fb3ad0SLinus Walleij void __init db8500_prcmu_early_init(void) 275105ec260eSLinus Walleij { 27529a47a8dcSLinus Walleij /* 27539a47a8dcSLinus Walleij * This is a temporary remap to bring up the clocks. It is 27549a47a8dcSLinus Walleij * subsequently replaces with a real remap. After the merge of 27559a47a8dcSLinus Walleij * the mailbox subsystem all of this early code goes away, and the 27569a47a8dcSLinus Walleij * clock driver can probe independently. An early initcall will 27579a47a8dcSLinus Walleij * still be needed, but it can be diverted into drivers/clk/ux500. 27589a47a8dcSLinus Walleij */ 275922fb3ad0SLinus Walleij struct device_node *np; 276022fb3ad0SLinus Walleij 276122fb3ad0SLinus Walleij np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu"); 276222fb3ad0SLinus Walleij prcmu_base = of_iomap(np, 0); 276322fb3ad0SLinus Walleij if (!prcmu_base) { 276422fb3ad0SLinus Walleij of_node_put(np); 27659a47a8dcSLinus Walleij pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); 276622fb3ad0SLinus Walleij return; 276722fb3ad0SLinus Walleij } 276822fb3ad0SLinus Walleij dbx500_fw_version_init(np); 276922fb3ad0SLinus Walleij of_node_put(np); 27709a47a8dcSLinus Walleij 27713df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock); 27723df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock); 27733df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock); 27743df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work); 2775650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock); 2776650c2a21SLinus Walleij init_completion(&mb1_transfer.work); 27774d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE; 27783df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock); 27793df57bcfSMattias Nilsson init_completion(&mb2_transfer.work); 27803df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock); 27813df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock); 27823df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock); 27833df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work); 27843df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock); 27853df57bcfSMattias Nilsson init_completion(&mb4_transfer.work); 2786650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock); 2787650c2a21SLinus Walleij init_completion(&mb5_transfer.work); 2788650c2a21SLinus Walleij 27893df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2790650c2a21SLinus Walleij } 2791650c2a21SLinus Walleij 2792a3888f62SNathan Chancellor static void init_prcm_registers(void) 2793d65e12d7SMattias Nilsson { 2794d65e12d7SMattias Nilsson u32 val; 2795d65e12d7SMattias Nilsson 2796d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN); 2797d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | 2798d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); 2799d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN)); 2800d65e12d7SMattias Nilsson } 2801d65e12d7SMattias Nilsson 28021032fbfdSBengt Jonsson /* 28031032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC 28041032fbfdSBengt Jonsson */ 28051032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = { 28061032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL), 28071032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), 28081032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), 28091032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), 28101032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), 2811ae840635SLee Jones REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), 28121032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */ 28131032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"), 28141032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"), 28151032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"), 28161032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"), 28171032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"), 28181032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"), 28191032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), 28201032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */ 28211032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"), 28221032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"), 28231032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"), 28241032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), 2825992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), 2826bc367481SLee Jones REGULATOR_SUPPLY("vddvario", "smsc911x.0"), 28271032fbfdSBengt Jonsson }; 28281032fbfdSBengt Jonsson 28291032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { 28301032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), 28311032fbfdSBengt Jonsson /* AV8100 regulator */ 28321032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), 28331032fbfdSBengt Jonsson }; 28341032fbfdSBengt Jonsson 28351032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { 2836992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"), 2837624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"), 2838624e87c2SBengt Jonsson }; 2839624e87c2SBengt Jonsson 2840624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */ 2841624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { 2842624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), 2843624e87c2SBengt Jonsson }; 2844624e87c2SBengt Jonsson 2845624e87c2SBengt Jonsson /* SVA pipe regulator switch */ 2846624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = { 2847624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"), 2848624e87c2SBengt Jonsson }; 2849624e87c2SBengt Jonsson 2850624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */ 2851624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { 2852624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), 2853624e87c2SBengt Jonsson }; 2854624e87c2SBengt Jonsson 2855624e87c2SBengt Jonsson /* SIA pipe regulator switch */ 2856624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = { 2857624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"), 2858624e87c2SBengt Jonsson }; 2859624e87c2SBengt Jonsson 2860624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = { 2861624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL), 2862624e87c2SBengt Jonsson }; 2863624e87c2SBengt Jonsson 2864624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */ 2865624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = { 2866624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"), 2867624e87c2SBengt Jonsson }; 2868624e87c2SBengt Jonsson 2869624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */ 2870624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = { 2871624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"), 2872624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"), 2873992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"), 28741032fbfdSBengt Jonsson }; 28751032fbfdSBengt Jonsson 28761032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { 28771032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = { 28781032fbfdSBengt Jonsson .constraints = { 28791032fbfdSBengt Jonsson .name = "db8500-vape", 28801032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28811e45860fSMark Brown .always_on = true, 28821032fbfdSBengt Jonsson }, 28831032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers, 28841032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), 28851032fbfdSBengt Jonsson }, 28861032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = { 28871032fbfdSBengt Jonsson .constraints = { 28881032fbfdSBengt Jonsson .name = "db8500-varm", 28891032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28901032fbfdSBengt Jonsson }, 28911032fbfdSBengt Jonsson }, 28921032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = { 28931032fbfdSBengt Jonsson .constraints = { 28941032fbfdSBengt Jonsson .name = "db8500-vmodem", 28951032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 28961032fbfdSBengt Jonsson }, 28971032fbfdSBengt Jonsson }, 28981032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = { 28991032fbfdSBengt Jonsson .constraints = { 29001032fbfdSBengt Jonsson .name = "db8500-vpll", 29011032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29021032fbfdSBengt Jonsson }, 29031032fbfdSBengt Jonsson }, 29041032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = { 29051032fbfdSBengt Jonsson .constraints = { 29061032fbfdSBengt Jonsson .name = "db8500-vsmps1", 29071032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29081032fbfdSBengt Jonsson }, 29091032fbfdSBengt Jonsson }, 29101032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = { 29111032fbfdSBengt Jonsson .constraints = { 29121032fbfdSBengt Jonsson .name = "db8500-vsmps2", 29131032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29141032fbfdSBengt Jonsson }, 29151032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers, 29161032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), 29171032fbfdSBengt Jonsson }, 29181032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = { 29191032fbfdSBengt Jonsson .constraints = { 29201032fbfdSBengt Jonsson .name = "db8500-vsmps3", 29211032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29221032fbfdSBengt Jonsson }, 29231032fbfdSBengt Jonsson }, 29241032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = { 29251032fbfdSBengt Jonsson .constraints = { 29261032fbfdSBengt Jonsson .name = "db8500-vrf1", 29271032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29281032fbfdSBengt Jonsson }, 29291032fbfdSBengt Jonsson }, 29301032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { 2931992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29321032fbfdSBengt Jonsson .constraints = { 29331032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp", 29341032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29351032fbfdSBengt Jonsson }, 2936624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers, 2937624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), 29381032fbfdSBengt Jonsson }, 29391032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { 29401032fbfdSBengt Jonsson .constraints = { 29411032fbfdSBengt Jonsson /* "ret" means "retention" */ 29421032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret", 29431032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29441032fbfdSBengt Jonsson }, 29451032fbfdSBengt Jonsson }, 29461032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = { 2947992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29481032fbfdSBengt Jonsson .constraints = { 29491032fbfdSBengt Jonsson .name = "db8500-sva-pipe", 29501032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29511032fbfdSBengt Jonsson }, 2952624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers, 2953624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), 29541032fbfdSBengt Jonsson }, 29551032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { 2956992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29571032fbfdSBengt Jonsson .constraints = { 29581032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp", 29591032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29601032fbfdSBengt Jonsson }, 2961624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers, 2962624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), 29631032fbfdSBengt Jonsson }, 29641032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { 29651032fbfdSBengt Jonsson .constraints = { 29661032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret", 29671032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29681032fbfdSBengt Jonsson }, 29691032fbfdSBengt Jonsson }, 29701032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = { 2971992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */ 29721032fbfdSBengt Jonsson .constraints = { 29731032fbfdSBengt Jonsson .name = "db8500-sia-pipe", 29741032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29751032fbfdSBengt Jonsson }, 2976624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers, 2977624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), 29781032fbfdSBengt Jonsson }, 29791032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = { 29801032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29811032fbfdSBengt Jonsson .constraints = { 29821032fbfdSBengt Jonsson .name = "db8500-sga", 29831032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29841032fbfdSBengt Jonsson }, 2985624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers, 2986624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), 2987624e87c2SBengt Jonsson 29881032fbfdSBengt Jonsson }, 29891032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { 29901032fbfdSBengt Jonsson .supply_regulator = "db8500-vape", 29911032fbfdSBengt Jonsson .constraints = { 29921032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde", 29931032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 29941032fbfdSBengt Jonsson }, 29951032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers, 29961032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), 29971032fbfdSBengt Jonsson }, 29981032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = { 2999992b133aSBengt Jonsson /* 3000992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off, 3001992b133aSBengt Jonsson * no need to hold Vape 3002992b133aSBengt Jonsson */ 30031032fbfdSBengt Jonsson .constraints = { 30041032fbfdSBengt Jonsson .name = "db8500-esram12", 30051032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30061032fbfdSBengt Jonsson }, 3007624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers, 3008624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), 30091032fbfdSBengt Jonsson }, 30101032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { 30111032fbfdSBengt Jonsson .constraints = { 30121032fbfdSBengt Jonsson .name = "db8500-esram12-ret", 30131032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30141032fbfdSBengt Jonsson }, 30151032fbfdSBengt Jonsson }, 30161032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = { 3017992b133aSBengt Jonsson /* 3018992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off, 3019992b133aSBengt Jonsson * no need to hold Vape 3020992b133aSBengt Jonsson */ 30211032fbfdSBengt Jonsson .constraints = { 30221032fbfdSBengt Jonsson .name = "db8500-esram34", 30231032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30241032fbfdSBengt Jonsson }, 3025624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers, 3026624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), 30271032fbfdSBengt Jonsson }, 30281032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { 30291032fbfdSBengt Jonsson .constraints = { 30301032fbfdSBengt Jonsson .name = "db8500-esram34-ret", 30311032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS, 30321032fbfdSBengt Jonsson }, 30331032fbfdSBengt Jonsson }, 30341032fbfdSBengt Jonsson }; 30351032fbfdSBengt Jonsson 3036b3aac62bSFabio Baltieri static struct ux500_wdt_data db8500_wdt_pdata = { 3037b3aac62bSFabio Baltieri .timeout = 600, /* 10 minutes */ 3038b3aac62bSFabio Baltieri .has_28_bits_resolution = true, 3039b3aac62bSFabio Baltieri }; 3040b3aac62bSFabio Baltieri 30415ac98553SGeert Uytterhoeven static const struct mfd_cell common_prcmu_devs[] = { 3042d98a5384SLee Jones { 3043d98a5384SLee Jones .name = "ux500_wdt", 3044d98a5384SLee Jones .platform_data = &db8500_wdt_pdata, 3045d98a5384SLee Jones .pdata_size = sizeof(db8500_wdt_pdata), 3046d98a5384SLee Jones .id = -1, 3047d98a5384SLee Jones }, 3048d98a5384SLee Jones }; 3049d98a5384SLee Jones 30505ac98553SGeert Uytterhoeven static const struct mfd_cell db8500_prcmu_devs[] = { 3051a04b4be6SLee Jones OF_MFD_CELL("db8500-prcmu-regulators", NULL, 3052a04b4be6SLee Jones &db8500_regulators, sizeof(db8500_regulators), 0, 3053a04b4be6SLee Jones "stericsson,db8500-prcmu-regulator"), 3054a04b4be6SLee Jones OF_MFD_CELL("cpuidle-dbx500", 3055a04b4be6SLee Jones NULL, NULL, 0, 0, "stericsson,cpuidle-dbx500"), 3056a04b4be6SLee Jones OF_MFD_CELL("db8500-thermal", 3057a04b4be6SLee Jones NULL, NULL, 0, 0, "stericsson,db8500-thermal"), 30583df57bcfSMattias Nilsson }; 30593df57bcfSMattias Nilsson 30604e657946SArnd Bergmann static int db8500_prcmu_register_ab8500(struct device *parent) 306155b175d7SArnd Bergmann { 3062f864c46aSLinus Walleij struct device_node *np; 30631c0769d2SStephan Gerhold struct resource ab850x_resource; 30645785a97eSKrzysztof Kozlowski const struct mfd_cell ab8500_cell = { 306555b175d7SArnd Bergmann .name = "ab8500-core", 306655b175d7SArnd Bergmann .of_compatible = "stericsson,ab8500", 306755b175d7SArnd Bergmann .id = AB8500_VERSION_AB8500, 30681c0769d2SStephan Gerhold .resources = &ab850x_resource, 306955b175d7SArnd Bergmann .num_resources = 1, 307055b175d7SArnd Bergmann }; 30711c0769d2SStephan Gerhold const struct mfd_cell ab8505_cell = { 30721c0769d2SStephan Gerhold .name = "ab8505-core", 30731c0769d2SStephan Gerhold .of_compatible = "stericsson,ab8505", 30741c0769d2SStephan Gerhold .id = AB8500_VERSION_AB8505, 30751c0769d2SStephan Gerhold .resources = &ab850x_resource, 30761c0769d2SStephan Gerhold .num_resources = 1, 30771c0769d2SStephan Gerhold }; 30781c0769d2SStephan Gerhold const struct mfd_cell *ab850x_cell; 307955b175d7SArnd Bergmann 3080f864c46aSLinus Walleij if (!parent->of_node) 3081f864c46aSLinus Walleij return -ENODEV; 3082f864c46aSLinus Walleij 3083f864c46aSLinus Walleij /* Look up the device node, sneak the IRQ out of it */ 3084f864c46aSLinus Walleij for_each_child_of_node(parent->of_node, np) { 30851c0769d2SStephan Gerhold if (of_device_is_compatible(np, ab8500_cell.of_compatible)) { 30861c0769d2SStephan Gerhold ab850x_cell = &ab8500_cell; 3087f864c46aSLinus Walleij break; 3088f864c46aSLinus Walleij } 30891c0769d2SStephan Gerhold if (of_device_is_compatible(np, ab8505_cell.of_compatible)) { 30901c0769d2SStephan Gerhold ab850x_cell = &ab8505_cell; 30911c0769d2SStephan Gerhold break; 30921c0769d2SStephan Gerhold } 30931c0769d2SStephan Gerhold } 3094f864c46aSLinus Walleij if (!np) { 30951c0769d2SStephan Gerhold dev_info(parent, "could not find AB850X node in the device tree\n"); 3096f864c46aSLinus Walleij return -ENODEV; 3097f864c46aSLinus Walleij } 30981c0769d2SStephan Gerhold of_irq_to_resource_table(np, &ab850x_resource, 1); 3099f864c46aSLinus Walleij 31001c0769d2SStephan Gerhold return mfd_add_devices(parent, 0, ab850x_cell, 1, NULL, 0, NULL); 310155b175d7SArnd Bergmann } 310255b175d7SArnd Bergmann 31033df57bcfSMattias Nilsson /** 31043df57bcfSMattias Nilsson * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 31053df57bcfSMattias Nilsson * 31063df57bcfSMattias Nilsson */ 3107f791be49SBill Pemberton static int db8500_prcmu_probe(struct platform_device *pdev) 31083df57bcfSMattias Nilsson { 3109ca7edd16SLee Jones struct device_node *np = pdev->dev.of_node; 311055b175d7SArnd Bergmann int irq = 0, err = 0; 311105ec260eSLinus Walleij struct resource *res; 31123df57bcfSMattias Nilsson 3113b047d981SLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); 3114b047d981SLinus Walleij if (!res) { 3115b047d981SLinus Walleij dev_err(&pdev->dev, "no prcmu memory region provided\n"); 31166bdf891aSLee Jones return -EINVAL; 3117b047d981SLinus Walleij } 3118b047d981SLinus Walleij prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 3119b047d981SLinus Walleij if (!prcmu_base) { 3120b047d981SLinus Walleij dev_err(&pdev->dev, 3121b047d981SLinus Walleij "failed to ioremap prcmu register memory\n"); 31226bdf891aSLee Jones return -ENOMEM; 3123b047d981SLinus Walleij } 31240508901cSMattias Nilsson init_prcm_registers(); 312505ec260eSLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); 312605ec260eSLinus Walleij if (!res) { 312705ec260eSLinus Walleij dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); 31286bdf891aSLee Jones return -EINVAL; 312905ec260eSLinus Walleij } 313005ec260eSLinus Walleij tcdm_base = devm_ioremap(&pdev->dev, res->start, 313105ec260eSLinus Walleij resource_size(res)); 313251a7e02bSPramod Gurav if (!tcdm_base) { 313351a7e02bSPramod Gurav dev_err(&pdev->dev, 313451a7e02bSPramod Gurav "failed to ioremap prcmu-tcdm register memory\n"); 31356bdf891aSLee Jones return -ENOMEM; 313651a7e02bSPramod Gurav } 313705ec260eSLinus Walleij 31383df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */ 3139c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); 31403df57bcfSMattias Nilsson 3141ca7edd16SLee Jones irq = platform_get_irq(pdev, 0); 3142802d9bd4SStephen Boyd if (irq <= 0) 31436bdf891aSLee Jones return irq; 3144ca7edd16SLee Jones 3145ca7edd16SLee Jones err = request_threaded_irq(irq, prcmu_irq_handler, 31463df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); 31473df57bcfSMattias Nilsson if (err < 0) { 31483df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); 31496bdf891aSLee Jones return err; 31503df57bcfSMattias Nilsson } 31513df57bcfSMattias Nilsson 3152f864c46aSLinus Walleij db8500_irq_init(np); 31533a8e39c9SLee Jones 31543df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 31553df57bcfSMattias Nilsson 3156d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs, 3157d98a5384SLee Jones ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain); 3158ca7edd16SLee Jones if (err) { 31593df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n"); 3160ca7edd16SLee Jones return err; 3161ca7edd16SLee Jones } 3162ca7edd16SLee Jones 3163d98a5384SLee Jones /* TODO: Remove restriction when clk definitions are available. */ 3164d98a5384SLee Jones if (!of_machine_is_compatible("st-ericsson,u8540")) { 3165d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3166d98a5384SLee Jones ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, 3167d98a5384SLee Jones db8500_irq_domain); 3168d98a5384SLee Jones if (err) { 3169d98a5384SLee Jones mfd_remove_devices(&pdev->dev); 3170d98a5384SLee Jones pr_err("prcmu: Failed to add subdevices\n"); 31716bdf891aSLee Jones return err; 3172d98a5384SLee Jones } 3173d98a5384SLee Jones } 3174d98a5384SLee Jones 31754e657946SArnd Bergmann err = db8500_prcmu_register_ab8500(&pdev->dev); 317655b175d7SArnd Bergmann if (err) { 317755b175d7SArnd Bergmann mfd_remove_devices(&pdev->dev); 317855b175d7SArnd Bergmann pr_err("prcmu: Failed to add ab8500 subdevice\n"); 31796bdf891aSLee Jones return err; 318055b175d7SArnd Bergmann } 318155b175d7SArnd Bergmann 31823df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n"); 31833df57bcfSMattias Nilsson return err; 31843df57bcfSMattias Nilsson } 31853c144762SLee Jones static const struct of_device_id db8500_prcmu_match[] = { 31863c144762SLee Jones { .compatible = "stericsson,db8500-prcmu"}, 31873c144762SLee Jones { }, 31883c144762SLee Jones }; 31893df57bcfSMattias Nilsson 31903df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = { 31913df57bcfSMattias Nilsson .driver = { 31923df57bcfSMattias Nilsson .name = "db8500-prcmu", 31933c144762SLee Jones .of_match_table = db8500_prcmu_match, 31943df57bcfSMattias Nilsson }, 31959fc63f67SLee Jones .probe = db8500_prcmu_probe, 31963df57bcfSMattias Nilsson }; 31973df57bcfSMattias Nilsson 31983df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void) 31993df57bcfSMattias Nilsson { 32009fc63f67SLee Jones return platform_driver_register(&db8500_prcmu_driver); 32013df57bcfSMattias Nilsson } 3202a661aca4SLee Jones core_initcall(db8500_prcmu_init); 3203