10376148fSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2650c2a21SLinus Walleij /*
3adef9cf5SPaul Gortmaker * DB8500 PRCM Unit driver
4adef9cf5SPaul Gortmaker *
5650c2a21SLinus Walleij * Copyright (C) STMicroelectronics 2009
6650c2a21SLinus Walleij * Copyright (C) ST-Ericsson SA 2010
7650c2a21SLinus Walleij *
8650c2a21SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
9650c2a21SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com>
10650c2a21SLinus Walleij * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
11650c2a21SLinus Walleij *
12650c2a21SLinus Walleij * U8500 PRCM Unit interface driver
13650c2a21SLinus Walleij */
14adef9cf5SPaul Gortmaker #include <linux/init.h>
15adef9cf5SPaul Gortmaker #include <linux/export.h>
163df57bcfSMattias Nilsson #include <linux/kernel.h>
173df57bcfSMattias Nilsson #include <linux/delay.h>
18650c2a21SLinus Walleij #include <linux/errno.h>
19650c2a21SLinus Walleij #include <linux/err.h>
203df57bcfSMattias Nilsson #include <linux/spinlock.h>
21650c2a21SLinus Walleij #include <linux/io.h>
223df57bcfSMattias Nilsson #include <linux/slab.h>
23650c2a21SLinus Walleij #include <linux/mutex.h>
24650c2a21SLinus Walleij #include <linux/completion.h>
253df57bcfSMattias Nilsson #include <linux/irq.h>
26650c2a21SLinus Walleij #include <linux/jiffies.h>
27650c2a21SLinus Walleij #include <linux/bitops.h>
283df57bcfSMattias Nilsson #include <linux/fs.h>
29d98a5384SLee Jones #include <linux/of.h>
3022fb3ad0SLinus Walleij #include <linux/of_address.h>
31f864c46aSLinus Walleij #include <linux/of_irq.h>
323df57bcfSMattias Nilsson #include <linux/platform_device.h>
333df57bcfSMattias Nilsson #include <linux/uaccess.h>
343df57bcfSMattias Nilsson #include <linux/mfd/core.h>
3573180f85SMattias Nilsson #include <linux/mfd/dbx500-prcmu.h>
363a8e39c9SLee Jones #include <linux/mfd/abx500/ab8500.h>
371032fbfdSBengt Jonsson #include <linux/regulator/db8500-prcmu.h>
381032fbfdSBengt Jonsson #include <linux/regulator/machine.h>
398f00b3c4SLinus Walleij #include "db8500-prcmu-regs.h"
40650c2a21SLinus Walleij
413df57bcfSMattias Nilsson /* Index of different voltages to be used when accessing AVSData */
423df57bcfSMattias Nilsson #define PRCM_AVS_BASE 0x2FC
433df57bcfSMattias Nilsson #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
443df57bcfSMattias Nilsson #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
453df57bcfSMattias Nilsson #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
463df57bcfSMattias Nilsson #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
473df57bcfSMattias Nilsson #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
483df57bcfSMattias Nilsson #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
493df57bcfSMattias Nilsson #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
503df57bcfSMattias Nilsson #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
513df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
523df57bcfSMattias Nilsson #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
533df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
543df57bcfSMattias Nilsson #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
553df57bcfSMattias Nilsson #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
56650c2a21SLinus Walleij
573df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE 0
583df57bcfSMattias Nilsson #define PRCM_AVS_VOLTAGE_MASK 0x3f
593df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP 6
603df57bcfSMattias Nilsson #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
61650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE 7
62650c2a21SLinus Walleij #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
63650c2a21SLinus Walleij
643df57bcfSMattias Nilsson #define PRCM_BOOT_STATUS 0xFFF
653df57bcfSMattias Nilsson #define PRCM_ROMCODE_A2P 0xFFE
663df57bcfSMattias Nilsson #define PRCM_ROMCODE_P2A 0xFFD
673df57bcfSMattias Nilsson #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
68650c2a21SLinus Walleij
693df57bcfSMattias Nilsson #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
703df57bcfSMattias Nilsson
713df57bcfSMattias Nilsson #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
723df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
733df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
743df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
753df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
763df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
773df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
783df57bcfSMattias Nilsson #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
793df57bcfSMattias Nilsson
803df57bcfSMattias Nilsson /* Req Mailboxes */
813df57bcfSMattias Nilsson #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
823df57bcfSMattias Nilsson #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
833df57bcfSMattias Nilsson #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
843df57bcfSMattias Nilsson #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
853df57bcfSMattias Nilsson #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
863df57bcfSMattias Nilsson #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
873df57bcfSMattias Nilsson
883df57bcfSMattias Nilsson /* Ack Mailboxes */
893df57bcfSMattias Nilsson #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
903df57bcfSMattias Nilsson #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
913df57bcfSMattias Nilsson #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
923df57bcfSMattias Nilsson #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
933df57bcfSMattias Nilsson #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
943df57bcfSMattias Nilsson #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
953df57bcfSMattias Nilsson
963df57bcfSMattias Nilsson /* Mailbox 0 headers */
973df57bcfSMattias Nilsson #define MB0H_POWER_STATE_TRANS 0
983df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_EXE 1
993df57bcfSMattias Nilsson #define MB0H_READ_WAKEUP_ACK 3
1003df57bcfSMattias Nilsson #define MB0H_CONFIG_WAKEUPS_SLEEP 4
1013df57bcfSMattias Nilsson
1023df57bcfSMattias Nilsson #define MB0H_WAKEUP_EXE 2
1033df57bcfSMattias Nilsson #define MB0H_WAKEUP_SLEEP 5
1043df57bcfSMattias Nilsson
1053df57bcfSMattias Nilsson /* Mailbox 0 REQs */
1063df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
1073df57bcfSMattias Nilsson #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
1083df57bcfSMattias Nilsson #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
1093df57bcfSMattias Nilsson #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
1103df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
1113df57bcfSMattias Nilsson #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
1123df57bcfSMattias Nilsson
1133df57bcfSMattias Nilsson /* Mailbox 0 ACKs */
1143df57bcfSMattias Nilsson #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
1153df57bcfSMattias Nilsson #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
1163df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
1173df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
1183df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
1193df57bcfSMattias Nilsson #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
1203df57bcfSMattias Nilsson #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
1213df57bcfSMattias Nilsson
1223df57bcfSMattias Nilsson /* Mailbox 1 headers */
1233df57bcfSMattias Nilsson #define MB1H_ARM_APE_OPP 0x0
1243df57bcfSMattias Nilsson #define MB1H_RESET_MODEM 0x2
1253df57bcfSMattias Nilsson #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
1263df57bcfSMattias Nilsson #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
1273df57bcfSMattias Nilsson #define MB1H_RELEASE_USB_WAKEUP 0x5
128a592c2e2SMattias Nilsson #define MB1H_PLL_ON_OFF 0x6
1293df57bcfSMattias Nilsson
1303df57bcfSMattias Nilsson /* Mailbox 1 Requests */
1313df57bcfSMattias Nilsson #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
1323df57bcfSMattias Nilsson #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
133a592c2e2SMattias Nilsson #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
1346b6fae2bSMattias Nilsson #define PLL_SOC0_OFF 0x1
1356b6fae2bSMattias Nilsson #define PLL_SOC0_ON 0x2
136a592c2e2SMattias Nilsson #define PLL_SOC1_OFF 0x4
137a592c2e2SMattias Nilsson #define PLL_SOC1_ON 0x8
1383df57bcfSMattias Nilsson
1393df57bcfSMattias Nilsson /* Mailbox 1 ACKs */
1403df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
1413df57bcfSMattias Nilsson #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
1423df57bcfSMattias Nilsson #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
1433df57bcfSMattias Nilsson #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
1443df57bcfSMattias Nilsson
1453df57bcfSMattias Nilsson /* Mailbox 2 headers */
1463df57bcfSMattias Nilsson #define MB2H_DPS 0x0
1473df57bcfSMattias Nilsson #define MB2H_AUTO_PWR 0x1
1483df57bcfSMattias Nilsson
1493df57bcfSMattias Nilsson /* Mailbox 2 REQs */
1503df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
1513df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
1523df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
1533df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
1543df57bcfSMattias Nilsson #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
1553df57bcfSMattias Nilsson #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
1563df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
1573df57bcfSMattias Nilsson #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
1583df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
1593df57bcfSMattias Nilsson #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
1603df57bcfSMattias Nilsson
1613df57bcfSMattias Nilsson /* Mailbox 2 ACKs */
1623df57bcfSMattias Nilsson #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
1633df57bcfSMattias Nilsson #define HWACC_PWR_ST_OK 0xFE
1643df57bcfSMattias Nilsson
1653df57bcfSMattias Nilsson /* Mailbox 3 headers */
1663df57bcfSMattias Nilsson #define MB3H_ANC 0x0
1673df57bcfSMattias Nilsson #define MB3H_SIDETONE 0x1
1683df57bcfSMattias Nilsson #define MB3H_SYSCLK 0xE
1693df57bcfSMattias Nilsson
1703df57bcfSMattias Nilsson /* Mailbox 3 Requests */
1713df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
1723df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
1733df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
1743df57bcfSMattias Nilsson #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
1753df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
1763df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
1773df57bcfSMattias Nilsson #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
1783df57bcfSMattias Nilsson
1793df57bcfSMattias Nilsson /* Mailbox 4 headers */
1803df57bcfSMattias Nilsson #define MB4H_DDR_INIT 0x0
1813df57bcfSMattias Nilsson #define MB4H_MEM_ST 0x1
1823df57bcfSMattias Nilsson #define MB4H_HOTDOG 0x12
1833df57bcfSMattias Nilsson #define MB4H_HOTMON 0x13
1843df57bcfSMattias Nilsson #define MB4H_HOT_PERIOD 0x14
185a592c2e2SMattias Nilsson #define MB4H_A9WDOG_CONF 0x16
186a592c2e2SMattias Nilsson #define MB4H_A9WDOG_EN 0x17
187a592c2e2SMattias Nilsson #define MB4H_A9WDOG_DIS 0x18
188a592c2e2SMattias Nilsson #define MB4H_A9WDOG_LOAD 0x19
189a592c2e2SMattias Nilsson #define MB4H_A9WDOG_KICK 0x20
1903df57bcfSMattias Nilsson
1913df57bcfSMattias Nilsson /* Mailbox 4 Requests */
1923df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
1933df57bcfSMattias Nilsson #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
1943df57bcfSMattias Nilsson #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
1953df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
1963df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
1973df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
1983df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
1993df57bcfSMattias Nilsson #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
2003df57bcfSMattias Nilsson #define HOTMON_CONFIG_LOW BIT(0)
2013df57bcfSMattias Nilsson #define HOTMON_CONFIG_HIGH BIT(1)
202a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
203a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
204a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
205a592c2e2SMattias Nilsson #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
206a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_EN BIT(7)
207a592c2e2SMattias Nilsson #define A9WDOG_AUTO_OFF_DIS 0
208a592c2e2SMattias Nilsson #define A9WDOG_ID_MASK 0xf
2093df57bcfSMattias Nilsson
2103df57bcfSMattias Nilsson /* Mailbox 5 Requests */
2113df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
2123df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
2133df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
2143df57bcfSMattias Nilsson #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
2157a4f2609SLinus Walleij #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
2167a4f2609SLinus Walleij #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
2173df57bcfSMattias Nilsson #define PRCMU_I2C_STOP_EN BIT(3)
2183df57bcfSMattias Nilsson
2193df57bcfSMattias Nilsson /* Mailbox 5 ACKs */
2203df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
2213df57bcfSMattias Nilsson #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
2223df57bcfSMattias Nilsson #define I2C_WR_OK 0x1
2233df57bcfSMattias Nilsson #define I2C_RD_OK 0x2
2243df57bcfSMattias Nilsson
2253df57bcfSMattias Nilsson #define NUM_MB 8
2263df57bcfSMattias Nilsson #define MBOX_BIT BIT
2273df57bcfSMattias Nilsson #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
2283df57bcfSMattias Nilsson
2293df57bcfSMattias Nilsson /*
2303df57bcfSMattias Nilsson * Wakeups/IRQs
2313df57bcfSMattias Nilsson */
2323df57bcfSMattias Nilsson
2333df57bcfSMattias Nilsson #define WAKEUP_BIT_RTC BIT(0)
2343df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT0 BIT(1)
2353df57bcfSMattias Nilsson #define WAKEUP_BIT_RTT1 BIT(2)
2363df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI0 BIT(3)
2373df57bcfSMattias Nilsson #define WAKEUP_BIT_HSI1 BIT(4)
2383df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_WAKE BIT(5)
2393df57bcfSMattias Nilsson #define WAKEUP_BIT_USB BIT(6)
2403df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB BIT(7)
2413df57bcfSMattias Nilsson #define WAKEUP_BIT_ABB_FIFO BIT(8)
2423df57bcfSMattias Nilsson #define WAKEUP_BIT_SYSCLK_OK BIT(9)
2433df57bcfSMattias Nilsson #define WAKEUP_BIT_CA_SLEEP BIT(10)
2443df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
2453df57bcfSMattias Nilsson #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
2463df57bcfSMattias Nilsson #define WAKEUP_BIT_ANC_OK BIT(13)
2473df57bcfSMattias Nilsson #define WAKEUP_BIT_SW_ERROR BIT(14)
2483df57bcfSMattias Nilsson #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
2493df57bcfSMattias Nilsson #define WAKEUP_BIT_ARM BIT(17)
2503df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_LOW BIT(18)
2513df57bcfSMattias Nilsson #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
2523df57bcfSMattias Nilsson #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
2533df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO0 BIT(23)
2543df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO1 BIT(24)
2553df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO2 BIT(25)
2563df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO3 BIT(26)
2573df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO4 BIT(27)
2583df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO5 BIT(28)
2593df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO6 BIT(29)
2603df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO7 BIT(30)
2613df57bcfSMattias Nilsson #define WAKEUP_BIT_GPIO8 BIT(31)
2623df57bcfSMattias Nilsson
263b58d12feSMattias Nilsson static struct {
264b58d12feSMattias Nilsson bool valid;
265b58d12feSMattias Nilsson struct prcmu_fw_version version;
266b58d12feSMattias Nilsson } fw_info;
267b58d12feSMattias Nilsson
268f3f1f0a1SLee Jones static struct irq_domain *db8500_irq_domain;
269f3f1f0a1SLee Jones
2703df57bcfSMattias Nilsson /*
2713df57bcfSMattias Nilsson * This vector maps irq numbers to the bits in the bit field used in
2723df57bcfSMattias Nilsson * communication with the PRCMU firmware.
2733df57bcfSMattias Nilsson *
2743df57bcfSMattias Nilsson * The reason for having this is to keep the irq numbers contiguous even though
2753df57bcfSMattias Nilsson * the bits in the bit field are not. (The bits also have a tendency to move
2763df57bcfSMattias Nilsson * around, to further complicate matters.)
2773df57bcfSMattias Nilsson */
27855b175d7SArnd Bergmann #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
2793df57bcfSMattias Nilsson #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
28055b175d7SArnd Bergmann
28155b175d7SArnd Bergmann #define IRQ_PRCMU_RTC 0
28255b175d7SArnd Bergmann #define IRQ_PRCMU_RTT0 1
28355b175d7SArnd Bergmann #define IRQ_PRCMU_RTT1 2
28455b175d7SArnd Bergmann #define IRQ_PRCMU_HSI0 3
28555b175d7SArnd Bergmann #define IRQ_PRCMU_HSI1 4
28655b175d7SArnd Bergmann #define IRQ_PRCMU_CA_WAKE 5
28755b175d7SArnd Bergmann #define IRQ_PRCMU_USB 6
28855b175d7SArnd Bergmann #define IRQ_PRCMU_ABB 7
28955b175d7SArnd Bergmann #define IRQ_PRCMU_ABB_FIFO 8
29055b175d7SArnd Bergmann #define IRQ_PRCMU_ARM 9
29155b175d7SArnd Bergmann #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
29255b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO0 11
29355b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO1 12
29455b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO2 13
29555b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO3 14
29655b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO4 15
29755b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO5 16
29855b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO6 17
29955b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO7 18
30055b175d7SArnd Bergmann #define IRQ_PRCMU_GPIO8 19
30155b175d7SArnd Bergmann #define IRQ_PRCMU_CA_SLEEP 20
30255b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_LOW 21
30355b175d7SArnd Bergmann #define IRQ_PRCMU_HOTMON_HIGH 22
30455b175d7SArnd Bergmann #define NUM_PRCMU_WAKEUPS 23
30555b175d7SArnd Bergmann
3063df57bcfSMattias Nilsson static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
3073df57bcfSMattias Nilsson IRQ_ENTRY(RTC),
3083df57bcfSMattias Nilsson IRQ_ENTRY(RTT0),
3093df57bcfSMattias Nilsson IRQ_ENTRY(RTT1),
3103df57bcfSMattias Nilsson IRQ_ENTRY(HSI0),
3113df57bcfSMattias Nilsson IRQ_ENTRY(HSI1),
3123df57bcfSMattias Nilsson IRQ_ENTRY(CA_WAKE),
3133df57bcfSMattias Nilsson IRQ_ENTRY(USB),
3143df57bcfSMattias Nilsson IRQ_ENTRY(ABB),
3153df57bcfSMattias Nilsson IRQ_ENTRY(ABB_FIFO),
3163df57bcfSMattias Nilsson IRQ_ENTRY(CA_SLEEP),
3173df57bcfSMattias Nilsson IRQ_ENTRY(ARM),
3183df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_LOW),
3193df57bcfSMattias Nilsson IRQ_ENTRY(HOTMON_HIGH),
3203df57bcfSMattias Nilsson IRQ_ENTRY(MODEM_SW_RESET_REQ),
3213df57bcfSMattias Nilsson IRQ_ENTRY(GPIO0),
3223df57bcfSMattias Nilsson IRQ_ENTRY(GPIO1),
3233df57bcfSMattias Nilsson IRQ_ENTRY(GPIO2),
3243df57bcfSMattias Nilsson IRQ_ENTRY(GPIO3),
3253df57bcfSMattias Nilsson IRQ_ENTRY(GPIO4),
3263df57bcfSMattias Nilsson IRQ_ENTRY(GPIO5),
3273df57bcfSMattias Nilsson IRQ_ENTRY(GPIO6),
3283df57bcfSMattias Nilsson IRQ_ENTRY(GPIO7),
3293df57bcfSMattias Nilsson IRQ_ENTRY(GPIO8)
330650c2a21SLinus Walleij };
331650c2a21SLinus Walleij
3323df57bcfSMattias Nilsson #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
3333df57bcfSMattias Nilsson #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
3343df57bcfSMattias Nilsson static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
3353df57bcfSMattias Nilsson WAKEUP_ENTRY(RTC),
3363df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT0),
3373df57bcfSMattias Nilsson WAKEUP_ENTRY(RTT1),
3383df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI0),
3393df57bcfSMattias Nilsson WAKEUP_ENTRY(HSI1),
3403df57bcfSMattias Nilsson WAKEUP_ENTRY(USB),
3413df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB),
3423df57bcfSMattias Nilsson WAKEUP_ENTRY(ABB_FIFO),
3433df57bcfSMattias Nilsson WAKEUP_ENTRY(ARM)
3443df57bcfSMattias Nilsson };
3453df57bcfSMattias Nilsson
3463df57bcfSMattias Nilsson /*
3473df57bcfSMattias Nilsson * mb0_transfer - state needed for mailbox 0 communication.
3483df57bcfSMattias Nilsson * @lock: The transaction lock.
3493df57bcfSMattias Nilsson * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
3503df57bcfSMattias Nilsson * the request data.
3513df57bcfSMattias Nilsson * @mask_work: Work structure used for (un)masking wakeup interrupts.
3523df57bcfSMattias Nilsson * @req: Request data that need to persist between requests.
3533df57bcfSMattias Nilsson */
3543df57bcfSMattias Nilsson static struct {
3553df57bcfSMattias Nilsson spinlock_t lock;
3563df57bcfSMattias Nilsson spinlock_t dbb_irqs_lock;
3573df57bcfSMattias Nilsson struct work_struct mask_work;
3583df57bcfSMattias Nilsson struct mutex ac_wake_lock;
3593df57bcfSMattias Nilsson struct completion ac_wake_work;
3603df57bcfSMattias Nilsson struct {
3613df57bcfSMattias Nilsson u32 dbb_irqs;
3623df57bcfSMattias Nilsson u32 dbb_wakeups;
3633df57bcfSMattias Nilsson u32 abb_events;
3643df57bcfSMattias Nilsson } req;
3653df57bcfSMattias Nilsson } mb0_transfer;
3663df57bcfSMattias Nilsson
3673df57bcfSMattias Nilsson /*
3683df57bcfSMattias Nilsson * mb1_transfer - state needed for mailbox 1 communication.
3693df57bcfSMattias Nilsson * @lock: The transaction lock.
3703df57bcfSMattias Nilsson * @work: The transaction completion structure.
3714d64d2e3SMattias Nilsson * @ape_opp: The current APE OPP.
3723df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data.
3733df57bcfSMattias Nilsson */
374650c2a21SLinus Walleij static struct {
375650c2a21SLinus Walleij struct mutex lock;
376650c2a21SLinus Walleij struct completion work;
3774d64d2e3SMattias Nilsson u8 ape_opp;
378650c2a21SLinus Walleij struct {
3793df57bcfSMattias Nilsson u8 header;
380650c2a21SLinus Walleij u8 arm_opp;
381650c2a21SLinus Walleij u8 ape_opp;
3823df57bcfSMattias Nilsson u8 ape_voltage_status;
383650c2a21SLinus Walleij } ack;
384650c2a21SLinus Walleij } mb1_transfer;
385650c2a21SLinus Walleij
3863df57bcfSMattias Nilsson /*
3873df57bcfSMattias Nilsson * mb2_transfer - state needed for mailbox 2 communication.
3883df57bcfSMattias Nilsson * @lock: The transaction lock.
3893df57bcfSMattias Nilsson * @work: The transaction completion structure.
3903df57bcfSMattias Nilsson * @auto_pm_lock: The autonomous power management configuration lock.
3913df57bcfSMattias Nilsson * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
3923df57bcfSMattias Nilsson * @req: Request data that need to persist between requests.
3933df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data.
3943df57bcfSMattias Nilsson */
395650c2a21SLinus Walleij static struct {
396650c2a21SLinus Walleij struct mutex lock;
397650c2a21SLinus Walleij struct completion work;
3983df57bcfSMattias Nilsson spinlock_t auto_pm_lock;
3993df57bcfSMattias Nilsson bool auto_pm_enabled;
4003df57bcfSMattias Nilsson struct {
4013df57bcfSMattias Nilsson u8 status;
4023df57bcfSMattias Nilsson } ack;
4033df57bcfSMattias Nilsson } mb2_transfer;
4043df57bcfSMattias Nilsson
4053df57bcfSMattias Nilsson /*
4063df57bcfSMattias Nilsson * mb3_transfer - state needed for mailbox 3 communication.
4073df57bcfSMattias Nilsson * @lock: The request lock.
4083df57bcfSMattias Nilsson * @sysclk_lock: A lock used to handle concurrent sysclk requests.
4093df57bcfSMattias Nilsson * @sysclk_work: Work structure used for sysclk requests.
4103df57bcfSMattias Nilsson */
4113df57bcfSMattias Nilsson static struct {
4123df57bcfSMattias Nilsson spinlock_t lock;
4133df57bcfSMattias Nilsson struct mutex sysclk_lock;
4143df57bcfSMattias Nilsson struct completion sysclk_work;
4153df57bcfSMattias Nilsson } mb3_transfer;
4163df57bcfSMattias Nilsson
4173df57bcfSMattias Nilsson /*
4183df57bcfSMattias Nilsson * mb4_transfer - state needed for mailbox 4 communication.
4193df57bcfSMattias Nilsson * @lock: The transaction lock.
4203df57bcfSMattias Nilsson * @work: The transaction completion structure.
4213df57bcfSMattias Nilsson */
4223df57bcfSMattias Nilsson static struct {
4233df57bcfSMattias Nilsson struct mutex lock;
4243df57bcfSMattias Nilsson struct completion work;
4253df57bcfSMattias Nilsson } mb4_transfer;
4263df57bcfSMattias Nilsson
4273df57bcfSMattias Nilsson /*
4283df57bcfSMattias Nilsson * mb5_transfer - state needed for mailbox 5 communication.
4293df57bcfSMattias Nilsson * @lock: The transaction lock.
4303df57bcfSMattias Nilsson * @work: The transaction completion structure.
4313df57bcfSMattias Nilsson * @ack: Reply ("acknowledge") data.
4323df57bcfSMattias Nilsson */
4333df57bcfSMattias Nilsson static struct {
4343df57bcfSMattias Nilsson struct mutex lock;
4353df57bcfSMattias Nilsson struct completion work;
436650c2a21SLinus Walleij struct {
437650c2a21SLinus Walleij u8 status;
438650c2a21SLinus Walleij u8 value;
439650c2a21SLinus Walleij } ack;
440650c2a21SLinus Walleij } mb5_transfer;
441650c2a21SLinus Walleij
4423df57bcfSMattias Nilsson static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
4433df57bcfSMattias Nilsson
4443df57bcfSMattias Nilsson /* Spinlocks */
445b4a6dbd5SMattias Nilsson static DEFINE_SPINLOCK(prcmu_lock);
4463df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clkout_lock);
4473df57bcfSMattias Nilsson
4483df57bcfSMattias Nilsson /* Global var to runtime determine TCDM base for v2 or v1 */
4493df57bcfSMattias Nilsson static __iomem void *tcdm_base;
450b047d981SLinus Walleij static __iomem void *prcmu_base;
4513df57bcfSMattias Nilsson
4523df57bcfSMattias Nilsson struct clk_mgt {
453b047d981SLinus Walleij u32 offset;
4543df57bcfSMattias Nilsson u32 pllsw;
4556b6fae2bSMattias Nilsson int branch;
4566b6fae2bSMattias Nilsson bool clk38div;
4576b6fae2bSMattias Nilsson };
4586b6fae2bSMattias Nilsson
4596b6fae2bSMattias Nilsson enum {
4606b6fae2bSMattias Nilsson PLL_RAW,
4616b6fae2bSMattias Nilsson PLL_FIX,
4626b6fae2bSMattias Nilsson PLL_DIV
4633df57bcfSMattias Nilsson };
4643df57bcfSMattias Nilsson
4653df57bcfSMattias Nilsson static DEFINE_SPINLOCK(clk_mgt_lock);
4663df57bcfSMattias Nilsson
4676b6fae2bSMattias Nilsson #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
4686b6fae2bSMattias Nilsson { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
4696746f232SSachin Kamat static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
4706b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
4716b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
4726b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
4736b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
4746b6fae2bSMattias Nilsson CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
4756b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
4766b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
4776b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
4786b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
4796b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
4806b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
4816b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
4826b6fae2bSMattias Nilsson CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
4836b6fae2bSMattias Nilsson CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
4846b6fae2bSMattias Nilsson CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
4856b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
4866b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
4876b6fae2bSMattias Nilsson CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
4886b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
4896b6fae2bSMattias Nilsson CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
4906b6fae2bSMattias Nilsson CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
4916b6fae2bSMattias Nilsson CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
4926b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
4936b6fae2bSMattias Nilsson CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
4946b6fae2bSMattias Nilsson CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
4956b6fae2bSMattias Nilsson CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
4966b6fae2bSMattias Nilsson CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
4976b6fae2bSMattias Nilsson CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
4986b6fae2bSMattias Nilsson CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
4996b6fae2bSMattias Nilsson };
5006b6fae2bSMattias Nilsson
5016b6fae2bSMattias Nilsson struct dsiclk {
5026b6fae2bSMattias Nilsson u32 divsel_mask;
5036b6fae2bSMattias Nilsson u32 divsel_shift;
5046b6fae2bSMattias Nilsson u32 divsel;
5056b6fae2bSMattias Nilsson };
5066b6fae2bSMattias Nilsson
5076b6fae2bSMattias Nilsson static struct dsiclk dsiclk[2] = {
5086b6fae2bSMattias Nilsson {
5096b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
5106b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
5116b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
5126b6fae2bSMattias Nilsson },
5136b6fae2bSMattias Nilsson {
5146b6fae2bSMattias Nilsson .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
5156b6fae2bSMattias Nilsson .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
5166b6fae2bSMattias Nilsson .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
5176b6fae2bSMattias Nilsson }
5186b6fae2bSMattias Nilsson };
5196b6fae2bSMattias Nilsson
5206b6fae2bSMattias Nilsson struct dsiescclk {
5216b6fae2bSMattias Nilsson u32 en;
5226b6fae2bSMattias Nilsson u32 div_mask;
5236b6fae2bSMattias Nilsson u32 div_shift;
5246b6fae2bSMattias Nilsson };
5256b6fae2bSMattias Nilsson
5266b6fae2bSMattias Nilsson static struct dsiescclk dsiescclk[3] = {
5276b6fae2bSMattias Nilsson {
5286b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
5296b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
5306b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
5316b6fae2bSMattias Nilsson },
5326b6fae2bSMattias Nilsson {
5336b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
5346b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
5356b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
5366b6fae2bSMattias Nilsson },
5376b6fae2bSMattias Nilsson {
5386b6fae2bSMattias Nilsson .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
5396b6fae2bSMattias Nilsson .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
5406b6fae2bSMattias Nilsson .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
5416b6fae2bSMattias Nilsson }
5423df57bcfSMattias Nilsson };
5433df57bcfSMattias Nilsson
db8500_prcmu_read(unsigned int reg)544b4a6dbd5SMattias Nilsson u32 db8500_prcmu_read(unsigned int reg)
5453df57bcfSMattias Nilsson {
546b047d981SLinus Walleij return readl(prcmu_base + reg);
5473df57bcfSMattias Nilsson }
5483df57bcfSMattias Nilsson
db8500_prcmu_write(unsigned int reg,u32 value)549b4a6dbd5SMattias Nilsson void db8500_prcmu_write(unsigned int reg, u32 value)
5503df57bcfSMattias Nilsson {
5513df57bcfSMattias Nilsson unsigned long flags;
5523df57bcfSMattias Nilsson
553b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags);
554b047d981SLinus Walleij writel(value, (prcmu_base + reg));
555b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags);
556b4a6dbd5SMattias Nilsson }
557b4a6dbd5SMattias Nilsson
db8500_prcmu_write_masked(unsigned int reg,u32 mask,u32 value)558b4a6dbd5SMattias Nilsson void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
559b4a6dbd5SMattias Nilsson {
560b4a6dbd5SMattias Nilsson u32 val;
561b4a6dbd5SMattias Nilsson unsigned long flags;
562b4a6dbd5SMattias Nilsson
563b4a6dbd5SMattias Nilsson spin_lock_irqsave(&prcmu_lock, flags);
564b047d981SLinus Walleij val = readl(prcmu_base + reg);
565b4a6dbd5SMattias Nilsson val = ((val & ~mask) | (value & mask));
566b047d981SLinus Walleij writel(val, (prcmu_base + reg));
567b4a6dbd5SMattias Nilsson spin_unlock_irqrestore(&prcmu_lock, flags);
5683df57bcfSMattias Nilsson }
5693df57bcfSMattias Nilsson
prcmu_get_fw_version(void)570b58d12feSMattias Nilsson struct prcmu_fw_version *prcmu_get_fw_version(void)
571b58d12feSMattias Nilsson {
572b58d12feSMattias Nilsson return fw_info.valid ? &fw_info.version : NULL;
573b58d12feSMattias Nilsson }
574b58d12feSMattias Nilsson
prcmu_is_ulppll_disabled(void)57522fb3ad0SLinus Walleij static bool prcmu_is_ulppll_disabled(void)
57622fb3ad0SLinus Walleij {
57722fb3ad0SLinus Walleij struct prcmu_fw_version *ver;
57822fb3ad0SLinus Walleij
57922fb3ad0SLinus Walleij ver = prcmu_get_fw_version();
58022fb3ad0SLinus Walleij return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK;
58122fb3ad0SLinus Walleij }
58222fb3ad0SLinus Walleij
prcmu_has_arm_maxopp(void)5833df57bcfSMattias Nilsson bool prcmu_has_arm_maxopp(void)
5843df57bcfSMattias Nilsson {
5853df57bcfSMattias Nilsson return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
5863df57bcfSMattias Nilsson PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
5873df57bcfSMattias Nilsson }
5883df57bcfSMattias Nilsson
5893df57bcfSMattias Nilsson /**
5903df57bcfSMattias Nilsson * prcmu_set_rc_a2p - This function is used to run few power state sequences
5913df57bcfSMattias Nilsson * @val: Value to be set, i.e. transition requested
5923df57bcfSMattias Nilsson * Returns: 0 on success, -EINVAL on invalid argument
5933df57bcfSMattias Nilsson *
5943df57bcfSMattias Nilsson * This function is used to run the following power state sequences -
5953df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
5963df57bcfSMattias Nilsson */
prcmu_set_rc_a2p(enum romcode_write val)5973df57bcfSMattias Nilsson int prcmu_set_rc_a2p(enum romcode_write val)
5983df57bcfSMattias Nilsson {
5993df57bcfSMattias Nilsson if (val < RDY_2_DS || val > RDY_2_XP70_RST)
6003df57bcfSMattias Nilsson return -EINVAL;
6013df57bcfSMattias Nilsson writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
6023df57bcfSMattias Nilsson return 0;
6033df57bcfSMattias Nilsson }
6043df57bcfSMattias Nilsson
6053df57bcfSMattias Nilsson /**
6063df57bcfSMattias Nilsson * prcmu_get_rc_p2a - This function is used to get power state sequences
6073df57bcfSMattias Nilsson * Returns: the power transition that has last happened
6083df57bcfSMattias Nilsson *
6093df57bcfSMattias Nilsson * This function can return the following transitions-
6103df57bcfSMattias Nilsson * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
6113df57bcfSMattias Nilsson */
prcmu_get_rc_p2a(void)6123df57bcfSMattias Nilsson enum romcode_read prcmu_get_rc_p2a(void)
6133df57bcfSMattias Nilsson {
6143df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ROMCODE_P2A);
6153df57bcfSMattias Nilsson }
6163df57bcfSMattias Nilsson
6173df57bcfSMattias Nilsson /**
618e00a953bSLee Jones * prcmu_get_xp70_current_state - Return the current XP70 power mode
6193df57bcfSMattias Nilsson * Returns: Returns the current AP(ARM) power mode: init,
6203df57bcfSMattias Nilsson * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
6213df57bcfSMattias Nilsson */
prcmu_get_xp70_current_state(void)6223df57bcfSMattias Nilsson enum ap_pwrst prcmu_get_xp70_current_state(void)
6233df57bcfSMattias Nilsson {
6243df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
6253df57bcfSMattias Nilsson }
6263df57bcfSMattias Nilsson
6273df57bcfSMattias Nilsson /**
6283df57bcfSMattias Nilsson * prcmu_config_clkout - Configure one of the programmable clock outputs.
6293df57bcfSMattias Nilsson * @clkout: The CLKOUT number (0 or 1).
6303df57bcfSMattias Nilsson * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
6313df57bcfSMattias Nilsson * @div: The divider to be applied.
6323df57bcfSMattias Nilsson *
6333df57bcfSMattias Nilsson * Configures one of the programmable clock outputs (CLKOUTs).
6343df57bcfSMattias Nilsson * @div should be in the range [1,63] to request a configuration, or 0 to
6353df57bcfSMattias Nilsson * inform that the configuration is no longer requested.
6363df57bcfSMattias Nilsson */
prcmu_config_clkout(u8 clkout,u8 source,u8 div)6373df57bcfSMattias Nilsson int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
6383df57bcfSMattias Nilsson {
6393df57bcfSMattias Nilsson static int requests[2];
6403df57bcfSMattias Nilsson int r = 0;
6413df57bcfSMattias Nilsson unsigned long flags;
6423df57bcfSMattias Nilsson u32 val;
6433df57bcfSMattias Nilsson u32 bits;
6443df57bcfSMattias Nilsson u32 mask;
6453df57bcfSMattias Nilsson u32 div_mask;
6463df57bcfSMattias Nilsson
6473df57bcfSMattias Nilsson BUG_ON(clkout > 1);
6483df57bcfSMattias Nilsson BUG_ON(div > 63);
6493df57bcfSMattias Nilsson BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
6503df57bcfSMattias Nilsson
6513df57bcfSMattias Nilsson if (!div && !requests[clkout])
6523df57bcfSMattias Nilsson return -EINVAL;
6533df57bcfSMattias Nilsson
654a7e46317SArnd Bergmann if (clkout == 0) {
6553df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
6563df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
6573df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
6583df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
659a7e46317SArnd Bergmann } else {
6603df57bcfSMattias Nilsson div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
6613df57bcfSMattias Nilsson mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
6623df57bcfSMattias Nilsson PRCM_CLKOCR_CLK1TYPE);
6633df57bcfSMattias Nilsson bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
6643df57bcfSMattias Nilsson (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
6653df57bcfSMattias Nilsson }
6663df57bcfSMattias Nilsson bits &= mask;
6673df57bcfSMattias Nilsson
6683df57bcfSMattias Nilsson spin_lock_irqsave(&clkout_lock, flags);
6693df57bcfSMattias Nilsson
670c553b3caSMattias Nilsson val = readl(PRCM_CLKOCR);
6713df57bcfSMattias Nilsson if (val & div_mask) {
6723df57bcfSMattias Nilsson if (div) {
6733df57bcfSMattias Nilsson if ((val & mask) != bits) {
6743df57bcfSMattias Nilsson r = -EBUSY;
6753df57bcfSMattias Nilsson goto unlock_and_return;
6763df57bcfSMattias Nilsson }
6773df57bcfSMattias Nilsson } else {
6783df57bcfSMattias Nilsson if ((val & mask & ~div_mask) != bits) {
6793df57bcfSMattias Nilsson r = -EINVAL;
6803df57bcfSMattias Nilsson goto unlock_and_return;
6813df57bcfSMattias Nilsson }
6823df57bcfSMattias Nilsson }
6833df57bcfSMattias Nilsson }
684c553b3caSMattias Nilsson writel((bits | (val & ~mask)), PRCM_CLKOCR);
6853df57bcfSMattias Nilsson requests[clkout] += (div ? 1 : -1);
6863df57bcfSMattias Nilsson
6873df57bcfSMattias Nilsson unlock_and_return:
6883df57bcfSMattias Nilsson spin_unlock_irqrestore(&clkout_lock, flags);
6893df57bcfSMattias Nilsson
6903df57bcfSMattias Nilsson return r;
6913df57bcfSMattias Nilsson }
6923df57bcfSMattias Nilsson
db8500_prcmu_set_power_state(u8 state,bool keep_ulp_clk,bool keep_ap_pll)69373180f85SMattias Nilsson int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
6943df57bcfSMattias Nilsson {
6953df57bcfSMattias Nilsson unsigned long flags;
6963df57bcfSMattias Nilsson
6973df57bcfSMattias Nilsson BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
6983df57bcfSMattias Nilsson
6993df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags);
7003df57bcfSMattias Nilsson
701c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
7023df57bcfSMattias Nilsson cpu_relax();
7033df57bcfSMattias Nilsson
7043df57bcfSMattias Nilsson writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
7053df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
7063df57bcfSMattias Nilsson writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
7073df57bcfSMattias Nilsson writeb((keep_ulp_clk ? 1 : 0),
7083df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
7093df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
710c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
7113df57bcfSMattias Nilsson
7123df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags);
7133df57bcfSMattias Nilsson
7143df57bcfSMattias Nilsson return 0;
7153df57bcfSMattias Nilsson }
7163df57bcfSMattias Nilsson
db8500_prcmu_get_power_state_result(void)7174d64d2e3SMattias Nilsson u8 db8500_prcmu_get_power_state_result(void)
7184d64d2e3SMattias Nilsson {
7194d64d2e3SMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
7204d64d2e3SMattias Nilsson }
7214d64d2e3SMattias Nilsson
7223df57bcfSMattias Nilsson /* This function should only be called while mb0_transfer.lock is held. */
config_wakeups(void)7233df57bcfSMattias Nilsson static void config_wakeups(void)
7243df57bcfSMattias Nilsson {
7253df57bcfSMattias Nilsson const u8 header[2] = {
7263df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_EXE,
7273df57bcfSMattias Nilsson MB0H_CONFIG_WAKEUPS_SLEEP
7283df57bcfSMattias Nilsson };
7293df57bcfSMattias Nilsson static u32 last_dbb_events;
7303df57bcfSMattias Nilsson static u32 last_abb_events;
7313df57bcfSMattias Nilsson u32 dbb_events;
7323df57bcfSMattias Nilsson u32 abb_events;
7333df57bcfSMattias Nilsson unsigned int i;
7343df57bcfSMattias Nilsson
7353df57bcfSMattias Nilsson dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
7363df57bcfSMattias Nilsson dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
7373df57bcfSMattias Nilsson
7383df57bcfSMattias Nilsson abb_events = mb0_transfer.req.abb_events;
7393df57bcfSMattias Nilsson
7403df57bcfSMattias Nilsson if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
7413df57bcfSMattias Nilsson return;
7423df57bcfSMattias Nilsson
7433df57bcfSMattias Nilsson for (i = 0; i < 2; i++) {
744c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
7453df57bcfSMattias Nilsson cpu_relax();
7463df57bcfSMattias Nilsson writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
7473df57bcfSMattias Nilsson writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
7483df57bcfSMattias Nilsson writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
749c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
7503df57bcfSMattias Nilsson }
7513df57bcfSMattias Nilsson last_dbb_events = dbb_events;
7523df57bcfSMattias Nilsson last_abb_events = abb_events;
7533df57bcfSMattias Nilsson }
7543df57bcfSMattias Nilsson
db8500_prcmu_enable_wakeups(u32 wakeups)75573180f85SMattias Nilsson void db8500_prcmu_enable_wakeups(u32 wakeups)
7563df57bcfSMattias Nilsson {
7573df57bcfSMattias Nilsson unsigned long flags;
7583df57bcfSMattias Nilsson u32 bits;
7593df57bcfSMattias Nilsson int i;
7603df57bcfSMattias Nilsson
7613df57bcfSMattias Nilsson BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
7623df57bcfSMattias Nilsson
7633df57bcfSMattias Nilsson for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
7643df57bcfSMattias Nilsson if (wakeups & BIT(i))
7653df57bcfSMattias Nilsson bits |= prcmu_wakeup_bit[i];
7663df57bcfSMattias Nilsson }
7673df57bcfSMattias Nilsson
7683df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags);
7693df57bcfSMattias Nilsson
7703df57bcfSMattias Nilsson mb0_transfer.req.dbb_wakeups = bits;
7713df57bcfSMattias Nilsson config_wakeups();
7723df57bcfSMattias Nilsson
7733df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags);
7743df57bcfSMattias Nilsson }
7753df57bcfSMattias Nilsson
db8500_prcmu_config_abb_event_readout(u32 abb_events)77673180f85SMattias Nilsson void db8500_prcmu_config_abb_event_readout(u32 abb_events)
7773df57bcfSMattias Nilsson {
7783df57bcfSMattias Nilsson unsigned long flags;
7793df57bcfSMattias Nilsson
7803df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags);
7813df57bcfSMattias Nilsson
7823df57bcfSMattias Nilsson mb0_transfer.req.abb_events = abb_events;
7833df57bcfSMattias Nilsson config_wakeups();
7843df57bcfSMattias Nilsson
7853df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags);
7863df57bcfSMattias Nilsson }
7873df57bcfSMattias Nilsson
db8500_prcmu_get_abb_event_buffer(void __iomem ** buf)78873180f85SMattias Nilsson void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
7893df57bcfSMattias Nilsson {
7903df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
7913df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
7923df57bcfSMattias Nilsson else
7933df57bcfSMattias Nilsson *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
7943df57bcfSMattias Nilsson }
7953df57bcfSMattias Nilsson
7963df57bcfSMattias Nilsson /**
79773180f85SMattias Nilsson * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
7983df57bcfSMattias Nilsson * @opp: The new ARM operating point to which transition is to be made
7993df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure
8003df57bcfSMattias Nilsson *
801*15ff0bbcSJiang Jian * This function sets the operating point of the ARM.
8023df57bcfSMattias Nilsson */
db8500_prcmu_set_arm_opp(u8 opp)80373180f85SMattias Nilsson int db8500_prcmu_set_arm_opp(u8 opp)
8043df57bcfSMattias Nilsson {
8053df57bcfSMattias Nilsson int r;
8063df57bcfSMattias Nilsson
8073df57bcfSMattias Nilsson if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
8083df57bcfSMattias Nilsson return -EINVAL;
8093df57bcfSMattias Nilsson
8103df57bcfSMattias Nilsson r = 0;
8113df57bcfSMattias Nilsson
8123df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock);
8133df57bcfSMattias Nilsson
814c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
8153df57bcfSMattias Nilsson cpu_relax();
8163df57bcfSMattias Nilsson
8173df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
8183df57bcfSMattias Nilsson writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
8193df57bcfSMattias Nilsson writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
8203df57bcfSMattias Nilsson
821c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
8223df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work);
8233df57bcfSMattias Nilsson
8243df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
8253df57bcfSMattias Nilsson (mb1_transfer.ack.arm_opp != opp))
8263df57bcfSMattias Nilsson r = -EIO;
8273df57bcfSMattias Nilsson
8283df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock);
8293df57bcfSMattias Nilsson
8303df57bcfSMattias Nilsson return r;
8313df57bcfSMattias Nilsson }
8323df57bcfSMattias Nilsson
8333df57bcfSMattias Nilsson /**
83473180f85SMattias Nilsson * db8500_prcmu_get_arm_opp - get the current ARM OPP
8353df57bcfSMattias Nilsson *
8363df57bcfSMattias Nilsson * Returns: the current ARM OPP
8373df57bcfSMattias Nilsson */
db8500_prcmu_get_arm_opp(void)83873180f85SMattias Nilsson int db8500_prcmu_get_arm_opp(void)
8393df57bcfSMattias Nilsson {
8403df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
8413df57bcfSMattias Nilsson }
8423df57bcfSMattias Nilsson
8433df57bcfSMattias Nilsson /**
8440508901cSMattias Nilsson * db8500_prcmu_get_ddr_opp - get the current DDR OPP
8453df57bcfSMattias Nilsson *
8463df57bcfSMattias Nilsson * Returns: the current DDR OPP
8473df57bcfSMattias Nilsson */
db8500_prcmu_get_ddr_opp(void)8480508901cSMattias Nilsson int db8500_prcmu_get_ddr_opp(void)
8493df57bcfSMattias Nilsson {
850c553b3caSMattias Nilsson return readb(PRCM_DDR_SUBSYS_APE_MINBW);
8513df57bcfSMattias Nilsson }
8523df57bcfSMattias Nilsson
8534d64d2e3SMattias Nilsson /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
request_even_slower_clocks(bool enable)8544d64d2e3SMattias Nilsson static void request_even_slower_clocks(bool enable)
8554d64d2e3SMattias Nilsson {
856b047d981SLinus Walleij u32 clock_reg[] = {
8574d64d2e3SMattias Nilsson PRCM_ACLK_MGT,
8584d64d2e3SMattias Nilsson PRCM_DMACLK_MGT
8594d64d2e3SMattias Nilsson };
8604d64d2e3SMattias Nilsson unsigned long flags;
8614d64d2e3SMattias Nilsson unsigned int i;
8624d64d2e3SMattias Nilsson
8634d64d2e3SMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags);
8644d64d2e3SMattias Nilsson
8654d64d2e3SMattias Nilsson /* Grab the HW semaphore. */
8664d64d2e3SMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
8674d64d2e3SMattias Nilsson cpu_relax();
8684d64d2e3SMattias Nilsson
8694d64d2e3SMattias Nilsson for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
8704d64d2e3SMattias Nilsson u32 val;
8714d64d2e3SMattias Nilsson u32 div;
8724d64d2e3SMattias Nilsson
873b047d981SLinus Walleij val = readl(prcmu_base + clock_reg[i]);
8744d64d2e3SMattias Nilsson div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
8754d64d2e3SMattias Nilsson if (enable) {
8764d64d2e3SMattias Nilsson if ((div <= 1) || (div > 15)) {
8774d64d2e3SMattias Nilsson pr_err("prcmu: Bad clock divider %d in %s\n",
8784d64d2e3SMattias Nilsson div, __func__);
8794d64d2e3SMattias Nilsson goto unlock_and_return;
8804d64d2e3SMattias Nilsson }
8814d64d2e3SMattias Nilsson div <<= 1;
8824d64d2e3SMattias Nilsson } else {
8834d64d2e3SMattias Nilsson if (div <= 2)
8844d64d2e3SMattias Nilsson goto unlock_and_return;
8854d64d2e3SMattias Nilsson div >>= 1;
8864d64d2e3SMattias Nilsson }
8874d64d2e3SMattias Nilsson val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
8884d64d2e3SMattias Nilsson (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
889b047d981SLinus Walleij writel(val, prcmu_base + clock_reg[i]);
8904d64d2e3SMattias Nilsson }
8914d64d2e3SMattias Nilsson
8924d64d2e3SMattias Nilsson unlock_and_return:
8934d64d2e3SMattias Nilsson /* Release the HW semaphore. */
8944d64d2e3SMattias Nilsson writel(0, PRCM_SEM);
8954d64d2e3SMattias Nilsson
8964d64d2e3SMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags);
8974d64d2e3SMattias Nilsson }
8984d64d2e3SMattias Nilsson
8993df57bcfSMattias Nilsson /**
900e00a953bSLee Jones * db8500_prcmu_set_ape_opp - set the appropriate APE OPP
9013df57bcfSMattias Nilsson * @opp: The new APE operating point to which transition is to be made
9023df57bcfSMattias Nilsson * Returns: 0 on success, non-zero on failure
9033df57bcfSMattias Nilsson *
9043df57bcfSMattias Nilsson * This function sets the operating point of the APE.
9053df57bcfSMattias Nilsson */
db8500_prcmu_set_ape_opp(u8 opp)9060508901cSMattias Nilsson int db8500_prcmu_set_ape_opp(u8 opp)
9073df57bcfSMattias Nilsson {
9083df57bcfSMattias Nilsson int r = 0;
9093df57bcfSMattias Nilsson
9104d64d2e3SMattias Nilsson if (opp == mb1_transfer.ape_opp)
9114d64d2e3SMattias Nilsson return 0;
9124d64d2e3SMattias Nilsson
9133df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock);
9143df57bcfSMattias Nilsson
9154d64d2e3SMattias Nilsson if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
9164d64d2e3SMattias Nilsson request_even_slower_clocks(false);
9174d64d2e3SMattias Nilsson
9184d64d2e3SMattias Nilsson if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
9194d64d2e3SMattias Nilsson goto skip_message;
9204d64d2e3SMattias Nilsson
921c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
9223df57bcfSMattias Nilsson cpu_relax();
9233df57bcfSMattias Nilsson
9243df57bcfSMattias Nilsson writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
9253df57bcfSMattias Nilsson writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
9264d64d2e3SMattias Nilsson writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
9274d64d2e3SMattias Nilsson (tcdm_base + PRCM_REQ_MB1_APE_OPP));
9283df57bcfSMattias Nilsson
929c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
9303df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work);
9313df57bcfSMattias Nilsson
9323df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
9333df57bcfSMattias Nilsson (mb1_transfer.ack.ape_opp != opp))
9343df57bcfSMattias Nilsson r = -EIO;
9353df57bcfSMattias Nilsson
9364d64d2e3SMattias Nilsson skip_message:
9374d64d2e3SMattias Nilsson if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
9384d64d2e3SMattias Nilsson (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
9394d64d2e3SMattias Nilsson request_even_slower_clocks(true);
9404d64d2e3SMattias Nilsson if (!r)
9414d64d2e3SMattias Nilsson mb1_transfer.ape_opp = opp;
9424d64d2e3SMattias Nilsson
9433df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock);
9443df57bcfSMattias Nilsson
9453df57bcfSMattias Nilsson return r;
9463df57bcfSMattias Nilsson }
9473df57bcfSMattias Nilsson
9483df57bcfSMattias Nilsson /**
9490508901cSMattias Nilsson * db8500_prcmu_get_ape_opp - get the current APE OPP
9503df57bcfSMattias Nilsson *
9513df57bcfSMattias Nilsson * Returns: the current APE OPP
9523df57bcfSMattias Nilsson */
db8500_prcmu_get_ape_opp(void)9530508901cSMattias Nilsson int db8500_prcmu_get_ape_opp(void)
9543df57bcfSMattias Nilsson {
9553df57bcfSMattias Nilsson return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
9563df57bcfSMattias Nilsson }
9573df57bcfSMattias Nilsson
9583df57bcfSMattias Nilsson /**
959686f871bSUlf Hansson * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
9603df57bcfSMattias Nilsson * @enable: true to request the higher voltage, false to drop a request.
9613df57bcfSMattias Nilsson *
9623df57bcfSMattias Nilsson * Calls to this function to enable and disable requests must be balanced.
9633df57bcfSMattias Nilsson */
db8500_prcmu_request_ape_opp_100_voltage(bool enable)964686f871bSUlf Hansson int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
9653df57bcfSMattias Nilsson {
9663df57bcfSMattias Nilsson int r = 0;
9673df57bcfSMattias Nilsson u8 header;
9683df57bcfSMattias Nilsson static unsigned int requests;
9693df57bcfSMattias Nilsson
9703df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock);
9713df57bcfSMattias Nilsson
9723df57bcfSMattias Nilsson if (enable) {
9733df57bcfSMattias Nilsson if (0 != requests++)
9743df57bcfSMattias Nilsson goto unlock_and_return;
9753df57bcfSMattias Nilsson header = MB1H_REQUEST_APE_OPP_100_VOLT;
9763df57bcfSMattias Nilsson } else {
9773df57bcfSMattias Nilsson if (requests == 0) {
9783df57bcfSMattias Nilsson r = -EIO;
9793df57bcfSMattias Nilsson goto unlock_and_return;
9803df57bcfSMattias Nilsson } else if (1 != requests--) {
9813df57bcfSMattias Nilsson goto unlock_and_return;
9823df57bcfSMattias Nilsson }
9833df57bcfSMattias Nilsson header = MB1H_RELEASE_APE_OPP_100_VOLT;
9843df57bcfSMattias Nilsson }
9853df57bcfSMattias Nilsson
986c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
9873df57bcfSMattias Nilsson cpu_relax();
9883df57bcfSMattias Nilsson
9893df57bcfSMattias Nilsson writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
9903df57bcfSMattias Nilsson
991c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
9923df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work);
9933df57bcfSMattias Nilsson
9943df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != header) ||
9953df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
9963df57bcfSMattias Nilsson r = -EIO;
9973df57bcfSMattias Nilsson
9983df57bcfSMattias Nilsson unlock_and_return:
9993df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock);
10003df57bcfSMattias Nilsson
10013df57bcfSMattias Nilsson return r;
10023df57bcfSMattias Nilsson }
10033df57bcfSMattias Nilsson
10043df57bcfSMattias Nilsson /**
10053df57bcfSMattias Nilsson * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
10063df57bcfSMattias Nilsson *
10073df57bcfSMattias Nilsson * This function releases the power state requirements of a USB wakeup.
10083df57bcfSMattias Nilsson */
prcmu_release_usb_wakeup_state(void)10093df57bcfSMattias Nilsson int prcmu_release_usb_wakeup_state(void)
10103df57bcfSMattias Nilsson {
10113df57bcfSMattias Nilsson int r = 0;
10123df57bcfSMattias Nilsson
10133df57bcfSMattias Nilsson mutex_lock(&mb1_transfer.lock);
10143df57bcfSMattias Nilsson
1015c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
10163df57bcfSMattias Nilsson cpu_relax();
10173df57bcfSMattias Nilsson
10183df57bcfSMattias Nilsson writeb(MB1H_RELEASE_USB_WAKEUP,
10193df57bcfSMattias Nilsson (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
10203df57bcfSMattias Nilsson
1021c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
10223df57bcfSMattias Nilsson wait_for_completion(&mb1_transfer.work);
10233df57bcfSMattias Nilsson
10243df57bcfSMattias Nilsson if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
10253df57bcfSMattias Nilsson ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
10263df57bcfSMattias Nilsson r = -EIO;
10273df57bcfSMattias Nilsson
10283df57bcfSMattias Nilsson mutex_unlock(&mb1_transfer.lock);
10293df57bcfSMattias Nilsson
10303df57bcfSMattias Nilsson return r;
10313df57bcfSMattias Nilsson }
10323df57bcfSMattias Nilsson
request_pll(u8 clock,bool enable)10330837bb72SMattias Nilsson static int request_pll(u8 clock, bool enable)
10340837bb72SMattias Nilsson {
10350837bb72SMattias Nilsson int r = 0;
10360837bb72SMattias Nilsson
10376b6fae2bSMattias Nilsson if (clock == PRCMU_PLLSOC0)
10386b6fae2bSMattias Nilsson clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
10396b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1)
10400837bb72SMattias Nilsson clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
10410837bb72SMattias Nilsson else
10420837bb72SMattias Nilsson return -EINVAL;
10430837bb72SMattias Nilsson
10440837bb72SMattias Nilsson mutex_lock(&mb1_transfer.lock);
10450837bb72SMattias Nilsson
10460837bb72SMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
10470837bb72SMattias Nilsson cpu_relax();
10480837bb72SMattias Nilsson
10490837bb72SMattias Nilsson writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
10500837bb72SMattias Nilsson writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
10510837bb72SMattias Nilsson
10520837bb72SMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
10530837bb72SMattias Nilsson wait_for_completion(&mb1_transfer.work);
10540837bb72SMattias Nilsson
10550837bb72SMattias Nilsson if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
10560837bb72SMattias Nilsson r = -EIO;
10570837bb72SMattias Nilsson
10580837bb72SMattias Nilsson mutex_unlock(&mb1_transfer.lock);
10590837bb72SMattias Nilsson
10600837bb72SMattias Nilsson return r;
10610837bb72SMattias Nilsson }
10620837bb72SMattias Nilsson
10633df57bcfSMattias Nilsson /**
106473180f85SMattias Nilsson * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
10653df57bcfSMattias Nilsson * @epod_id: The EPOD to set
10663df57bcfSMattias Nilsson * @epod_state: The new EPOD state
10673df57bcfSMattias Nilsson *
10683df57bcfSMattias Nilsson * This function sets the state of a EPOD (power domain). It may not be called
10693df57bcfSMattias Nilsson * from interrupt context.
10703df57bcfSMattias Nilsson */
db8500_prcmu_set_epod(u16 epod_id,u8 epod_state)107173180f85SMattias Nilsson int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
10723df57bcfSMattias Nilsson {
10733df57bcfSMattias Nilsson int r = 0;
10743df57bcfSMattias Nilsson bool ram_retention = false;
10753df57bcfSMattias Nilsson int i;
10763df57bcfSMattias Nilsson
10773df57bcfSMattias Nilsson /* check argument */
10783df57bcfSMattias Nilsson BUG_ON(epod_id >= NUM_EPOD_ID);
10793df57bcfSMattias Nilsson
10803df57bcfSMattias Nilsson /* set flag if retention is possible */
10813df57bcfSMattias Nilsson switch (epod_id) {
10823df57bcfSMattias Nilsson case EPOD_ID_SVAMMDSP:
10833df57bcfSMattias Nilsson case EPOD_ID_SIAMMDSP:
10843df57bcfSMattias Nilsson case EPOD_ID_ESRAM12:
10853df57bcfSMattias Nilsson case EPOD_ID_ESRAM34:
10863df57bcfSMattias Nilsson ram_retention = true;
10873df57bcfSMattias Nilsson break;
10883df57bcfSMattias Nilsson }
10893df57bcfSMattias Nilsson
10903df57bcfSMattias Nilsson /* check argument */
10913df57bcfSMattias Nilsson BUG_ON(epod_state > EPOD_STATE_ON);
10923df57bcfSMattias Nilsson BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
10933df57bcfSMattias Nilsson
10943df57bcfSMattias Nilsson /* get lock */
10953df57bcfSMattias Nilsson mutex_lock(&mb2_transfer.lock);
10963df57bcfSMattias Nilsson
10973df57bcfSMattias Nilsson /* wait for mailbox */
1098c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
10993df57bcfSMattias Nilsson cpu_relax();
11003df57bcfSMattias Nilsson
11013df57bcfSMattias Nilsson /* fill in mailbox */
11023df57bcfSMattias Nilsson for (i = 0; i < NUM_EPOD_ID; i++)
11033df57bcfSMattias Nilsson writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
11043df57bcfSMattias Nilsson writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
11053df57bcfSMattias Nilsson
11063df57bcfSMattias Nilsson writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
11073df57bcfSMattias Nilsson
1108c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
11093df57bcfSMattias Nilsson
11103df57bcfSMattias Nilsson /*
11113df57bcfSMattias Nilsson * The current firmware version does not handle errors correctly,
11123df57bcfSMattias Nilsson * and we cannot recover if there is an error.
11133df57bcfSMattias Nilsson * This is expected to change when the firmware is updated.
11143df57bcfSMattias Nilsson */
11153df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb2_transfer.work,
11163df57bcfSMattias Nilsson msecs_to_jiffies(20000))) {
11173df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
11183df57bcfSMattias Nilsson __func__);
11193df57bcfSMattias Nilsson r = -EIO;
11203df57bcfSMattias Nilsson goto unlock_and_return;
11213df57bcfSMattias Nilsson }
11223df57bcfSMattias Nilsson
11233df57bcfSMattias Nilsson if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
11243df57bcfSMattias Nilsson r = -EIO;
11253df57bcfSMattias Nilsson
11263df57bcfSMattias Nilsson unlock_and_return:
11273df57bcfSMattias Nilsson mutex_unlock(&mb2_transfer.lock);
11283df57bcfSMattias Nilsson return r;
11293df57bcfSMattias Nilsson }
11303df57bcfSMattias Nilsson
11313df57bcfSMattias Nilsson /**
11323df57bcfSMattias Nilsson * prcmu_configure_auto_pm - Configure autonomous power management.
11333df57bcfSMattias Nilsson * @sleep: Configuration for ApSleep.
11343df57bcfSMattias Nilsson * @idle: Configuration for ApIdle.
11353df57bcfSMattias Nilsson */
prcmu_configure_auto_pm(struct prcmu_auto_pm_config * sleep,struct prcmu_auto_pm_config * idle)11363df57bcfSMattias Nilsson void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
11373df57bcfSMattias Nilsson struct prcmu_auto_pm_config *idle)
11383df57bcfSMattias Nilsson {
11393df57bcfSMattias Nilsson u32 sleep_cfg;
11403df57bcfSMattias Nilsson u32 idle_cfg;
11413df57bcfSMattias Nilsson unsigned long flags;
11423df57bcfSMattias Nilsson
11433df57bcfSMattias Nilsson BUG_ON((sleep == NULL) || (idle == NULL));
11443df57bcfSMattias Nilsson
11453df57bcfSMattias Nilsson sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
11463df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
11473df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
11483df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
11493df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
11503df57bcfSMattias Nilsson sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
11513df57bcfSMattias Nilsson
11523df57bcfSMattias Nilsson idle_cfg = (idle->sva_auto_pm_enable & 0xF);
11533df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
11543df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
11553df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
11563df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
11573df57bcfSMattias Nilsson idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
11583df57bcfSMattias Nilsson
11593df57bcfSMattias Nilsson spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
11603df57bcfSMattias Nilsson
11613df57bcfSMattias Nilsson /*
11623df57bcfSMattias Nilsson * The autonomous power management configuration is done through
11633df57bcfSMattias Nilsson * fields in mailbox 2, but these fields are only used as shared
11643df57bcfSMattias Nilsson * variables - i.e. there is no need to send a message.
11653df57bcfSMattias Nilsson */
11663df57bcfSMattias Nilsson writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
11673df57bcfSMattias Nilsson writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
11683df57bcfSMattias Nilsson
11693df57bcfSMattias Nilsson mb2_transfer.auto_pm_enabled =
11703df57bcfSMattias Nilsson ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
11713df57bcfSMattias Nilsson (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
11723df57bcfSMattias Nilsson (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
11733df57bcfSMattias Nilsson (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
11743df57bcfSMattias Nilsson
11753df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
11763df57bcfSMattias Nilsson }
11773df57bcfSMattias Nilsson EXPORT_SYMBOL(prcmu_configure_auto_pm);
11783df57bcfSMattias Nilsson
prcmu_is_auto_pm_enabled(void)11793df57bcfSMattias Nilsson bool prcmu_is_auto_pm_enabled(void)
11803df57bcfSMattias Nilsson {
11813df57bcfSMattias Nilsson return mb2_transfer.auto_pm_enabled;
11823df57bcfSMattias Nilsson }
11833df57bcfSMattias Nilsson
request_sysclk(bool enable)11843df57bcfSMattias Nilsson static int request_sysclk(bool enable)
11853df57bcfSMattias Nilsson {
11863df57bcfSMattias Nilsson int r;
11873df57bcfSMattias Nilsson unsigned long flags;
11883df57bcfSMattias Nilsson
11893df57bcfSMattias Nilsson r = 0;
11903df57bcfSMattias Nilsson
11913df57bcfSMattias Nilsson mutex_lock(&mb3_transfer.sysclk_lock);
11923df57bcfSMattias Nilsson
11933df57bcfSMattias Nilsson spin_lock_irqsave(&mb3_transfer.lock, flags);
11943df57bcfSMattias Nilsson
1195c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
11963df57bcfSMattias Nilsson cpu_relax();
11973df57bcfSMattias Nilsson
11983df57bcfSMattias Nilsson writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
11993df57bcfSMattias Nilsson
12003df57bcfSMattias Nilsson writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1201c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
12023df57bcfSMattias Nilsson
12033df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb3_transfer.lock, flags);
12043df57bcfSMattias Nilsson
12053df57bcfSMattias Nilsson /*
12063df57bcfSMattias Nilsson * The firmware only sends an ACK if we want to enable the
12073df57bcfSMattias Nilsson * SysClk, and it succeeds.
12083df57bcfSMattias Nilsson */
12093df57bcfSMattias Nilsson if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
12103df57bcfSMattias Nilsson msecs_to_jiffies(20000))) {
12113df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
12123df57bcfSMattias Nilsson __func__);
12133df57bcfSMattias Nilsson r = -EIO;
12143df57bcfSMattias Nilsson }
12153df57bcfSMattias Nilsson
12163df57bcfSMattias Nilsson mutex_unlock(&mb3_transfer.sysclk_lock);
12173df57bcfSMattias Nilsson
12183df57bcfSMattias Nilsson return r;
12193df57bcfSMattias Nilsson }
12203df57bcfSMattias Nilsson
request_timclk(bool enable)12213df57bcfSMattias Nilsson static int request_timclk(bool enable)
12223df57bcfSMattias Nilsson {
122322fb3ad0SLinus Walleij u32 val;
122422fb3ad0SLinus Walleij
122522fb3ad0SLinus Walleij /*
122622fb3ad0SLinus Walleij * On the U8420_CLKSEL firmware, the ULP (Ultra Low Power)
122722fb3ad0SLinus Walleij * PLL is disabled so we cannot use doze mode, this will
122822fb3ad0SLinus Walleij * stop the clock on this firmware.
122922fb3ad0SLinus Walleij */
123022fb3ad0SLinus Walleij if (prcmu_is_ulppll_disabled())
123122fb3ad0SLinus Walleij val = 0;
123222fb3ad0SLinus Walleij else
123322fb3ad0SLinus Walleij val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
12343df57bcfSMattias Nilsson
12353df57bcfSMattias Nilsson if (!enable)
123622fb3ad0SLinus Walleij val |= PRCM_TCR_STOP_TIMERS |
123722fb3ad0SLinus Walleij PRCM_TCR_DOZE_MODE |
123822fb3ad0SLinus Walleij PRCM_TCR_TENSEL_MASK;
123922fb3ad0SLinus Walleij
1240c553b3caSMattias Nilsson writel(val, PRCM_TCR);
12413df57bcfSMattias Nilsson
12423df57bcfSMattias Nilsson return 0;
12433df57bcfSMattias Nilsson }
12443df57bcfSMattias Nilsson
request_clock(u8 clock,bool enable)12456b6fae2bSMattias Nilsson static int request_clock(u8 clock, bool enable)
12463df57bcfSMattias Nilsson {
12473df57bcfSMattias Nilsson u32 val;
12483df57bcfSMattias Nilsson unsigned long flags;
12493df57bcfSMattias Nilsson
12503df57bcfSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags);
12513df57bcfSMattias Nilsson
12523df57bcfSMattias Nilsson /* Grab the HW semaphore. */
1253c553b3caSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
12543df57bcfSMattias Nilsson cpu_relax();
12553df57bcfSMattias Nilsson
1256b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset);
12573df57bcfSMattias Nilsson if (enable) {
12583df57bcfSMattias Nilsson val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
12593df57bcfSMattias Nilsson } else {
12603df57bcfSMattias Nilsson clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
12613df57bcfSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
12623df57bcfSMattias Nilsson }
1263b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset);
12643df57bcfSMattias Nilsson
12653df57bcfSMattias Nilsson /* Release the HW semaphore. */
1266c553b3caSMattias Nilsson writel(0, PRCM_SEM);
12673df57bcfSMattias Nilsson
12683df57bcfSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags);
12693df57bcfSMattias Nilsson
12703df57bcfSMattias Nilsson return 0;
12713df57bcfSMattias Nilsson }
12723df57bcfSMattias Nilsson
request_sga_clock(u8 clock,bool enable)12730837bb72SMattias Nilsson static int request_sga_clock(u8 clock, bool enable)
12740837bb72SMattias Nilsson {
12750837bb72SMattias Nilsson u32 val;
12760837bb72SMattias Nilsson int ret;
12770837bb72SMattias Nilsson
12780837bb72SMattias Nilsson if (enable) {
12790837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS);
12800837bb72SMattias Nilsson writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
12810837bb72SMattias Nilsson }
12820837bb72SMattias Nilsson
12836b6fae2bSMattias Nilsson ret = request_clock(clock, enable);
12840837bb72SMattias Nilsson
12850837bb72SMattias Nilsson if (!ret && !enable) {
12860837bb72SMattias Nilsson val = readl(PRCM_CGATING_BYPASS);
12870837bb72SMattias Nilsson writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
12880837bb72SMattias Nilsson }
12890837bb72SMattias Nilsson
12900837bb72SMattias Nilsson return ret;
12910837bb72SMattias Nilsson }
12920837bb72SMattias Nilsson
plldsi_locked(void)12936b6fae2bSMattias Nilsson static inline bool plldsi_locked(void)
12946b6fae2bSMattias Nilsson {
12956b6fae2bSMattias Nilsson return (readl(PRCM_PLLDSI_LOCKP) &
12966b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
12976b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
12986b6fae2bSMattias Nilsson (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
12996b6fae2bSMattias Nilsson PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
13006b6fae2bSMattias Nilsson }
13016b6fae2bSMattias Nilsson
request_plldsi(bool enable)13026b6fae2bSMattias Nilsson static int request_plldsi(bool enable)
13036b6fae2bSMattias Nilsson {
13046b6fae2bSMattias Nilsson int r = 0;
13056b6fae2bSMattias Nilsson u32 val;
13066b6fae2bSMattias Nilsson
13076b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
13086b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
13096b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
13106b6fae2bSMattias Nilsson
13116b6fae2bSMattias Nilsson val = readl(PRCM_PLLDSI_ENABLE);
13126b6fae2bSMattias Nilsson if (enable)
13136b6fae2bSMattias Nilsson val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
13146b6fae2bSMattias Nilsson else
13156b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
13166b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE);
13176b6fae2bSMattias Nilsson
13186b6fae2bSMattias Nilsson if (enable) {
13196b6fae2bSMattias Nilsson unsigned int i;
13206b6fae2bSMattias Nilsson bool locked = plldsi_locked();
13216b6fae2bSMattias Nilsson
13226b6fae2bSMattias Nilsson for (i = 10; !locked && (i > 0); --i) {
13236b6fae2bSMattias Nilsson udelay(100);
13246b6fae2bSMattias Nilsson locked = plldsi_locked();
13256b6fae2bSMattias Nilsson }
13266b6fae2bSMattias Nilsson if (locked) {
13276b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN,
13286b6fae2bSMattias Nilsson PRCM_APE_RESETN_SET);
13296b6fae2bSMattias Nilsson } else {
13306b6fae2bSMattias Nilsson writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
13316b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
13326b6fae2bSMattias Nilsson PRCM_MMIP_LS_CLAMP_SET);
13336b6fae2bSMattias Nilsson val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
13346b6fae2bSMattias Nilsson writel(val, PRCM_PLLDSI_ENABLE);
13356b6fae2bSMattias Nilsson r = -EAGAIN;
13366b6fae2bSMattias Nilsson }
13376b6fae2bSMattias Nilsson } else {
13386b6fae2bSMattias Nilsson writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
13396b6fae2bSMattias Nilsson }
13406b6fae2bSMattias Nilsson return r;
13416b6fae2bSMattias Nilsson }
13426b6fae2bSMattias Nilsson
request_dsiclk(u8 n,bool enable)13436b6fae2bSMattias Nilsson static int request_dsiclk(u8 n, bool enable)
13446b6fae2bSMattias Nilsson {
13456b6fae2bSMattias Nilsson u32 val;
13466b6fae2bSMattias Nilsson
13476b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL);
13486b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask;
13496b6fae2bSMattias Nilsson val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
13506b6fae2bSMattias Nilsson dsiclk[n].divsel_shift);
13516b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL);
13526b6fae2bSMattias Nilsson return 0;
13536b6fae2bSMattias Nilsson }
13546b6fae2bSMattias Nilsson
request_dsiescclk(u8 n,bool enable)13556b6fae2bSMattias Nilsson static int request_dsiescclk(u8 n, bool enable)
13566b6fae2bSMattias Nilsson {
13576b6fae2bSMattias Nilsson u32 val;
13586b6fae2bSMattias Nilsson
13596b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV);
13606b6fae2bSMattias Nilsson enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
13616b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV);
13626b6fae2bSMattias Nilsson return 0;
13636b6fae2bSMattias Nilsson }
13646b6fae2bSMattias Nilsson
13653df57bcfSMattias Nilsson /**
136673180f85SMattias Nilsson * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
13673df57bcfSMattias Nilsson * @clock: The clock for which the request is made.
13683df57bcfSMattias Nilsson * @enable: Whether the clock should be enabled (true) or disabled (false).
13693df57bcfSMattias Nilsson *
13703df57bcfSMattias Nilsson * This function should only be used by the clock implementation.
13713df57bcfSMattias Nilsson * Do not use it from any other place!
13723df57bcfSMattias Nilsson */
db8500_prcmu_request_clock(u8 clock,bool enable)137373180f85SMattias Nilsson int db8500_prcmu_request_clock(u8 clock, bool enable)
13743df57bcfSMattias Nilsson {
13756b6fae2bSMattias Nilsson if (clock == PRCMU_SGACLK)
13760837bb72SMattias Nilsson return request_sga_clock(clock, enable);
13776b6fae2bSMattias Nilsson else if (clock < PRCMU_NUM_REG_CLOCKS)
13786b6fae2bSMattias Nilsson return request_clock(clock, enable);
13796b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK)
13803df57bcfSMattias Nilsson return request_timclk(enable);
13816b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
13826b6fae2bSMattias Nilsson return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
13836b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
13846b6fae2bSMattias Nilsson return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
13856b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI)
13866b6fae2bSMattias Nilsson return request_plldsi(enable);
13876b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK)
13883df57bcfSMattias Nilsson return request_sysclk(enable);
13896b6fae2bSMattias Nilsson else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
13900837bb72SMattias Nilsson return request_pll(clock, enable);
13916b6fae2bSMattias Nilsson else
13926b6fae2bSMattias Nilsson return -EINVAL;
13936b6fae2bSMattias Nilsson }
13946b6fae2bSMattias Nilsson
pll_rate(void __iomem * reg,unsigned long src_rate,int branch)13956b6fae2bSMattias Nilsson static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
13966b6fae2bSMattias Nilsson int branch)
13976b6fae2bSMattias Nilsson {
13986b6fae2bSMattias Nilsson u64 rate;
13996b6fae2bSMattias Nilsson u32 val;
14006b6fae2bSMattias Nilsson u32 d;
14016b6fae2bSMattias Nilsson u32 div = 1;
14026b6fae2bSMattias Nilsson
14036b6fae2bSMattias Nilsson val = readl(reg);
14046b6fae2bSMattias Nilsson
14056b6fae2bSMattias Nilsson rate = src_rate;
14066b6fae2bSMattias Nilsson rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
14076b6fae2bSMattias Nilsson
14086b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
14096b6fae2bSMattias Nilsson if (d > 1)
14106b6fae2bSMattias Nilsson div *= d;
14116b6fae2bSMattias Nilsson
14126b6fae2bSMattias Nilsson d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
14136b6fae2bSMattias Nilsson if (d > 1)
14146b6fae2bSMattias Nilsson div *= d;
14156b6fae2bSMattias Nilsson
14166b6fae2bSMattias Nilsson if (val & PRCM_PLL_FREQ_SELDIV2)
14176b6fae2bSMattias Nilsson div *= 2;
14186b6fae2bSMattias Nilsson
14196b6fae2bSMattias Nilsson if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
14206b6fae2bSMattias Nilsson (val & PRCM_PLL_FREQ_DIV2EN) &&
14216b6fae2bSMattias Nilsson ((reg == PRCM_PLLSOC0_FREQ) ||
142220aee5b6SMichel Jaouen (reg == PRCM_PLLARM_FREQ) ||
14236b6fae2bSMattias Nilsson (reg == PRCM_PLLDDR_FREQ))))
14246b6fae2bSMattias Nilsson div *= 2;
14256b6fae2bSMattias Nilsson
14266b6fae2bSMattias Nilsson (void)do_div(rate, div);
14276b6fae2bSMattias Nilsson
14286b6fae2bSMattias Nilsson return (unsigned long)rate;
14296b6fae2bSMattias Nilsson }
14306b6fae2bSMattias Nilsson
14316b6fae2bSMattias Nilsson #define ROOT_CLOCK_RATE 38400000
14326b6fae2bSMattias Nilsson
clock_rate(u8 clock)14336b6fae2bSMattias Nilsson static unsigned long clock_rate(u8 clock)
14346b6fae2bSMattias Nilsson {
14356b6fae2bSMattias Nilsson u32 val;
14366b6fae2bSMattias Nilsson u32 pllsw;
14376b6fae2bSMattias Nilsson unsigned long rate = ROOT_CLOCK_RATE;
14386b6fae2bSMattias Nilsson
1439b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset);
14406b6fae2bSMattias Nilsson
14416b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) {
14426b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
14436b6fae2bSMattias Nilsson rate /= 2;
14446b6fae2bSMattias Nilsson return rate;
14456b6fae2bSMattias Nilsson }
14466b6fae2bSMattias Nilsson
14476b6fae2bSMattias Nilsson val |= clk_mgt[clock].pllsw;
14486b6fae2bSMattias Nilsson pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
14496b6fae2bSMattias Nilsson
14506b6fae2bSMattias Nilsson if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
14516b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
14526b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
14536b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
14546b6fae2bSMattias Nilsson else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
14556b6fae2bSMattias Nilsson rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
14566b6fae2bSMattias Nilsson else
14576b6fae2bSMattias Nilsson return 0;
14586b6fae2bSMattias Nilsson
14596b6fae2bSMattias Nilsson if ((clock == PRCMU_SGACLK) &&
14606b6fae2bSMattias Nilsson (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
14616b6fae2bSMattias Nilsson u64 r = (rate * 10);
14626b6fae2bSMattias Nilsson
14636b6fae2bSMattias Nilsson (void)do_div(r, 25);
14646b6fae2bSMattias Nilsson return (unsigned long)r;
14656b6fae2bSMattias Nilsson }
14666b6fae2bSMattias Nilsson val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
14676b6fae2bSMattias Nilsson if (val)
14686b6fae2bSMattias Nilsson return rate / val;
14696b6fae2bSMattias Nilsson else
14706b6fae2bSMattias Nilsson return 0;
14716b6fae2bSMattias Nilsson }
147220aee5b6SMichel Jaouen
armss_rate(void)1473b2302c87SUlf Hansson static unsigned long armss_rate(void)
147420aee5b6SMichel Jaouen {
147520aee5b6SMichel Jaouen u32 r;
147620aee5b6SMichel Jaouen unsigned long rate;
147720aee5b6SMichel Jaouen
147820aee5b6SMichel Jaouen r = readl(PRCM_ARM_CHGCLKREQ);
147920aee5b6SMichel Jaouen
148020aee5b6SMichel Jaouen if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
148120aee5b6SMichel Jaouen /* External ARMCLKFIX clock */
148220aee5b6SMichel Jaouen
148320aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
148420aee5b6SMichel Jaouen
148520aee5b6SMichel Jaouen /* Check PRCM_ARM_CHGCLKREQ divider */
148620aee5b6SMichel Jaouen if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
148720aee5b6SMichel Jaouen rate /= 2;
148820aee5b6SMichel Jaouen
148920aee5b6SMichel Jaouen /* Check PRCM_ARMCLKFIX_MGT divider */
149020aee5b6SMichel Jaouen r = readl(PRCM_ARMCLKFIX_MGT);
149120aee5b6SMichel Jaouen r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
149220aee5b6SMichel Jaouen rate /= r;
149320aee5b6SMichel Jaouen
149420aee5b6SMichel Jaouen } else {/* ARM PLL */
149520aee5b6SMichel Jaouen rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
149620aee5b6SMichel Jaouen }
149720aee5b6SMichel Jaouen
1498b2302c87SUlf Hansson return rate;
149920aee5b6SMichel Jaouen }
15006b6fae2bSMattias Nilsson
dsiclk_rate(u8 n)15016b6fae2bSMattias Nilsson static unsigned long dsiclk_rate(u8 n)
15026b6fae2bSMattias Nilsson {
15036b6fae2bSMattias Nilsson u32 divsel;
15046b6fae2bSMattias Nilsson u32 div = 1;
15056b6fae2bSMattias Nilsson
15066b6fae2bSMattias Nilsson divsel = readl(PRCM_DSI_PLLOUT_SEL);
15076b6fae2bSMattias Nilsson divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
15086b6fae2bSMattias Nilsson
15096b6fae2bSMattias Nilsson if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
15106b6fae2bSMattias Nilsson divsel = dsiclk[n].divsel;
1511e9d7b4b5SUlf Hansson else
1512e9d7b4b5SUlf Hansson dsiclk[n].divsel = divsel;
15136b6fae2bSMattias Nilsson
15146b6fae2bSMattias Nilsson switch (divsel) {
15156b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_4:
15166b6fae2bSMattias Nilsson div *= 2;
1517df561f66SGustavo A. R. Silva fallthrough;
15186b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI_2:
15196b6fae2bSMattias Nilsson div *= 2;
1520df561f66SGustavo A. R. Silva fallthrough;
15216b6fae2bSMattias Nilsson case PRCM_DSI_PLLOUT_SEL_PHI:
15226b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
15236b6fae2bSMattias Nilsson PLL_RAW) / div;
1524e62ccf3aSLinus Walleij default:
15256b6fae2bSMattias Nilsson return 0;
15266b6fae2bSMattias Nilsson }
15276b6fae2bSMattias Nilsson }
15286b6fae2bSMattias Nilsson
dsiescclk_rate(u8 n)15296b6fae2bSMattias Nilsson static unsigned long dsiescclk_rate(u8 n)
15306b6fae2bSMattias Nilsson {
15316b6fae2bSMattias Nilsson u32 div;
15326b6fae2bSMattias Nilsson
15336b6fae2bSMattias Nilsson div = readl(PRCM_DSITVCLK_DIV);
15346b6fae2bSMattias Nilsson div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
15356b6fae2bSMattias Nilsson return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
15366b6fae2bSMattias Nilsson }
15376b6fae2bSMattias Nilsson
prcmu_clock_rate(u8 clock)15386b6fae2bSMattias Nilsson unsigned long prcmu_clock_rate(u8 clock)
15396b6fae2bSMattias Nilsson {
15406b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS)
15416b6fae2bSMattias Nilsson return clock_rate(clock);
15426b6fae2bSMattias Nilsson else if (clock == PRCMU_TIMCLK)
154322fb3ad0SLinus Walleij return prcmu_is_ulppll_disabled() ?
154422fb3ad0SLinus Walleij 32768 : ROOT_CLOCK_RATE / 16;
15456b6fae2bSMattias Nilsson else if (clock == PRCMU_SYSCLK)
15466b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE;
15476b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC0)
15486b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
15496b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLSOC1)
15506b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
155120aee5b6SMichel Jaouen else if (clock == PRCMU_ARMSS)
155220aee5b6SMichel Jaouen return armss_rate();
15536b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDDR)
15546b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
15556b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI)
15566b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
15576b6fae2bSMattias Nilsson PLL_RAW);
15586b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
15596b6fae2bSMattias Nilsson return dsiclk_rate(clock - PRCMU_DSI0CLK);
15606b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
15616b6fae2bSMattias Nilsson return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
15626b6fae2bSMattias Nilsson else
15636b6fae2bSMattias Nilsson return 0;
15646b6fae2bSMattias Nilsson }
15656b6fae2bSMattias Nilsson
clock_source_rate(u32 clk_mgt_val,int branch)15666b6fae2bSMattias Nilsson static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
15676b6fae2bSMattias Nilsson {
15686b6fae2bSMattias Nilsson if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
15696b6fae2bSMattias Nilsson return ROOT_CLOCK_RATE;
15706b6fae2bSMattias Nilsson clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
15716b6fae2bSMattias Nilsson if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
15726b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
15736b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
15746b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
15756b6fae2bSMattias Nilsson else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
15766b6fae2bSMattias Nilsson return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
15776b6fae2bSMattias Nilsson else
15786b6fae2bSMattias Nilsson return 0;
15796b6fae2bSMattias Nilsson }
15806b6fae2bSMattias Nilsson
clock_divider(unsigned long src_rate,unsigned long rate)15816b6fae2bSMattias Nilsson static u32 clock_divider(unsigned long src_rate, unsigned long rate)
15826b6fae2bSMattias Nilsson {
15836b6fae2bSMattias Nilsson u32 div;
15846b6fae2bSMattias Nilsson
15856b6fae2bSMattias Nilsson div = (src_rate / rate);
15866b6fae2bSMattias Nilsson if (div == 0)
15876b6fae2bSMattias Nilsson return 1;
15886b6fae2bSMattias Nilsson if (rate < (src_rate / div))
15896b6fae2bSMattias Nilsson div++;
15906b6fae2bSMattias Nilsson return div;
15916b6fae2bSMattias Nilsson }
15926b6fae2bSMattias Nilsson
round_clock_rate(u8 clock,unsigned long rate)15936b6fae2bSMattias Nilsson static long round_clock_rate(u8 clock, unsigned long rate)
15946b6fae2bSMattias Nilsson {
15956b6fae2bSMattias Nilsson u32 val;
15966b6fae2bSMattias Nilsson u32 div;
15976b6fae2bSMattias Nilsson unsigned long src_rate;
15986b6fae2bSMattias Nilsson long rounded_rate;
15996b6fae2bSMattias Nilsson
1600b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset);
16016b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
16026b6fae2bSMattias Nilsson clk_mgt[clock].branch);
16036b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate);
16046b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) {
16056b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) {
16066b6fae2bSMattias Nilsson if (div > 2)
16076b6fae2bSMattias Nilsson div = 2;
16086b6fae2bSMattias Nilsson } else {
16096b6fae2bSMattias Nilsson div = 1;
16106b6fae2bSMattias Nilsson }
16116b6fae2bSMattias Nilsson } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
16126b6fae2bSMattias Nilsson u64 r = (src_rate * 10);
16136b6fae2bSMattias Nilsson
16146b6fae2bSMattias Nilsson (void)do_div(r, 25);
16156b6fae2bSMattias Nilsson if (r <= rate)
16166b6fae2bSMattias Nilsson return (unsigned long)r;
16176b6fae2bSMattias Nilsson }
16186b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)31));
16196b6fae2bSMattias Nilsson
16206b6fae2bSMattias Nilsson return rounded_rate;
16216b6fae2bSMattias Nilsson }
16226b6fae2bSMattias Nilsson
1623fea3ac55SLinus Walleij static const unsigned long db8500_armss_freqs[] = {
1624ec343111SLinus Walleij 199680000,
1625ec343111SLinus Walleij 399360000,
1626ec343111SLinus Walleij 798720000,
1627836a1e25SLinus Walleij 998400000
1628b2302c87SUlf Hansson };
1629b2302c87SUlf Hansson
1630fea3ac55SLinus Walleij /* The DB8520 has slightly higher ARMSS max frequency */
1631fea3ac55SLinus Walleij static const unsigned long db8520_armss_freqs[] = {
1632ec343111SLinus Walleij 199680000,
1633ec343111SLinus Walleij 399360000,
1634ec343111SLinus Walleij 798720000,
1635fea3ac55SLinus Walleij 1152000000
1636fea3ac55SLinus Walleij };
1637fea3ac55SLinus Walleij
round_armss_rate(unsigned long rate)1638b2302c87SUlf Hansson static long round_armss_rate(unsigned long rate)
1639b2302c87SUlf Hansson {
1640836a1e25SLinus Walleij unsigned long freq = 0;
1641fea3ac55SLinus Walleij const unsigned long *freqs;
1642fea3ac55SLinus Walleij int nfreqs;
1643836a1e25SLinus Walleij int i;
1644b2302c87SUlf Hansson
1645fea3ac55SLinus Walleij if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1646fea3ac55SLinus Walleij freqs = db8520_armss_freqs;
1647fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1648fea3ac55SLinus Walleij } else {
1649fea3ac55SLinus Walleij freqs = db8500_armss_freqs;
1650fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1651fea3ac55SLinus Walleij }
1652fea3ac55SLinus Walleij
1653b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */
1654fea3ac55SLinus Walleij for (i = 0; i < nfreqs; i++) {
1655fea3ac55SLinus Walleij freq = freqs[i];
1656836a1e25SLinus Walleij if (rate <= freq)
1657b2302c87SUlf Hansson break;
1658b2302c87SUlf Hansson }
1659b2302c87SUlf Hansson
1660b2302c87SUlf Hansson /* Return the last valid value, even if a match was not found. */
1661836a1e25SLinus Walleij return freq;
1662b2302c87SUlf Hansson }
1663b2302c87SUlf Hansson
16646b6fae2bSMattias Nilsson #define MIN_PLL_VCO_RATE 600000000ULL
16656b6fae2bSMattias Nilsson #define MAX_PLL_VCO_RATE 1680640000ULL
16666b6fae2bSMattias Nilsson
round_plldsi_rate(unsigned long rate)16676b6fae2bSMattias Nilsson static long round_plldsi_rate(unsigned long rate)
16686b6fae2bSMattias Nilsson {
16696b6fae2bSMattias Nilsson long rounded_rate = 0;
16706b6fae2bSMattias Nilsson unsigned long src_rate;
16716b6fae2bSMattias Nilsson unsigned long rem;
16726b6fae2bSMattias Nilsson u32 r;
16736b6fae2bSMattias Nilsson
16746b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK);
16756b6fae2bSMattias Nilsson rem = rate;
16766b6fae2bSMattias Nilsson
16776b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) {
16786b6fae2bSMattias Nilsson u64 d;
16796b6fae2bSMattias Nilsson
16806b6fae2bSMattias Nilsson d = (r * rate);
16816b6fae2bSMattias Nilsson (void)do_div(d, src_rate);
16826b6fae2bSMattias Nilsson if (d < 6)
16836b6fae2bSMattias Nilsson d = 6;
16846b6fae2bSMattias Nilsson else if (d > 255)
16856b6fae2bSMattias Nilsson d = 255;
16866b6fae2bSMattias Nilsson d *= src_rate;
16876b6fae2bSMattias Nilsson if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
16886b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * d)))
16896b6fae2bSMattias Nilsson continue;
16906b6fae2bSMattias Nilsson (void)do_div(d, r);
16916b6fae2bSMattias Nilsson if (rate < d) {
16926b6fae2bSMattias Nilsson if (rounded_rate == 0)
16936b6fae2bSMattias Nilsson rounded_rate = (long)d;
1694e62ccf3aSLinus Walleij break;
1695e62ccf3aSLinus Walleij }
16966b6fae2bSMattias Nilsson if ((rate - d) < rem) {
16976b6fae2bSMattias Nilsson rem = (rate - d);
16986b6fae2bSMattias Nilsson rounded_rate = (long)d;
16996b6fae2bSMattias Nilsson }
17006b6fae2bSMattias Nilsson }
17016b6fae2bSMattias Nilsson return rounded_rate;
17026b6fae2bSMattias Nilsson }
17036b6fae2bSMattias Nilsson
round_dsiclk_rate(unsigned long rate)17046b6fae2bSMattias Nilsson static long round_dsiclk_rate(unsigned long rate)
17056b6fae2bSMattias Nilsson {
17066b6fae2bSMattias Nilsson u32 div;
17076b6fae2bSMattias Nilsson unsigned long src_rate;
17086b6fae2bSMattias Nilsson long rounded_rate;
17096b6fae2bSMattias Nilsson
17106b6fae2bSMattias Nilsson src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
17116b6fae2bSMattias Nilsson PLL_RAW);
17126b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate);
17136b6fae2bSMattias Nilsson rounded_rate = (src_rate / ((div > 2) ? 4 : div));
17146b6fae2bSMattias Nilsson
17156b6fae2bSMattias Nilsson return rounded_rate;
17166b6fae2bSMattias Nilsson }
17176b6fae2bSMattias Nilsson
round_dsiescclk_rate(unsigned long rate)17186b6fae2bSMattias Nilsson static long round_dsiescclk_rate(unsigned long rate)
17196b6fae2bSMattias Nilsson {
17206b6fae2bSMattias Nilsson u32 div;
17216b6fae2bSMattias Nilsson unsigned long src_rate;
17226b6fae2bSMattias Nilsson long rounded_rate;
17236b6fae2bSMattias Nilsson
17246b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_TVCLK);
17256b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate);
17266b6fae2bSMattias Nilsson rounded_rate = (src_rate / min(div, (u32)255));
17276b6fae2bSMattias Nilsson
17286b6fae2bSMattias Nilsson return rounded_rate;
17296b6fae2bSMattias Nilsson }
17306b6fae2bSMattias Nilsson
prcmu_round_clock_rate(u8 clock,unsigned long rate)17316b6fae2bSMattias Nilsson long prcmu_round_clock_rate(u8 clock, unsigned long rate)
17326b6fae2bSMattias Nilsson {
1733e62ccf3aSLinus Walleij if (clock < PRCMU_NUM_REG_CLOCKS)
17346b6fae2bSMattias Nilsson return round_clock_rate(clock, rate);
1735b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS)
1736b2302c87SUlf Hansson return round_armss_rate(rate);
17376b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI)
17386b6fae2bSMattias Nilsson return round_plldsi_rate(rate);
17396b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
17406b6fae2bSMattias Nilsson return round_dsiclk_rate(rate);
17416b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
17426b6fae2bSMattias Nilsson return round_dsiescclk_rate(rate);
17436b6fae2bSMattias Nilsson else
17446b6fae2bSMattias Nilsson return (long)prcmu_clock_rate(clock);
17456b6fae2bSMattias Nilsson }
17466b6fae2bSMattias Nilsson
set_clock_rate(u8 clock,unsigned long rate)17476b6fae2bSMattias Nilsson static void set_clock_rate(u8 clock, unsigned long rate)
17486b6fae2bSMattias Nilsson {
17496b6fae2bSMattias Nilsson u32 val;
17506b6fae2bSMattias Nilsson u32 div;
17516b6fae2bSMattias Nilsson unsigned long src_rate;
17526b6fae2bSMattias Nilsson unsigned long flags;
17536b6fae2bSMattias Nilsson
17546b6fae2bSMattias Nilsson spin_lock_irqsave(&clk_mgt_lock, flags);
17556b6fae2bSMattias Nilsson
17566b6fae2bSMattias Nilsson /* Grab the HW semaphore. */
17576b6fae2bSMattias Nilsson while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
17586b6fae2bSMattias Nilsson cpu_relax();
17596b6fae2bSMattias Nilsson
1760b047d981SLinus Walleij val = readl(prcmu_base + clk_mgt[clock].offset);
17616b6fae2bSMattias Nilsson src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
17626b6fae2bSMattias Nilsson clk_mgt[clock].branch);
17636b6fae2bSMattias Nilsson div = clock_divider(src_rate, rate);
17646b6fae2bSMattias Nilsson if (val & PRCM_CLK_MGT_CLK38) {
17656b6fae2bSMattias Nilsson if (clk_mgt[clock].clk38div) {
17666b6fae2bSMattias Nilsson if (div > 1)
17676b6fae2bSMattias Nilsson val |= PRCM_CLK_MGT_CLK38DIV;
17686b6fae2bSMattias Nilsson else
17696b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLK38DIV;
17706b6fae2bSMattias Nilsson }
17716b6fae2bSMattias Nilsson } else if (clock == PRCMU_SGACLK) {
17726b6fae2bSMattias Nilsson val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
17736b6fae2bSMattias Nilsson PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
17746b6fae2bSMattias Nilsson if (div == 3) {
17756b6fae2bSMattias Nilsson u64 r = (src_rate * 10);
17766b6fae2bSMattias Nilsson
17776b6fae2bSMattias Nilsson (void)do_div(r, 25);
17786b6fae2bSMattias Nilsson if (r <= rate) {
17796b6fae2bSMattias Nilsson val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
17806b6fae2bSMattias Nilsson div = 0;
17816b6fae2bSMattias Nilsson }
17826b6fae2bSMattias Nilsson }
17836b6fae2bSMattias Nilsson val |= min(div, (u32)31);
17846b6fae2bSMattias Nilsson } else {
17856b6fae2bSMattias Nilsson val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
17866b6fae2bSMattias Nilsson val |= min(div, (u32)31);
17876b6fae2bSMattias Nilsson }
1788b047d981SLinus Walleij writel(val, prcmu_base + clk_mgt[clock].offset);
17896b6fae2bSMattias Nilsson
17906b6fae2bSMattias Nilsson /* Release the HW semaphore. */
17916b6fae2bSMattias Nilsson writel(0, PRCM_SEM);
17926b6fae2bSMattias Nilsson
17936b6fae2bSMattias Nilsson spin_unlock_irqrestore(&clk_mgt_lock, flags);
17946b6fae2bSMattias Nilsson }
17956b6fae2bSMattias Nilsson
set_armss_rate(unsigned long rate)1796b2302c87SUlf Hansson static int set_armss_rate(unsigned long rate)
1797b2302c87SUlf Hansson {
1798836a1e25SLinus Walleij unsigned long freq;
1799836a1e25SLinus Walleij u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1800fea3ac55SLinus Walleij const unsigned long *freqs;
1801fea3ac55SLinus Walleij int nfreqs;
1802836a1e25SLinus Walleij int i;
1803b2302c87SUlf Hansson
1804fea3ac55SLinus Walleij if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1805fea3ac55SLinus Walleij freqs = db8520_armss_freqs;
1806fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1807fea3ac55SLinus Walleij } else {
1808fea3ac55SLinus Walleij freqs = db8500_armss_freqs;
1809fea3ac55SLinus Walleij nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1810fea3ac55SLinus Walleij }
1811fea3ac55SLinus Walleij
1812b2302c87SUlf Hansson /* Find the corresponding arm opp from the cpufreq table. */
1813fea3ac55SLinus Walleij for (i = 0; i < nfreqs; i++) {
1814fea3ac55SLinus Walleij freq = freqs[i];
1815836a1e25SLinus Walleij if (rate == freq)
1816b2302c87SUlf Hansson break;
1817836a1e25SLinus Walleij }
1818b2302c87SUlf Hansson
1819836a1e25SLinus Walleij if (rate != freq)
1820b2302c87SUlf Hansson return -EINVAL;
1821b2302c87SUlf Hansson
1822b2302c87SUlf Hansson /* Set the new arm opp. */
1823836a1e25SLinus Walleij pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1824836a1e25SLinus Walleij return db8500_prcmu_set_arm_opp(opps[i]);
1825b2302c87SUlf Hansson }
1826b2302c87SUlf Hansson
set_plldsi_rate(unsigned long rate)18276b6fae2bSMattias Nilsson static int set_plldsi_rate(unsigned long rate)
18286b6fae2bSMattias Nilsson {
18296b6fae2bSMattias Nilsson unsigned long src_rate;
18306b6fae2bSMattias Nilsson unsigned long rem;
18316b6fae2bSMattias Nilsson u32 pll_freq = 0;
18326b6fae2bSMattias Nilsson u32 r;
18336b6fae2bSMattias Nilsson
18346b6fae2bSMattias Nilsson src_rate = clock_rate(PRCMU_HDMICLK);
18356b6fae2bSMattias Nilsson rem = rate;
18366b6fae2bSMattias Nilsson
18376b6fae2bSMattias Nilsson for (r = 7; (rem > 0) && (r > 0); r--) {
18386b6fae2bSMattias Nilsson u64 d;
18396b6fae2bSMattias Nilsson u64 hwrate;
18406b6fae2bSMattias Nilsson
18416b6fae2bSMattias Nilsson d = (r * rate);
18426b6fae2bSMattias Nilsson (void)do_div(d, src_rate);
18436b6fae2bSMattias Nilsson if (d < 6)
18446b6fae2bSMattias Nilsson d = 6;
18456b6fae2bSMattias Nilsson else if (d > 255)
18466b6fae2bSMattias Nilsson d = 255;
18476b6fae2bSMattias Nilsson hwrate = (d * src_rate);
18486b6fae2bSMattias Nilsson if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
18496b6fae2bSMattias Nilsson ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
18506b6fae2bSMattias Nilsson continue;
18516b6fae2bSMattias Nilsson (void)do_div(hwrate, r);
18526b6fae2bSMattias Nilsson if (rate < hwrate) {
18536b6fae2bSMattias Nilsson if (pll_freq == 0)
18546b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
18556b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT));
18566b6fae2bSMattias Nilsson break;
18576b6fae2bSMattias Nilsson }
18586b6fae2bSMattias Nilsson if ((rate - hwrate) < rem) {
18596b6fae2bSMattias Nilsson rem = (rate - hwrate);
18606b6fae2bSMattias Nilsson pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
18616b6fae2bSMattias Nilsson (r << PRCM_PLL_FREQ_R_SHIFT));
18626b6fae2bSMattias Nilsson }
18636b6fae2bSMattias Nilsson }
18646b6fae2bSMattias Nilsson if (pll_freq == 0)
18653df57bcfSMattias Nilsson return -EINVAL;
18666b6fae2bSMattias Nilsson
18676b6fae2bSMattias Nilsson pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
18686b6fae2bSMattias Nilsson writel(pll_freq, PRCM_PLLDSI_FREQ);
18696b6fae2bSMattias Nilsson
18706b6fae2bSMattias Nilsson return 0;
18716b6fae2bSMattias Nilsson }
18726b6fae2bSMattias Nilsson
set_dsiclk_rate(u8 n,unsigned long rate)18736b6fae2bSMattias Nilsson static void set_dsiclk_rate(u8 n, unsigned long rate)
18746b6fae2bSMattias Nilsson {
18756b6fae2bSMattias Nilsson u32 val;
18766b6fae2bSMattias Nilsson u32 div;
18776b6fae2bSMattias Nilsson
18786b6fae2bSMattias Nilsson div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
18796b6fae2bSMattias Nilsson clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
18806b6fae2bSMattias Nilsson
18816b6fae2bSMattias Nilsson dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
18826b6fae2bSMattias Nilsson (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
18836b6fae2bSMattias Nilsson /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
18846b6fae2bSMattias Nilsson
18856b6fae2bSMattias Nilsson val = readl(PRCM_DSI_PLLOUT_SEL);
18866b6fae2bSMattias Nilsson val &= ~dsiclk[n].divsel_mask;
18876b6fae2bSMattias Nilsson val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
18886b6fae2bSMattias Nilsson writel(val, PRCM_DSI_PLLOUT_SEL);
18896b6fae2bSMattias Nilsson }
18906b6fae2bSMattias Nilsson
set_dsiescclk_rate(u8 n,unsigned long rate)18916b6fae2bSMattias Nilsson static void set_dsiescclk_rate(u8 n, unsigned long rate)
18926b6fae2bSMattias Nilsson {
18936b6fae2bSMattias Nilsson u32 val;
18946b6fae2bSMattias Nilsson u32 div;
18956b6fae2bSMattias Nilsson
18966b6fae2bSMattias Nilsson div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
18976b6fae2bSMattias Nilsson val = readl(PRCM_DSITVCLK_DIV);
18986b6fae2bSMattias Nilsson val &= ~dsiescclk[n].div_mask;
18996b6fae2bSMattias Nilsson val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
19006b6fae2bSMattias Nilsson writel(val, PRCM_DSITVCLK_DIV);
19016b6fae2bSMattias Nilsson }
19026b6fae2bSMattias Nilsson
prcmu_set_clock_rate(u8 clock,unsigned long rate)19036b6fae2bSMattias Nilsson int prcmu_set_clock_rate(u8 clock, unsigned long rate)
19046b6fae2bSMattias Nilsson {
19056b6fae2bSMattias Nilsson if (clock < PRCMU_NUM_REG_CLOCKS)
19066b6fae2bSMattias Nilsson set_clock_rate(clock, rate);
1907b2302c87SUlf Hansson else if (clock == PRCMU_ARMSS)
1908b2302c87SUlf Hansson return set_armss_rate(rate);
19096b6fae2bSMattias Nilsson else if (clock == PRCMU_PLLDSI)
19106b6fae2bSMattias Nilsson return set_plldsi_rate(rate);
19116b6fae2bSMattias Nilsson else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
19126b6fae2bSMattias Nilsson set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
19136b6fae2bSMattias Nilsson else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
19146b6fae2bSMattias Nilsson set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
19156b6fae2bSMattias Nilsson return 0;
19163df57bcfSMattias Nilsson }
19173df57bcfSMattias Nilsson
db8500_prcmu_config_esram0_deep_sleep(u8 state)191873180f85SMattias Nilsson int db8500_prcmu_config_esram0_deep_sleep(u8 state)
19193df57bcfSMattias Nilsson {
19203df57bcfSMattias Nilsson if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
19213df57bcfSMattias Nilsson (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
19223df57bcfSMattias Nilsson return -EINVAL;
19233df57bcfSMattias Nilsson
19243df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock);
19253df57bcfSMattias Nilsson
1926c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
19273df57bcfSMattias Nilsson cpu_relax();
19283df57bcfSMattias Nilsson
19293df57bcfSMattias Nilsson writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
19303df57bcfSMattias Nilsson writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
19313df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
19323df57bcfSMattias Nilsson writeb(DDR_PWR_STATE_ON,
19333df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
19343df57bcfSMattias Nilsson writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
19353df57bcfSMattias Nilsson
1936c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
19373df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work);
19383df57bcfSMattias Nilsson
19393df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock);
19403df57bcfSMattias Nilsson
19413df57bcfSMattias Nilsson return 0;
19423df57bcfSMattias Nilsson }
19433df57bcfSMattias Nilsson
db8500_prcmu_config_hotdog(u8 threshold)19440508901cSMattias Nilsson int db8500_prcmu_config_hotdog(u8 threshold)
19453df57bcfSMattias Nilsson {
19463df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock);
19473df57bcfSMattias Nilsson
1948c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
19493df57bcfSMattias Nilsson cpu_relax();
19503df57bcfSMattias Nilsson
19513df57bcfSMattias Nilsson writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
19523df57bcfSMattias Nilsson writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
19533df57bcfSMattias Nilsson
1954c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
19553df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work);
19563df57bcfSMattias Nilsson
19573df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock);
19583df57bcfSMattias Nilsson
19593df57bcfSMattias Nilsson return 0;
19603df57bcfSMattias Nilsson }
19613df57bcfSMattias Nilsson
db8500_prcmu_config_hotmon(u8 low,u8 high)19620508901cSMattias Nilsson int db8500_prcmu_config_hotmon(u8 low, u8 high)
19633df57bcfSMattias Nilsson {
19643df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock);
19653df57bcfSMattias Nilsson
1966c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
19673df57bcfSMattias Nilsson cpu_relax();
19683df57bcfSMattias Nilsson
19693df57bcfSMattias Nilsson writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
19703df57bcfSMattias Nilsson writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
19713df57bcfSMattias Nilsson writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
19723df57bcfSMattias Nilsson (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
19733df57bcfSMattias Nilsson writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
19743df57bcfSMattias Nilsson
1975c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
19763df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work);
19773df57bcfSMattias Nilsson
19783df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock);
19793df57bcfSMattias Nilsson
19803df57bcfSMattias Nilsson return 0;
19813df57bcfSMattias Nilsson }
198226716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
19833df57bcfSMattias Nilsson
config_hot_period(u16 val)19843df57bcfSMattias Nilsson static int config_hot_period(u16 val)
19853df57bcfSMattias Nilsson {
19863df57bcfSMattias Nilsson mutex_lock(&mb4_transfer.lock);
19873df57bcfSMattias Nilsson
1988c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
19893df57bcfSMattias Nilsson cpu_relax();
19903df57bcfSMattias Nilsson
19913df57bcfSMattias Nilsson writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
19923df57bcfSMattias Nilsson writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
19933df57bcfSMattias Nilsson
1994c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
19953df57bcfSMattias Nilsson wait_for_completion(&mb4_transfer.work);
19963df57bcfSMattias Nilsson
19973df57bcfSMattias Nilsson mutex_unlock(&mb4_transfer.lock);
19983df57bcfSMattias Nilsson
19993df57bcfSMattias Nilsson return 0;
20003df57bcfSMattias Nilsson }
20013df57bcfSMattias Nilsson
db8500_prcmu_start_temp_sense(u16 cycles32k)20020508901cSMattias Nilsson int db8500_prcmu_start_temp_sense(u16 cycles32k)
20033df57bcfSMattias Nilsson {
20043df57bcfSMattias Nilsson if (cycles32k == 0xFFFF)
20053df57bcfSMattias Nilsson return -EINVAL;
20063df57bcfSMattias Nilsson
20073df57bcfSMattias Nilsson return config_hot_period(cycles32k);
20083df57bcfSMattias Nilsson }
200926716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
20103df57bcfSMattias Nilsson
db8500_prcmu_stop_temp_sense(void)20110508901cSMattias Nilsson int db8500_prcmu_stop_temp_sense(void)
20123df57bcfSMattias Nilsson {
20133df57bcfSMattias Nilsson return config_hot_period(0xFFFF);
20143df57bcfSMattias Nilsson }
201526716ce1SArnd Bergmann EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
20163df57bcfSMattias Nilsson
prcmu_a9wdog(u8 cmd,u8 d0,u8 d1,u8 d2,u8 d3)201784165b80SJonas Aberg static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
201884165b80SJonas Aberg {
201984165b80SJonas Aberg
202084165b80SJonas Aberg mutex_lock(&mb4_transfer.lock);
202184165b80SJonas Aberg
202284165b80SJonas Aberg while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
202384165b80SJonas Aberg cpu_relax();
202484165b80SJonas Aberg
202584165b80SJonas Aberg writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
202684165b80SJonas Aberg writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
202784165b80SJonas Aberg writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
202884165b80SJonas Aberg writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
202984165b80SJonas Aberg
203084165b80SJonas Aberg writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
203184165b80SJonas Aberg
203284165b80SJonas Aberg writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
203384165b80SJonas Aberg wait_for_completion(&mb4_transfer.work);
203484165b80SJonas Aberg
203584165b80SJonas Aberg mutex_unlock(&mb4_transfer.lock);
203684165b80SJonas Aberg
203784165b80SJonas Aberg return 0;
203884165b80SJonas Aberg
203984165b80SJonas Aberg }
204084165b80SJonas Aberg
db8500_prcmu_config_a9wdog(u8 num,bool sleep_auto_off)20410508901cSMattias Nilsson int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
204284165b80SJonas Aberg {
204384165b80SJonas Aberg BUG_ON(num == 0 || num > 0xf);
204484165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
204584165b80SJonas Aberg sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
204684165b80SJonas Aberg A9WDOG_AUTO_OFF_DIS);
204784165b80SJonas Aberg }
20486f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
204984165b80SJonas Aberg
db8500_prcmu_enable_a9wdog(u8 id)20500508901cSMattias Nilsson int db8500_prcmu_enable_a9wdog(u8 id)
205184165b80SJonas Aberg {
205284165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
205384165b80SJonas Aberg }
20546f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
205584165b80SJonas Aberg
db8500_prcmu_disable_a9wdog(u8 id)20560508901cSMattias Nilsson int db8500_prcmu_disable_a9wdog(u8 id)
205784165b80SJonas Aberg {
205884165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
205984165b80SJonas Aberg }
20606f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
206184165b80SJonas Aberg
db8500_prcmu_kick_a9wdog(u8 id)20620508901cSMattias Nilsson int db8500_prcmu_kick_a9wdog(u8 id)
206384165b80SJonas Aberg {
206484165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
206584165b80SJonas Aberg }
20666f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
206784165b80SJonas Aberg
206884165b80SJonas Aberg /*
206984165b80SJonas Aberg * timeout is 28 bit, in ms.
207084165b80SJonas Aberg */
db8500_prcmu_load_a9wdog(u8 id,u32 timeout)20710508901cSMattias Nilsson int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
207284165b80SJonas Aberg {
207384165b80SJonas Aberg return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
207484165b80SJonas Aberg (id & A9WDOG_ID_MASK) |
207584165b80SJonas Aberg /*
207684165b80SJonas Aberg * Put the lowest 28 bits of timeout at
207784165b80SJonas Aberg * offset 4. Four first bits are used for id.
207884165b80SJonas Aberg */
207984165b80SJonas Aberg (u8)((timeout << 4) & 0xf0),
208084165b80SJonas Aberg (u8)((timeout >> 4) & 0xff),
208184165b80SJonas Aberg (u8)((timeout >> 12) & 0xff),
208284165b80SJonas Aberg (u8)((timeout >> 20) & 0xff));
208384165b80SJonas Aberg }
20846f8cfa99SFabio Baltieri EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
208584165b80SJonas Aberg
20863df57bcfSMattias Nilsson /**
2087650c2a21SLinus Walleij * prcmu_abb_read() - Read register value(s) from the ABB.
2088650c2a21SLinus Walleij * @slave: The I2C slave address.
2089650c2a21SLinus Walleij * @reg: The (start) register address.
2090650c2a21SLinus Walleij * @value: The read out value(s).
2091650c2a21SLinus Walleij * @size: The number of registers to read.
2092650c2a21SLinus Walleij *
2093650c2a21SLinus Walleij * Reads register value(s) from the ABB.
2094650c2a21SLinus Walleij * @size has to be 1 for the current firmware version.
2095650c2a21SLinus Walleij */
prcmu_abb_read(u8 slave,u8 reg,u8 * value,u8 size)2096650c2a21SLinus Walleij int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2097650c2a21SLinus Walleij {
2098650c2a21SLinus Walleij int r;
2099650c2a21SLinus Walleij
2100650c2a21SLinus Walleij if (size != 1)
2101650c2a21SLinus Walleij return -EINVAL;
2102650c2a21SLinus Walleij
21033df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock);
2104650c2a21SLinus Walleij
2105c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2106650c2a21SLinus Walleij cpu_relax();
2107650c2a21SLinus Walleij
21083c3e4898SMattias Nilsson writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
21093df57bcfSMattias Nilsson writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
21103df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
21113df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
21123df57bcfSMattias Nilsson writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2113650c2a21SLinus Walleij
2114c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
21153df57bcfSMattias Nilsson
2116650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work,
21173df57bcfSMattias Nilsson msecs_to_jiffies(20000))) {
21183df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
21193df57bcfSMattias Nilsson __func__);
2120650c2a21SLinus Walleij r = -EIO;
21213df57bcfSMattias Nilsson } else {
2122650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
21233df57bcfSMattias Nilsson }
21243df57bcfSMattias Nilsson
2125650c2a21SLinus Walleij if (!r)
2126650c2a21SLinus Walleij *value = mb5_transfer.ack.value;
2127650c2a21SLinus Walleij
2128650c2a21SLinus Walleij mutex_unlock(&mb5_transfer.lock);
21293df57bcfSMattias Nilsson
2130650c2a21SLinus Walleij return r;
2131650c2a21SLinus Walleij }
2132650c2a21SLinus Walleij
2133650c2a21SLinus Walleij /**
21343c3e4898SMattias Nilsson * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2135650c2a21SLinus Walleij * @slave: The I2C slave address.
2136650c2a21SLinus Walleij * @reg: The (start) register address.
2137650c2a21SLinus Walleij * @value: The value(s) to write.
21383c3e4898SMattias Nilsson * @mask: The mask(s) to use.
2139650c2a21SLinus Walleij * @size: The number of registers to write.
2140650c2a21SLinus Walleij *
21413c3e4898SMattias Nilsson * Writes masked register value(s) to the ABB.
21423c3e4898SMattias Nilsson * For each @value, only the bits set to 1 in the corresponding @mask
21433c3e4898SMattias Nilsson * will be written. The other bits are not changed.
2144650c2a21SLinus Walleij * @size has to be 1 for the current firmware version.
2145650c2a21SLinus Walleij */
prcmu_abb_write_masked(u8 slave,u8 reg,u8 * value,u8 * mask,u8 size)21463c3e4898SMattias Nilsson int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2147650c2a21SLinus Walleij {
2148650c2a21SLinus Walleij int r;
2149650c2a21SLinus Walleij
2150650c2a21SLinus Walleij if (size != 1)
2151650c2a21SLinus Walleij return -EINVAL;
2152650c2a21SLinus Walleij
21533df57bcfSMattias Nilsson mutex_lock(&mb5_transfer.lock);
2154650c2a21SLinus Walleij
2155c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2156650c2a21SLinus Walleij cpu_relax();
2157650c2a21SLinus Walleij
21583c3e4898SMattias Nilsson writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
21593df57bcfSMattias Nilsson writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
21603df57bcfSMattias Nilsson writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
21613df57bcfSMattias Nilsson writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
21623df57bcfSMattias Nilsson writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2163650c2a21SLinus Walleij
2164c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
21653df57bcfSMattias Nilsson
2166650c2a21SLinus Walleij if (!wait_for_completion_timeout(&mb5_transfer.work,
21673df57bcfSMattias Nilsson msecs_to_jiffies(20000))) {
21683df57bcfSMattias Nilsson pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
21693df57bcfSMattias Nilsson __func__);
2170650c2a21SLinus Walleij r = -EIO;
21713df57bcfSMattias Nilsson } else {
2172650c2a21SLinus Walleij r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
21733df57bcfSMattias Nilsson }
21743df57bcfSMattias Nilsson
21753df57bcfSMattias Nilsson mutex_unlock(&mb5_transfer.lock);
21763df57bcfSMattias Nilsson
21773df57bcfSMattias Nilsson return r;
21783df57bcfSMattias Nilsson }
21793df57bcfSMattias Nilsson
21803df57bcfSMattias Nilsson /**
21813c3e4898SMattias Nilsson * prcmu_abb_write() - Write register value(s) to the ABB.
21823c3e4898SMattias Nilsson * @slave: The I2C slave address.
21833c3e4898SMattias Nilsson * @reg: The (start) register address.
21843c3e4898SMattias Nilsson * @value: The value(s) to write.
21853c3e4898SMattias Nilsson * @size: The number of registers to write.
21863c3e4898SMattias Nilsson *
21873c3e4898SMattias Nilsson * Writes register value(s) to the ABB.
21883c3e4898SMattias Nilsson * @size has to be 1 for the current firmware version.
21893c3e4898SMattias Nilsson */
prcmu_abb_write(u8 slave,u8 reg,u8 * value,u8 size)21903c3e4898SMattias Nilsson int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
21913c3e4898SMattias Nilsson {
21923c3e4898SMattias Nilsson u8 mask = ~0;
21933c3e4898SMattias Nilsson
21943c3e4898SMattias Nilsson return prcmu_abb_write_masked(slave, reg, value, &mask, size);
21953c3e4898SMattias Nilsson }
21963c3e4898SMattias Nilsson
21973c3e4898SMattias Nilsson /**
21983df57bcfSMattias Nilsson * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
21993df57bcfSMattias Nilsson */
prcmu_ac_wake_req(void)22005261e101SArun Murthy int prcmu_ac_wake_req(void)
22013df57bcfSMattias Nilsson {
22023df57bcfSMattias Nilsson u32 val;
22035261e101SArun Murthy int ret = 0;
22043df57bcfSMattias Nilsson
22053df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock);
22063df57bcfSMattias Nilsson
2207c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ);
22083df57bcfSMattias Nilsson if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
22093df57bcfSMattias Nilsson goto unlock_and_return;
22103df57bcfSMattias Nilsson
22113df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 1);
22123df57bcfSMattias Nilsson
22135261e101SArun Murthy /*
22145261e101SArun Murthy * Force Modem Wake-up before hostaccess_req ping-pong.
22155261e101SArun Murthy * It prevents Modem to enter in Sleep while acking the hostaccess
22165261e101SArun Murthy * request. The 31us delay has been calculated by HWI.
22175261e101SArun Murthy */
22185261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
22195261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ);
22205261e101SArun Murthy
22215261e101SArun Murthy udelay(31);
22225261e101SArun Murthy
22235261e101SArun Murthy val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
22245261e101SArun Murthy writel(val, PRCM_HOSTACCESS_REQ);
22253df57bcfSMattias Nilsson
22263df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2227d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) {
222857265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2229d6e3002eSMattias Nilsson __func__);
22305261e101SArun Murthy ret = -EFAULT;
22313df57bcfSMattias Nilsson }
2232650c2a21SLinus Walleij
2233650c2a21SLinus Walleij unlock_and_return:
22343df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock);
22355261e101SArun Murthy return ret;
2236650c2a21SLinus Walleij }
2237650c2a21SLinus Walleij
22383df57bcfSMattias Nilsson /**
22393df57bcfSMattias Nilsson * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
22403df57bcfSMattias Nilsson */
prcmu_ac_sleep_req(void)2241ffb01160SSachin Kamat void prcmu_ac_sleep_req(void)
2242650c2a21SLinus Walleij {
22433df57bcfSMattias Nilsson u32 val;
2244650c2a21SLinus Walleij
22453df57bcfSMattias Nilsson mutex_lock(&mb0_transfer.ac_wake_lock);
2246650c2a21SLinus Walleij
2247c553b3caSMattias Nilsson val = readl(PRCM_HOSTACCESS_REQ);
22483df57bcfSMattias Nilsson if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
22493df57bcfSMattias Nilsson goto unlock_and_return;
22503df57bcfSMattias Nilsson
22513df57bcfSMattias Nilsson writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2252c553b3caSMattias Nilsson PRCM_HOSTACCESS_REQ);
22533df57bcfSMattias Nilsson
22543df57bcfSMattias Nilsson if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2255d6e3002eSMattias Nilsson msecs_to_jiffies(5000))) {
225657265bc1SLinus Walleij pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
22573df57bcfSMattias Nilsson __func__);
22583df57bcfSMattias Nilsson }
22593df57bcfSMattias Nilsson
22603df57bcfSMattias Nilsson atomic_set(&ac_wake_req_state, 0);
22613df57bcfSMattias Nilsson
22623df57bcfSMattias Nilsson unlock_and_return:
22633df57bcfSMattias Nilsson mutex_unlock(&mb0_transfer.ac_wake_lock);
22643df57bcfSMattias Nilsson }
22653df57bcfSMattias Nilsson
db8500_prcmu_is_ac_wake_requested(void)226673180f85SMattias Nilsson bool db8500_prcmu_is_ac_wake_requested(void)
22673df57bcfSMattias Nilsson {
22683df57bcfSMattias Nilsson return (atomic_read(&ac_wake_req_state) != 0);
22693df57bcfSMattias Nilsson }
22703df57bcfSMattias Nilsson
22713df57bcfSMattias Nilsson /**
227273180f85SMattias Nilsson * db8500_prcmu_system_reset - System reset
22733df57bcfSMattias Nilsson *
227473180f85SMattias Nilsson * Saves the reset reason code and then sets the APE_SOFTRST register which
22753df57bcfSMattias Nilsson * fires interrupt to fw
22763ecbcd20SLee Jones *
22773ecbcd20SLee Jones * @reset_code: The reason for system reset
22783df57bcfSMattias Nilsson */
db8500_prcmu_system_reset(u16 reset_code)227973180f85SMattias Nilsson void db8500_prcmu_system_reset(u16 reset_code)
22803df57bcfSMattias Nilsson {
22813df57bcfSMattias Nilsson writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2282c553b3caSMattias Nilsson writel(1, PRCM_APE_SOFTRST);
22833df57bcfSMattias Nilsson }
22843df57bcfSMattias Nilsson
22853df57bcfSMattias Nilsson /**
2286597045deSSebastian Rasmussen * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2287597045deSSebastian Rasmussen *
2288597045deSSebastian Rasmussen * Retrieves the reset reason code stored by prcmu_system_reset() before
2289597045deSSebastian Rasmussen * last restart.
2290597045deSSebastian Rasmussen */
db8500_prcmu_get_reset_code(void)2291597045deSSebastian Rasmussen u16 db8500_prcmu_get_reset_code(void)
2292597045deSSebastian Rasmussen {
2293597045deSSebastian Rasmussen return readw(tcdm_base + PRCM_SW_RST_REASON);
2294597045deSSebastian Rasmussen }
2295597045deSSebastian Rasmussen
2296597045deSSebastian Rasmussen /**
2297e00a953bSLee Jones * db8500_prcmu_modem_reset - ask the PRCMU to reset modem
22983df57bcfSMattias Nilsson */
db8500_prcmu_modem_reset(void)22990508901cSMattias Nilsson void db8500_prcmu_modem_reset(void)
23003df57bcfSMattias Nilsson {
2301650c2a21SLinus Walleij mutex_lock(&mb1_transfer.lock);
2302650c2a21SLinus Walleij
2303c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2304650c2a21SLinus Walleij cpu_relax();
2305650c2a21SLinus Walleij
23063df57bcfSMattias Nilsson writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2307c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2308650c2a21SLinus Walleij wait_for_completion(&mb1_transfer.work);
23093df57bcfSMattias Nilsson
23103df57bcfSMattias Nilsson /*
23113df57bcfSMattias Nilsson * No need to check return from PRCMU as modem should go in reset state
23123df57bcfSMattias Nilsson * This state is already managed by upper layer
23133df57bcfSMattias Nilsson */
2314650c2a21SLinus Walleij
2315650c2a21SLinus Walleij mutex_unlock(&mb1_transfer.lock);
2316650c2a21SLinus Walleij }
2317650c2a21SLinus Walleij
ack_dbb_wakeup(void)23183df57bcfSMattias Nilsson static void ack_dbb_wakeup(void)
2319650c2a21SLinus Walleij {
23203df57bcfSMattias Nilsson unsigned long flags;
2321650c2a21SLinus Walleij
23223df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags);
2323650c2a21SLinus Walleij
2324c553b3caSMattias Nilsson while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
23253df57bcfSMattias Nilsson cpu_relax();
2326650c2a21SLinus Walleij
23273df57bcfSMattias Nilsson writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2328c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2329650c2a21SLinus Walleij
23303df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2331650c2a21SLinus Walleij }
2332650c2a21SLinus Walleij
print_unknown_header_warning(u8 n,u8 header)23333df57bcfSMattias Nilsson static inline void print_unknown_header_warning(u8 n, u8 header)
2334650c2a21SLinus Walleij {
233581d30edaSJoe Perches pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
23363df57bcfSMattias Nilsson header, n);
2337650c2a21SLinus Walleij }
2338650c2a21SLinus Walleij
read_mailbox_0(void)23393df57bcfSMattias Nilsson static bool read_mailbox_0(void)
2340650c2a21SLinus Walleij {
23413df57bcfSMattias Nilsson bool r;
23423df57bcfSMattias Nilsson u32 ev;
23433df57bcfSMattias Nilsson unsigned int n;
23443df57bcfSMattias Nilsson u8 header;
23453df57bcfSMattias Nilsson
23463df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
23473df57bcfSMattias Nilsson switch (header) {
23483df57bcfSMattias Nilsson case MB0H_WAKEUP_EXE:
23493df57bcfSMattias Nilsson case MB0H_WAKEUP_SLEEP:
23503df57bcfSMattias Nilsson if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
23513df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
23523df57bcfSMattias Nilsson else
23533df57bcfSMattias Nilsson ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
23543df57bcfSMattias Nilsson
23553df57bcfSMattias Nilsson if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
23563df57bcfSMattias Nilsson complete(&mb0_transfer.ac_wake_work);
23573df57bcfSMattias Nilsson if (ev & WAKEUP_BIT_SYSCLK_OK)
23583df57bcfSMattias Nilsson complete(&mb3_transfer.sysclk_work);
23593df57bcfSMattias Nilsson
23603df57bcfSMattias Nilsson ev &= mb0_transfer.req.dbb_irqs;
23613df57bcfSMattias Nilsson
23623df57bcfSMattias Nilsson for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
23633df57bcfSMattias Nilsson if (ev & prcmu_irq_bit[n])
23643b0cccefSMarc Zyngier generic_handle_domain_irq(db8500_irq_domain, n);
23653df57bcfSMattias Nilsson }
23663df57bcfSMattias Nilsson r = true;
23673df57bcfSMattias Nilsson break;
23683df57bcfSMattias Nilsson default:
23693df57bcfSMattias Nilsson print_unknown_header_warning(0, header);
23703df57bcfSMattias Nilsson r = false;
23713df57bcfSMattias Nilsson break;
23723df57bcfSMattias Nilsson }
2373c553b3caSMattias Nilsson writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
23743df57bcfSMattias Nilsson return r;
23753df57bcfSMattias Nilsson }
23763df57bcfSMattias Nilsson
read_mailbox_1(void)23773df57bcfSMattias Nilsson static bool read_mailbox_1(void)
23783df57bcfSMattias Nilsson {
23793df57bcfSMattias Nilsson mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
23803df57bcfSMattias Nilsson mb1_transfer.ack.arm_opp = readb(tcdm_base +
23813df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_ARM_OPP);
23823df57bcfSMattias Nilsson mb1_transfer.ack.ape_opp = readb(tcdm_base +
23833df57bcfSMattias Nilsson PRCM_ACK_MB1_CURRENT_APE_OPP);
23843df57bcfSMattias Nilsson mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
23853df57bcfSMattias Nilsson PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2386c553b3caSMattias Nilsson writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2387650c2a21SLinus Walleij complete(&mb1_transfer.work);
23883df57bcfSMattias Nilsson return false;
2389650c2a21SLinus Walleij }
2390650c2a21SLinus Walleij
read_mailbox_2(void)23913df57bcfSMattias Nilsson static bool read_mailbox_2(void)
2392650c2a21SLinus Walleij {
23933df57bcfSMattias Nilsson mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2394c553b3caSMattias Nilsson writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
23953df57bcfSMattias Nilsson complete(&mb2_transfer.work);
23963df57bcfSMattias Nilsson return false;
2397650c2a21SLinus Walleij }
2398650c2a21SLinus Walleij
read_mailbox_3(void)23993df57bcfSMattias Nilsson static bool read_mailbox_3(void)
2400650c2a21SLinus Walleij {
2401c553b3caSMattias Nilsson writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
24023df57bcfSMattias Nilsson return false;
2403650c2a21SLinus Walleij }
2404650c2a21SLinus Walleij
read_mailbox_4(void)24053df57bcfSMattias Nilsson static bool read_mailbox_4(void)
2406650c2a21SLinus Walleij {
24073df57bcfSMattias Nilsson u8 header;
24083df57bcfSMattias Nilsson bool do_complete = true;
24093df57bcfSMattias Nilsson
24103df57bcfSMattias Nilsson header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
24113df57bcfSMattias Nilsson switch (header) {
24123df57bcfSMattias Nilsson case MB4H_MEM_ST:
24133df57bcfSMattias Nilsson case MB4H_HOTDOG:
24143df57bcfSMattias Nilsson case MB4H_HOTMON:
24153df57bcfSMattias Nilsson case MB4H_HOT_PERIOD:
2416a592c2e2SMattias Nilsson case MB4H_A9WDOG_CONF:
2417a592c2e2SMattias Nilsson case MB4H_A9WDOG_EN:
2418a592c2e2SMattias Nilsson case MB4H_A9WDOG_DIS:
2419a592c2e2SMattias Nilsson case MB4H_A9WDOG_LOAD:
2420a592c2e2SMattias Nilsson case MB4H_A9WDOG_KICK:
24213df57bcfSMattias Nilsson break;
24223df57bcfSMattias Nilsson default:
24233df57bcfSMattias Nilsson print_unknown_header_warning(4, header);
24243df57bcfSMattias Nilsson do_complete = false;
24253df57bcfSMattias Nilsson break;
2426650c2a21SLinus Walleij }
2427650c2a21SLinus Walleij
2428c553b3caSMattias Nilsson writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
24293df57bcfSMattias Nilsson
24303df57bcfSMattias Nilsson if (do_complete)
24313df57bcfSMattias Nilsson complete(&mb4_transfer.work);
24323df57bcfSMattias Nilsson
24333df57bcfSMattias Nilsson return false;
24343df57bcfSMattias Nilsson }
24353df57bcfSMattias Nilsson
read_mailbox_5(void)24363df57bcfSMattias Nilsson static bool read_mailbox_5(void)
2437650c2a21SLinus Walleij {
24383df57bcfSMattias Nilsson mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
24393df57bcfSMattias Nilsson mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2440c553b3caSMattias Nilsson writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2441650c2a21SLinus Walleij complete(&mb5_transfer.work);
24423df57bcfSMattias Nilsson return false;
2443650c2a21SLinus Walleij }
2444650c2a21SLinus Walleij
read_mailbox_6(void)24453df57bcfSMattias Nilsson static bool read_mailbox_6(void)
2446650c2a21SLinus Walleij {
2447c553b3caSMattias Nilsson writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
24483df57bcfSMattias Nilsson return false;
2449650c2a21SLinus Walleij }
2450650c2a21SLinus Walleij
read_mailbox_7(void)24513df57bcfSMattias Nilsson static bool read_mailbox_7(void)
2452650c2a21SLinus Walleij {
2453c553b3caSMattias Nilsson writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
24543df57bcfSMattias Nilsson return false;
2455650c2a21SLinus Walleij }
2456650c2a21SLinus Walleij
24573df57bcfSMattias Nilsson static bool (* const read_mailbox[NUM_MB])(void) = {
2458650c2a21SLinus Walleij read_mailbox_0,
2459650c2a21SLinus Walleij read_mailbox_1,
2460650c2a21SLinus Walleij read_mailbox_2,
2461650c2a21SLinus Walleij read_mailbox_3,
2462650c2a21SLinus Walleij read_mailbox_4,
2463650c2a21SLinus Walleij read_mailbox_5,
2464650c2a21SLinus Walleij read_mailbox_6,
2465650c2a21SLinus Walleij read_mailbox_7
2466650c2a21SLinus Walleij };
2467650c2a21SLinus Walleij
prcmu_irq_handler(int irq,void * data)2468650c2a21SLinus Walleij static irqreturn_t prcmu_irq_handler(int irq, void *data)
2469650c2a21SLinus Walleij {
2470650c2a21SLinus Walleij u32 bits;
2471650c2a21SLinus Walleij u8 n;
24723df57bcfSMattias Nilsson irqreturn_t r;
2473650c2a21SLinus Walleij
2474c553b3caSMattias Nilsson bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2475650c2a21SLinus Walleij if (unlikely(!bits))
2476650c2a21SLinus Walleij return IRQ_NONE;
2477650c2a21SLinus Walleij
24783df57bcfSMattias Nilsson r = IRQ_HANDLED;
2479650c2a21SLinus Walleij for (n = 0; bits; n++) {
2480650c2a21SLinus Walleij if (bits & MBOX_BIT(n)) {
2481650c2a21SLinus Walleij bits -= MBOX_BIT(n);
24823df57bcfSMattias Nilsson if (read_mailbox[n]())
24833df57bcfSMattias Nilsson r = IRQ_WAKE_THREAD;
2484650c2a21SLinus Walleij }
2485650c2a21SLinus Walleij }
24863df57bcfSMattias Nilsson return r;
24873df57bcfSMattias Nilsson }
24883df57bcfSMattias Nilsson
prcmu_irq_thread_fn(int irq,void * data)24893df57bcfSMattias Nilsson static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
24903df57bcfSMattias Nilsson {
24913df57bcfSMattias Nilsson ack_dbb_wakeup();
2492650c2a21SLinus Walleij return IRQ_HANDLED;
2493650c2a21SLinus Walleij }
2494650c2a21SLinus Walleij
prcmu_mask_work(struct work_struct * work)24953df57bcfSMattias Nilsson static void prcmu_mask_work(struct work_struct *work)
24963df57bcfSMattias Nilsson {
24973df57bcfSMattias Nilsson unsigned long flags;
24983df57bcfSMattias Nilsson
24993df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.lock, flags);
25003df57bcfSMattias Nilsson
25013df57bcfSMattias Nilsson config_wakeups();
25023df57bcfSMattias Nilsson
25033df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.lock, flags);
25043df57bcfSMattias Nilsson }
25053df57bcfSMattias Nilsson
prcmu_irq_mask(struct irq_data * d)25063df57bcfSMattias Nilsson static void prcmu_irq_mask(struct irq_data *d)
25073df57bcfSMattias Nilsson {
25083df57bcfSMattias Nilsson unsigned long flags;
25093df57bcfSMattias Nilsson
25103df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
25113df57bcfSMattias Nilsson
2512f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
25133df57bcfSMattias Nilsson
25143df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
25153df57bcfSMattias Nilsson
25163df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP)
25173df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work);
25183df57bcfSMattias Nilsson }
25193df57bcfSMattias Nilsson
prcmu_irq_unmask(struct irq_data * d)25203df57bcfSMattias Nilsson static void prcmu_irq_unmask(struct irq_data *d)
25213df57bcfSMattias Nilsson {
25223df57bcfSMattias Nilsson unsigned long flags;
25233df57bcfSMattias Nilsson
25243df57bcfSMattias Nilsson spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
25253df57bcfSMattias Nilsson
2526f3f1f0a1SLee Jones mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
25273df57bcfSMattias Nilsson
25283df57bcfSMattias Nilsson spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
25293df57bcfSMattias Nilsson
25303df57bcfSMattias Nilsson if (d->irq != IRQ_PRCMU_CA_SLEEP)
25313df57bcfSMattias Nilsson schedule_work(&mb0_transfer.mask_work);
25323df57bcfSMattias Nilsson }
25333df57bcfSMattias Nilsson
noop(struct irq_data * d)25343df57bcfSMattias Nilsson static void noop(struct irq_data *d)
25353df57bcfSMattias Nilsson {
25363df57bcfSMattias Nilsson }
25373df57bcfSMattias Nilsson
25383df57bcfSMattias Nilsson static struct irq_chip prcmu_irq_chip = {
25393df57bcfSMattias Nilsson .name = "prcmu",
25403df57bcfSMattias Nilsson .irq_disable = prcmu_irq_mask,
25413df57bcfSMattias Nilsson .irq_ack = noop,
25423df57bcfSMattias Nilsson .irq_mask = prcmu_irq_mask,
25433df57bcfSMattias Nilsson .irq_unmask = prcmu_irq_unmask,
25443df57bcfSMattias Nilsson };
25453df57bcfSMattias Nilsson
fw_project_name(u32 project)2546a3888f62SNathan Chancellor static char *fw_project_name(u32 project)
2547b58d12feSMattias Nilsson {
2548b58d12feSMattias Nilsson switch (project) {
2549b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U8500:
2550b58d12feSMattias Nilsson return "U8500";
255105ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8400:
255205ec260eSLinus Walleij return "U8400";
2553b58d12feSMattias Nilsson case PRCMU_FW_PROJECT_U9500:
2554b58d12feSMattias Nilsson return "U9500";
255505ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBB:
255605ec260eSLinus Walleij return "U8500 MBB";
255705ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C1:
255805ec260eSLinus Walleij return "U8500 C1";
255905ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C2:
256005ec260eSLinus Walleij return "U8500 C2";
256105ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C3:
256205ec260eSLinus Walleij return "U8500 C3";
256305ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_C4:
256405ec260eSLinus Walleij return "U8500 C4";
256505ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9500_MBL:
256605ec260eSLinus Walleij return "U9500 MBL";
25679050ad81SLinus Walleij case PRCMU_FW_PROJECT_U8500_SSG1:
25689050ad81SLinus Walleij return "U8500 Samsung 1";
256905ec260eSLinus Walleij case PRCMU_FW_PROJECT_U8500_MBL2:
257005ec260eSLinus Walleij return "U8500 MBL2";
25715f96a1a6SBengt Jonsson case PRCMU_FW_PROJECT_U8520:
257205ec260eSLinus Walleij return "U8520 MBL";
25731927ddf6SBengt Jonsson case PRCMU_FW_PROJECT_U8420:
25741927ddf6SBengt Jonsson return "U8420";
25759050ad81SLinus Walleij case PRCMU_FW_PROJECT_U8500_SSG2:
25769050ad81SLinus Walleij return "U8500 Samsung 2";
257722fb3ad0SLinus Walleij case PRCMU_FW_PROJECT_U8420_SYSCLK:
257822fb3ad0SLinus Walleij return "U8420-sysclk";
257905ec260eSLinus Walleij case PRCMU_FW_PROJECT_U9540:
258005ec260eSLinus Walleij return "U9540";
258105ec260eSLinus Walleij case PRCMU_FW_PROJECT_A9420:
258205ec260eSLinus Walleij return "A9420";
258305ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8540:
258405ec260eSLinus Walleij return "L8540";
258505ec260eSLinus Walleij case PRCMU_FW_PROJECT_L8580:
258605ec260eSLinus Walleij return "L8580";
2587b58d12feSMattias Nilsson default:
2588b58d12feSMattias Nilsson return "Unknown";
2589b58d12feSMattias Nilsson }
2590b58d12feSMattias Nilsson }
2591b58d12feSMattias Nilsson
db8500_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hwirq)2592f3f1f0a1SLee Jones static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2593f3f1f0a1SLee Jones irq_hw_number_t hwirq)
2594f3f1f0a1SLee Jones {
2595f3f1f0a1SLee Jones irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2596f3f1f0a1SLee Jones handle_simple_irq);
2597f3f1f0a1SLee Jones
2598f3f1f0a1SLee Jones return 0;
2599f3f1f0a1SLee Jones }
2600f3f1f0a1SLee Jones
26017ce7b26fSKrzysztof Kozlowski static const struct irq_domain_ops db8500_irq_ops = {
2602f3f1f0a1SLee Jones .map = db8500_irq_map,
2603f3f1f0a1SLee Jones .xlate = irq_domain_xlate_twocell,
2604f3f1f0a1SLee Jones };
2605f3f1f0a1SLee Jones
db8500_irq_init(struct device_node * np)2606f864c46aSLinus Walleij static int db8500_irq_init(struct device_node *np)
2607f3f1f0a1SLee Jones {
260889d9b1c9SLinus Walleij int i;
2609a7238e43SLinus Walleij
2610a7238e43SLinus Walleij db8500_irq_domain = irq_domain_add_simple(
2611f864c46aSLinus Walleij np, NUM_PRCMU_WAKEUPS, 0,
2612a7238e43SLinus Walleij &db8500_irq_ops, NULL);
2613f3f1f0a1SLee Jones
2614f3f1f0a1SLee Jones if (!db8500_irq_domain) {
2615f3f1f0a1SLee Jones pr_err("Failed to create irqdomain\n");
2616f3f1f0a1SLee Jones return -ENOSYS;
2617f3f1f0a1SLee Jones }
2618f3f1f0a1SLee Jones
261989d9b1c9SLinus Walleij /* All wakeups will be used, so create mappings for all */
262089d9b1c9SLinus Walleij for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
262189d9b1c9SLinus Walleij irq_create_mapping(db8500_irq_domain, i);
262289d9b1c9SLinus Walleij
2623f3f1f0a1SLee Jones return 0;
2624f3f1f0a1SLee Jones }
2625f3f1f0a1SLee Jones
dbx500_fw_version_init(struct device_node * np)262622fb3ad0SLinus Walleij static void dbx500_fw_version_init(struct device_node *np)
2627650c2a21SLinus Walleij {
262805ec260eSLinus Walleij void __iomem *tcpm_base;
2629741cdecfSLee Jones u32 version;
26303df57bcfSMattias Nilsson
263122fb3ad0SLinus Walleij tcpm_base = of_iomap(np, 1);
2632741cdecfSLee Jones if (!tcpm_base) {
263322fb3ad0SLinus Walleij pr_err("no prcmu tcpm mem region provided\n");
2634741cdecfSLee Jones return;
2635741cdecfSLee Jones }
263605ec260eSLinus Walleij
263722fb3ad0SLinus Walleij version = readl(tcpm_base + DB8500_PRCMU_FW_VERSION_OFFSET);
263805ec260eSLinus Walleij fw_info.version.project = (version & 0xFF);
2639b58d12feSMattias Nilsson fw_info.version.api_version = (version >> 8) & 0xFF;
2640b58d12feSMattias Nilsson fw_info.version.func_version = (version >> 16) & 0xFF;
2641b58d12feSMattias Nilsson fw_info.version.errata = (version >> 24) & 0xFF;
264205ec260eSLinus Walleij strncpy(fw_info.version.project_name,
2643b58d12feSMattias Nilsson fw_project_name(fw_info.version.project),
264405ec260eSLinus Walleij PRCMU_FW_PROJECT_NAME_LEN);
264505ec260eSLinus Walleij fw_info.valid = true;
264605ec260eSLinus Walleij pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
264705ec260eSLinus Walleij fw_info.version.project_name,
264805ec260eSLinus Walleij fw_info.version.project,
264905ec260eSLinus Walleij fw_info.version.api_version,
265005ec260eSLinus Walleij fw_info.version.func_version,
265105ec260eSLinus Walleij fw_info.version.errata);
26523df57bcfSMattias Nilsson iounmap(tcpm_base);
26533df57bcfSMattias Nilsson }
2654650c2a21SLinus Walleij
db8500_prcmu_early_init(void)265522fb3ad0SLinus Walleij void __init db8500_prcmu_early_init(void)
265605ec260eSLinus Walleij {
26579a47a8dcSLinus Walleij /*
26589a47a8dcSLinus Walleij * This is a temporary remap to bring up the clocks. It is
26599a47a8dcSLinus Walleij * subsequently replaces with a real remap. After the merge of
26609a47a8dcSLinus Walleij * the mailbox subsystem all of this early code goes away, and the
26619a47a8dcSLinus Walleij * clock driver can probe independently. An early initcall will
26629a47a8dcSLinus Walleij * still be needed, but it can be diverted into drivers/clk/ux500.
26639a47a8dcSLinus Walleij */
266422fb3ad0SLinus Walleij struct device_node *np;
266522fb3ad0SLinus Walleij
266622fb3ad0SLinus Walleij np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
266722fb3ad0SLinus Walleij prcmu_base = of_iomap(np, 0);
266822fb3ad0SLinus Walleij if (!prcmu_base) {
266922fb3ad0SLinus Walleij of_node_put(np);
26709a47a8dcSLinus Walleij pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
267122fb3ad0SLinus Walleij return;
267222fb3ad0SLinus Walleij }
267322fb3ad0SLinus Walleij dbx500_fw_version_init(np);
267422fb3ad0SLinus Walleij of_node_put(np);
26759a47a8dcSLinus Walleij
26763df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.lock);
26773df57bcfSMattias Nilsson spin_lock_init(&mb0_transfer.dbb_irqs_lock);
26783df57bcfSMattias Nilsson mutex_init(&mb0_transfer.ac_wake_lock);
26793df57bcfSMattias Nilsson init_completion(&mb0_transfer.ac_wake_work);
2680650c2a21SLinus Walleij mutex_init(&mb1_transfer.lock);
2681650c2a21SLinus Walleij init_completion(&mb1_transfer.work);
26824d64d2e3SMattias Nilsson mb1_transfer.ape_opp = APE_NO_CHANGE;
26833df57bcfSMattias Nilsson mutex_init(&mb2_transfer.lock);
26843df57bcfSMattias Nilsson init_completion(&mb2_transfer.work);
26853df57bcfSMattias Nilsson spin_lock_init(&mb2_transfer.auto_pm_lock);
26863df57bcfSMattias Nilsson spin_lock_init(&mb3_transfer.lock);
26873df57bcfSMattias Nilsson mutex_init(&mb3_transfer.sysclk_lock);
26883df57bcfSMattias Nilsson init_completion(&mb3_transfer.sysclk_work);
26893df57bcfSMattias Nilsson mutex_init(&mb4_transfer.lock);
26903df57bcfSMattias Nilsson init_completion(&mb4_transfer.work);
2691650c2a21SLinus Walleij mutex_init(&mb5_transfer.lock);
2692650c2a21SLinus Walleij init_completion(&mb5_transfer.work);
2693650c2a21SLinus Walleij
26943df57bcfSMattias Nilsson INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2695650c2a21SLinus Walleij }
2696650c2a21SLinus Walleij
init_prcm_registers(void)2697a3888f62SNathan Chancellor static void init_prcm_registers(void)
2698d65e12d7SMattias Nilsson {
2699d65e12d7SMattias Nilsson u32 val;
2700d65e12d7SMattias Nilsson
2701d65e12d7SMattias Nilsson val = readl(PRCM_A9PL_FORCE_CLKEN);
2702d65e12d7SMattias Nilsson val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2703d65e12d7SMattias Nilsson PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2704d65e12d7SMattias Nilsson writel(val, (PRCM_A9PL_FORCE_CLKEN));
2705d65e12d7SMattias Nilsson }
2706d65e12d7SMattias Nilsson
27071032fbfdSBengt Jonsson /*
27081032fbfdSBengt Jonsson * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
27091032fbfdSBengt Jonsson */
27101032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vape_consumers[] = {
27111032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", NULL),
27121032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
27131032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
27141032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
27151032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2716ae840635SLee Jones REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
27171032fbfdSBengt Jonsson /* "v-mmc" changed to "vcore" in the mainline kernel */
27181032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi0"),
27191032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi1"),
27201032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi2"),
27211032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi3"),
27221032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "sdi4"),
27231032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-dma", "dma40.0"),
27241032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
27251032fbfdSBengt Jonsson /* "v-uart" changed to "vcore" in the mainline kernel */
27261032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart0"),
27271032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart1"),
27281032fbfdSBengt Jonsson REGULATOR_SUPPLY("vcore", "uart2"),
27291032fbfdSBengt Jonsson REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2730992b133aSBengt Jonsson REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2731bc367481SLee Jones REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
27321032fbfdSBengt Jonsson };
27331032fbfdSBengt Jonsson
27341032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
27351032fbfdSBengt Jonsson REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
27361032fbfdSBengt Jonsson /* AV8100 regulator */
27371032fbfdSBengt Jonsson REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
27381032fbfdSBengt Jonsson };
27391032fbfdSBengt Jonsson
27401032fbfdSBengt Jonsson static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2741992b133aSBengt Jonsson REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2742624e87c2SBengt Jonsson REGULATOR_SUPPLY("vsupply", "mcde"),
2743624e87c2SBengt Jonsson };
2744624e87c2SBengt Jonsson
2745624e87c2SBengt Jonsson /* SVA MMDSP regulator switch */
2746624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2747624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2748624e87c2SBengt Jonsson };
2749624e87c2SBengt Jonsson
2750624e87c2SBengt Jonsson /* SVA pipe regulator switch */
2751624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2752624e87c2SBengt Jonsson REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2753624e87c2SBengt Jonsson };
2754624e87c2SBengt Jonsson
2755624e87c2SBengt Jonsson /* SIA MMDSP regulator switch */
2756624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2757624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2758624e87c2SBengt Jonsson };
2759624e87c2SBengt Jonsson
2760624e87c2SBengt Jonsson /* SIA pipe regulator switch */
2761624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2762624e87c2SBengt Jonsson REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2763624e87c2SBengt Jonsson };
2764624e87c2SBengt Jonsson
2765624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_sga_consumers[] = {
2766624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-mali", NULL),
2767624e87c2SBengt Jonsson };
2768624e87c2SBengt Jonsson
2769624e87c2SBengt Jonsson /* ESRAM1 and 2 regulator switch */
2770624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2771624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram12", "cm_control"),
2772624e87c2SBengt Jonsson };
2773624e87c2SBengt Jonsson
2774624e87c2SBengt Jonsson /* ESRAM3 and 4 regulator switch */
2775624e87c2SBengt Jonsson static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2776624e87c2SBengt Jonsson REGULATOR_SUPPLY("v-esram34", "mcde"),
2777624e87c2SBengt Jonsson REGULATOR_SUPPLY("esram34", "cm_control"),
2778992b133aSBengt Jonsson REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
27791032fbfdSBengt Jonsson };
27801032fbfdSBengt Jonsson
27811032fbfdSBengt Jonsson static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
27821032fbfdSBengt Jonsson [DB8500_REGULATOR_VAPE] = {
27831032fbfdSBengt Jonsson .constraints = {
27841032fbfdSBengt Jonsson .name = "db8500-vape",
27851032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
27861e45860fSMark Brown .always_on = true,
27871032fbfdSBengt Jonsson },
27881032fbfdSBengt Jonsson .consumer_supplies = db8500_vape_consumers,
27891032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
27901032fbfdSBengt Jonsson },
27911032fbfdSBengt Jonsson [DB8500_REGULATOR_VARM] = {
27921032fbfdSBengt Jonsson .constraints = {
27931032fbfdSBengt Jonsson .name = "db8500-varm",
27941032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
27951032fbfdSBengt Jonsson },
27961032fbfdSBengt Jonsson },
27971032fbfdSBengt Jonsson [DB8500_REGULATOR_VMODEM] = {
27981032fbfdSBengt Jonsson .constraints = {
27991032fbfdSBengt Jonsson .name = "db8500-vmodem",
28001032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28011032fbfdSBengt Jonsson },
28021032fbfdSBengt Jonsson },
28031032fbfdSBengt Jonsson [DB8500_REGULATOR_VPLL] = {
28041032fbfdSBengt Jonsson .constraints = {
28051032fbfdSBengt Jonsson .name = "db8500-vpll",
28061032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28071032fbfdSBengt Jonsson },
28081032fbfdSBengt Jonsson },
28091032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS1] = {
28101032fbfdSBengt Jonsson .constraints = {
28111032fbfdSBengt Jonsson .name = "db8500-vsmps1",
28121032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28131032fbfdSBengt Jonsson },
28141032fbfdSBengt Jonsson },
28151032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS2] = {
28161032fbfdSBengt Jonsson .constraints = {
28171032fbfdSBengt Jonsson .name = "db8500-vsmps2",
28181032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28191032fbfdSBengt Jonsson },
28201032fbfdSBengt Jonsson .consumer_supplies = db8500_vsmps2_consumers,
28211032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
28221032fbfdSBengt Jonsson },
28231032fbfdSBengt Jonsson [DB8500_REGULATOR_VSMPS3] = {
28241032fbfdSBengt Jonsson .constraints = {
28251032fbfdSBengt Jonsson .name = "db8500-vsmps3",
28261032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28271032fbfdSBengt Jonsson },
28281032fbfdSBengt Jonsson },
28291032fbfdSBengt Jonsson [DB8500_REGULATOR_VRF1] = {
28301032fbfdSBengt Jonsson .constraints = {
28311032fbfdSBengt Jonsson .name = "db8500-vrf1",
28321032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28331032fbfdSBengt Jonsson },
28341032fbfdSBengt Jonsson },
28351032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2836992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */
28371032fbfdSBengt Jonsson .constraints = {
28381032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp",
28391032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28401032fbfdSBengt Jonsson },
2841624e87c2SBengt Jonsson .consumer_supplies = db8500_svammdsp_consumers,
2842624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
28431032fbfdSBengt Jonsson },
28441032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
28451032fbfdSBengt Jonsson .constraints = {
28461032fbfdSBengt Jonsson /* "ret" means "retention" */
28471032fbfdSBengt Jonsson .name = "db8500-sva-mmdsp-ret",
28481032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28491032fbfdSBengt Jonsson },
28501032fbfdSBengt Jonsson },
28511032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2852992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */
28531032fbfdSBengt Jonsson .constraints = {
28541032fbfdSBengt Jonsson .name = "db8500-sva-pipe",
28551032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28561032fbfdSBengt Jonsson },
2857624e87c2SBengt Jonsson .consumer_supplies = db8500_svapipe_consumers,
2858624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
28591032fbfdSBengt Jonsson },
28601032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2861992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */
28621032fbfdSBengt Jonsson .constraints = {
28631032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp",
28641032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28651032fbfdSBengt Jonsson },
2866624e87c2SBengt Jonsson .consumer_supplies = db8500_siammdsp_consumers,
2867624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
28681032fbfdSBengt Jonsson },
28691032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
28701032fbfdSBengt Jonsson .constraints = {
28711032fbfdSBengt Jonsson .name = "db8500-sia-mmdsp-ret",
28721032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28731032fbfdSBengt Jonsson },
28741032fbfdSBengt Jonsson },
28751032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2876992b133aSBengt Jonsson /* dependency to u8500-vape is handled outside regulator framework */
28771032fbfdSBengt Jonsson .constraints = {
28781032fbfdSBengt Jonsson .name = "db8500-sia-pipe",
28791032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28801032fbfdSBengt Jonsson },
2881624e87c2SBengt Jonsson .consumer_supplies = db8500_siapipe_consumers,
2882624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
28831032fbfdSBengt Jonsson },
28841032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_SGA] = {
28851032fbfdSBengt Jonsson .supply_regulator = "db8500-vape",
28861032fbfdSBengt Jonsson .constraints = {
28871032fbfdSBengt Jonsson .name = "db8500-sga",
28881032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28891032fbfdSBengt Jonsson },
2890624e87c2SBengt Jonsson .consumer_supplies = db8500_sga_consumers,
2891624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2892624e87c2SBengt Jonsson
28931032fbfdSBengt Jonsson },
28941032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
28951032fbfdSBengt Jonsson .supply_regulator = "db8500-vape",
28961032fbfdSBengt Jonsson .constraints = {
28971032fbfdSBengt Jonsson .name = "db8500-b2r2-mcde",
28981032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
28991032fbfdSBengt Jonsson },
29001032fbfdSBengt Jonsson .consumer_supplies = db8500_b2r2_mcde_consumers,
29011032fbfdSBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
29021032fbfdSBengt Jonsson },
29031032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2904992b133aSBengt Jonsson /*
2905992b133aSBengt Jonsson * esram12 is set in retention and supplied by Vsafe when Vape is off,
2906992b133aSBengt Jonsson * no need to hold Vape
2907992b133aSBengt Jonsson */
29081032fbfdSBengt Jonsson .constraints = {
29091032fbfdSBengt Jonsson .name = "db8500-esram12",
29101032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
29111032fbfdSBengt Jonsson },
2912624e87c2SBengt Jonsson .consumer_supplies = db8500_esram12_consumers,
2913624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
29141032fbfdSBengt Jonsson },
29151032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
29161032fbfdSBengt Jonsson .constraints = {
29171032fbfdSBengt Jonsson .name = "db8500-esram12-ret",
29181032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
29191032fbfdSBengt Jonsson },
29201032fbfdSBengt Jonsson },
29211032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2922992b133aSBengt Jonsson /*
2923992b133aSBengt Jonsson * esram34 is set in retention and supplied by Vsafe when Vape is off,
2924992b133aSBengt Jonsson * no need to hold Vape
2925992b133aSBengt Jonsson */
29261032fbfdSBengt Jonsson .constraints = {
29271032fbfdSBengt Jonsson .name = "db8500-esram34",
29281032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
29291032fbfdSBengt Jonsson },
2930624e87c2SBengt Jonsson .consumer_supplies = db8500_esram34_consumers,
2931624e87c2SBengt Jonsson .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
29321032fbfdSBengt Jonsson },
29331032fbfdSBengt Jonsson [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
29341032fbfdSBengt Jonsson .constraints = {
29351032fbfdSBengt Jonsson .name = "db8500-esram34-ret",
29361032fbfdSBengt Jonsson .valid_ops_mask = REGULATOR_CHANGE_STATUS,
29371032fbfdSBengt Jonsson },
29381032fbfdSBengt Jonsson },
29391032fbfdSBengt Jonsson };
29401032fbfdSBengt Jonsson
29415ac98553SGeert Uytterhoeven static const struct mfd_cell common_prcmu_devs[] = {
2942c7388880SLinus Walleij MFD_CELL_NAME("db8500_wdt"),
2943f28fd3b6SLinus Walleij MFD_CELL_NAME("db8500-cpuidle"),
2944d98a5384SLee Jones };
2945d98a5384SLee Jones
29465ac98553SGeert Uytterhoeven static const struct mfd_cell db8500_prcmu_devs[] = {
2947db783e76SLee Jones MFD_CELL_OF("db8500-prcmu-regulators", NULL,
2948a04b4be6SLee Jones &db8500_regulators, sizeof(db8500_regulators), 0,
2949a04b4be6SLee Jones "stericsson,db8500-prcmu-regulator"),
2950db783e76SLee Jones MFD_CELL_OF("db8500-thermal",
2951a04b4be6SLee Jones NULL, NULL, 0, 0, "stericsson,db8500-thermal"),
29523df57bcfSMattias Nilsson };
29533df57bcfSMattias Nilsson
db8500_prcmu_register_ab8500(struct device * parent)29544e657946SArnd Bergmann static int db8500_prcmu_register_ab8500(struct device *parent)
295555b175d7SArnd Bergmann {
2956f864c46aSLinus Walleij struct device_node *np;
29571c0769d2SStephan Gerhold struct resource ab850x_resource;
29585785a97eSKrzysztof Kozlowski const struct mfd_cell ab8500_cell = {
295955b175d7SArnd Bergmann .name = "ab8500-core",
296055b175d7SArnd Bergmann .of_compatible = "stericsson,ab8500",
296155b175d7SArnd Bergmann .id = AB8500_VERSION_AB8500,
29621c0769d2SStephan Gerhold .resources = &ab850x_resource,
296355b175d7SArnd Bergmann .num_resources = 1,
296455b175d7SArnd Bergmann };
29651c0769d2SStephan Gerhold const struct mfd_cell ab8505_cell = {
29661c0769d2SStephan Gerhold .name = "ab8505-core",
29671c0769d2SStephan Gerhold .of_compatible = "stericsson,ab8505",
29681c0769d2SStephan Gerhold .id = AB8500_VERSION_AB8505,
29691c0769d2SStephan Gerhold .resources = &ab850x_resource,
29701c0769d2SStephan Gerhold .num_resources = 1,
29711c0769d2SStephan Gerhold };
29721c0769d2SStephan Gerhold const struct mfd_cell *ab850x_cell;
297355b175d7SArnd Bergmann
2974f864c46aSLinus Walleij if (!parent->of_node)
2975f864c46aSLinus Walleij return -ENODEV;
2976f864c46aSLinus Walleij
2977f864c46aSLinus Walleij /* Look up the device node, sneak the IRQ out of it */
2978f864c46aSLinus Walleij for_each_child_of_node(parent->of_node, np) {
29791c0769d2SStephan Gerhold if (of_device_is_compatible(np, ab8500_cell.of_compatible)) {
29801c0769d2SStephan Gerhold ab850x_cell = &ab8500_cell;
2981f864c46aSLinus Walleij break;
2982f864c46aSLinus Walleij }
29831c0769d2SStephan Gerhold if (of_device_is_compatible(np, ab8505_cell.of_compatible)) {
29841c0769d2SStephan Gerhold ab850x_cell = &ab8505_cell;
29851c0769d2SStephan Gerhold break;
29861c0769d2SStephan Gerhold }
29871c0769d2SStephan Gerhold }
2988f864c46aSLinus Walleij if (!np) {
29891c0769d2SStephan Gerhold dev_info(parent, "could not find AB850X node in the device tree\n");
2990f864c46aSLinus Walleij return -ENODEV;
2991f864c46aSLinus Walleij }
29921c0769d2SStephan Gerhold of_irq_to_resource_table(np, &ab850x_resource, 1);
2993f864c46aSLinus Walleij
29941c0769d2SStephan Gerhold return mfd_add_devices(parent, 0, ab850x_cell, 1, NULL, 0, NULL);
299555b175d7SArnd Bergmann }
299655b175d7SArnd Bergmann
db8500_prcmu_probe(struct platform_device * pdev)2997f791be49SBill Pemberton static int db8500_prcmu_probe(struct platform_device *pdev)
29983df57bcfSMattias Nilsson {
2999ca7edd16SLee Jones struct device_node *np = pdev->dev.of_node;
300055b175d7SArnd Bergmann int irq = 0, err = 0;
300105ec260eSLinus Walleij struct resource *res;
30023df57bcfSMattias Nilsson
3003b047d981SLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3004b047d981SLinus Walleij if (!res) {
3005b047d981SLinus Walleij dev_err(&pdev->dev, "no prcmu memory region provided\n");
30066bdf891aSLee Jones return -EINVAL;
3007b047d981SLinus Walleij }
3008b047d981SLinus Walleij prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3009b047d981SLinus Walleij if (!prcmu_base) {
3010b047d981SLinus Walleij dev_err(&pdev->dev,
3011b047d981SLinus Walleij "failed to ioremap prcmu register memory\n");
30126bdf891aSLee Jones return -ENOMEM;
3013b047d981SLinus Walleij }
30140508901cSMattias Nilsson init_prcm_registers();
301505ec260eSLinus Walleij res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
301605ec260eSLinus Walleij if (!res) {
301705ec260eSLinus Walleij dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
30186bdf891aSLee Jones return -EINVAL;
301905ec260eSLinus Walleij }
302005ec260eSLinus Walleij tcdm_base = devm_ioremap(&pdev->dev, res->start,
302105ec260eSLinus Walleij resource_size(res));
302251a7e02bSPramod Gurav if (!tcdm_base) {
302351a7e02bSPramod Gurav dev_err(&pdev->dev,
302451a7e02bSPramod Gurav "failed to ioremap prcmu-tcdm register memory\n");
30256bdf891aSLee Jones return -ENOMEM;
302651a7e02bSPramod Gurav }
302705ec260eSLinus Walleij
30283df57bcfSMattias Nilsson /* Clean up the mailbox interrupts after pre-kernel code. */
3029c553b3caSMattias Nilsson writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
30303df57bcfSMattias Nilsson
3031ca7edd16SLee Jones irq = platform_get_irq(pdev, 0);
3032802d9bd4SStephen Boyd if (irq <= 0)
30336bdf891aSLee Jones return irq;
3034ca7edd16SLee Jones
3035ca7edd16SLee Jones err = request_threaded_irq(irq, prcmu_irq_handler,
30363df57bcfSMattias Nilsson prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
30373df57bcfSMattias Nilsson if (err < 0) {
30383df57bcfSMattias Nilsson pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
30396bdf891aSLee Jones return err;
30403df57bcfSMattias Nilsson }
30413df57bcfSMattias Nilsson
3042f864c46aSLinus Walleij db8500_irq_init(np);
30433a8e39c9SLee Jones
30443df57bcfSMattias Nilsson prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
30453df57bcfSMattias Nilsson
3046d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3047d98a5384SLee Jones ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3048ca7edd16SLee Jones if (err) {
30493df57bcfSMattias Nilsson pr_err("prcmu: Failed to add subdevices\n");
3050ca7edd16SLee Jones return err;
3051ca7edd16SLee Jones }
3052ca7edd16SLee Jones
3053d98a5384SLee Jones /* TODO: Remove restriction when clk definitions are available. */
3054d98a5384SLee Jones if (!of_machine_is_compatible("st-ericsson,u8540")) {
3055d98a5384SLee Jones err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3056d98a5384SLee Jones ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3057d98a5384SLee Jones db8500_irq_domain);
3058d98a5384SLee Jones if (err) {
3059d98a5384SLee Jones mfd_remove_devices(&pdev->dev);
3060d98a5384SLee Jones pr_err("prcmu: Failed to add subdevices\n");
30616bdf891aSLee Jones return err;
3062d98a5384SLee Jones }
3063d98a5384SLee Jones }
3064d98a5384SLee Jones
30654e657946SArnd Bergmann err = db8500_prcmu_register_ab8500(&pdev->dev);
306655b175d7SArnd Bergmann if (err) {
306755b175d7SArnd Bergmann mfd_remove_devices(&pdev->dev);
306855b175d7SArnd Bergmann pr_err("prcmu: Failed to add ab8500 subdevice\n");
30696bdf891aSLee Jones return err;
307055b175d7SArnd Bergmann }
307155b175d7SArnd Bergmann
30723df57bcfSMattias Nilsson pr_info("DB8500 PRCMU initialized\n");
30733df57bcfSMattias Nilsson return err;
30743df57bcfSMattias Nilsson }
30753c144762SLee Jones static const struct of_device_id db8500_prcmu_match[] = {
30763c144762SLee Jones { .compatible = "stericsson,db8500-prcmu"},
30773c144762SLee Jones { },
30783c144762SLee Jones };
30793df57bcfSMattias Nilsson
30803df57bcfSMattias Nilsson static struct platform_driver db8500_prcmu_driver = {
30813df57bcfSMattias Nilsson .driver = {
30823df57bcfSMattias Nilsson .name = "db8500-prcmu",
30833c144762SLee Jones .of_match_table = db8500_prcmu_match,
30843df57bcfSMattias Nilsson },
30859fc63f67SLee Jones .probe = db8500_prcmu_probe,
30863df57bcfSMattias Nilsson };
30873df57bcfSMattias Nilsson
db8500_prcmu_init(void)30883df57bcfSMattias Nilsson static int __init db8500_prcmu_init(void)
30893df57bcfSMattias Nilsson {
30909fc63f67SLee Jones return platform_driver_register(&db8500_prcmu_driver);
30913df57bcfSMattias Nilsson }
3092a661aca4SLee Jones core_initcall(db8500_prcmu_init);
3093