1*8f00b3c4SLinus Walleij /* SPDX-License-Identifier: GPL-2.0-only */ 2*8f00b3c4SLinus Walleij /* 3*8f00b3c4SLinus Walleij * Copyright (C) STMicroelectronics 2009 4*8f00b3c4SLinus Walleij * Copyright (C) ST-Ericsson SA 2010 5*8f00b3c4SLinus Walleij * 6*8f00b3c4SLinus Walleij * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 7*8f00b3c4SLinus Walleij * Author: Sundar Iyer <sundar.iyer@stericsson.com> 8*8f00b3c4SLinus Walleij * 9*8f00b3c4SLinus Walleij * PRCM Unit registers 10*8f00b3c4SLinus Walleij */ 11*8f00b3c4SLinus Walleij 12*8f00b3c4SLinus Walleij #ifndef __DB8500_PRCMU_REGS_H 13*8f00b3c4SLinus Walleij #define __DB8500_PRCMU_REGS_H 14*8f00b3c4SLinus Walleij 15*8f00b3c4SLinus Walleij #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) 16*8f00b3c4SLinus Walleij 17*8f00b3c4SLinus Walleij #define PRCM_ACLK_MGT (0x004) 18*8f00b3c4SLinus Walleij #define PRCM_SVAMMCSPCLK_MGT (0x008) 19*8f00b3c4SLinus Walleij #define PRCM_SIAMMDSPCLK_MGT (0x00C) 20*8f00b3c4SLinus Walleij #define PRCM_SGACLK_MGT (0x014) 21*8f00b3c4SLinus Walleij #define PRCM_UARTCLK_MGT (0x018) 22*8f00b3c4SLinus Walleij #define PRCM_MSP02CLK_MGT (0x01C) 23*8f00b3c4SLinus Walleij #define PRCM_I2CCLK_MGT (0x020) 24*8f00b3c4SLinus Walleij #define PRCM_SDMMCCLK_MGT (0x024) 25*8f00b3c4SLinus Walleij #define PRCM_SLIMCLK_MGT (0x028) 26*8f00b3c4SLinus Walleij #define PRCM_PER1CLK_MGT (0x02C) 27*8f00b3c4SLinus Walleij #define PRCM_PER2CLK_MGT (0x030) 28*8f00b3c4SLinus Walleij #define PRCM_PER3CLK_MGT (0x034) 29*8f00b3c4SLinus Walleij #define PRCM_PER5CLK_MGT (0x038) 30*8f00b3c4SLinus Walleij #define PRCM_PER6CLK_MGT (0x03C) 31*8f00b3c4SLinus Walleij #define PRCM_PER7CLK_MGT (0x040) 32*8f00b3c4SLinus Walleij #define PRCM_LCDCLK_MGT (0x044) 33*8f00b3c4SLinus Walleij #define PRCM_BMLCLK_MGT (0x04C) 34*8f00b3c4SLinus Walleij #define PRCM_HSITXCLK_MGT (0x050) 35*8f00b3c4SLinus Walleij #define PRCM_HSIRXCLK_MGT (0x054) 36*8f00b3c4SLinus Walleij #define PRCM_HDMICLK_MGT (0x058) 37*8f00b3c4SLinus Walleij #define PRCM_APEATCLK_MGT (0x05C) 38*8f00b3c4SLinus Walleij #define PRCM_APETRACECLK_MGT (0x060) 39*8f00b3c4SLinus Walleij #define PRCM_MCDECLK_MGT (0x064) 40*8f00b3c4SLinus Walleij #define PRCM_IPI2CCLK_MGT (0x068) 41*8f00b3c4SLinus Walleij #define PRCM_DSIALTCLK_MGT (0x06C) 42*8f00b3c4SLinus Walleij #define PRCM_DMACLK_MGT (0x074) 43*8f00b3c4SLinus Walleij #define PRCM_B2R2CLK_MGT (0x078) 44*8f00b3c4SLinus Walleij #define PRCM_TVCLK_MGT (0x07C) 45*8f00b3c4SLinus Walleij #define PRCM_UNIPROCLK_MGT (0x278) 46*8f00b3c4SLinus Walleij #define PRCM_SSPCLK_MGT (0x280) 47*8f00b3c4SLinus Walleij #define PRCM_RNGCLK_MGT (0x284) 48*8f00b3c4SLinus Walleij #define PRCM_UICCCLK_MGT (0x27C) 49*8f00b3c4SLinus Walleij #define PRCM_MSP1CLK_MGT (0x288) 50*8f00b3c4SLinus Walleij 51*8f00b3c4SLinus Walleij #define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118) 52*8f00b3c4SLinus Walleij #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f 53*8f00b3c4SLinus Walleij #define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf 54*8f00b3c4SLinus Walleij 55*8f00b3c4SLinus Walleij #define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8) 56*8f00b3c4SLinus Walleij #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 57*8f00b3c4SLinus Walleij 58*8f00b3c4SLinus Walleij #define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114) 59*8f00b3c4SLinus Walleij #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) 60*8f00b3c4SLinus Walleij #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) 61*8f00b3c4SLinus Walleij 62*8f00b3c4SLinus Walleij #define PRCM_PLLARM_ENABLE (prcmu_base + 0x98) 63*8f00b3c4SLinus Walleij #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 64*8f00b3c4SLinus Walleij #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 65*8f00b3c4SLinus Walleij 66*8f00b3c4SLinus Walleij #define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0) 67*8f00b3c4SLinus Walleij #define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C) 68*8f00b3c4SLinus Walleij #define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4) 69*8f00b3c4SLinus Walleij #define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0) 70*8f00b3c4SLinus Walleij #define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c) 71*8f00b3c4SLinus Walleij #define PRCM_SRAM_A9 (prcmu_base + 0x308) 72*8f00b3c4SLinus Walleij 73*8f00b3c4SLinus Walleij #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) 74*8f00b3c4SLinus Walleij #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) 75*8f00b3c4SLinus Walleij 76*8f00b3c4SLinus Walleij /* CPU mailbox registers */ 77*8f00b3c4SLinus Walleij #define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc) 78*8f00b3c4SLinus Walleij #define PRCM_MBOX_CPU_SET (prcmu_base + 0x100) 79*8f00b3c4SLinus Walleij #define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104) 80*8f00b3c4SLinus Walleij 81*8f00b3c4SLinus Walleij #define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334) 82*8f00b3c4SLinus Walleij #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 83*8f00b3c4SLinus Walleij #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) 84*8f00b3c4SLinus Walleij #define ARM_WAKEUP_MODEM 0x1 85*8f00b3c4SLinus Walleij 86*8f00b3c4SLinus Walleij #define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C) 87*8f00b3c4SLinus Walleij #define PRCM_ARM_IT1_VAL (prcmu_base + 0x494) 88*8f00b3c4SLinus Walleij #define PRCM_HOLD_EVT (prcmu_base + 0x174) 89*8f00b3c4SLinus Walleij 90*8f00b3c4SLinus Walleij #define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0) 91*8f00b3c4SLinus Walleij #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) 92*8f00b3c4SLinus Walleij #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) 93*8f00b3c4SLinus Walleij #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) 94*8f00b3c4SLinus Walleij 95*8f00b3c4SLinus Walleij #define PRCM_ITSTATUS0 (prcmu_base + 0x148) 96*8f00b3c4SLinus Walleij #define PRCM_ITSTATUS1 (prcmu_base + 0x150) 97*8f00b3c4SLinus Walleij #define PRCM_ITSTATUS2 (prcmu_base + 0x158) 98*8f00b3c4SLinus Walleij #define PRCM_ITSTATUS3 (prcmu_base + 0x160) 99*8f00b3c4SLinus Walleij #define PRCM_ITSTATUS4 (prcmu_base + 0x168) 100*8f00b3c4SLinus Walleij #define PRCM_ITSTATUS5 (prcmu_base + 0x484) 101*8f00b3c4SLinus Walleij #define PRCM_ITCLEAR5 (prcmu_base + 0x488) 102*8f00b3c4SLinus Walleij #define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018) 103*8f00b3c4SLinus Walleij 104*8f00b3c4SLinus Walleij /* System reset register */ 105*8f00b3c4SLinus Walleij #define PRCM_APE_SOFTRST (prcmu_base + 0x228) 106*8f00b3c4SLinus Walleij 107*8f00b3c4SLinus Walleij /* Level shifter and clamp control registers */ 108*8f00b3c4SLinus Walleij #define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420) 109*8f00b3c4SLinus Walleij #define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424) 110*8f00b3c4SLinus Walleij 111*8f00b3c4SLinus Walleij #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) 112*8f00b3c4SLinus Walleij #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) 113*8f00b3c4SLinus Walleij 114*8f00b3c4SLinus Walleij /* PRCMU clock/PLL/reset registers */ 115*8f00b3c4SLinus Walleij #define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080) 116*8f00b3c4SLinus Walleij #define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084) 117*8f00b3c4SLinus Walleij #define PRCM_PLLARM_FREQ (prcmu_base + 0x088) 118*8f00b3c4SLinus Walleij #define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C) 119*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_D_SHIFT 0 120*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) 121*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_N_SHIFT 8 122*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_N_MASK BITS(8, 13) 123*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_R_SHIFT 16 124*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_R_MASK BITS(16, 18) 125*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_SELDIV2 BIT(24) 126*8f00b3c4SLinus Walleij #define PRCM_PLL_FREQ_DIV2EN BIT(25) 127*8f00b3c4SLinus Walleij 128*8f00b3c4SLinus Walleij #define PRCM_PLLDSI_FREQ (prcmu_base + 0x500) 129*8f00b3c4SLinus Walleij #define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504) 130*8f00b3c4SLinus Walleij #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) 131*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530) 132*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C) 133*8f00b3c4SLinus Walleij #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) 134*8f00b3c4SLinus Walleij #define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4) 135*8f00b3c4SLinus Walleij #define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8) 136*8f00b3c4SLinus Walleij 137*8f00b3c4SLinus Walleij #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) 138*8f00b3c4SLinus Walleij 139*8f00b3c4SLinus Walleij #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0) 140*8f00b3c4SLinus Walleij #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1) 141*8f00b3c4SLinus Walleij 142*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0 143*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2) 144*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8 145*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10) 146*8f00b3c4SLinus Walleij 147*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_OFF 0 148*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_PHI 1 149*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_PHI_2 2 150*8f00b3c4SLinus Walleij #define PRCM_DSI_PLLOUT_SEL_PHI_4 3 151*8f00b3c4SLinus Walleij 152*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0 153*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7) 154*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8 155*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15) 156*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16 157*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23) 158*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24) 159*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25) 160*8f00b3c4SLinus Walleij #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26) 161*8f00b3c4SLinus Walleij 162*8f00b3c4SLinus Walleij #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) 163*8f00b3c4SLinus Walleij 164*8f00b3c4SLinus Walleij #define PRCM_CLKOCR (prcmu_base + 0x1CC) 165*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) 166*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) 167*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) 168*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) 169*8f00b3c4SLinus Walleij 170*8f00b3c4SLinus Walleij /* ePOD and memory power signal control registers */ 171*8f00b3c4SLinus Walleij #define PRCM_EPOD_C_SET (prcmu_base + 0x410) 172*8f00b3c4SLinus Walleij #define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304) 173*8f00b3c4SLinus Walleij 174*8f00b3c4SLinus Walleij /* Debug power control unit registers */ 175*8f00b3c4SLinus Walleij #define PRCM_POWER_STATE_SET (prcmu_base + 0x254) 176*8f00b3c4SLinus Walleij 177*8f00b3c4SLinus Walleij /* Miscellaneous unit registers */ 178*8f00b3c4SLinus Walleij #define PRCM_DSI_SW_RESET (prcmu_base + 0x324) 179*8f00b3c4SLinus Walleij #define PRCM_GPIOCR (prcmu_base + 0x138) 180*8f00b3c4SLinus Walleij #define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 181*8f00b3c4SLinus Walleij #define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 182*8f00b3c4SLinus Walleij 183*8f00b3c4SLinus Walleij /* PRCMU HW semaphore */ 184*8f00b3c4SLinus Walleij #define PRCM_SEM (prcmu_base + 0x400) 185*8f00b3c4SLinus Walleij #define PRCM_SEM_PRCM_SEM BIT(0) 186*8f00b3c4SLinus Walleij 187*8f00b3c4SLinus Walleij #define PRCM_TCR (prcmu_base + 0x1C8) 188*8f00b3c4SLinus Walleij #define PRCM_TCR_TENSEL_MASK BITS(0, 7) 189*8f00b3c4SLinus Walleij #define PRCM_TCR_STOP_TIMERS BIT(16) 190*8f00b3c4SLinus Walleij #define PRCM_TCR_DOZE_MODE BIT(17) 191*8f00b3c4SLinus Walleij 192*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKODIV0_SHIFT 0 193*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5) 194*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOSEL0_SHIFT 6 195*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8) 196*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKODIV1_SHIFT 16 197*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21) 198*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOSEL1_SHIFT 22 199*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) 200*8f00b3c4SLinus Walleij #define PRCM_CLKOCR_CLK1TYPE BIT(28) 201*8f00b3c4SLinus Walleij 202*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) 203*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) 204*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) 205*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) 206*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) 207*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLKEN BIT(8) 208*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLK38 BIT(9) 209*8f00b3c4SLinus Walleij #define PRCM_CLK_MGT_CLK38DIV BIT(11) 210*8f00b3c4SLinus Walleij #define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) 211*8f00b3c4SLinus Walleij 212*8f00b3c4SLinus Walleij /* GPIOCR register */ 213*8f00b3c4SLinus Walleij #define PRCM_GPIOCR_SPI2_SELECT BIT(23) 214*8f00b3c4SLinus Walleij 215*8f00b3c4SLinus Walleij #define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438) 216*8f00b3c4SLinus Walleij #define PRCM_CGATING_BYPASS (prcmu_base + 0x134) 217*8f00b3c4SLinus Walleij #define PRCM_CGATING_BYPASS_ICN2 BIT(6) 218*8f00b3c4SLinus Walleij 219*8f00b3c4SLinus Walleij /* Miscellaneous unit registers */ 220*8f00b3c4SLinus Walleij #define PRCM_RESOUTN_SET (prcmu_base + 0x214) 221*8f00b3c4SLinus Walleij #define PRCM_RESOUTN_CLR (prcmu_base + 0x218) 222*8f00b3c4SLinus Walleij 223*8f00b3c4SLinus Walleij /* System reset register */ 224*8f00b3c4SLinus Walleij #define PRCM_APE_SOFTRST (prcmu_base + 0x228) 225*8f00b3c4SLinus Walleij 226*8f00b3c4SLinus Walleij #endif /* __DB8500_PRCMU_REGS_H */ 227